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authorOlof Johansson <olof@lixom.net>2014-05-22 01:16:30 -0400
committerOlof Johansson <olof@lixom.net>2014-05-22 01:16:30 -0400
commit3bc4a87c03e75c88471450380cb194bf30ea4a87 (patch)
tree8e757ceeeeddf927ce5feda60154962f745547ee
parent4b660a7f5c8099d88d1a43d8ae138965112592c7 (diff)
parent702b691e4a711e699cf3cccba879c1d945665c0d (diff)
Merge tag 'samsung-fixes' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Samsung fixes for 3.15 from Kukjin Kim: - Remove g2d_pd and mau_pd nodes on exynos5420. Since the power domains are linked to the CMU blocks, kernel panic happens during access clocks when the power domains are disabled. Now this is a best solution. - Enable HS-I2C on exynos5 by default MMC partition cannot be mounted for RFS without the enabling HS-I2C because regulators for MMC power are connected to HS-I2C bus. - Disable MDMA1 node on exynos5420 When MDMA1 runs in secure mode it makes kernel fault, so need to disalbe it on exynos5420 by default instead of each board. - Fix the secondary CPU boot for exynos4212 * tag 'samsung-fixes' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Remove g2d_pd node for exynos5420 ARM: dts: Remove mau_pd node for exynos5420 ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount ARM: dts: disable MDMA1 node for exynos5420 ARM: EXYNOS: fix the secondary CPU boot of exynos4212 Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts12
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi18
-rw-r--r--arch/arm/configs/exynos_defconfig1
-rw-r--r--arch/arm/mach-exynos/firmware.c15
4 files changed, 22 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 80a3bf4c5986..896a2a6619e0 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -364,16 +364,4 @@
364 gpio-key,wakeup; 364 gpio-key,wakeup;
365 }; 365 };
366 }; 366 };
367
368 amba {
369 mdma1: mdma@11C10000 {
370 /*
371 * MDMA1 can support both secure and non-secure
372 * AXI transactions. When this is enabled in the kernel
373 * for boards that run in secure mode, we are getting
374 * imprecise external aborts causing the kernel to oops.
375 */
376 status = "disabled";
377 };
378 };
379}; 367};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..418f2506aaf0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -219,16 +219,6 @@
219 reg = <0x100440C0 0x20>; 219 reg = <0x100440C0 0x20>;
220 }; 220 };
221 221
222 mau_pd: power-domain@100440E0 {
223 compatible = "samsung,exynos4210-pd";
224 reg = <0x100440E0 0x20>;
225 };
226
227 g2d_pd: power-domain@10044100 {
228 compatible = "samsung,exynos4210-pd";
229 reg = <0x10044100 0x20>;
230 };
231
232 msc_pd: power-domain@10044120 { 222 msc_pd: power-domain@10044120 {
233 compatible = "samsung,exynos4210-pd"; 223 compatible = "samsung,exynos4210-pd";
234 reg = <0x10044120 0x20>; 224 reg = <0x10044120 0x20>;
@@ -336,6 +326,13 @@
336 #dma-cells = <1>; 326 #dma-cells = <1>;
337 #dma-channels = <8>; 327 #dma-channels = <8>;
338 #dma-requests = <1>; 328 #dma-requests = <1>;
329 /*
330 * MDMA1 can support both secure and non-secure
331 * AXI transactions. When this is enabled in the kernel
332 * for boards that run in secure mode, we are getting
333 * imprecise external aborts causing the kernel to oops.
334 */
335 status = "disabled";
339 }; 336 };
340 }; 337 };
341 338
@@ -730,6 +727,5 @@
730 interrupts = <0 112 0>; 727 interrupts = <0 112 0>;
731 clocks = <&clock 471>; 728 clocks = <&clock 471>;
732 clock-names = "secss"; 729 clock-names = "secss";
733 samsung,power-domain = <&g2d_pd>;
734 }; 730 };
735}; 731};
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 4ce7b70ea901..e07a227ec0db 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
65CONFIG_I2C=y 65CONFIG_I2C=y
66CONFIG_I2C_MUX=y 66CONFIG_I2C_MUX=y
67CONFIG_I2C_ARB_GPIO_CHALLENGE=y 67CONFIG_I2C_ARB_GPIO_CHALLENGE=y
68CONFIG_I2C_EXYNOS5=y
68CONFIG_I2C_S3C2410=y 69CONFIG_I2C_S3C2410=y
69CONFIG_DEBUG_GPIO=y 70CONFIG_DEBUG_GPIO=y
70# CONFIG_HWMON is not set 71# CONFIG_HWMON is not set
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129ef26c6..aa01c4222b40 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,6 +18,8 @@
18 18
19#include <mach/map.h> 19#include <mach/map.h>
20 20
21#include <plat/cpu.h>
22
21#include "smc.h" 23#include "smc.h"
22 24
23static int exynos_do_idle(void) 25static int exynos_do_idle(void)
@@ -28,13 +30,24 @@ static int exynos_do_idle(void)
28 30
29static int exynos_cpu_boot(int cpu) 31static int exynos_cpu_boot(int cpu)
30{ 32{
33 /*
34 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
35 * But, Exynos4212 has only one secondary CPU so second parameter
36 * isn't used for informing secure firmware about CPU id.
37 */
38 if (soc_is_exynos4212())
39 cpu = 0;
40
31 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 41 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
32 return 0; 42 return 0;
33} 43}
34 44
35static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 45static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
36{ 46{
37 void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu; 47 void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
48
49 if (!soc_is_exynos4212())
50 boot_reg += 4*cpu;
38 51
39 __raw_writel(boot_addr, boot_reg); 52 __raw_writel(boot_addr, boot_reg);
40 return 0; 53 return 0;