aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2011-12-20 00:09:48 -0500
committerOlof Johansson <olof@lixom.net>2011-12-20 00:09:48 -0500
commit3b0d597139efddfd8960b44249b4a4c977d172f1 (patch)
tree51c16913c15b52f06f0f4b5b721226e8885e3663
parentb86c7842ef176df0fef3d3d05f83900b3599223d (diff)
parent6b6fa98c3e6d29eb7b515d807139590a27e6b9b0 (diff)
Merge branch 'omap/uart' into next/pm
* omap/uart: (32 commits) ARM: omap: pass minimal SoC/board data for UART from dt arm/dts: Add minimal device tree support for omap2420 and omap2430 omap-serial: Add minimal device tree support omap-serial: Use default clock speed (48Mhz) if not specified omap-serial: Get rid of all pdev->id usage ARM: OMAP2+: UART: Fix compilation/sparse warnings ARM: OMAP2+: UART: Remove omap_uart_can_sleep and add pm_qos ARM: OMAP2+: UART: Do not gate uart clocks if used for debug_prints ARM: OMAP2+: UART: Avoid uart idling on suspend for no_console_suspend usecase ARM: OMAP2+: UART: Avoid console uart idling during bootup ARM: OMAP2+: UART: remove temporary variable used to count uart instance ARM: OMAP2+: UART: Make the RX_TIMEOUT for DMA configurable for each UART ARM: OMAP2+: UART: Allow UART parameters to be configured from board file. ARM: OMAP2+: UART: Remove old and unused clocks handling funcs ARM: OMAP2+: UART: Add wakeup mechanism for omap-uarts ARM: OMAP2+: UART: Move errata handling from serial.c to omap-serial ARM: OMAP2+: UART: Get context loss count to context restore ARM: OMAP2+: UART: Remove uart reset function. ARM: OMAP2+: UART: Ensure all reg values configured are available from port structure ARM: OMAP2+: UART: Remove context_save and move context restore to driver ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/serial/omap_serial.txt10
-rw-r--r--arch/arm/boot/dts/omap2.dtsi67
-rw-r--r--arch/arm/boot/dts/omap3.dtsi31
-rw-r--r--arch/arm/boot/dts/omap4.dtsi28
-rw-r--r--arch/arm/mach-omap2/Kconfig11
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c100
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c68
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c6
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c68
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c11
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c6
-rw-r--r--arch/arm/mach-omap2/common.c48
-rw-r--r--arch/arm/mach-omap2/common.h23
-rw-r--r--arch/arm/mach-omap2/control.h8
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c6
-rw-r--r--arch/arm/mach-omap2/id.c52
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-omap2/io.c38
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-omap2/opp2xxx.h2
-rw-r--r--arch/arm/mach-omap2/pm24xx.c20
-rw-r--r--arch/arm/mach-omap2/pm34xx.c43
-rw-r--r--arch/arm/mach-omap2/serial.c907
-rw-r--r--arch/arm/plat-omap/Makefile1
-rw-r--r--arch/arm/plat-omap/include/plat/am33xx.h25
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h4
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h56
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h3
-rw-r--r--arch/arm/plat-omap/include/plat/io.h12
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h37
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h2
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h24
-rw-r--r--arch/arm/plat-omap/include/plat/ti81xx.h (renamed from arch/arm/plat-omap/include/plat/ti816x.h)18
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h8
-rw-r--r--drivers/tty/serial/omap-serial.c428
38 files changed, 1066 insertions, 1124 deletions
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
new file mode 100644
index 000000000000..342eedd10050
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -0,0 +1,10 @@
1OMAP UART controller
2
3Required properties:
4- compatible : should be "ti,omap2-uart" for OMAP2 controllers
5- compatible : should be "ti,omap3-uart" for OMAP3 controllers
6- compatible : should be "ti,omap4-uart" for OMAP4 controllers
7- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
8
9Optional properties:
10- clock-frequency : frequency of the clock input to the UART
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
new file mode 100644
index 000000000000..f2ab4ea7cc0e
--- /dev/null
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -0,0 +1,67 @@
1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 };
21
22 cpus {
23 cpu@0 {
24 compatible = "arm,arm1136jf-s";
25 };
26 };
27
28 soc {
29 compatible = "ti,omap-infra";
30 mpu {
31 compatible = "ti,omap2-mpu";
32 ti,hwmods = "mpu";
33 };
34 };
35
36 ocp {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41 ti,hwmods = "l3_main";
42
43 intc: interrupt-controller@1 {
44 compatible = "ti,omap2-intc";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 uart1: serial@4806a000 {
50 compatible = "ti,omap2-uart";
51 ti,hwmods = "uart1";
52 clock-frequency = <48000000>;
53 };
54
55 uart2: serial@4806c000 {
56 compatible = "ti,omap2-uart";
57 ti,hwmods = "uart2";
58 clock-frequency = <48000000>;
59 };
60
61 uart3: serial@4806e000 {
62 compatible = "ti,omap2-uart";
63 ti,hwmods = "uart3";
64 clock-frequency = <48000000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d202bb5ec7ef..216c3317461d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,6 +13,13 @@
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 };
22
16 cpus { 23 cpus {
17 cpu@0 { 24 cpu@0 {
18 compatible = "arm,cortex-a8"; 25 compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
59 interrupt-controller; 66 interrupt-controller;
60 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
61 }; 68 };
69
70 uart1: serial@0x4806a000 {
71 compatible = "ti,omap3-uart";
72 ti,hwmods = "uart1";
73 clock-frequency = <48000000>;
74 };
75
76 uart2: serial@0x4806c000 {
77 compatible = "ti,omap3-uart";
78 ti,hwmods = "uart2";
79 clock-frequency = <48000000>;
80 };
81
82 uart3: serial@0x49020000 {
83 compatible = "ti,omap3-uart";
84 ti,hwmods = "uart3";
85 clock-frequency = <48000000>;
86 };
87
88 uart4: serial@0x49042000 {
89 compatible = "ti,omap3-uart";
90 ti,hwmods = "uart4";
91 clock-frequency = <48000000>;
92 };
62 }; 93 };
63}; 94};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c829043a..e8fe75fac7c5 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -21,6 +21,10 @@
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 22
23 aliases { 23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
24 }; 28 };
25 29
26 cpus { 30 cpus {
@@ -99,5 +103,29 @@
99 reg = <0x48241000 0x1000>, 103 reg = <0x48241000 0x1000>,
100 <0x48240100 0x0100>; 104 <0x48240100 0x0100>;
101 }; 105 };
106
107 uart1: serial@0x4806a000 {
108 compatible = "ti,omap4-uart";
109 ti,hwmods = "uart1";
110 clock-frequency = <48000000>;
111 };
112
113 uart2: serial@0x4806c000 {
114 compatible = "ti,omap4-uart";
115 ti,hwmods = "uart2";
116 clock-frequency = <48000000>;
117 };
118
119 uart3: serial@0x48020000 {
120 compatible = "ti,omap4-uart";
121 ti,hwmods = "uart3";
122 clock-frequency = <48000000>;
123 };
124
125 uart4: serial@0x4806e000 {
126 compatible = "ti,omap4-uart";
127 ti,hwmods = "uart4";
128 clock-frequency = <48000000>;
129 };
102 }; 130 };
103}; 131};
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 50f43942c1aa..a34d0f7d1bfa 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,8 +76,13 @@ config SOC_OMAP3430
76 default y 76 default y
77 select ARCH_OMAP_OTG 77 select ARCH_OMAP_OTG
78 78
79config SOC_OMAPTI816X 79config SOC_OMAPTI81XX
80 bool "TI816X support" 80 bool "TI81XX support"
81 depends on ARCH_OMAP3
82 default y
83
84config SOC_OMAPAM33XX
85 bool "AM33XX support"
81 depends on ARCH_OMAP3 86 depends on ARCH_OMAP3
82 default y 87 default y
83 88
@@ -314,7 +319,7 @@ config MACH_OMAP_3630SDP
314 319
315config MACH_TI8168EVM 320config MACH_TI8168EVM
316 bool "TI8168 Evaluation Module" 321 bool "TI8168 Evaluation Module"
317 depends on SOC_OMAPTI816X 322 depends on SOC_OMAPTI81XX
318 default y 323 default y
319 324
320config MACH_OMAP_4430SDP 325config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 83126368ed99..109b434159f5 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
475static struct omap_board_mux board_mux[] __initdata = { 475static struct omap_board_mux board_mux[] __initdata = {
476 { .reg_offset = OMAP_MUX_TERMINATOR }, 476 { .reg_offset = OMAP_MUX_TERMINATOR },
477}; 477};
478
479static struct omap_device_pad serial1_pads[] __initdata = {
480 /*
481 * Note that off output enable is an active low
482 * signal. So setting this means pin is a
483 * input enabled in off mode
484 */
485 OMAP_MUX_STATIC("uart1_cts.uart1_cts",
486 OMAP_PIN_INPUT |
487 OMAP_PIN_OFF_INPUT_PULLDOWN |
488 OMAP_OFFOUT_EN |
489 OMAP_MUX_MODE0),
490 OMAP_MUX_STATIC("uart1_rts.uart1_rts",
491 OMAP_PIN_OUTPUT |
492 OMAP_OFF_EN |
493 OMAP_MUX_MODE0),
494 OMAP_MUX_STATIC("uart1_rx.uart1_rx",
495 OMAP_PIN_INPUT |
496 OMAP_PIN_OFF_INPUT_PULLDOWN |
497 OMAP_OFFOUT_EN |
498 OMAP_MUX_MODE0),
499 OMAP_MUX_STATIC("uart1_tx.uart1_tx",
500 OMAP_PIN_OUTPUT |
501 OMAP_OFF_EN |
502 OMAP_MUX_MODE0),
503};
504
505static struct omap_device_pad serial2_pads[] __initdata = {
506 OMAP_MUX_STATIC("uart2_cts.uart2_cts",
507 OMAP_PIN_INPUT_PULLUP |
508 OMAP_PIN_OFF_INPUT_PULLDOWN |
509 OMAP_OFFOUT_EN |
510 OMAP_MUX_MODE0),
511 OMAP_MUX_STATIC("uart2_rts.uart2_rts",
512 OMAP_PIN_OUTPUT |
513 OMAP_OFF_EN |
514 OMAP_MUX_MODE0),
515 OMAP_MUX_STATIC("uart2_rx.uart2_rx",
516 OMAP_PIN_INPUT |
517 OMAP_PIN_OFF_INPUT_PULLDOWN |
518 OMAP_OFFOUT_EN |
519 OMAP_MUX_MODE0),
520 OMAP_MUX_STATIC("uart2_tx.uart2_tx",
521 OMAP_PIN_OUTPUT |
522 OMAP_OFF_EN |
523 OMAP_MUX_MODE0),
524};
525
526static struct omap_device_pad serial3_pads[] __initdata = {
527 OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
528 OMAP_PIN_INPUT_PULLDOWN |
529 OMAP_PIN_OFF_INPUT_PULLDOWN |
530 OMAP_OFFOUT_EN |
531 OMAP_MUX_MODE0),
532 OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
533 OMAP_PIN_OUTPUT |
534 OMAP_OFF_EN |
535 OMAP_MUX_MODE0),
536 OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
537 OMAP_PIN_INPUT |
538 OMAP_PIN_OFF_INPUT_PULLDOWN |
539 OMAP_OFFOUT_EN |
540 OMAP_MUX_MODE0),
541 OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
542 OMAP_PIN_OUTPUT |
543 OMAP_OFF_EN |
544 OMAP_MUX_MODE0),
545};
546
547static struct omap_board_data serial1_data __initdata = {
548 .id = 0,
549 .pads = serial1_pads,
550 .pads_cnt = ARRAY_SIZE(serial1_pads),
551};
552
553static struct omap_board_data serial2_data __initdata = {
554 .id = 1,
555 .pads = serial2_pads,
556 .pads_cnt = ARRAY_SIZE(serial2_pads),
557};
558
559static struct omap_board_data serial3_data __initdata = {
560 .id = 2,
561 .pads = serial3_pads,
562 .pads_cnt = ARRAY_SIZE(serial3_pads),
563};
564
565static inline void board_serial_init(void)
566{
567 omap_serial_init_port(&serial1_data);
568 omap_serial_init_port(&serial2_data);
569 omap_serial_init_port(&serial3_data);
570}
571#else 478#else
572#define board_mux NULL 479#define board_mux NULL
573
574static inline void board_serial_init(void)
575{
576 omap_serial_init();
577}
578#endif 480#endif
579 481
580/* 482/*
@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
711 else 613 else
712 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; 614 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
713 omap_ads7846_init(1, gpio_pendown, 310, NULL); 615 omap_ads7846_init(1, gpio_pendown, 310, NULL);
714 board_serial_init(); 616 omap_serial_init();
715 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); 617 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
716 usb_musb_init(NULL); 618 usb_musb_init(NULL);
717 board_smc91x_init(); 619 board_smc91x_init();
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index ef2bbc09428a..5f264fad69bc 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -837,74 +837,8 @@ static struct omap_board_mux board_mux[] __initdata = {
837 { .reg_offset = OMAP_MUX_TERMINATOR }, 837 { .reg_offset = OMAP_MUX_TERMINATOR },
838}; 838};
839 839
840static struct omap_device_pad serial2_pads[] __initdata = {
841 OMAP_MUX_STATIC("uart2_cts.uart2_cts",
842 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
843 OMAP_MUX_STATIC("uart2_rts.uart2_rts",
844 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
845 OMAP_MUX_STATIC("uart2_rx.uart2_rx",
846 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
847 OMAP_MUX_STATIC("uart2_tx.uart2_tx",
848 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
849};
850
851static struct omap_device_pad serial3_pads[] __initdata = {
852 OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
853 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
854 OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
855 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
856 OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
857 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
858 OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
859 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
860};
861
862static struct omap_device_pad serial4_pads[] __initdata = {
863 OMAP_MUX_STATIC("uart4_rx.uart4_rx",
864 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
865 OMAP_MUX_STATIC("uart4_tx.uart4_tx",
866 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
867};
868
869static struct omap_board_data serial2_data __initdata = {
870 .id = 1,
871 .pads = serial2_pads,
872 .pads_cnt = ARRAY_SIZE(serial2_pads),
873};
874
875static struct omap_board_data serial3_data __initdata = {
876 .id = 2,
877 .pads = serial3_pads,
878 .pads_cnt = ARRAY_SIZE(serial3_pads),
879};
880
881static struct omap_board_data serial4_data __initdata = {
882 .id = 3,
883 .pads = serial4_pads,
884 .pads_cnt = ARRAY_SIZE(serial4_pads),
885};
886
887static inline void board_serial_init(void)
888{
889 struct omap_board_data bdata;
890 bdata.flags = 0;
891 bdata.pads = NULL;
892 bdata.pads_cnt = 0;
893 bdata.id = 0;
894 /* pass dummy data for UART1 */
895 omap_serial_init_port(&bdata);
896
897 omap_serial_init_port(&serial2_data);
898 omap_serial_init_port(&serial3_data);
899 omap_serial_init_port(&serial4_data);
900}
901#else 840#else
902#define board_mux NULL 841#define board_mux NULL
903
904static inline void board_serial_init(void)
905{
906 omap_serial_init();
907}
908 #endif 842 #endif
909 843
910static void omap4_sdp4430_wifi_mux_init(void) 844static void omap4_sdp4430_wifi_mux_init(void)
@@ -954,7 +888,7 @@ static void __init omap_4430sdp_init(void)
954 omap4_i2c_init(); 888 omap4_i2c_init();
955 omap_sfh7741prox_init(); 889 omap_sfh7741prox_init();
956 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); 890 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
957 board_serial_init(); 891 omap_serial_init();
958 omap_sdrc_init(NULL, NULL); 892 omap_sdrc_init(NULL, NULL);
959 omap4_sdp4430_wifi_init(); 893 omap4_sdp4430_wifi_init();
960 omap4_twl6030_hsmmc_init(mmc); 894 omap4_twl6030_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 63b54163b993..a508ed5cc890 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -69,7 +69,6 @@ static void __init omap_generic_init(void)
69 if (node) 69 if (node)
70 irq_domain_add_simple(node, 0); 70 irq_domain_add_simple(node, 0);
71 71
72 omap_serial_init();
73 omap_sdrc_init(NULL, NULL); 72 omap_sdrc_init(NULL, NULL);
74 73
75 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); 74 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index bebd3d84365e..118f38c4b37d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -644,15 +644,15 @@ static inline void board_serial_init(void)
644 bdata.pads_cnt = 0; 644 bdata.pads_cnt = 0;
645 645
646 bdata.id = 0; 646 bdata.id = 0;
647 omap_serial_init_port(&bdata); 647 omap_serial_init_port(&bdata, NULL);
648 648
649 bdata.id = 1; 649 bdata.id = 1;
650 omap_serial_init_port(&bdata); 650 omap_serial_init_port(&bdata, NULL);
651 651
652 bdata.id = 2; 652 bdata.id = 2;
653 bdata.pads = serial2_pads; 653 bdata.pads = serial2_pads;
654 bdata.pads_cnt = ARRAY_SIZE(serial2_pads); 654 bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
655 omap_serial_init_port(&bdata); 655 omap_serial_init_port(&bdata, NULL);
656} 656}
657 657
658#else 658#else
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b6f114436dbc..ea45f5835103 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = {
364 { .reg_offset = OMAP_MUX_TERMINATOR }, 364 { .reg_offset = OMAP_MUX_TERMINATOR },
365}; 365};
366 366
367static struct omap_device_pad serial2_pads[] __initdata = {
368 OMAP_MUX_STATIC("uart2_cts.uart2_cts",
369 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
370 OMAP_MUX_STATIC("uart2_rts.uart2_rts",
371 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
372 OMAP_MUX_STATIC("uart2_rx.uart2_rx",
373 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
374 OMAP_MUX_STATIC("uart2_tx.uart2_tx",
375 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
376};
377
378static struct omap_device_pad serial3_pads[] __initdata = {
379 OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
380 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
381 OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
382 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
383 OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
384 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
385 OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
386 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
387};
388
389static struct omap_device_pad serial4_pads[] __initdata = {
390 OMAP_MUX_STATIC("uart4_rx.uart4_rx",
391 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
392 OMAP_MUX_STATIC("uart4_tx.uart4_tx",
393 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
394};
395
396static struct omap_board_data serial2_data __initdata = {
397 .id = 1,
398 .pads = serial2_pads,
399 .pads_cnt = ARRAY_SIZE(serial2_pads),
400};
401
402static struct omap_board_data serial3_data __initdata = {
403 .id = 2,
404 .pads = serial3_pads,
405 .pads_cnt = ARRAY_SIZE(serial3_pads),
406};
407
408static struct omap_board_data serial4_data __initdata = {
409 .id = 3,
410 .pads = serial4_pads,
411 .pads_cnt = ARRAY_SIZE(serial4_pads),
412};
413
414static inline void board_serial_init(void)
415{
416 struct omap_board_data bdata;
417 bdata.flags = 0;
418 bdata.pads = NULL;
419 bdata.pads_cnt = 0;
420 bdata.id = 0;
421 /* pass dummy data for UART1 */
422 omap_serial_init_port(&bdata);
423
424 omap_serial_init_port(&serial2_data);
425 omap_serial_init_port(&serial3_data);
426 omap_serial_init_port(&serial4_data);
427}
428#else 367#else
429#define board_mux NULL 368#define board_mux NULL
430
431static inline void board_serial_init(void)
432{
433 omap_serial_init();
434}
435#endif 369#endif
436 370
437/* Display DVI */ 371/* Display DVI */
@@ -562,7 +496,7 @@ static void __init omap4_panda_init(void)
562 omap4_panda_i2c_init(); 496 omap4_panda_i2c_init();
563 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 497 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
564 platform_device_register(&omap_vwlan_device); 498 platform_device_register(&omap_vwlan_device);
565 board_serial_init(); 499 omap_serial_init();
566 omap_sdrc_init(NULL, NULL); 500 omap_sdrc_init(NULL, NULL);
567 omap4_twl6030_hsmmc_init(mmc); 501 omap4_twl6030_hsmmc_init(mmc);
568 omap4_ehci_init(); 502 omap4_ehci_init();
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 8402b39b2840..b236fcc023ac 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -35,17 +35,12 @@ static void __init ti8168_evm_init(void)
35 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); 35 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
36} 36}
37 37
38static void __init ti8168_evm_map_io(void)
39{
40 omapti816x_map_common_io();
41}
42
43MACHINE_START(TI8168EVM, "ti8168evm") 38MACHINE_START(TI8168EVM, "ti8168evm")
44 /* Maintainer: Texas Instruments */ 39 /* Maintainer: Texas Instruments */
45 .atag_offset = 0x100, 40 .atag_offset = 0x100,
46 .map_io = ti8168_evm_map_io, 41 .map_io = ti81xx_map_io,
47 .init_early = ti816x_init_early, 42 .init_early = ti81xx_init_early,
48 .init_irq = ti816x_init_irq, 43 .init_irq = ti81xx_init_irq,
49 .timer = &omap3_timer, 44 .timer = &omap3_timer,
50 .init_machine = ti8168_evm_init, 45 .init_machine = ti8168_evm_init,
51MACHINE_END 46MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f8d695..f57ed5baeccf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
35#include "cm-regbits-24xx.h" 35#include "cm-regbits-24xx.h"
36#include "cm-regbits-34xx.h" 36#include "cm-regbits-34xx.h"
37 37
38u8 cpu_mask; 38u16 cpu_mask;
39 39
40/* 40/*
41 * clkdm_control: if true, then when a clock is enabled in the 41 * clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2311bc217226..b8c2a686481c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
132 const char *core_ck_name, 132 const char *core_ck_name,
133 const char *mpu_ck_name); 133 const char *mpu_ck_name);
134 134
135extern u8 cpu_mask; 135extern u16 cpu_mask;
136 136
137extern const struct clkops clkops_omap2_dflt_wait; 137extern const struct clkops clkops_omap2_dflt_wait;
138extern const struct clkops clkops_dummy; 138extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 5d0064a4fb5a..60424f41156b 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3517,6 +3517,10 @@ int __init omap3xxx_clk_init(void)
3517 } else if (cpu_is_ti816x()) { 3517 } else if (cpu_is_ti816x()) {
3518 cpu_mask = RATE_IN_TI816X; 3518 cpu_mask = RATE_IN_TI816X;
3519 cpu_clkflg = CK_TI816X; 3519 cpu_clkflg = CK_TI816X;
3520 } else if (cpu_is_am33xx()) {
3521 cpu_mask = RATE_IN_AM33XX;
3522 } else if (cpu_is_ti814x()) {
3523 cpu_mask = RATE_IN_TI814X;
3520 } else if (cpu_is_omap34xx()) { 3524 } else if (cpu_is_omap34xx()) {
3521 if (omap_rev() == OMAP3430_REV_ES1_0) { 3525 if (omap_rev() == OMAP3430_REV_ES1_0) {
3522 cpu_mask = RATE_IN_3430ES1; 3526 cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3604,7 @@ int __init omap3xxx_clk_init(void)
3600 * Lock DPLL5 -- here only until other device init code can 3604 * Lock DPLL5 -- here only until other device init code can
3601 * handle this 3605 * handle this
3602 */ 3606 */
3603 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) 3607 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3604 omap3_clk_lock_dpll5(); 3608 omap3_clk_lock_dpll5();
3605 3609
3606 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ 3610 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 684b8a7cd401..aaf421178c91 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
110 110
111/* 111/*
112 * Adjust TAP register base such that omap3_check_revision accesses the correct 112 * Adjust TAP register base such that omap3_check_revision accesses the correct
113 * TI816X register for checking device ID (it adds 0x204 to tap base while 113 * TI81XX register for checking device ID (it adds 0x204 to tap base while
114 * TI816X DEVICE ID register is at offset 0x600 from control base). 114 * TI81XX DEVICE ID register is at offset 0x600 from control base).
115 */ 115 */
116#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ 116#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
117 TI816X_CONTROL_DEVICE_ID - 0x204) 117 TI81XX_CONTROL_DEVICE_ID - 0x204)
118 118
119static struct omap_globals ti816x_globals = { 119static struct omap_globals ti81xx_globals = {
120 .class = OMAP343X_CLASS, 120 .class = OMAP343X_CLASS,
121 .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), 121 .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
122 .ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE), 122 .ctrl = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
123 .prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE), 123 .prm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
124 .cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE), 124 .cm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
125}; 125};
126 126
127void __init omap2_set_globals_ti816x(void) 127void __init omap2_set_globals_ti81xx(void)
128{ 128{
129 __omap2_set_globals(&ti816x_globals); 129 __omap2_set_globals(&ti81xx_globals);
130}
131
132void __init ti81xx_map_io(void)
133{
134 omapti81xx_map_common_io();
135}
136
137#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \
138 TI81XX_CONTROL_DEVICE_ID - 0x204)
139
140static struct omap_globals am33xx_globals = {
141 .class = AM335X_CLASS,
142 .tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
143 .ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
144 .prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
145 .cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
146};
147
148void __init omap2_set_globals_am33xx(void)
149{
150 __omap2_set_globals(&am33xx_globals);
151}
152
153void __init am33xx_map_io(void)
154{
155 omapam33xx_map_common_io();
130} 156}
131#endif 157#endif
132 158
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0911e843f079..90bd2ae85596 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -54,10 +54,18 @@ static inline void omap34xx_map_common_io(void)
54} 54}
55#endif 55#endif
56 56
57#ifdef CONFIG_SOC_OMAPTI816X 57#ifdef CONFIG_SOC_OMAPTI81XX
58extern void omapti816x_map_common_io(void); 58extern void omapti81xx_map_common_io(void);
59#else 59#else
60static inline void omapti816x_map_common_io(void) 60static inline void omapti81xx_map_common_io(void)
61{
62}
63#endif
64
65#ifdef CONFIG_SOC_OMAPAM33XX
66extern void omapam33xx_map_common_io(void);
67#else
68static inline void omapam33xx_map_common_io(void)
61{ 69{
62} 70}
63#endif 71#endif
@@ -84,7 +92,7 @@ void omap35xx_init_early(void);
84void omap3630_init_early(void); 92void omap3630_init_early(void);
85void omap3_init_early(void); /* Do not use this one */ 93void omap3_init_early(void); /* Do not use this one */
86void am35xx_init_early(void); 94void am35xx_init_early(void);
87void ti816x_init_early(void); 95void ti81xx_init_early(void);
88void omap4430_init_early(void); 96void omap4430_init_early(void);
89 97
90/* 98/*
@@ -108,7 +116,8 @@ void omap2_set_globals_242x(void);
108void omap2_set_globals_243x(void); 116void omap2_set_globals_243x(void);
109void omap2_set_globals_3xxx(void); 117void omap2_set_globals_3xxx(void);
110void omap2_set_globals_443x(void); 118void omap2_set_globals_443x(void);
111void omap2_set_globals_ti816x(void); 119void omap2_set_globals_ti81xx(void);
120void omap2_set_globals_am33xx(void);
112 121
113/* These get called from omap2_set_globals_xxxx(), do not call these */ 122/* These get called from omap2_set_globals_xxxx(), do not call these */
114void omap2_set_globals_tap(struct omap_globals *); 123void omap2_set_globals_tap(struct omap_globals *);
@@ -119,7 +128,9 @@ void omap2_set_globals_prcm(struct omap_globals *);
119void omap242x_map_io(void); 128void omap242x_map_io(void);
120void omap243x_map_io(void); 129void omap243x_map_io(void);
121void omap3_map_io(void); 130void omap3_map_io(void);
131void am33xx_map_io(void);
122void omap4_map_io(void); 132void omap4_map_io(void);
133void ti81xx_map_io(void);
123 134
124/** 135/**
125 * omap_test_timeout - busy-loop, testing a condition 136 * omap_test_timeout - busy-loop, testing a condition
@@ -148,7 +159,7 @@ extern struct device *omap4_get_dsp_device(void);
148 159
149void omap2_init_irq(void); 160void omap2_init_irq(void);
150void omap3_init_irq(void); 161void omap3_init_irq(void);
151void ti816x_init_irq(void); 162void ti81xx_init_irq(void);
152extern int omap_irq_pending(void); 163extern int omap_irq_pending(void);
153void omap_intc_save_context(void); 164void omap_intc_save_context(void);
154void omap_intc_restore_context(void); 165void omap_intc_restore_context(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a382..0ba68d3764bc 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
52#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 52#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
53#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 53#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
54 54
55/* TI816X spefic control submodules */ 55/* TI81XX spefic control submodules */
56#define TI816X_CONTROL_DEVCONF 0x600 56#define TI81XX_CONTROL_DEVCONF 0x600
57 57
58/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 58/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
59 59
@@ -244,8 +244,8 @@
244#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 244#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
245#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 245#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
246 246
247/* TI816X CONTROL_DEVCONF register offsets */ 247/* TI81XX CONTROL_DEVCONF register offsets */
248#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) 248#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
249 249
250/* 250/*
251 * REVISIT: This list of registers is not comprehensive - there are more 251 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 1f71ebb6c12c..464cffde58fe 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -31,7 +31,6 @@
31#include <plat/irqs.h> 31#include <plat/irqs.h>
32#include "powerdomain.h" 32#include "powerdomain.h"
33#include "clockdomain.h" 33#include "clockdomain.h"
34#include <plat/serial.h>
35 34
36#include "pm.h" 35#include "pm.h"
37#include "control.h" 36#include "control.h"
@@ -260,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
260 struct omap3_idle_statedata *cx; 259 struct omap3_idle_statedata *cx;
261 int ret; 260 int ret;
262 261
263 if (!omap3_can_sleep()) {
264 new_state_idx = drv->safe_state_index;
265 goto select_state;
266 }
267
268 /* 262 /*
269 * Prevent idle completely if CAM is active. 263 * Prevent idle completely if CAM is active.
270 * CAM does not have wakeup capability in OMAP3. 264 * CAM does not have wakeup capability in OMAP3.
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 27ad722df637..6c5826605eae 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
226 } 226 }
227} 227}
228 228
229static void __init ti816x_check_features(void) 229static void __init ti81xx_check_features(void)
230{ 230{
231 omap_features = OMAP3_HAS_NEON; 231 omap_features = OMAP3_HAS_NEON;
232} 232}
@@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
340 break; 340 break;
341 } 341 }
342 break; 342 break;
343 case 0xb944:
344 omap_revision = AM335X_REV_ES1_0;
345 *cpu_rev = "1.0";
346 case 0xb8f2:
347 switch (rev) {
348 case 0:
349 /* FALLTHROUGH */
350 case 1:
351 omap_revision = TI8148_REV_ES1_0;
352 *cpu_rev = "1.0";
353 break;
354 case 2:
355 omap_revision = TI8148_REV_ES2_0;
356 *cpu_rev = "2.0";
357 break;
358 case 3:
359 /* FALLTHROUGH */
360 default:
361 omap_revision = TI8148_REV_ES2_1;
362 *cpu_rev = "2.1";
363 break;
364 }
365 break;
343 default: 366 default:
344 /* Unknown default to latest silicon rev as default */ 367 /* Unknown default to latest silicon rev as default */
345 omap_revision = OMAP3630_REV_ES1_2; 368 omap_revision = OMAP3630_REV_ES1_2;
@@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
367 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 390 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
368 * Use ARM register to detect the correct ES version 391 * Use ARM register to detect the correct ES version
369 */ 392 */
370 if (!rev && (hawkeye != 0xb94e)) { 393 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
371 idcode = read_cpuid(CPUID_ID); 394 idcode = read_cpuid(CPUID_ID);
372 rev = (idcode & 0xf) - 1; 395 rev = (idcode & 0xf) - 1;
373 } 396 }
@@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
389 omap_revision = OMAP4430_REV_ES2_1; 412 omap_revision = OMAP4430_REV_ES2_1;
390 break; 413 break;
391 case 4: 414 case 4:
392 default:
393 omap_revision = OMAP4430_REV_ES2_2; 415 omap_revision = OMAP4430_REV_ES2_2;
416 break;
417 case 6:
418 default:
419 omap_revision = OMAP4430_REV_ES2_3;
394 } 420 }
395 break; 421 break;
396 case 0xb94e: 422 case 0xb94e:
@@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
401 break; 427 break;
402 } 428 }
403 break; 429 break;
430 case 0xb975:
431 switch (rev) {
432 case 0:
433 default:
434 omap_revision = OMAP4470_REV_ES1_0;
435 break;
436 }
437 break;
404 default: 438 default:
405 /* Unknown default to latest silicon rev as default */ 439 /* Unknown default to latest silicon rev as default */
406 omap_revision = OMAP4430_REV_ES2_2; 440 omap_revision = OMAP4430_REV_ES2_3;
407 } 441 }
408 442
409 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, 443 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
432 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 466 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
433 } else if (cpu_is_ti816x()) { 467 } else if (cpu_is_ti816x()) {
434 cpu_name = "TI816X"; 468 cpu_name = "TI816X";
469 } else if (cpu_is_am335x()) {
470 cpu_name = "AM335X";
471 } else if (cpu_is_ti814x()) {
472 cpu_name = "TI814X";
435 } else if (omap3_has_iva() && omap3_has_sgx()) { 473 } else if (omap3_has_iva() && omap3_has_sgx()) {
436 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 474 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
437 cpu_name = "OMAP3430/3530"; 475 cpu_name = "OMAP3430/3530";
@@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
472 } else if (cpu_is_omap34xx()) { 510 } else if (cpu_is_omap34xx()) {
473 omap3_check_revision(&cpu_rev); 511 omap3_check_revision(&cpu_rev);
474 512
475 /* TI816X doesn't have feature register */ 513 /* TI81XX doesn't have feature register */
476 if (!cpu_is_ti816x()) 514 if (!cpu_is_ti81xx())
477 omap3_check_features(); 515 omap3_check_features();
478 else 516 else
479 ti816x_check_features(); 517 ti81xx_check_features();
480 518
481 omap3_cpuinfo(cpu_rev); 519 omap3_cpuinfo(cpu_rev);
482 return; 520 return;
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 13f98e59cfef..cdfc2a1f0e75 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -66,11 +66,11 @@ omap_uart_lsr: .word 0
66 beq 34f @ configure OMAP3UART4 66 beq 34f @ configure OMAP3UART4
67 cmp \rp, #OMAP4UART4 @ only on 44xx 67 cmp \rp, #OMAP4UART4 @ only on 44xx
68 beq 44f @ configure OMAP4UART4 68 beq 44f @ configure OMAP4UART4
69 cmp \rp, #TI816XUART1 @ ti816x UART offsets different 69 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
70 beq 81f @ configure UART1 70 beq 81f @ configure UART1
71 cmp \rp, #TI816XUART2 @ ti816x UART offsets different 71 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
72 beq 82f @ configure UART2 72 beq 82f @ configure UART2
73 cmp \rp, #TI816XUART3 @ ti816x UART offsets different 73 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
74 beq 83f @ configure UART3 74 beq 83f @ configure UART3
75 cmp \rp, #ZOOM_UART @ only on zoom2/3 75 cmp \rp, #ZOOM_UART @ only on zoom2/3
76 beq 95f @ configure ZOOM_UART 76 beq 95f @ configure ZOOM_UART
@@ -94,11 +94,11 @@ omap_uart_lsr: .word 0
94 b 98f 94 b 98f
9544: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) 9544: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
96 b 98f 96 b 98f
9781: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) 9781: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
98 b 98f 98 b 98f
9982: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) 9982: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
100 b 98f 100 b 98f
10183: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) 10183: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
102 b 98f 102 b 98f
103 103
10495: ldr \rp, =ZOOM_UART_BASE 10495: ldr \rp, =ZOOM_UART_BASE
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 65843390e7f0..3f174d51f67f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
176}; 176};
177#endif 177#endif
178 178
179#ifdef CONFIG_SOC_OMAPTI816X 179#ifdef CONFIG_SOC_OMAPTI81XX
180static struct map_desc omapti816x_io_desc[] __initdata = { 180static struct map_desc omapti81xx_io_desc[] __initdata = {
181 {
182 .virtual = L4_34XX_VIRT,
183 .pfn = __phys_to_pfn(L4_34XX_PHYS),
184 .length = L4_34XX_SIZE,
185 .type = MT_DEVICE
186 }
187};
188#endif
189
190#ifdef CONFIG_SOC_OMAPAM33XX
191static struct map_desc omapam33xx_io_desc[] __initdata = {
181 { 192 {
182 .virtual = L4_34XX_VIRT, 193 .virtual = L4_34XX_VIRT,
183 .pfn = __phys_to_pfn(L4_34XX_PHYS), 194 .pfn = __phys_to_pfn(L4_34XX_PHYS),
184 .length = L4_34XX_SIZE, 195 .length = L4_34XX_SIZE,
185 .type = MT_DEVICE 196 .type = MT_DEVICE
186 }, 197 },
198 {
199 .virtual = L4_WK_AM33XX_VIRT,
200 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
201 .length = L4_WK_AM33XX_SIZE,
202 .type = MT_DEVICE
203 }
187}; 204};
188#endif 205#endif
189 206
@@ -272,10 +289,17 @@ void __init omap34xx_map_common_io(void)
272} 289}
273#endif 290#endif
274 291
275#ifdef CONFIG_SOC_OMAPTI816X 292#ifdef CONFIG_SOC_OMAPTI81XX
276void __init omapti816x_map_common_io(void) 293void __init omapti81xx_map_common_io(void)
294{
295 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
296}
297#endif
298
299#ifdef CONFIG_SOC_OMAPAM33XX
300void __init omapam33xx_map_common_io(void)
277{ 301{
278 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); 302 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
279} 303}
280#endif 304#endif
281 305
@@ -427,9 +451,9 @@ void __init am35xx_init_early(void)
427 omap3_init_early(); 451 omap3_init_early();
428} 452}
429 453
430void __init ti816x_init_early(void) 454void __init ti81xx_init_early(void)
431{ 455{
432 omap2_set_globals_ti816x(); 456 omap2_set_globals_ti81xx();
433 omap_common_init_early(); 457 omap_common_init_early();
434 omap3xxx_voltagedomains_init(); 458 omap3xxx_voltagedomains_init();
435 omap3xxx_powerdomains_init(); 459 omap3xxx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 42b1d6591912..1fef061f7927 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -193,7 +193,7 @@ void __init omap3_init_irq(void)
193 omap_init_irq(OMAP34XX_IC_BASE, 96); 193 omap_init_irq(OMAP34XX_IC_BASE, 96);
194} 194}
195 195
196void __init ti816x_init_irq(void) 196void __init ti81xx_init_irq(void)
197{ 197{
198 omap_init_irq(OMAP34XX_IC_BASE, 128); 198 omap_init_irq(OMAP34XX_IC_BASE, 128);
199} 199}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66a92c2..8fae534eb157 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
51 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 51 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
52 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 52 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
53 unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 53 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
54 unsigned char flags; 54 unsigned short flags;
55}; 55};
56 56
57 57
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index ef8595c80296..b8822f8b2891 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -30,7 +30,6 @@
30#include <linux/irq.h> 30#include <linux/irq.h>
31#include <linux/time.h> 31#include <linux/time.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/console.h>
34 33
35#include <asm/mach/time.h> 34#include <asm/mach/time.h>
36#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
@@ -127,27 +126,11 @@ static void omap2_enter_full_retention(void)
127 if (omap_irq_pending()) 126 if (omap_irq_pending())
128 goto no_sleep; 127 goto no_sleep;
129 128
130 /* Block console output in case it is on one of the OMAP UARTs */
131 if (!is_suspending())
132 if (!console_trylock())
133 goto no_sleep;
134
135 omap_uart_prepare_idle(0);
136 omap_uart_prepare_idle(1);
137 omap_uart_prepare_idle(2);
138
139 /* Jump to SRAM suspend code */ 129 /* Jump to SRAM suspend code */
140 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), 130 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
141 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), 131 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
142 OMAP_SDRC_REGADDR(SDRC_POWER)); 132 OMAP_SDRC_REGADDR(SDRC_POWER));
143 133
144 omap_uart_resume_idle(2);
145 omap_uart_resume_idle(1);
146 omap_uart_resume_idle(0);
147
148 if (!is_suspending())
149 console_unlock();
150
151no_sleep: 134no_sleep:
152 omap2_gpio_resume_after_idle(); 135 omap2_gpio_resume_after_idle();
153 136
@@ -239,8 +222,6 @@ static int omap2_can_sleep(void)
239{ 222{
240 if (omap2_fclks_active()) 223 if (omap2_fclks_active())
241 return 0; 224 return 0;
242 if (!omap_uart_can_sleep())
243 return 0;
244 if (osc_ck->usecount > 1) 225 if (osc_ck->usecount > 1)
245 return 0; 226 return 0;
246 if (omap_dma_running()) 227 if (omap_dma_running())
@@ -291,7 +272,6 @@ static int omap2_pm_suspend(void)
291 mir1 = omap_readl(0x480fe0a4); 272 mir1 = omap_readl(0x480fe0a4);
292 omap_writel(1 << 5, 0x480fe0ac); 273 omap_writel(1 << 5, 0x480fe0ac);
293 274
294 omap_uart_prepare_suspend();
295 omap2_enter_full_retention(); 275 omap2_enter_full_retention();
296 276
297 omap_writel(mir1, 0x480fe0a4); 277 omap_writel(mir1, 0x480fe0a4);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 53b5b1a71e0e..fc6987578920 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,7 +28,6 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/console.h>
32#include <trace/events/power.h> 31#include <trace/events/power.h>
33 32
34#include <asm/suspend.h> 33#include <asm/suspend.h>
@@ -36,7 +35,6 @@
36#include <plat/sram.h> 35#include <plat/sram.h>
37#include "clockdomain.h" 36#include "clockdomain.h"
38#include "powerdomain.h" 37#include "powerdomain.h"
39#include <plat/serial.h>
40#include <plat/sdrc.h> 38#include <plat/sdrc.h>
41#include <plat/prcm.h> 39#include <plat/prcm.h>
42#include <plat/gpmc.h> 40#include <plat/gpmc.h>
@@ -54,15 +52,6 @@
54 52
55#ifdef CONFIG_SUSPEND 53#ifdef CONFIG_SUSPEND
56static suspend_state_t suspend_state = PM_SUSPEND_ON; 54static suspend_state_t suspend_state = PM_SUSPEND_ON;
57static inline bool is_suspending(void)
58{
59 return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
60}
61#else
62static inline bool is_suspending(void)
63{
64 return false;
65}
66#endif 55#endif
67 56
68/* pm34xx errata defined in pm.h */ 57/* pm34xx errata defined in pm.h */
@@ -337,20 +326,11 @@ void omap_sram_idle(void)
337 omap3_enable_io_chain(); 326 omap3_enable_io_chain();
338 } 327 }
339 328
340 /* Block console output in case it is on one of the OMAP UARTs */
341 if (!is_suspending())
342 if (per_next_state < PWRDM_POWER_ON ||
343 core_next_state < PWRDM_POWER_ON)
344 if (!console_trylock())
345 goto console_still_active;
346
347 pwrdm_pre_transition(); 329 pwrdm_pre_transition();
348 330
349 /* PER */ 331 /* PER */
350 if (per_next_state < PWRDM_POWER_ON) { 332 if (per_next_state < PWRDM_POWER_ON) {
351 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 333 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
352 omap_uart_prepare_idle(2);
353 omap_uart_prepare_idle(3);
354 omap2_gpio_prepare_for_idle(per_going_off); 334 omap2_gpio_prepare_for_idle(per_going_off);
355 if (per_next_state == PWRDM_POWER_OFF) 335 if (per_next_state == PWRDM_POWER_OFF)
356 omap3_per_save_context(); 336 omap3_per_save_context();
@@ -358,8 +338,6 @@ void omap_sram_idle(void)
358 338
359 /* CORE */ 339 /* CORE */
360 if (core_next_state < PWRDM_POWER_ON) { 340 if (core_next_state < PWRDM_POWER_ON) {
361 omap_uart_prepare_idle(0);
362 omap_uart_prepare_idle(1);
363 if (core_next_state == PWRDM_POWER_OFF) { 341 if (core_next_state == PWRDM_POWER_OFF) {
364 omap3_core_save_context(); 342 omap3_core_save_context();
365 omap3_cm_save_context(); 343 omap3_cm_save_context();
@@ -408,8 +386,6 @@ void omap_sram_idle(void)
408 omap3_sram_restore_context(); 386 omap3_sram_restore_context();
409 omap2_sms_restore_context(); 387 omap2_sms_restore_context();
410 } 388 }
411 omap_uart_resume_idle(0);
412 omap_uart_resume_idle(1);
413 if (core_next_state == PWRDM_POWER_OFF) 389 if (core_next_state == PWRDM_POWER_OFF)
414 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 390 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
415 OMAP3430_GR_MOD, 391 OMAP3430_GR_MOD,
@@ -425,14 +401,8 @@ void omap_sram_idle(void)
425 omap2_gpio_resume_after_idle(); 401 omap2_gpio_resume_after_idle();
426 if (per_prev_state == PWRDM_POWER_OFF) 402 if (per_prev_state == PWRDM_POWER_OFF)
427 omap3_per_restore_context(); 403 omap3_per_restore_context();
428 omap_uart_resume_idle(2);
429 omap_uart_resume_idle(3);
430 } 404 }
431 405
432 if (!is_suspending())
433 console_unlock();
434
435console_still_active:
436 /* Disable IO-PAD and IO-CHAIN wakeup */ 406 /* Disable IO-PAD and IO-CHAIN wakeup */
437 if (omap3_has_io_wakeup() && 407 if (omap3_has_io_wakeup() &&
438 (per_next_state < PWRDM_POWER_ON || 408 (per_next_state < PWRDM_POWER_ON ||
@@ -446,21 +416,11 @@ console_still_active:
446 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 416 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
447} 417}
448 418
449int omap3_can_sleep(void)
450{
451 if (!omap_uart_can_sleep())
452 return 0;
453 return 1;
454}
455
456static void omap3_pm_idle(void) 419static void omap3_pm_idle(void)
457{ 420{
458 local_irq_disable(); 421 local_irq_disable();
459 local_fiq_disable(); 422 local_fiq_disable();
460 423
461 if (!omap3_can_sleep())
462 goto out;
463
464 if (omap_irq_pending() || need_resched()) 424 if (omap_irq_pending() || need_resched())
465 goto out; 425 goto out;
466 426
@@ -494,7 +454,6 @@ static int omap3_pm_suspend(void)
494 goto restore; 454 goto restore;
495 } 455 }
496 456
497 omap_uart_prepare_suspend();
498 omap3_intc_suspend(); 457 omap3_intc_suspend();
499 458
500 omap_sram_idle(); 459 omap_sram_idle();
@@ -541,7 +500,6 @@ static int omap3_pm_begin(suspend_state_t state)
541{ 500{
542 disable_hlt(); 501 disable_hlt();
543 suspend_state = state; 502 suspend_state = state;
544 omap_uart_enable_irqs(0);
545 omap_prcm_irq_prepare(); 503 omap_prcm_irq_prepare();
546 return 0; 504 return 0;
547} 505}
@@ -549,7 +507,6 @@ static int omap3_pm_begin(suspend_state_t state)
549static void omap3_pm_end(void) 507static void omap3_pm_end(void)
550{ 508{
551 suspend_state = PM_SUSPEND_ON; 509 suspend_state = PM_SUSPEND_ON;
552 omap_uart_enable_irqs(1);
553 enable_hlt(); 510 enable_hlt();
554 return; 511 return;
555} 512}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 42c326732a29..247d89478f24 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,26 +19,21 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/serial_reg.h>
23#include <linux/clk.h> 22#include <linux/clk.h>
24#include <linux/io.h> 23#include <linux/io.h>
25#include <linux/delay.h> 24#include <linux/delay.h>
26#include <linux/platform_device.h> 25#include <linux/platform_device.h>
27#include <linux/slab.h> 26#include <linux/slab.h>
28#include <linux/serial_8250.h>
29#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
30#include <linux/console.h> 28#include <linux/console.h>
31 29
32#ifdef CONFIG_SERIAL_OMAP
33#include <plat/omap-serial.h> 30#include <plat/omap-serial.h>
34#endif
35
36#include "common.h" 31#include "common.h"
37#include <plat/board.h> 32#include <plat/board.h>
38#include <plat/clock.h>
39#include <plat/dma.h> 33#include <plat/dma.h>
40#include <plat/omap_hwmod.h> 34#include <plat/omap_hwmod.h>
41#include <plat/omap_device.h> 35#include <plat/omap_device.h>
36#include <plat/omap-pm.h>
42 37
43#include "prm2xxx_3xxx.h" 38#include "prm2xxx_3xxx.h"
44#include "pm.h" 39#include "pm.h"
@@ -47,603 +42,226 @@
47#include "control.h" 42#include "control.h"
48#include "mux.h" 43#include "mux.h"
49 44
50#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
51#define UART_OMAP_WER 0x17 /* Wake-up enable register */
52
53#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
54#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
55
56/* 45/*
57 * NOTE: By default the serial timeout is disabled as it causes lost characters 46 * NOTE: By default the serial auto_suspend timeout is disabled as it causes
58 * over the serial ports. This means that the UART clocks will stay on until 47 * lost characters over the serial ports. This means that the UART clocks will
59 * disabled via sysfs. This also causes that any deeper omap sleep states are 48 * stay on until power/autosuspend_delay is set for the uart from sysfs.
60 * blocked. 49 * This also causes that any deeper omap sleep states are blocked.
61 */ 50 */
62#define DEFAULT_TIMEOUT 0 51#define DEFAULT_AUTOSUSPEND_DELAY -1
63 52
64#define MAX_UART_HWMOD_NAME_LEN 16 53#define MAX_UART_HWMOD_NAME_LEN 16
65 54
66struct omap_uart_state { 55struct omap_uart_state {
67 int num; 56 int num;
68 int can_sleep; 57 int can_sleep;
69 struct timer_list timer;
70 u32 timeout;
71
72 void __iomem *wk_st;
73 void __iomem *wk_en;
74 u32 wk_mask;
75 u32 padconf;
76 u32 dma_enabled;
77
78 struct clk *ick;
79 struct clk *fck;
80 int clocked;
81
82 int irq;
83 int regshift;
84 int irqflags;
85 void __iomem *membase;
86 resource_size_t mapbase;
87 58
88 struct list_head node; 59 struct list_head node;
89 struct omap_hwmod *oh; 60 struct omap_hwmod *oh;
90 struct platform_device *pdev; 61 struct platform_device *pdev;
91
92 u32 errata;
93#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
94 int context_valid;
95
96 /* Registers to be saved/restored for OFF-mode */
97 u16 dll;
98 u16 dlh;
99 u16 ier;
100 u16 sysc;
101 u16 scr;
102 u16 wer;
103 u16 mcr;
104#endif
105}; 62};
106 63
107static LIST_HEAD(uart_list); 64static LIST_HEAD(uart_list);
108static u8 num_uarts; 65static u8 num_uarts;
66static u8 console_uart_id = -1;
67static u8 no_console_suspend;
68static u8 uart_debug;
69
70#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
71#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
72#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
73
74static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
75 {
76 .dma_enabled = false,
77 .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
78 .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
79 .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
80 .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
81 },
82};
109 83
110static inline unsigned int __serial_read_reg(struct uart_port *up, 84#ifdef CONFIG_PM
111 int offset) 85static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
112{
113 offset <<= up->regshift;
114 return (unsigned int)__raw_readb(up->membase + offset);
115}
116
117static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
118 int offset)
119{ 86{
120 offset <<= uart->regshift; 87 struct omap_device *od = to_omap_device(pdev);
121 return (unsigned int)__raw_readb(uart->membase + offset);
122}
123 88
124static inline void __serial_write_reg(struct uart_port *up, int offset, 89 if (!od)
125 int value) 90 return;
126{
127 offset <<= up->regshift;
128 __raw_writeb(value, up->membase + offset);
129}
130 91
131static inline void serial_write_reg(struct omap_uart_state *uart, int offset, 92 if (enable)
132 int value) 93 omap_hwmod_enable_wakeup(od->hwmods[0]);
133{ 94 else
134 offset <<= uart->regshift; 95 omap_hwmod_disable_wakeup(od->hwmods[0]);
135 __raw_writeb(value, uart->membase + offset);
136} 96}
137 97
138/* 98/*
139 * Internal UARTs need to be initialized for the 8250 autoconfig to work 99 * Errata i291: [UART]:Cannot Acknowledge Idle Requests
140 * properly. Note that the TX watermark initialization may not be needed 100 * in Smartidle Mode When Configured for DMA Operations.
141 * once the 8250.c watermark handling code is merged. 101 * WA: configure uart in force idle mode.
142 */ 102 */
143 103static void omap_uart_set_noidle(struct platform_device *pdev)
144static inline void __init omap_uart_reset(struct omap_uart_state *uart)
145{ 104{
146 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 105 struct omap_device *od = to_omap_device(pdev);
147 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
148 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
149}
150
151#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
152 106
153/* 107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
154 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
155 * The access to uart register after MDR1 Access
156 * causes UART to corrupt data.
157 *
158 * Need a delay =
159 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
160 * give 10 times as much
161 */
162static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
163 u8 fcr_val)
164{
165 u8 timeout = 255;
166
167 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
168 udelay(2);
169 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
170 UART_FCR_CLEAR_RCVR);
171 /*
172 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
173 * TX_FIFO_E bit is 1.
174 */
175 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
176 (UART_LSR_THRE | UART_LSR_DR))) {
177 timeout--;
178 if (!timeout) {
179 /* Should *never* happen. we warn and carry on */
180 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
181 serial_read_reg(uart, UART_LSR));
182 break;
183 }
184 udelay(1);
185 }
186} 108}
187 109
188static void omap_uart_save_context(struct omap_uart_state *uart) 110static void omap_uart_set_forceidle(struct platform_device *pdev)
189{ 111{
190 u16 lcr = 0; 112 struct omap_device *od = to_omap_device(pdev);
191 113
192 if (!enable_off_mode) 114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
193 return;
194
195 lcr = serial_read_reg(uart, UART_LCR);
196 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
197 uart->dll = serial_read_reg(uart, UART_DLL);
198 uart->dlh = serial_read_reg(uart, UART_DLM);
199 serial_write_reg(uart, UART_LCR, lcr);
200 uart->ier = serial_read_reg(uart, UART_IER);
201 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
202 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
203 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
204 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
205 uart->mcr = serial_read_reg(uart, UART_MCR);
206 serial_write_reg(uart, UART_LCR, lcr);
207
208 uart->context_valid = 1;
209} 115}
210 116
211static void omap_uart_restore_context(struct omap_uart_state *uart)
212{
213 u16 efr = 0;
214
215 if (!enable_off_mode)
216 return;
217
218 if (!uart->context_valid)
219 return;
220
221 uart->context_valid = 0;
222
223 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
224 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
225 else
226 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
227
228 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
229 efr = serial_read_reg(uart, UART_EFR);
230 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
231 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
232 serial_write_reg(uart, UART_IER, 0x0);
233 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
234 serial_write_reg(uart, UART_DLL, uart->dll);
235 serial_write_reg(uart, UART_DLM, uart->dlh);
236 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
237 serial_write_reg(uart, UART_IER, uart->ier);
238 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
239 serial_write_reg(uart, UART_MCR, uart->mcr);
240 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
241 serial_write_reg(uart, UART_EFR, efr);
242 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
243 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
244 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
245 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
246
247 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
248 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
249 else
250 /* UART 16x mode */
251 serial_write_reg(uart, UART_OMAP_MDR1,
252 UART_OMAP_MDR1_16X_MODE);
253}
254#else 117#else
255static inline void omap_uart_save_context(struct omap_uart_state *uart) {} 118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
256static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} 119{}
257#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ 120static void omap_uart_set_noidle(struct platform_device *pdev) {}
258 121static void omap_uart_set_forceidle(struct platform_device *pdev) {}
259static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) 122#endif /* CONFIG_PM */
260{
261 if (uart->clocked)
262 return;
263
264 omap_device_enable(uart->pdev);
265 uart->clocked = 1;
266 omap_uart_restore_context(uart);
267}
268
269#ifdef CONFIG_PM
270
271static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
272{
273 if (!uart->clocked)
274 return;
275
276 omap_uart_save_context(uart);
277 uart->clocked = 0;
278 omap_device_idle(uart->pdev);
279}
280
281static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
282{
283 /* Set wake-enable bit */
284 if (uart->wk_en && uart->wk_mask) {
285 u32 v = __raw_readl(uart->wk_en);
286 v |= uart->wk_mask;
287 __raw_writel(v, uart->wk_en);
288 }
289
290 /* Ensure IOPAD wake-enables are set */
291 if (cpu_is_omap34xx() && uart->padconf) {
292 u16 v = omap_ctrl_readw(uart->padconf);
293 v |= OMAP3_PADCONF_WAKEUPENABLE0;
294 omap_ctrl_writew(v, uart->padconf);
295 }
296}
297
298static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
299{
300 /* Clear wake-enable bit */
301 if (uart->wk_en && uart->wk_mask) {
302 u32 v = __raw_readl(uart->wk_en);
303 v &= ~uart->wk_mask;
304 __raw_writel(v, uart->wk_en);
305 }
306
307 /* Ensure IOPAD wake-enables are cleared */
308 if (cpu_is_omap34xx() && uart->padconf) {
309 u16 v = omap_ctrl_readw(uart->padconf);
310 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
311 omap_ctrl_writew(v, uart->padconf);
312 }
313}
314
315static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
316 int enable)
317{
318 u8 idlemode;
319
320 if (enable) {
321 /**
322 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
323 * in Smartidle Mode When Configured for DMA Operations.
324 */
325 if (uart->dma_enabled)
326 idlemode = HWMOD_IDLEMODE_FORCE;
327 else
328 idlemode = HWMOD_IDLEMODE_SMART;
329 } else {
330 idlemode = HWMOD_IDLEMODE_NO;
331 }
332
333 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
334}
335
336static void omap_uart_block_sleep(struct omap_uart_state *uart)
337{
338 omap_uart_enable_clocks(uart);
339
340 omap_uart_smart_idle_enable(uart, 0);
341 uart->can_sleep = 0;
342 if (uart->timeout)
343 mod_timer(&uart->timer, jiffies + uart->timeout);
344 else
345 del_timer(&uart->timer);
346}
347
348static void omap_uart_allow_sleep(struct omap_uart_state *uart)
349{
350 if (device_may_wakeup(&uart->pdev->dev))
351 omap_uart_enable_wakeup(uart);
352 else
353 omap_uart_disable_wakeup(uart);
354
355 if (!uart->clocked)
356 return;
357
358 omap_uart_smart_idle_enable(uart, 1);
359 uart->can_sleep = 1;
360 del_timer(&uart->timer);
361}
362
363static void omap_uart_idle_timer(unsigned long data)
364{
365 struct omap_uart_state *uart = (struct omap_uart_state *)data;
366
367 omap_uart_allow_sleep(uart);
368}
369
370void omap_uart_prepare_idle(int num)
371{
372 struct omap_uart_state *uart;
373
374 list_for_each_entry(uart, &uart_list, node) {
375 if (num == uart->num && uart->can_sleep) {
376 omap_uart_disable_clocks(uart);
377 return;
378 }
379 }
380}
381
382void omap_uart_resume_idle(int num)
383{
384 struct omap_uart_state *uart;
385
386 list_for_each_entry(uart, &uart_list, node) {
387 if (num == uart->num && uart->can_sleep) {
388 omap_uart_enable_clocks(uart);
389
390 /* Check for IO pad wakeup */
391 if (cpu_is_omap34xx() && uart->padconf) {
392 u16 p = omap_ctrl_readw(uart->padconf);
393
394 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
395 omap_uart_block_sleep(uart);
396 }
397
398 /* Check for normal UART wakeup */
399 if (__raw_readl(uart->wk_st) & uart->wk_mask)
400 omap_uart_block_sleep(uart);
401 return;
402 }
403 }
404}
405
406void omap_uart_prepare_suspend(void)
407{
408 struct omap_uart_state *uart;
409
410 list_for_each_entry(uart, &uart_list, node) {
411 omap_uart_allow_sleep(uart);
412 }
413}
414
415int omap_uart_can_sleep(void)
416{
417 struct omap_uart_state *uart;
418 int can_sleep = 1;
419
420 list_for_each_entry(uart, &uart_list, node) {
421 if (!uart->clocked)
422 continue;
423
424 if (!uart->can_sleep) {
425 can_sleep = 0;
426 continue;
427 }
428
429 /* This UART can now safely sleep. */
430 omap_uart_allow_sleep(uart);
431 }
432
433 return can_sleep;
434}
435 123
436/** 124#ifdef CONFIG_OMAP_MUX
437 * omap_uart_interrupt() 125static struct omap_device_pad default_uart1_pads[] __initdata = {
438 * 126 {
439 * This handler is used only to detect that *any* UART interrupt has 127 .name = "uart1_cts.uart1_cts",
440 * occurred. It does _nothing_ to handle the interrupt. Rather, 128 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
441 * any UART interrupt will trigger the inactivity timer so the 129 },
442 * UART will not idle or sleep for its timeout period. 130 {
443 * 131 .name = "uart1_rts.uart1_rts",
444 **/ 132 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
445/* static int first_interrupt; */ 133 },
446static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) 134 {
447{ 135 .name = "uart1_tx.uart1_tx",
448 struct omap_uart_state *uart = dev_id; 136 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
137 },
138 {
139 .name = "uart1_rx.uart1_rx",
140 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
141 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
142 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
143 },
144};
449 145
450 omap_uart_block_sleep(uart); 146static struct omap_device_pad default_uart2_pads[] __initdata = {
147 {
148 .name = "uart2_cts.uart2_cts",
149 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
150 },
151 {
152 .name = "uart2_rts.uart2_rts",
153 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
154 },
155 {
156 .name = "uart2_tx.uart2_tx",
157 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
158 },
159 {
160 .name = "uart2_rx.uart2_rx",
161 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
162 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
163 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
164 },
165};
451 166
452 return IRQ_NONE; 167static struct omap_device_pad default_uart3_pads[] __initdata = {
453} 168 {
169 .name = "uart3_cts_rctx.uart3_cts_rctx",
170 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
171 },
172 {
173 .name = "uart3_rts_sd.uart3_rts_sd",
174 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
175 },
176 {
177 .name = "uart3_tx_irtx.uart3_tx_irtx",
178 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
179 },
180 {
181 .name = "uart3_rx_irrx.uart3_rx_irrx",
182 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
183 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
184 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
185 },
186};
454 187
455static void omap_uart_idle_init(struct omap_uart_state *uart) 188static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
456{ 189 {
457 int ret; 190 .name = "gpmc_wait2.uart4_tx",
458 191 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
459 uart->can_sleep = 0; 192 },
460 uart->timeout = DEFAULT_TIMEOUT; 193 {
461 setup_timer(&uart->timer, omap_uart_idle_timer, 194 .name = "gpmc_wait3.uart4_rx",
462 (unsigned long) uart); 195 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
463 if (uart->timeout) 196 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
464 mod_timer(&uart->timer, jiffies + uart->timeout); 197 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
465 omap_uart_smart_idle_enable(uart, 0); 198 },
466 199};
467 if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
468 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
469 u32 wk_mask = 0;
470 u32 padconf = 0;
471
472 /* XXX These PRM accesses do not belong here */
473 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
474 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
475 switch (uart->num) {
476 case 0:
477 wk_mask = OMAP3430_ST_UART1_MASK;
478 padconf = 0x182;
479 break;
480 case 1:
481 wk_mask = OMAP3430_ST_UART2_MASK;
482 padconf = 0x17a;
483 break;
484 case 2:
485 wk_mask = OMAP3430_ST_UART3_MASK;
486 padconf = 0x19e;
487 break;
488 case 3:
489 wk_mask = OMAP3630_ST_UART4_MASK;
490 padconf = 0x0d2;
491 break;
492 }
493 uart->wk_mask = wk_mask;
494 uart->padconf = padconf;
495 } else if (cpu_is_omap24xx()) {
496 u32 wk_mask = 0;
497 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
498
499 switch (uart->num) {
500 case 0:
501 wk_mask = OMAP24XX_ST_UART1_MASK;
502 break;
503 case 1:
504 wk_mask = OMAP24XX_ST_UART2_MASK;
505 break;
506 case 2:
507 wk_en = OMAP24XX_PM_WKEN2;
508 wk_st = OMAP24XX_PM_WKST2;
509 wk_mask = OMAP24XX_ST_UART3_MASK;
510 break;
511 }
512 uart->wk_mask = wk_mask;
513 if (cpu_is_omap2430()) {
514 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
515 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
516 } else if (cpu_is_omap2420()) {
517 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
518 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
519 }
520 } else {
521 uart->wk_en = NULL;
522 uart->wk_st = NULL;
523 uart->wk_mask = 0;
524 uart->padconf = 0;
525 }
526 200
527 uart->irqflags |= IRQF_SHARED; 201static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
528 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, 202 {
529 IRQF_SHARED, "serial idle", (void *)uart); 203 .name = "uart4_tx.uart4_tx",
530 WARN_ON(ret); 204 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
531} 205 },
206 {
207 .name = "uart4_rx.uart4_rx",
208 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
209 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
210 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
211 },
212};
532 213
533void omap_uart_enable_irqs(int enable) 214static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
534{ 215{
535 int ret; 216 switch (bdata->id) {
536 struct omap_uart_state *uart; 217 case 0:
537 218 bdata->pads = default_uart1_pads;
538 list_for_each_entry(uart, &uart_list, node) { 219 bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
539 if (enable) { 220 break;
540 pm_runtime_put_sync(&uart->pdev->dev); 221 case 1:
541 ret = request_threaded_irq(uart->irq, NULL, 222 bdata->pads = default_uart2_pads;
542 omap_uart_interrupt, 223 bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
543 IRQF_SHARED, 224 break;
544 "serial idle", 225 case 2:
545 (void *)uart); 226 bdata->pads = default_uart3_pads;
546 } else { 227 bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
547 pm_runtime_get_noresume(&uart->pdev->dev); 228 break;
548 free_irq(uart->irq, (void *)uart); 229 case 3:
230 if (cpu_is_omap44xx()) {
231 bdata->pads = default_omap4_uart4_pads;
232 bdata->pads_cnt =
233 ARRAY_SIZE(default_omap4_uart4_pads);
234 } else if (cpu_is_omap3630()) {
235 bdata->pads = default_omap36xx_uart4_pads;
236 bdata->pads_cnt =
237 ARRAY_SIZE(default_omap36xx_uart4_pads);
549 } 238 }
239 break;
240 default:
241 break;
550 } 242 }
551} 243}
552
553static ssize_t sleep_timeout_show(struct device *dev,
554 struct device_attribute *attr,
555 char *buf)
556{
557 struct platform_device *pdev = to_platform_device(dev);
558 struct omap_device *odev = to_omap_device(pdev);
559 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
560
561 return sprintf(buf, "%u\n", uart->timeout / HZ);
562}
563
564static ssize_t sleep_timeout_store(struct device *dev,
565 struct device_attribute *attr,
566 const char *buf, size_t n)
567{
568 struct platform_device *pdev = to_platform_device(dev);
569 struct omap_device *odev = to_omap_device(pdev);
570 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
571 unsigned int value;
572
573 if (sscanf(buf, "%u", &value) != 1) {
574 dev_err(dev, "sleep_timeout_store: Invalid value\n");
575 return -EINVAL;
576 }
577
578 uart->timeout = value * HZ;
579 if (uart->timeout)
580 mod_timer(&uart->timer, jiffies + uart->timeout);
581 else
582 /* A zero value means disable timeout feature */
583 omap_uart_block_sleep(uart);
584
585 return n;
586}
587
588static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
589 sleep_timeout_store);
590#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
591#else 244#else
592static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} 245static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
593static void omap_uart_block_sleep(struct omap_uart_state *uart) 246#endif
594{
595 /* Needed to enable UART clocks when built without CONFIG_PM */
596 omap_uart_enable_clocks(uart);
597}
598#define DEV_CREATE_FILE(dev, attr)
599#endif /* CONFIG_PM */
600
601#ifndef CONFIG_SERIAL_OMAP
602/*
603 * Override the default 8250 read handler: mem_serial_in()
604 * Empty RX fifo read causes an abort on omap3630 and omap4
605 * This function makes sure that an empty rx fifo is not read on these silicons
606 * (OMAP1/2/3430 are not affected)
607 */
608static unsigned int serial_in_override(struct uart_port *up, int offset)
609{
610 if (UART_RX == offset) {
611 unsigned int lsr;
612 lsr = __serial_read_reg(up, UART_LSR);
613 if (!(lsr & UART_LSR_DR))
614 return -EPERM;
615 }
616
617 return __serial_read_reg(up, offset);
618}
619 247
620static void serial_out_override(struct uart_port *up, int offset, int value) 248char *cmdline_find_option(char *str)
621{ 249{
622 unsigned int status, tmout = 10000; 250 extern char *saved_command_line;
623 251
624 status = __serial_read_reg(up, UART_LSR); 252 return strstr(saved_command_line, str);
625 while (!(status & UART_LSR_THRE)) {
626 /* Wait up to 10ms for the character(s) to be sent. */
627 if (--tmout == 0)
628 break;
629 udelay(1);
630 status = __serial_read_reg(up, UART_LSR);
631 }
632 __serial_write_reg(up, offset, value);
633} 253}
634#endif
635 254
636static int __init omap_serial_early_init(void) 255static int __init omap_serial_early_init(void)
637{ 256{
638 int i = 0;
639
640 do { 257 do {
641 char oh_name[MAX_UART_HWMOD_NAME_LEN]; 258 char oh_name[MAX_UART_HWMOD_NAME_LEN];
642 struct omap_hwmod *oh; 259 struct omap_hwmod *oh;
643 struct omap_uart_state *uart; 260 struct omap_uart_state *uart;
261 char uart_name[MAX_UART_HWMOD_NAME_LEN];
644 262
645 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, 263 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
646 "uart%d", i + 1); 264 "uart%d", num_uarts + 1);
647 oh = omap_hwmod_lookup(oh_name); 265 oh = omap_hwmod_lookup(oh_name);
648 if (!oh) 266 if (!oh)
649 break; 267 break;
@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
653 return -ENODEV; 271 return -ENODEV;
654 272
655 uart->oh = oh; 273 uart->oh = oh;
656 uart->num = i++; 274 uart->num = num_uarts++;
657 list_add_tail(&uart->node, &uart_list); 275 list_add_tail(&uart->node, &uart_list);
658 num_uarts++; 276 snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
659 277 "%s%d", OMAP_SERIAL_NAME, uart->num);
660 /* 278
661 * NOTE: omap_hwmod_setup*() has not yet been called, 279 if (cmdline_find_option(uart_name)) {
662 * so no hwmod functions will work yet. 280 console_uart_id = uart->num;
663 */ 281
664 282 if (console_loglevel >= 10) {
665 /* 283 uart_debug = true;
666 * During UART early init, device need to be probed 284 pr_info("%s used as console in debug mode"
667 * to determine SoC specific init before omap_device 285 " uart%d clocks will not be"
668 * is ready. Therefore, don't allow idle here 286 " gated", uart_name, uart->num);
669 */ 287 }
670 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; 288
289 if (cmdline_find_option("no_console_suspend"))
290 no_console_suspend = true;
291
292 /*
293 * omap-uart can be used for earlyprintk logs
294 * So if omap-uart is used as console then prevent
295 * uart reset and idle to get logs from omap-uart
296 * until uart console driver is available to take
297 * care for console messages.
298 * Idling or resetting omap-uart while printing logs
299 * early boot logs can stall the boot-up.
300 */
301 oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
302 }
671 } while (1); 303 } while (1);
672 304
673 return 0; 305 return 0;
@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
677/** 309/**
678 * omap_serial_init_port() - initialize single serial port 310 * omap_serial_init_port() - initialize single serial port
679 * @bdata: port specific board data pointer 311 * @bdata: port specific board data pointer
312 * @info: platform specific data pointer
680 * 313 *
681 * This function initialies serial driver for given port only. 314 * This function initialies serial driver for given port only.
682 * Platforms can call this function instead of omap_serial_init() 315 * Platforms can call this function instead of omap_serial_init()
@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
685 * Don't mix calls to omap_serial_init_port() and omap_serial_init(), 318 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
686 * use only one of the two. 319 * use only one of the two.
687 */ 320 */
688void __init omap_serial_init_port(struct omap_board_data *bdata) 321void __init omap_serial_init_port(struct omap_board_data *bdata,
322 struct omap_uart_port_info *info)
689{ 323{
690 struct omap_uart_state *uart; 324 struct omap_uart_state *uart;
691 struct omap_hwmod *oh; 325 struct omap_hwmod *oh;
@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
693 void *pdata = NULL; 327 void *pdata = NULL;
694 u32 pdata_size = 0; 328 u32 pdata_size = 0;
695 char *name; 329 char *name;
696#ifndef CONFIG_SERIAL_OMAP
697 struct plat_serial8250_port ports[2] = {
698 {},
699 {.flags = 0},
700 };
701 struct plat_serial8250_port *p = &ports[0];
702#else
703 struct omap_uart_port_info omap_up; 330 struct omap_uart_port_info omap_up;
704#endif
705 331
706 if (WARN_ON(!bdata)) 332 if (WARN_ON(!bdata))
707 return; 333 return;
@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
713 list_for_each_entry(uart, &uart_list, node) 339 list_for_each_entry(uart, &uart_list, node)
714 if (bdata->id == uart->num) 340 if (bdata->id == uart->num)
715 break; 341 break;
342 if (!info)
343 info = omap_serial_default_info;
716 344
717 oh = uart->oh; 345 oh = uart->oh;
718 uart->dma_enabled = 0;
719#ifndef CONFIG_SERIAL_OMAP
720 name = "serial8250";
721
722 /*
723 * !! 8250 driver does not use standard IORESOURCE* It
724 * has it's own custom pdata that can be taken from
725 * the hwmod resource data. But, this needs to be
726 * done after the build.
727 *
728 * ?? does it have to be done before the register ??
729 * YES, because platform_device_data_add() copies
730 * pdata, it does not use a pointer.
731 */
732 p->flags = UPF_BOOT_AUTOCONF;
733 p->iotype = UPIO_MEM;
734 p->regshift = 2;
735 p->uartclk = OMAP24XX_BASE_BAUD * 16;
736 p->irq = oh->mpu_irqs[0].irq;
737 p->mapbase = oh->slaves[0]->addr->pa_start;
738 p->membase = omap_hwmod_get_mpu_rt_va(oh);
739 p->irqflags = IRQF_SHARED;
740 p->private_data = uart;
741
742 /*
743 * omap44xx, ti816x: Never read empty UART fifo
744 * omap3xxx: Never read empty UART fifo on UARTs
745 * with IP rev >=0x52
746 */
747 uart->regshift = p->regshift;
748 uart->membase = p->membase;
749 if (cpu_is_omap44xx() || cpu_is_ti816x())
750 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
751 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
752 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
753 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
754
755 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
756 p->serial_in = serial_in_override;
757 p->serial_out = serial_out_override;
758 }
759
760 pdata = &ports[0];
761 pdata_size = 2 * sizeof(struct plat_serial8250_port);
762#else
763
764 name = DRIVER_NAME; 346 name = DRIVER_NAME;
765 347
766 omap_up.dma_enabled = uart->dma_enabled; 348 omap_up.dma_enabled = info->dma_enabled;
767 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; 349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
768 omap_up.mapbase = oh->slaves[0]->addr->pa_start; 350 omap_up.flags = UPF_BOOT_AUTOCONF;
769 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); 351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
770 omap_up.irqflags = IRQF_SHARED; 352 omap_up.set_forceidle = omap_uart_set_forceidle;
771 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 353 omap_up.set_noidle = omap_uart_set_noidle;
354 omap_up.enable_wakeup = omap_uart_enable_wakeup;
355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
356 omap_up.dma_rx_timeout = info->dma_rx_timeout;
357 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
358 omap_up.autosuspend_timeout = info->autosuspend_timeout;
359
360 /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
361 if (!cpu_is_omap2420() && !cpu_is_ti816x())
362 omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
363
364 /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
365 if (cpu_is_omap34xx() || cpu_is_omap3630())
366 omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
772 367
773 pdata = &omap_up; 368 pdata = &omap_up;
774 pdata_size = sizeof(struct omap_uart_port_info); 369 pdata_size = sizeof(struct omap_uart_port_info);
775#endif
776 370
777 if (WARN_ON(!oh)) 371 if (WARN_ON(!oh))
778 return; 372 return;
@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
782 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", 376 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
783 name, oh->name); 377 name, oh->name);
784 378
785 omap_device_disable_idle_on_suspend(pdev); 379 if ((console_uart_id == bdata->id) && no_console_suspend)
380 omap_device_disable_idle_on_suspend(pdev);
381
786 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); 382 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
787 383
788 uart->irq = oh->mpu_irqs[0].irq;
789 uart->regshift = 2;
790 uart->mapbase = oh->slaves[0]->addr->pa_start;
791 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
792 uart->pdev = pdev; 384 uart->pdev = pdev;
793 385
794 oh->dev_attr = uart; 386 oh->dev_attr = uart;
795 387
796 console_lock(); /* in case the earlycon is on the UART */ 388 if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
797 389 && !uart_debug)
798 /*
799 * Because of early UART probing, UART did not get idled
800 * on init. Now that omap_device is ready, ensure full idle
801 * before doing omap_device_enable().
802 */
803 omap_hwmod_idle(uart->oh);
804
805 omap_device_enable(uart->pdev);
806 omap_uart_idle_init(uart);
807 omap_uart_reset(uart);
808 omap_hwmod_enable_wakeup(uart->oh);
809 omap_device_idle(uart->pdev);
810
811 /*
812 * Need to block sleep long enough for interrupt driven
813 * driver to start. Console driver is in polling mode
814 * so device needs to be kept enabled while polling driver
815 * is in use.
816 */
817 if (uart->timeout)
818 uart->timeout = (30 * HZ);
819 omap_uart_block_sleep(uart);
820 uart->timeout = DEFAULT_TIMEOUT;
821
822 console_unlock();
823
824 if ((cpu_is_omap34xx() && uart->padconf) ||
825 (uart->wk_en && uart->wk_mask)) {
826 device_init_wakeup(&pdev->dev, true); 390 device_init_wakeup(&pdev->dev, true);
827 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
828 }
829
830 /* Enable the MDR1 errata for OMAP3 */
831 if (cpu_is_omap34xx() && !cpu_is_ti816x())
832 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
833} 391}
834 392
835/** 393/**
836 * omap_serial_init() - initialize all supported serial ports 394 * omap_serial_board_init() - initialize all supported serial ports
395 * @info: platform specific data pointer
837 * 396 *
838 * Initializes all available UARTs as serial ports. Platforms 397 * Initializes all available UARTs as serial ports. Platforms
839 * can call this function when they want to have default behaviour 398 * can call this function when they want to have default behaviour
840 * for serial ports (e.g initialize them all as serial ports). 399 * for serial ports (e.g initialize them all as serial ports).
841 */ 400 */
842void __init omap_serial_init(void) 401void __init omap_serial_board_init(struct omap_uart_port_info *info)
843{ 402{
844 struct omap_uart_state *uart; 403 struct omap_uart_state *uart;
845 struct omap_board_data bdata; 404 struct omap_board_data bdata;
@@ -849,7 +408,25 @@ void __init omap_serial_init(void)
849 bdata.flags = 0; 408 bdata.flags = 0;
850 bdata.pads = NULL; 409 bdata.pads = NULL;
851 bdata.pads_cnt = 0; 410 bdata.pads_cnt = 0;
852 omap_serial_init_port(&bdata);
853 411
412 if (cpu_is_omap44xx() || cpu_is_omap34xx())
413 omap_serial_fill_default_pads(&bdata);
414
415 if (!info)
416 omap_serial_init_port(&bdata, NULL);
417 else
418 omap_serial_init_port(&bdata, &info[uart->num]);
854 } 419 }
855} 420}
421
422/**
423 * omap_serial_init() - initialize all supported serial ports
424 *
425 * Initializes all available UARTs.
426 * Platforms can call this function when they want to have default behaviour
427 * for serial ports (e.g initialize them all as serial ports).
428 */
429void __init omap_serial_init(void)
430{
431 omap_serial_board_init(NULL);
432}
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 3df04d944e4d..9a584614e7e6 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
19 19
20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
21 21
22obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
23obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 22obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
24obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 23obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
25obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 24obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
new file mode 100644
index 000000000000..06c19bb7bca6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/am33xx.h
@@ -0,0 +1,25 @@
1/*
2 * This file contains the address info for various AM33XX modules.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_AM33XX_H
17#define __ASM_ARCH_AM33XX_H
18
19#define L4_SLOW_AM33XX_BASE 0x48000000
20
21#define AM33XX_SCM_BASE 0x44E10000
22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
23#define AM33XX_PRCM_BASE 0x44E00000
24
25#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index eb73ab40e955..240a7b9fd946 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,8 @@ struct clkops {
59#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_4430 (1 << 5)
60#define RATE_IN_TI816X (1 << 6) 60#define RATE_IN_TI816X (1 << 6)
61#define RATE_IN_4460 (1 << 7) 61#define RATE_IN_4460 (1 << 7)
62#define RATE_IN_AM33XX (1 << 8)
63#define RATE_IN_TI814X (1 << 9)
62 64
63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 65#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 66#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +86,7 @@ struct clkops {
84struct clksel_rate { 86struct clksel_rate {
85 u32 val; 87 u32 val;
86 u8 div; 88 u8 div;
87 u8 flags; 89 u16 flags;
88}; 90};
89 91
90/** 92/**
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 408a12f79205..6b51086fce18 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -69,6 +69,7 @@ unsigned int omap_rev(void);
69 * cpu_is_omap343x(): True for OMAP3430 69 * cpu_is_omap343x(): True for OMAP3430
70 * cpu_is_omap443x(): True for OMAP4430 70 * cpu_is_omap443x(): True for OMAP4430
71 * cpu_is_omap446x(): True for OMAP4460 71 * cpu_is_omap446x(): True for OMAP4460
72 * cpu_is_omap447x(): True for OMAP4470
72 */ 73 */
73#define GET_OMAP_CLASS (omap_rev() & 0xff) 74#define GET_OMAP_CLASS (omap_rev() & 0xff)
74 75
@@ -78,6 +79,22 @@ static inline int is_omap ##class (void) \
78 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ 79 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
79} 80}
80 81
82#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff)
83
84#define IS_AM_CLASS(class, id) \
85static inline int is_am ##class (void) \
86{ \
87 return (GET_AM_CLASS == (id)) ? 1 : 0; \
88}
89
90#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
91
92#define IS_TI_CLASS(class, id) \
93static inline int is_ti ##class (void) \
94{ \
95 return (GET_TI_CLASS == (id)) ? 1 : 0; \
96}
97
81#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) 98#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
82 99
83#define IS_OMAP_SUBCLASS(subclass, id) \ 100#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void) \
92 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ 109 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
93} 110}
94 111
112#define IS_AM_SUBCLASS(subclass, id) \
113static inline int is_am ##subclass (void) \
114{ \
115 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
116}
117
95IS_OMAP_CLASS(7xx, 0x07) 118IS_OMAP_CLASS(7xx, 0x07)
96IS_OMAP_CLASS(15xx, 0x15) 119IS_OMAP_CLASS(15xx, 0x15)
97IS_OMAP_CLASS(16xx, 0x16) 120IS_OMAP_CLASS(16xx, 0x16)
98IS_OMAP_CLASS(24xx, 0x24) 121IS_OMAP_CLASS(24xx, 0x24)
99IS_OMAP_CLASS(34xx, 0x34) 122IS_OMAP_CLASS(34xx, 0x34)
100IS_OMAP_CLASS(44xx, 0x44) 123IS_OMAP_CLASS(44xx, 0x44)
124IS_AM_CLASS(33xx, 0x33)
125
126IS_TI_CLASS(81xx, 0x81)
101 127
102IS_OMAP_SUBCLASS(242x, 0x242) 128IS_OMAP_SUBCLASS(242x, 0x242)
103IS_OMAP_SUBCLASS(243x, 0x243) 129IS_OMAP_SUBCLASS(243x, 0x243)
@@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
105IS_OMAP_SUBCLASS(363x, 0x363) 131IS_OMAP_SUBCLASS(363x, 0x363)
106IS_OMAP_SUBCLASS(443x, 0x443) 132IS_OMAP_SUBCLASS(443x, 0x443)
107IS_OMAP_SUBCLASS(446x, 0x446) 133IS_OMAP_SUBCLASS(446x, 0x446)
134IS_OMAP_SUBCLASS(447x, 0x447)
108 135
109IS_TI_SUBCLASS(816x, 0x816) 136IS_TI_SUBCLASS(816x, 0x816)
137IS_TI_SUBCLASS(814x, 0x814)
138IS_AM_SUBCLASS(335x, 0x335)
110 139
111#define cpu_is_omap7xx() 0 140#define cpu_is_omap7xx() 0
112#define cpu_is_omap15xx() 0 141#define cpu_is_omap15xx() 0
@@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
116#define cpu_is_omap243x() 0 145#define cpu_is_omap243x() 0
117#define cpu_is_omap34xx() 0 146#define cpu_is_omap34xx() 0
118#define cpu_is_omap343x() 0 147#define cpu_is_omap343x() 0
148#define cpu_is_ti81xx() 0
119#define cpu_is_ti816x() 0 149#define cpu_is_ti816x() 0
150#define cpu_is_ti814x() 0
151#define cpu_is_am33xx() 0
152#define cpu_is_am335x() 0
120#define cpu_is_omap44xx() 0 153#define cpu_is_omap44xx() 0
121#define cpu_is_omap443x() 0 154#define cpu_is_omap443x() 0
122#define cpu_is_omap446x() 0 155#define cpu_is_omap446x() 0
156#define cpu_is_omap447x() 0
123 157
124#if defined(MULTI_OMAP1) 158#if defined(MULTI_OMAP1)
125# if defined(CONFIG_ARCH_OMAP730) 159# if defined(CONFIG_ARCH_OMAP730)
@@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
322# undef cpu_is_omap3530 356# undef cpu_is_omap3530
323# undef cpu_is_omap3505 357# undef cpu_is_omap3505
324# undef cpu_is_omap3517 358# undef cpu_is_omap3517
359# undef cpu_is_ti81xx
325# undef cpu_is_ti816x 360# undef cpu_is_ti816x
361# undef cpu_is_ti814x
362# undef cpu_is_am33xx
363# undef cpu_is_am335x
326# define cpu_is_omap3430() is_omap3430() 364# define cpu_is_omap3430() is_omap3430()
327# define cpu_is_omap3503() (cpu_is_omap3430() && \ 365# define cpu_is_omap3503() (cpu_is_omap3430() && \
328 (!omap3_has_iva()) && \ 366 (!omap3_has_iva()) && \
@@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
339 !omap3_has_sgx()) 377 !omap3_has_sgx())
340# undef cpu_is_omap3630 378# undef cpu_is_omap3630
341# define cpu_is_omap3630() is_omap363x() 379# define cpu_is_omap3630() is_omap363x()
380# define cpu_is_ti81xx() is_ti81xx()
342# define cpu_is_ti816x() is_ti816x() 381# define cpu_is_ti816x() is_ti816x()
382# define cpu_is_ti814x() is_ti814x()
383# define cpu_is_am33xx() is_am33xx()
384# define cpu_is_am335x() is_am335x()
343#endif 385#endif
344 386
345# if defined(CONFIG_ARCH_OMAP4) 387# if defined(CONFIG_ARCH_OMAP4)
346# undef cpu_is_omap44xx 388# undef cpu_is_omap44xx
347# undef cpu_is_omap443x 389# undef cpu_is_omap443x
348# undef cpu_is_omap446x 390# undef cpu_is_omap446x
391# undef cpu_is_omap447x
349# define cpu_is_omap44xx() is_omap44xx() 392# define cpu_is_omap44xx() is_omap44xx()
350# define cpu_is_omap443x() is_omap443x() 393# define cpu_is_omap443x() is_omap443x()
351# define cpu_is_omap446x() is_omap446x() 394# define cpu_is_omap446x() is_omap446x()
395# define cpu_is_omap447x() is_omap447x()
352# endif 396# endif
353 397
354/* Macros to detect if we have OMAP1 or OMAP2 */ 398/* Macros to detect if we have OMAP1 or OMAP2 */
@@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517)
386#define TI8168_REV_ES1_0 TI816X_CLASS 430#define TI8168_REV_ES1_0 TI816X_CLASS
387#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) 431#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
388 432
433#define TI814X_CLASS 0x81400034
434#define TI8148_REV_ES1_0 TI814X_CLASS
435#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
436#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
437
438#define AM335X_CLASS 0x33500034
439#define AM335X_REV_ES1_0 AM335X_CLASS
440
389#define OMAP443X_CLASS 0x44300044 441#define OMAP443X_CLASS 0x44300044
390#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 442#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
391#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) 443#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
392#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) 444#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
393#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) 445#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
446#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8))
394 447
395#define OMAP446X_CLASS 0x44600044 448#define OMAP446X_CLASS 0x44600044
396#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) 449#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
397 450
451#define OMAP447X_CLASS 0x44700044
452#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
453
398void omap2_check_revision(void); 454void omap2_check_revision(void);
399 455
400/* 456/*
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1499b8..e897978371c2 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,7 @@
286#include <plat/omap24xx.h> 286#include <plat/omap24xx.h>
287#include <plat/omap34xx.h> 287#include <plat/omap34xx.h>
288#include <plat/omap44xx.h> 288#include <plat/omap44xx.h>
289#include <plat/ti816x.h> 289#include <plat/ti81xx.h>
290#include <plat/am33xx.h>
290 291
291#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 292#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 1234944a4da0..0696bae1818b 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -73,6 +73,9 @@
73#define OMAP4_L3_IO_OFFSET 0xb4000000 73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75 75
76#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
77#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
78
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 79#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) 80#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78 81
@@ -154,6 +157,15 @@
154#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 157#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
155 158
156/* 159/*
160 * ----------------------------------------------------------------------------
161 * AM33XX specific IO mapping
162 * ----------------------------------------------------------------------------
163 */
164#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
165#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
166#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
167
168/*
157 * Need to look at the Size 4M for L4. 169 * Need to look at the Size 4M for L4.
158 * VPOM3430 was not working for Int controller 170 * VPOM3430 was not working for Int controller
159 */ 171 */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 2682043f5a5b..9ff444469f3d 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -19,6 +19,7 @@
19 19
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/pm_qos.h>
22 23
23#include <plat/mux.h> 24#include <plat/mux.h>
24 25
@@ -33,6 +34,8 @@
33 34
34#define OMAP_MODE13X_SPEED 230400 35#define OMAP_MODE13X_SPEED 230400
35 36
37#define OMAP_UART_SCR_TX_EMPTY 0x08
38
36/* WER = 0x7F 39/* WER = 0x7F
37 * Enable module level wakeup in WER reg 40 * Enable module level wakeup in WER reg
38 */ 41 */
@@ -51,18 +54,27 @@
51 54
52#define OMAP_UART_DMA_CH_FREE -1 55#define OMAP_UART_DMA_CH_FREE -1
53 56
54#define RX_TIMEOUT (3 * HZ)
55#define OMAP_MAX_HSUART_PORTS 4 57#define OMAP_MAX_HSUART_PORTS 4
56 58
57#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 59#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
58 60
61#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
62#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
63
59struct omap_uart_port_info { 64struct omap_uart_port_info {
60 bool dma_enabled; /* To specify DMA Mode */ 65 bool dma_enabled; /* To specify DMA Mode */
61 unsigned int uartclk; /* UART clock rate */ 66 unsigned int uartclk; /* UART clock rate */
62 void __iomem *membase; /* ioremap cookie or NULL */
63 resource_size_t mapbase; /* resource base */
64 unsigned long irqflags; /* request_irq flags */
65 upf_t flags; /* UPF_* flags */ 67 upf_t flags; /* UPF_* flags */
68 u32 errata;
69 unsigned int dma_rx_buf_size;
70 unsigned int dma_rx_timeout;
71 unsigned int autosuspend_timeout;
72 unsigned int dma_rx_poll_rate;
73
74 int (*get_context_loss_count)(struct device *);
75 void (*set_forceidle)(struct platform_device *);
76 void (*set_noidle)(struct platform_device *);
77 void (*enable_wakeup)(struct platform_device *, bool);
66}; 78};
67 79
68struct uart_omap_dma { 80struct uart_omap_dma {
@@ -86,8 +98,9 @@ struct uart_omap_dma {
86 spinlock_t rx_lock; 98 spinlock_t rx_lock;
87 /* timer to poll activity on rx dma */ 99 /* timer to poll activity on rx dma */
88 struct timer_list rx_timer; 100 struct timer_list rx_timer;
89 int rx_buf_size; 101 unsigned int rx_buf_size;
90 int rx_timeout; 102 unsigned int rx_poll_rate;
103 unsigned int rx_timeout;
91}; 104};
92 105
93struct uart_omap_port { 106struct uart_omap_port {
@@ -100,6 +113,10 @@ struct uart_omap_port {
100 unsigned char mcr; 113 unsigned char mcr;
101 unsigned char fcr; 114 unsigned char fcr;
102 unsigned char efr; 115 unsigned char efr;
116 unsigned char dll;
117 unsigned char dlh;
118 unsigned char mdr1;
119 unsigned char scr;
103 120
104 int use_dma; 121 int use_dma;
105 /* 122 /*
@@ -111,6 +128,14 @@ struct uart_omap_port {
111 unsigned char msr_saved_flags; 128 unsigned char msr_saved_flags;
112 char name[20]; 129 char name[20];
113 unsigned long port_activity; 130 unsigned long port_activity;
131 u32 context_loss_cnt;
132 u32 errata;
133 u8 wakeups_enabled;
134
135 struct pm_qos_request pm_qos_request;
136 u32 latency;
137 u32 calc_latency;
138 struct work_struct qos_work;
114}; 139};
115 140
116#endif /* __OMAP_SERIAL_H__ */ 141#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index b9e85886b9d6..0d818acf3917 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -35,6 +35,8 @@
35#define L4_EMU_34XX_BASE 0x54000000 35#define L4_EMU_34XX_BASE 0x54000000
36#define L3_34XX_BASE 0x68000000 36#define L3_34XX_BASE 0x68000000
37 37
38#define L4_WK_AM33XX_BASE 0x44C00000
39
38#define OMAP3430_32KSYNCT_BASE 0x48320000 40#define OMAP3430_32KSYNCT_BASE 0x48320000
39#define OMAP3430_CM_BASE 0x48004800 41#define OMAP3430_CM_BASE 0x48004800
40#define OMAP3430_PRM_BASE 0x48306800 42#define OMAP3430_PRM_BASE 0x48306800
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 1ab9fd6abe6d..38b3e38df2a0 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,10 +51,10 @@
51#define OMAP4_UART3_BASE 0x48020000 51#define OMAP4_UART3_BASE 0x48020000
52#define OMAP4_UART4_BASE 0x4806e000 52#define OMAP4_UART4_BASE 0x4806e000
53 53
54/* TI816X serial ports */ 54/* TI81XX serial ports */
55#define TI816X_UART1_BASE 0x48020000 55#define TI81XX_UART1_BASE 0x48020000
56#define TI816X_UART2_BASE 0x48022000 56#define TI81XX_UART2_BASE 0x48022000
57#define TI816X_UART3_BASE 0x48024000 57#define TI81XX_UART3_BASE 0x48024000
58 58
59/* AM3505/3517 UART4 */ 59/* AM3505/3517 UART4 */
60#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ 60#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
@@ -89,9 +89,9 @@
89#define OMAP4UART2 OMAP2UART2 89#define OMAP4UART2 OMAP2UART2
90#define OMAP4UART3 43 90#define OMAP4UART3 43
91#define OMAP4UART4 44 91#define OMAP4UART4 44
92#define TI816XUART1 81 92#define TI81XXUART1 81
93#define TI816XUART2 82 93#define TI81XXUART2 82
94#define TI816XUART3 83 94#define TI81XXUART3 83
95#define ZOOM_UART 95 /* Only on zoom2/3 */ 95#define ZOOM_UART 95 /* Only on zoom2/3 */
96 96
97/* This is only used by 8250.c for omap1510 */ 97/* This is only used by 8250.c for omap1510 */
@@ -106,15 +106,13 @@
106#ifndef __ASSEMBLER__ 106#ifndef __ASSEMBLER__
107 107
108struct omap_board_data; 108struct omap_board_data;
109struct omap_uart_port_info;
109 110
110extern void omap_serial_init(void); 111extern void omap_serial_init(void);
111extern void omap_serial_init_port(struct omap_board_data *bdata);
112extern int omap_uart_can_sleep(void); 112extern int omap_uart_can_sleep(void);
113extern void omap_uart_check_wakeup(void); 113extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
114extern void omap_uart_prepare_suspend(void); 114extern void omap_serial_init_port(struct omap_board_data *bdata,
115extern void omap_uart_prepare_idle(int num); 115 struct omap_uart_port_info *platform_data);
116extern void omap_uart_resume_idle(int num);
117extern void omap_uart_enable_irqs(int enable);
118#endif 116#endif
119 117
120#endif 118#endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5dda1e..8f9843f78422 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * This file contains the address data for various TI816X modules. 2 * This file contains the address data for various TI81XX modules.
3 * 3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * 5 *
@@ -13,15 +13,15 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16#ifndef __ASM_ARCH_TI816X_H 16#ifndef __ASM_ARCH_TI81XX_H
17#define __ASM_ARCH_TI816X_H 17#define __ASM_ARCH_TI81XX_H
18 18
19#define L4_SLOW_TI816X_BASE 0x48000000 19#define L4_SLOW_TI81XX_BASE 0x48000000
20 20
21#define TI816X_SCM_BASE 0x48140000 21#define TI81XX_SCM_BASE 0x48140000
22#define TI816X_CTRL_BASE TI816X_SCM_BASE 22#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
23#define TI816X_PRCM_BASE 0x48180000 23#define TI81XX_PRCM_BASE 0x48180000
24 24
25#define TI816X_ARM_INTC_BASE 0x48200000 25#define TI81XX_ARM_INTC_BASE 0x48200000
26 26
27#endif /* __ASM_ARCH_TI816X_H */ 27#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 2f472e989ec6..7fbc361946b5 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -99,9 +99,9 @@ static inline void flush(void)
99#define DEBUG_LL_ZOOM(mach) \ 99#define DEBUG_LL_ZOOM(mach) \
100 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) 100 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
101 101
102#define DEBUG_LL_TI816X(p, mach) \ 102#define DEBUG_LL_TI81XX(p, mach) \
103 _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ 103 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
104 TI816XUART##p) 104 TI81XXUART##p)
105 105
106static inline void __arch_decomp_setup(unsigned long arch_id) 106static inline void __arch_decomp_setup(unsigned long arch_id)
107{ 107{
@@ -177,7 +177,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
177 DEBUG_LL_ZOOM(omap_zoom3); 177 DEBUG_LL_ZOOM(omap_zoom3);
178 178
179 /* TI8168 base boards using UART3 */ 179 /* TI8168 base boards using UART3 */
180 DEBUG_LL_TI816X(3, ti8168evm); 180 DEBUG_LL_TI81XX(3, ti8168evm);
181 181
182 } while (0); 182 } while (0);
183} 183}
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 5e713d3ef1f4..ca24ab37d11c 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -37,17 +37,24 @@
37#include <linux/clk.h> 37#include <linux/clk.h>
38#include <linux/serial_core.h> 38#include <linux/serial_core.h>
39#include <linux/irq.h> 39#include <linux/irq.h>
40#include <linux/pm_runtime.h>
41#include <linux/of.h>
40 42
41#include <plat/dma.h> 43#include <plat/dma.h>
42#include <plat/dmtimer.h> 44#include <plat/dmtimer.h>
43#include <plat/omap-serial.h> 45#include <plat/omap-serial.h>
44 46
47#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
48
45static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 49static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
46 50
47/* Forward declaration of functions */ 51/* Forward declaration of functions */
48static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); 52static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
49static void serial_omap_rx_timeout(unsigned long uart_no); 53static void serial_omap_rxdma_poll(unsigned long uart_no);
50static int serial_omap_start_rxdma(struct uart_omap_port *up); 54static int serial_omap_start_rxdma(struct uart_omap_port *up);
55static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
56
57static struct workqueue_struct *serial_omap_uart_wq;
51 58
52static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 59static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
53{ 60{
@@ -102,6 +109,8 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
102 omap_free_dma(up->uart_dma.rx_dma_channel); 109 omap_free_dma(up->uart_dma.rx_dma_channel);
103 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 110 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
104 up->uart_dma.rx_dma_used = false; 111 up->uart_dma.rx_dma_used = false;
112 pm_runtime_mark_last_busy(&up->pdev->dev);
113 pm_runtime_put_autosuspend(&up->pdev->dev);
105 } 114 }
106} 115}
107 116
@@ -109,9 +118,12 @@ static void serial_omap_enable_ms(struct uart_port *port)
109{ 118{
110 struct uart_omap_port *up = (struct uart_omap_port *)port; 119 struct uart_omap_port *up = (struct uart_omap_port *)port;
111 120
112 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); 121 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
122
123 pm_runtime_get_sync(&up->pdev->dev);
113 up->ier |= UART_IER_MSI; 124 up->ier |= UART_IER_MSI;
114 serial_out(up, UART_IER, up->ier); 125 serial_out(up, UART_IER, up->ier);
126 pm_runtime_put(&up->pdev->dev);
115} 127}
116 128
117static void serial_omap_stop_tx(struct uart_port *port) 129static void serial_omap_stop_tx(struct uart_port *port)
@@ -129,30 +141,40 @@ static void serial_omap_stop_tx(struct uart_port *port)
129 omap_stop_dma(up->uart_dma.tx_dma_channel); 141 omap_stop_dma(up->uart_dma.tx_dma_channel);
130 omap_free_dma(up->uart_dma.tx_dma_channel); 142 omap_free_dma(up->uart_dma.tx_dma_channel);
131 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 143 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
144 pm_runtime_mark_last_busy(&up->pdev->dev);
145 pm_runtime_put_autosuspend(&up->pdev->dev);
132 } 146 }
133 147
148 pm_runtime_get_sync(&up->pdev->dev);
134 if (up->ier & UART_IER_THRI) { 149 if (up->ier & UART_IER_THRI) {
135 up->ier &= ~UART_IER_THRI; 150 up->ier &= ~UART_IER_THRI;
136 serial_out(up, UART_IER, up->ier); 151 serial_out(up, UART_IER, up->ier);
137 } 152 }
153
154 pm_runtime_mark_last_busy(&up->pdev->dev);
155 pm_runtime_put_autosuspend(&up->pdev->dev);
138} 156}
139 157
140static void serial_omap_stop_rx(struct uart_port *port) 158static void serial_omap_stop_rx(struct uart_port *port)
141{ 159{
142 struct uart_omap_port *up = (struct uart_omap_port *)port; 160 struct uart_omap_port *up = (struct uart_omap_port *)port;
143 161
162 pm_runtime_get_sync(&up->pdev->dev);
144 if (up->use_dma) 163 if (up->use_dma)
145 serial_omap_stop_rxdma(up); 164 serial_omap_stop_rxdma(up);
146 up->ier &= ~UART_IER_RLSI; 165 up->ier &= ~UART_IER_RLSI;
147 up->port.read_status_mask &= ~UART_LSR_DR; 166 up->port.read_status_mask &= ~UART_LSR_DR;
148 serial_out(up, UART_IER, up->ier); 167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(&up->pdev->dev);
169 pm_runtime_put_autosuspend(&up->pdev->dev);
149} 170}
150 171
151static inline void receive_chars(struct uart_omap_port *up, int *status) 172static inline void receive_chars(struct uart_omap_port *up,
173 unsigned int *status)
152{ 174{
153 struct tty_struct *tty = up->port.state->port.tty; 175 struct tty_struct *tty = up->port.state->port.tty;
154 unsigned int flag; 176 unsigned int flag, lsr = *status;
155 unsigned char ch, lsr = *status; 177 unsigned char ch = 0;
156 int max_count = 256; 178 int max_count = 256;
157 179
158 do { 180 do {
@@ -262,7 +284,10 @@ static void serial_omap_start_tx(struct uart_port *port)
262 int ret = 0; 284 int ret = 0;
263 285
264 if (!up->use_dma) { 286 if (!up->use_dma) {
287 pm_runtime_get_sync(&up->pdev->dev);
265 serial_omap_enable_ier_thri(up); 288 serial_omap_enable_ier_thri(up);
289 pm_runtime_mark_last_busy(&up->pdev->dev);
290 pm_runtime_put_autosuspend(&up->pdev->dev);
266 return; 291 return;
267 } 292 }
268 293
@@ -272,6 +297,7 @@ static void serial_omap_start_tx(struct uart_port *port)
272 xmit = &up->port.state->xmit; 297 xmit = &up->port.state->xmit;
273 298
274 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { 299 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
300 pm_runtime_get_sync(&up->pdev->dev);
275 ret = omap_request_dma(up->uart_dma.uart_dma_tx, 301 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
276 "UART Tx DMA", 302 "UART Tx DMA",
277 (void *)uart_tx_dma_callback, up, 303 (void *)uart_tx_dma_callback, up,
@@ -354,9 +380,13 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
354 unsigned int iir, lsr; 380 unsigned int iir, lsr;
355 unsigned long flags; 381 unsigned long flags;
356 382
383 pm_runtime_get_sync(&up->pdev->dev);
357 iir = serial_in(up, UART_IIR); 384 iir = serial_in(up, UART_IIR);
358 if (iir & UART_IIR_NO_INT) 385 if (iir & UART_IIR_NO_INT) {
386 pm_runtime_mark_last_busy(&up->pdev->dev);
387 pm_runtime_put_autosuspend(&up->pdev->dev);
359 return IRQ_NONE; 388 return IRQ_NONE;
389 }
360 390
361 spin_lock_irqsave(&up->port.lock, flags); 391 spin_lock_irqsave(&up->port.lock, flags);
362 lsr = serial_in(up, UART_LSR); 392 lsr = serial_in(up, UART_LSR);
@@ -378,6 +408,9 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
378 transmit_chars(up); 408 transmit_chars(up);
379 409
380 spin_unlock_irqrestore(&up->port.lock, flags); 410 spin_unlock_irqrestore(&up->port.lock, flags);
411 pm_runtime_mark_last_busy(&up->pdev->dev);
412 pm_runtime_put_autosuspend(&up->pdev->dev);
413
381 up->port_activity = jiffies; 414 up->port_activity = jiffies;
382 return IRQ_HANDLED; 415 return IRQ_HANDLED;
383} 416}
@@ -388,11 +421,12 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
388 unsigned long flags = 0; 421 unsigned long flags = 0;
389 unsigned int ret = 0; 422 unsigned int ret = 0;
390 423
391 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); 424 pm_runtime_get_sync(&up->pdev->dev);
425 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
392 spin_lock_irqsave(&up->port.lock, flags); 426 spin_lock_irqsave(&up->port.lock, flags);
393 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 427 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
394 spin_unlock_irqrestore(&up->port.lock, flags); 428 spin_unlock_irqrestore(&up->port.lock, flags);
395 429 pm_runtime_put(&up->pdev->dev);
396 return ret; 430 return ret;
397} 431}
398 432
@@ -402,8 +436,11 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
402 unsigned char status; 436 unsigned char status;
403 unsigned int ret = 0; 437 unsigned int ret = 0;
404 438
439 pm_runtime_get_sync(&up->pdev->dev);
405 status = check_modem_status(up); 440 status = check_modem_status(up);
406 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); 441 pm_runtime_put(&up->pdev->dev);
442
443 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
407 444
408 if (status & UART_MSR_DCD) 445 if (status & UART_MSR_DCD)
409 ret |= TIOCM_CAR; 446 ret |= TIOCM_CAR;
@@ -421,7 +458,7 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
421 struct uart_omap_port *up = (struct uart_omap_port *)port; 458 struct uart_omap_port *up = (struct uart_omap_port *)port;
422 unsigned char mcr = 0; 459 unsigned char mcr = 0;
423 460
424 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); 461 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
425 if (mctrl & TIOCM_RTS) 462 if (mctrl & TIOCM_RTS)
426 mcr |= UART_MCR_RTS; 463 mcr |= UART_MCR_RTS;
427 if (mctrl & TIOCM_DTR) 464 if (mctrl & TIOCM_DTR)
@@ -433,8 +470,11 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
433 if (mctrl & TIOCM_LOOP) 470 if (mctrl & TIOCM_LOOP)
434 mcr |= UART_MCR_LOOP; 471 mcr |= UART_MCR_LOOP;
435 472
436 mcr |= up->mcr; 473 pm_runtime_get_sync(&up->pdev->dev);
437 serial_out(up, UART_MCR, mcr); 474 up->mcr = serial_in(up, UART_MCR);
475 up->mcr |= mcr;
476 serial_out(up, UART_MCR, up->mcr);
477 pm_runtime_put(&up->pdev->dev);
438} 478}
439 479
440static void serial_omap_break_ctl(struct uart_port *port, int break_state) 480static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -442,7 +482,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
442 struct uart_omap_port *up = (struct uart_omap_port *)port; 482 struct uart_omap_port *up = (struct uart_omap_port *)port;
443 unsigned long flags = 0; 483 unsigned long flags = 0;
444 484
445 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); 485 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
486 pm_runtime_get_sync(&up->pdev->dev);
446 spin_lock_irqsave(&up->port.lock, flags); 487 spin_lock_irqsave(&up->port.lock, flags);
447 if (break_state == -1) 488 if (break_state == -1)
448 up->lcr |= UART_LCR_SBC; 489 up->lcr |= UART_LCR_SBC;
@@ -450,6 +491,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
450 up->lcr &= ~UART_LCR_SBC; 491 up->lcr &= ~UART_LCR_SBC;
451 serial_out(up, UART_LCR, up->lcr); 492 serial_out(up, UART_LCR, up->lcr);
452 spin_unlock_irqrestore(&up->port.lock, flags); 493 spin_unlock_irqrestore(&up->port.lock, flags);
494 pm_runtime_put(&up->pdev->dev);
453} 495}
454 496
455static int serial_omap_startup(struct uart_port *port) 497static int serial_omap_startup(struct uart_port *port)
@@ -466,8 +508,9 @@ static int serial_omap_startup(struct uart_port *port)
466 if (retval) 508 if (retval)
467 return retval; 509 return retval;
468 510
469 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); 511 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
470 512
513 pm_runtime_get_sync(&up->pdev->dev);
471 /* 514 /*
472 * Clear the FIFO buffers and disable them. 515 * Clear the FIFO buffers and disable them.
473 * (they will be reenabled in set_termios()) 516 * (they will be reenabled in set_termios())
@@ -505,8 +548,8 @@ static int serial_omap_startup(struct uart_port *port)
505 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), 548 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
506 0); 549 0);
507 init_timer(&(up->uart_dma.rx_timer)); 550 init_timer(&(up->uart_dma.rx_timer));
508 up->uart_dma.rx_timer.function = serial_omap_rx_timeout; 551 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
509 up->uart_dma.rx_timer.data = up->pdev->id; 552 up->uart_dma.rx_timer.data = up->port.line;
510 /* Currently the buffer size is 4KB. Can increase it */ 553 /* Currently the buffer size is 4KB. Can increase it */
511 up->uart_dma.rx_buf = dma_alloc_coherent(NULL, 554 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
512 up->uart_dma.rx_buf_size, 555 up->uart_dma.rx_buf_size,
@@ -523,6 +566,8 @@ static int serial_omap_startup(struct uart_port *port)
523 /* Enable module level wake up */ 566 /* Enable module level wake up */
524 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 567 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
525 568
569 pm_runtime_mark_last_busy(&up->pdev->dev);
570 pm_runtime_put_autosuspend(&up->pdev->dev);
526 up->port_activity = jiffies; 571 up->port_activity = jiffies;
527 return 0; 572 return 0;
528} 573}
@@ -532,7 +577,9 @@ static void serial_omap_shutdown(struct uart_port *port)
532 struct uart_omap_port *up = (struct uart_omap_port *)port; 577 struct uart_omap_port *up = (struct uart_omap_port *)port;
533 unsigned long flags = 0; 578 unsigned long flags = 0;
534 579
535 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); 580 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
581
582 pm_runtime_get_sync(&up->pdev->dev);
536 /* 583 /*
537 * Disable interrupts from this port 584 * Disable interrupts from this port
538 */ 585 */
@@ -566,6 +613,8 @@ static void serial_omap_shutdown(struct uart_port *port)
566 up->uart_dma.rx_buf_dma_phys); 613 up->uart_dma.rx_buf_dma_phys);
567 up->uart_dma.rx_buf = NULL; 614 up->uart_dma.rx_buf = NULL;
568 } 615 }
616
617 pm_runtime_put(&up->pdev->dev);
569 free_irq(up->port.irq, up); 618 free_irq(up->port.irq, up);
570} 619}
571 620
@@ -573,8 +622,6 @@ static inline void
573serial_omap_configure_xonxoff 622serial_omap_configure_xonxoff
574 (struct uart_omap_port *up, struct ktermios *termios) 623 (struct uart_omap_port *up, struct ktermios *termios)
575{ 624{
576 unsigned char efr = 0;
577
578 up->lcr = serial_in(up, UART_LCR); 625 up->lcr = serial_in(up, UART_LCR);
579 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 626 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
580 up->efr = serial_in(up, UART_EFR); 627 up->efr = serial_in(up, UART_EFR);
@@ -584,8 +631,7 @@ serial_omap_configure_xonxoff
584 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 631 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
585 632
586 /* clear SW control mode bits */ 633 /* clear SW control mode bits */
587 efr = up->efr; 634 up->efr &= OMAP_UART_SW_CLR;
588 efr &= OMAP_UART_SW_CLR;
589 635
590 /* 636 /*
591 * IXON Flag: 637 * IXON Flag:
@@ -593,7 +639,7 @@ serial_omap_configure_xonxoff
593 * Transmit XON1, XOFF1 639 * Transmit XON1, XOFF1
594 */ 640 */
595 if (termios->c_iflag & IXON) 641 if (termios->c_iflag & IXON)
596 efr |= OMAP_UART_SW_TX; 642 up->efr |= OMAP_UART_SW_TX;
597 643
598 /* 644 /*
599 * IXOFF Flag: 645 * IXOFF Flag:
@@ -601,7 +647,7 @@ serial_omap_configure_xonxoff
601 * Receiver compares XON1, XOFF1. 647 * Receiver compares XON1, XOFF1.
602 */ 648 */
603 if (termios->c_iflag & IXOFF) 649 if (termios->c_iflag & IXOFF)
604 efr |= OMAP_UART_SW_RX; 650 up->efr |= OMAP_UART_SW_RX;
605 651
606 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 652 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
607 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 653 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
@@ -624,13 +670,21 @@ serial_omap_configure_xonxoff
624 * load the new software flow control mode IXON or IXOFF 670 * load the new software flow control mode IXON or IXOFF
625 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. 671 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
626 */ 672 */
627 serial_out(up, UART_EFR, efr | UART_EFR_SCD); 673 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
628 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 674 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
629 675
630 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); 676 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
631 serial_out(up, UART_LCR, up->lcr); 677 serial_out(up, UART_LCR, up->lcr);
632} 678}
633 679
680static void serial_omap_uart_qos_work(struct work_struct *work)
681{
682 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
683 qos_work);
684
685 pm_qos_update_request(&up->pm_qos_request, up->latency);
686}
687
634static void 688static void
635serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 689serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
636 struct ktermios *old) 690 struct ktermios *old)
@@ -671,6 +725,16 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
671 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 725 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
672 quot = serial_omap_get_divisor(port, baud); 726 quot = serial_omap_get_divisor(port, baud);
673 727
728 /* calculate wakeup latency constraint */
729 up->calc_latency = (1000000 * up->port.fifosize) /
730 (1000 * baud / 8);
731 up->latency = up->calc_latency;
732 schedule_work(&up->qos_work);
733
734 up->dll = quot & 0xff;
735 up->dlh = quot >> 8;
736 up->mdr1 = UART_OMAP_MDR1_DISABLE;
737
674 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 738 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
675 UART_FCR_ENABLE_FIFO; 739 UART_FCR_ENABLE_FIFO;
676 if (up->use_dma) 740 if (up->use_dma)
@@ -680,6 +744,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
680 * Ok, we're now changing the port state. Do it with 744 * Ok, we're now changing the port state. Do it with
681 * interrupts disabled. 745 * interrupts disabled.
682 */ 746 */
747 pm_runtime_get_sync(&up->pdev->dev);
683 spin_lock_irqsave(&up->port.lock, flags); 748 spin_lock_irqsave(&up->port.lock, flags);
684 749
685 /* 750 /*
@@ -723,6 +788,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
723 up->ier |= UART_IER_MSI; 788 up->ier |= UART_IER_MSI;
724 serial_out(up, UART_IER, up->ier); 789 serial_out(up, UART_IER, up->ier);
725 serial_out(up, UART_LCR, cval); /* reset DLAB */ 790 serial_out(up, UART_LCR, cval); /* reset DLAB */
791 up->lcr = cval;
792 up->scr = OMAP_UART_SCR_TX_EMPTY;
726 793
727 /* FIFOs and DMA Settings */ 794 /* FIFOs and DMA Settings */
728 795
@@ -749,17 +816,22 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
749 816
750 if (up->use_dma) { 817 if (up->use_dma) {
751 serial_out(up, UART_TI752_TLR, 0); 818 serial_out(up, UART_TI752_TLR, 0);
752 serial_out(up, UART_OMAP_SCR, 819 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
753 (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
754 } 820 }
755 821
822 serial_out(up, UART_OMAP_SCR, up->scr);
823
756 serial_out(up, UART_EFR, up->efr); 824 serial_out(up, UART_EFR, up->efr);
757 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 825 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
758 serial_out(up, UART_MCR, up->mcr); 826 serial_out(up, UART_MCR, up->mcr);
759 827
760 /* Protocol, Baud Rate, and Interrupt Settings */ 828 /* Protocol, Baud Rate, and Interrupt Settings */
761 829
762 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 830 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
831 serial_omap_mdr1_errataset(up, up->mdr1);
832 else
833 serial_out(up, UART_OMAP_MDR1, up->mdr1);
834
763 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
764 836
765 up->efr = serial_in(up, UART_EFR); 837 up->efr = serial_in(up, UART_EFR);
@@ -769,8 +841,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
769 serial_out(up, UART_IER, 0); 841 serial_out(up, UART_IER, 0);
770 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
771 843
772 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ 844 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
773 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ 845 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
774 846
775 serial_out(up, UART_LCR, 0); 847 serial_out(up, UART_LCR, 0);
776 serial_out(up, UART_IER, up->ier); 848 serial_out(up, UART_IER, up->ier);
@@ -780,9 +852,14 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
780 serial_out(up, UART_LCR, cval); 852 serial_out(up, UART_LCR, cval);
781 853
782 if (baud > 230400 && baud != 3000000) 854 if (baud > 230400 && baud != 3000000)
783 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE); 855 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
784 else 856 else
785 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); 857 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
858
859 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
860 serial_omap_mdr1_errataset(up, up->mdr1);
861 else
862 serial_out(up, UART_OMAP_MDR1, up->mdr1);
786 863
787 /* Hardware Flow Control Configuration */ 864 /* Hardware Flow Control Configuration */
788 865
@@ -809,7 +886,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
809 serial_omap_configure_xonxoff(up, termios); 886 serial_omap_configure_xonxoff(up, termios);
810 887
811 spin_unlock_irqrestore(&up->port.lock, flags); 888 spin_unlock_irqrestore(&up->port.lock, flags);
812 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); 889 pm_runtime_put(&up->pdev->dev);
890 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
813} 891}
814 892
815static void 893static void
@@ -819,7 +897,9 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
819 struct uart_omap_port *up = (struct uart_omap_port *)port; 897 struct uart_omap_port *up = (struct uart_omap_port *)port;
820 unsigned char efr; 898 unsigned char efr;
821 899
822 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); 900 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
901
902 pm_runtime_get_sync(&up->pdev->dev);
823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
824 efr = serial_in(up, UART_EFR); 904 efr = serial_in(up, UART_EFR);
825 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 905 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
@@ -829,6 +909,15 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
829 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
830 serial_out(up, UART_EFR, efr); 910 serial_out(up, UART_EFR, efr);
831 serial_out(up, UART_LCR, 0); 911 serial_out(up, UART_LCR, 0);
912
913 if (!device_may_wakeup(&up->pdev->dev)) {
914 if (!state)
915 pm_runtime_forbid(&up->pdev->dev);
916 else
917 pm_runtime_allow(&up->pdev->dev);
918 }
919
920 pm_runtime_put(&up->pdev->dev);
832} 921}
833 922
834static void serial_omap_release_port(struct uart_port *port) 923static void serial_omap_release_port(struct uart_port *port)
@@ -847,7 +936,7 @@ static void serial_omap_config_port(struct uart_port *port, int flags)
847 struct uart_omap_port *up = (struct uart_omap_port *)port; 936 struct uart_omap_port *up = (struct uart_omap_port *)port;
848 937
849 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 938 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
850 up->pdev->id); 939 up->port.line);
851 up->port.type = PORT_OMAP; 940 up->port.type = PORT_OMAP;
852} 941}
853 942
@@ -864,7 +953,7 @@ serial_omap_type(struct uart_port *port)
864{ 953{
865 struct uart_omap_port *up = (struct uart_omap_port *)port; 954 struct uart_omap_port *up = (struct uart_omap_port *)port;
866 955
867 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); 956 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
868 return up->name; 957 return up->name;
869} 958}
870 959
@@ -906,19 +995,26 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
906static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 995static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
907{ 996{
908 struct uart_omap_port *up = (struct uart_omap_port *)port; 997 struct uart_omap_port *up = (struct uart_omap_port *)port;
998
999 pm_runtime_get_sync(&up->pdev->dev);
909 wait_for_xmitr(up); 1000 wait_for_xmitr(up);
910 serial_out(up, UART_TX, ch); 1001 serial_out(up, UART_TX, ch);
1002 pm_runtime_put(&up->pdev->dev);
911} 1003}
912 1004
913static int serial_omap_poll_get_char(struct uart_port *port) 1005static int serial_omap_poll_get_char(struct uart_port *port)
914{ 1006{
915 struct uart_omap_port *up = (struct uart_omap_port *)port; 1007 struct uart_omap_port *up = (struct uart_omap_port *)port;
916 unsigned int status = serial_in(up, UART_LSR); 1008 unsigned int status;
917 1009
1010 pm_runtime_get_sync(&up->pdev->dev);
1011 status = serial_in(up, UART_LSR);
918 if (!(status & UART_LSR_DR)) 1012 if (!(status & UART_LSR_DR))
919 return NO_POLL_CHAR; 1013 return NO_POLL_CHAR;
920 1014
921 return serial_in(up, UART_RX); 1015 status = serial_in(up, UART_RX);
1016 pm_runtime_put(&up->pdev->dev);
1017 return status;
922} 1018}
923 1019
924#endif /* CONFIG_CONSOLE_POLL */ 1020#endif /* CONFIG_CONSOLE_POLL */
@@ -946,6 +1042,8 @@ serial_omap_console_write(struct console *co, const char *s,
946 unsigned int ier; 1042 unsigned int ier;
947 int locked = 1; 1043 int locked = 1;
948 1044
1045 pm_runtime_get_sync(&up->pdev->dev);
1046
949 local_irq_save(flags); 1047 local_irq_save(flags);
950 if (up->port.sysrq) 1048 if (up->port.sysrq)
951 locked = 0; 1049 locked = 0;
@@ -978,6 +1076,8 @@ serial_omap_console_write(struct console *co, const char *s,
978 if (up->msr_saved_flags) 1076 if (up->msr_saved_flags)
979 check_modem_status(up); 1077 check_modem_status(up);
980 1078
1079 pm_runtime_mark_last_busy(&up->pdev->dev);
1080 pm_runtime_put_autosuspend(&up->pdev->dev);
981 if (locked) 1081 if (locked)
982 spin_unlock(&up->port.lock); 1082 spin_unlock(&up->port.lock);
983 local_irq_restore(flags); 1083 local_irq_restore(flags);
@@ -1014,7 +1114,7 @@ static struct console serial_omap_console = {
1014 1114
1015static void serial_omap_add_console_port(struct uart_omap_port *up) 1115static void serial_omap_add_console_port(struct uart_omap_port *up)
1016{ 1116{
1017 serial_omap_console_ports[up->pdev->id] = up; 1117 serial_omap_console_ports[up->port.line] = up;
1018} 1118}
1019 1119
1020#define OMAP_CONSOLE (&serial_omap_console) 1120#define OMAP_CONSOLE (&serial_omap_console)
@@ -1060,26 +1160,30 @@ static struct uart_driver serial_omap_reg = {
1060 .cons = OMAP_CONSOLE, 1160 .cons = OMAP_CONSOLE,
1061}; 1161};
1062 1162
1063static int 1163#ifdef CONFIG_SUSPEND
1064serial_omap_suspend(struct platform_device *pdev, pm_message_t state) 1164static int serial_omap_suspend(struct device *dev)
1065{ 1165{
1066 struct uart_omap_port *up = platform_get_drvdata(pdev); 1166 struct uart_omap_port *up = dev_get_drvdata(dev);
1067 1167
1068 if (up) 1168 if (up) {
1069 uart_suspend_port(&serial_omap_reg, &up->port); 1169 uart_suspend_port(&serial_omap_reg, &up->port);
1170 flush_work_sync(&up->qos_work);
1171 }
1172
1070 return 0; 1173 return 0;
1071} 1174}
1072 1175
1073static int serial_omap_resume(struct platform_device *dev) 1176static int serial_omap_resume(struct device *dev)
1074{ 1177{
1075 struct uart_omap_port *up = platform_get_drvdata(dev); 1178 struct uart_omap_port *up = dev_get_drvdata(dev);
1076 1179
1077 if (up) 1180 if (up)
1078 uart_resume_port(&serial_omap_reg, &up->port); 1181 uart_resume_port(&serial_omap_reg, &up->port);
1079 return 0; 1182 return 0;
1080} 1183}
1184#endif
1081 1185
1082static void serial_omap_rx_timeout(unsigned long uart_no) 1186static void serial_omap_rxdma_poll(unsigned long uart_no)
1083{ 1187{
1084 struct uart_omap_port *up = ui[uart_no]; 1188 struct uart_omap_port *up = ui[uart_no];
1085 unsigned int curr_dma_pos, curr_transmitted_size; 1189 unsigned int curr_dma_pos, curr_transmitted_size;
@@ -1089,9 +1193,9 @@ static void serial_omap_rx_timeout(unsigned long uart_no)
1089 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || 1193 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1090 (curr_dma_pos == 0)) { 1194 (curr_dma_pos == 0)) {
1091 if (jiffies_to_msecs(jiffies - up->port_activity) < 1195 if (jiffies_to_msecs(jiffies - up->port_activity) <
1092 RX_TIMEOUT) { 1196 up->uart_dma.rx_timeout) {
1093 mod_timer(&up->uart_dma.rx_timer, jiffies + 1197 mod_timer(&up->uart_dma.rx_timer, jiffies +
1094 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1198 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1095 } else { 1199 } else {
1096 serial_omap_stop_rxdma(up); 1200 serial_omap_stop_rxdma(up);
1097 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1201 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
@@ -1120,7 +1224,7 @@ static void serial_omap_rx_timeout(unsigned long uart_no)
1120 } 1224 }
1121 } else { 1225 } else {
1122 mod_timer(&up->uart_dma.rx_timer, jiffies + 1226 mod_timer(&up->uart_dma.rx_timer, jiffies +
1123 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1227 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1124 } 1228 }
1125 up->port_activity = jiffies; 1229 up->port_activity = jiffies;
1126} 1230}
@@ -1135,6 +1239,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
1135 int ret = 0; 1239 int ret = 0;
1136 1240
1137 if (up->uart_dma.rx_dma_channel == -1) { 1241 if (up->uart_dma.rx_dma_channel == -1) {
1242 pm_runtime_get_sync(&up->pdev->dev);
1138 ret = omap_request_dma(up->uart_dma.uart_dma_rx, 1243 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1139 "UART Rx DMA", 1244 "UART Rx DMA",
1140 (void *)uart_rx_dma_callback, up, 1245 (void *)uart_rx_dma_callback, up,
@@ -1158,7 +1263,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
1158 /* FIXME: Cache maintenance needed here? */ 1263 /* FIXME: Cache maintenance needed here? */
1159 omap_start_dma(up->uart_dma.rx_dma_channel); 1264 omap_start_dma(up->uart_dma.rx_dma_channel);
1160 mod_timer(&up->uart_dma.rx_timer, jiffies + 1265 mod_timer(&up->uart_dma.rx_timer, jiffies +
1161 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1266 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1162 up->uart_dma.rx_dma_used = true; 1267 up->uart_dma.rx_dma_used = true;
1163 return ret; 1268 return ret;
1164} 1269}
@@ -1221,6 +1326,19 @@ static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1221 return; 1326 return;
1222} 1327}
1223 1328
1329static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1330{
1331 struct omap_uart_port_info *omap_up_info;
1332
1333 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1334 if (!omap_up_info)
1335 return NULL; /* out of memory */
1336
1337 of_property_read_u32(dev->of_node, "clock-frequency",
1338 &omap_up_info->uartclk);
1339 return omap_up_info;
1340}
1341
1224static int serial_omap_probe(struct platform_device *pdev) 1342static int serial_omap_probe(struct platform_device *pdev)
1225{ 1343{
1226 struct uart_omap_port *up; 1344 struct uart_omap_port *up;
@@ -1228,6 +1346,9 @@ static int serial_omap_probe(struct platform_device *pdev)
1228 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1346 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1229 int ret = -ENOSPC; 1347 int ret = -ENOSPC;
1230 1348
1349 if (pdev->dev.of_node)
1350 omap_up_info = of_get_uart_port_info(&pdev->dev);
1351
1231 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1352 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232 if (!mem) { 1353 if (!mem) {
1233 dev_err(&pdev->dev, "no mem resource?\n"); 1354 dev_err(&pdev->dev, "no mem resource?\n");
@@ -1263,7 +1384,6 @@ static int serial_omap_probe(struct platform_device *pdev)
1263 ret = -ENOMEM; 1384 ret = -ENOMEM;
1264 goto do_release_region; 1385 goto do_release_region;
1265 } 1386 }
1266 sprintf(up->name, "OMAP UART%d", pdev->id);
1267 up->pdev = pdev; 1387 up->pdev = pdev;
1268 up->port.dev = &pdev->dev; 1388 up->port.dev = &pdev->dev;
1269 up->port.type = PORT_OMAP; 1389 up->port.type = PORT_OMAP;
@@ -1273,34 +1393,74 @@ static int serial_omap_probe(struct platform_device *pdev)
1273 up->port.regshift = 2; 1393 up->port.regshift = 2;
1274 up->port.fifosize = 64; 1394 up->port.fifosize = 64;
1275 up->port.ops = &serial_omap_pops; 1395 up->port.ops = &serial_omap_pops;
1276 up->port.line = pdev->id;
1277 1396
1278 up->port.membase = omap_up_info->membase; 1397 if (pdev->dev.of_node)
1279 up->port.mapbase = omap_up_info->mapbase; 1398 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1399 else
1400 up->port.line = pdev->id;
1401
1402 if (up->port.line < 0) {
1403 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1404 up->port.line);
1405 ret = -ENODEV;
1406 goto err;
1407 }
1408
1409 sprintf(up->name, "OMAP UART%d", up->port.line);
1410 up->port.mapbase = mem->start;
1411 up->port.membase = ioremap(mem->start, resource_size(mem));
1412 if (!up->port.membase) {
1413 dev_err(&pdev->dev, "can't ioremap UART\n");
1414 ret = -ENOMEM;
1415 goto err;
1416 }
1417
1280 up->port.flags = omap_up_info->flags; 1418 up->port.flags = omap_up_info->flags;
1281 up->port.irqflags = omap_up_info->irqflags;
1282 up->port.uartclk = omap_up_info->uartclk; 1419 up->port.uartclk = omap_up_info->uartclk;
1420 if (!up->port.uartclk) {
1421 up->port.uartclk = DEFAULT_CLK_SPEED;
1422 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1423 "%d\n", DEFAULT_CLK_SPEED);
1424 }
1283 up->uart_dma.uart_base = mem->start; 1425 up->uart_dma.uart_base = mem->start;
1426 up->errata = omap_up_info->errata;
1284 1427
1285 if (omap_up_info->dma_enabled) { 1428 if (omap_up_info->dma_enabled) {
1286 up->uart_dma.uart_dma_tx = dma_tx->start; 1429 up->uart_dma.uart_dma_tx = dma_tx->start;
1287 up->uart_dma.uart_dma_rx = dma_rx->start; 1430 up->uart_dma.uart_dma_rx = dma_rx->start;
1288 up->use_dma = 1; 1431 up->use_dma = 1;
1289 up->uart_dma.rx_buf_size = 4096; 1432 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1290 up->uart_dma.rx_timeout = 2; 1433 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1434 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1291 spin_lock_init(&(up->uart_dma.tx_lock)); 1435 spin_lock_init(&(up->uart_dma.tx_lock));
1292 spin_lock_init(&(up->uart_dma.rx_lock)); 1436 spin_lock_init(&(up->uart_dma.rx_lock));
1293 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 1437 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1294 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 1438 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1295 } 1439 }
1296 1440
1297 ui[pdev->id] = up; 1441 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1442 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1443 pm_qos_add_request(&up->pm_qos_request,
1444 PM_QOS_CPU_DMA_LATENCY, up->latency);
1445 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1446 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1447
1448 pm_runtime_use_autosuspend(&pdev->dev);
1449 pm_runtime_set_autosuspend_delay(&pdev->dev,
1450 omap_up_info->autosuspend_timeout);
1451
1452 pm_runtime_irq_safe(&pdev->dev);
1453 pm_runtime_enable(&pdev->dev);
1454 pm_runtime_get_sync(&pdev->dev);
1455
1456 ui[up->port.line] = up;
1298 serial_omap_add_console_port(up); 1457 serial_omap_add_console_port(up);
1299 1458
1300 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1459 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1301 if (ret != 0) 1460 if (ret != 0)
1302 goto do_release_region; 1461 goto do_release_region;
1303 1462
1463 pm_runtime_put(&pdev->dev);
1304 platform_set_drvdata(pdev, up); 1464 platform_set_drvdata(pdev, up);
1305 return 0; 1465 return 0;
1306err: 1466err:
@@ -1315,22 +1475,168 @@ static int serial_omap_remove(struct platform_device *dev)
1315{ 1475{
1316 struct uart_omap_port *up = platform_get_drvdata(dev); 1476 struct uart_omap_port *up = platform_get_drvdata(dev);
1317 1477
1318 platform_set_drvdata(dev, NULL);
1319 if (up) { 1478 if (up) {
1479 pm_runtime_disable(&up->pdev->dev);
1320 uart_remove_one_port(&serial_omap_reg, &up->port); 1480 uart_remove_one_port(&serial_omap_reg, &up->port);
1481 pm_qos_remove_request(&up->pm_qos_request);
1482
1321 kfree(up); 1483 kfree(up);
1322 } 1484 }
1485
1486 platform_set_drvdata(dev, NULL);
1487 return 0;
1488}
1489
1490/*
1491 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1492 * The access to uart register after MDR1 Access
1493 * causes UART to corrupt data.
1494 *
1495 * Need a delay =
1496 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1497 * give 10 times as much
1498 */
1499static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1500{
1501 u8 timeout = 255;
1502
1503 serial_out(up, UART_OMAP_MDR1, mdr1);
1504 udelay(2);
1505 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1506 UART_FCR_CLEAR_RCVR);
1507 /*
1508 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1509 * TX_FIFO_E bit is 1.
1510 */
1511 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1512 (UART_LSR_THRE | UART_LSR_DR))) {
1513 timeout--;
1514 if (!timeout) {
1515 /* Should *never* happen. we warn and carry on */
1516 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1517 serial_in(up, UART_LSR));
1518 break;
1519 }
1520 udelay(1);
1521 }
1522}
1523
1524static void serial_omap_restore_context(struct uart_omap_port *up)
1525{
1526 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1527 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1528 else
1529 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1530
1531 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1532 serial_out(up, UART_EFR, UART_EFR_ECB);
1533 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1534 serial_out(up, UART_IER, 0x0);
1535 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1536 serial_out(up, UART_DLL, up->dll);
1537 serial_out(up, UART_DLM, up->dlh);
1538 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1539 serial_out(up, UART_IER, up->ier);
1540 serial_out(up, UART_FCR, up->fcr);
1541 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1542 serial_out(up, UART_MCR, up->mcr);
1543 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1544 serial_out(up, UART_OMAP_SCR, up->scr);
1545 serial_out(up, UART_EFR, up->efr);
1546 serial_out(up, UART_LCR, up->lcr);
1547 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1548 serial_omap_mdr1_errataset(up, up->mdr1);
1549 else
1550 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1551}
1552
1553#ifdef CONFIG_PM_RUNTIME
1554static int serial_omap_runtime_suspend(struct device *dev)
1555{
1556 struct uart_omap_port *up = dev_get_drvdata(dev);
1557 struct omap_uart_port_info *pdata = dev->platform_data;
1558
1559 if (!up)
1560 return -EINVAL;
1561
1562 if (!pdata || !pdata->enable_wakeup)
1563 return 0;
1564
1565 if (pdata->get_context_loss_count)
1566 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1567
1568 if (device_may_wakeup(dev)) {
1569 if (!up->wakeups_enabled) {
1570 pdata->enable_wakeup(up->pdev, true);
1571 up->wakeups_enabled = true;
1572 }
1573 } else {
1574 if (up->wakeups_enabled) {
1575 pdata->enable_wakeup(up->pdev, false);
1576 up->wakeups_enabled = false;
1577 }
1578 }
1579
1580 /* Errata i291 */
1581 if (up->use_dma && pdata->set_forceidle &&
1582 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1583 pdata->set_forceidle(up->pdev);
1584
1585 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1586 schedule_work(&up->qos_work);
1587
1588 return 0;
1589}
1590
1591static int serial_omap_runtime_resume(struct device *dev)
1592{
1593 struct uart_omap_port *up = dev_get_drvdata(dev);
1594 struct omap_uart_port_info *pdata = dev->platform_data;
1595
1596 if (up) {
1597 if (pdata->get_context_loss_count) {
1598 u32 loss_cnt = pdata->get_context_loss_count(dev);
1599
1600 if (up->context_loss_cnt != loss_cnt)
1601 serial_omap_restore_context(up);
1602 }
1603
1604 /* Errata i291 */
1605 if (up->use_dma && pdata->set_noidle &&
1606 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1607 pdata->set_noidle(up->pdev);
1608
1609 up->latency = up->calc_latency;
1610 schedule_work(&up->qos_work);
1611 }
1612
1323 return 0; 1613 return 0;
1324} 1614}
1615#endif
1616
1617static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1618 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1619 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1620 serial_omap_runtime_resume, NULL)
1621};
1622
1623#if defined(CONFIG_OF)
1624static const struct of_device_id omap_serial_of_match[] = {
1625 { .compatible = "ti,omap2-uart" },
1626 { .compatible = "ti,omap3-uart" },
1627 { .compatible = "ti,omap4-uart" },
1628 {},
1629};
1630MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1631#endif
1325 1632
1326static struct platform_driver serial_omap_driver = { 1633static struct platform_driver serial_omap_driver = {
1327 .probe = serial_omap_probe, 1634 .probe = serial_omap_probe,
1328 .remove = serial_omap_remove, 1635 .remove = serial_omap_remove,
1329
1330 .suspend = serial_omap_suspend,
1331 .resume = serial_omap_resume,
1332 .driver = { 1636 .driver = {
1333 .name = DRIVER_NAME, 1637 .name = DRIVER_NAME,
1638 .pm = &serial_omap_dev_pm_ops,
1639 .of_match_table = of_match_ptr(omap_serial_of_match),
1334 }, 1640 },
1335}; 1641};
1336 1642
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 13:38:48 -0500