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authorArnd Bergmann <arnd@arndb.de>2014-09-26 08:15:54 -0400
committerArnd Bergmann <arnd@arndb.de>2014-09-26 08:17:26 -0400
commit3a75d1ad9a14dfbc8ea02824457729b79444e74f (patch)
treea688bb45040a9eda7c046d853419bd361edb0b3c
parent32bb231845325ca4d19bba414f8883f3e0d6436f (diff)
Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt"
Apparently most of the newly added nodes had the same problem, so instead of reverting the individual patches, this undoes the effect of the merge and backs out all of them at once. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2-dkb.dts33
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2.dtsi301
2 files changed, 0 insertions, 334 deletions
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 375a10c6e88b..05b44c272c9a 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,36 +51,3 @@
51&uart0 { 51&uart0 {
52 status = "okay"; 52 status = "okay";
53}; 53};
54
55&gmac0 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 phy-handle = <&phy2>;
59 phy-mode = "mii";
60 /* Placeholder, overwritten by bootloader */
61 mac-address = [00 00 00 00 00 00];
62 status = "okay";
63
64 phy2: ethernet-phy@2 {
65 reg = <2>;
66 };
67};
68
69&gmac1 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 phy-handle = <&phy1>;
73 phy-mode = "rgmii";
74 /* Placeholder, overwritten by bootloader */
75 mac-address = [00 00 00 00 00 00];
76 status = "okay";
77
78 phy1: ethernet-phy@1 {
79 reg = <1>;
80 };
81};
82
83&ahci {
84 phys = <&sata_phy>;
85 phy-names = "sata-phy";
86};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 152f3ad1af6b..f85ba2924ff7 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,240 +131,6 @@
131 clock-names = "apb_pclk"; 131 clock-names = "apb_pclk";
132 status = "disabled"; 132 status = "disabled";
133 }; 133 };
134
135 gpio0: gpio@b20000 {
136 compatible = "arm,pl061", "arm,primecell";
137 reg = <0xb20000 0x1000>;
138 interrupts = <0 108 0x4>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 clocks = <&clock HIX5HD2_FIXED_100M>;
142 clock-names = "apb_pclk";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 status = "disabled";
146 };
147
148 gpio1: gpio@b21000 {
149 compatible = "arm,pl061", "arm,primecell";
150 reg = <0xb21000 0x1000>;
151 interrupts = <0 109 0x4>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 clocks = <&clock HIX5HD2_FIXED_100M>;
155 clock-names = "apb_pclk";
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 status = "disabled";
159 };
160
161 gpio2: gpio@b22000 {
162 compatible = "arm,pl061", "arm,primecell";
163 reg = <0xb22000 0x1000>;
164 interrupts = <0 110 0x4>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 clocks = <&clock HIX5HD2_FIXED_100M>;
168 clock-names = "apb_pclk";
169 interrupt-controller;
170 #interrupt-cells = <2>;
171 status = "disabled";
172 };
173
174 gpio3: gpio@b23000 {
175 compatible = "arm,pl061", "arm,primecell";
176 reg = <0xb23000 0x1000>;
177 interrupts = <0 111 0x4>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 clocks = <&clock HIX5HD2_FIXED_100M>;
181 clock-names = "apb_pclk";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 status = "disabled";
185 };
186
187 gpio4: gpio@b24000 {
188 compatible = "arm,pl061", "arm,primecell";
189 reg = <0xb24000 0x1000>;
190 interrupts = <0 112 0x4>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 clocks = <&clock HIX5HD2_FIXED_100M>;
194 clock-names = "apb_pclk";
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 status = "disabled";
198 };
199
200 gpio5: gpio@004000 {
201 compatible = "arm,pl061", "arm,primecell";
202 reg = <0x004000 0x1000>;
203 interrupts = <0 113 0x4>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 clocks = <&clock HIX5HD2_FIXED_100M>;
207 clock-names = "apb_pclk";
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 status = "disabled";
211 };
212
213 gpio6: gpio@b26000 {
214 compatible = "arm,pl061", "arm,primecell";
215 reg = <0xb26000 0x1000>;
216 interrupts = <0 114 0x4>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 clocks = <&clock HIX5HD2_FIXED_100M>;
220 clock-names = "apb_pclk";
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 status = "disabled";
224 };
225
226 gpio7: gpio@b27000 {
227 compatible = "arm,pl061", "arm,primecell";
228 reg = <0xb27000 0x1000>;
229 interrupts = <0 115 0x4>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 clocks = <&clock HIX5HD2_FIXED_100M>;
233 clock-names = "apb_pclk";
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 status = "disabled";
237 };
238
239 gpio8: gpio@b28000 {
240 compatible = "arm,pl061", "arm,primecell";
241 reg = <0xb28000 0x1000>;
242 interrupts = <0 116 0x4>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 clocks = <&clock HIX5HD2_FIXED_100M>;
246 clock-names = "apb_pclk";
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 status = "disabled";
250 };
251
252 gpio9: gpio@b29000 {
253 compatible = "arm,pl061", "arm,primecell";
254 reg = <0xb29000 0x1000>;
255 interrupts = <0 117 0x4>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 clocks = <&clock HIX5HD2_FIXED_100M>;
259 clock-names = "apb_pclk";
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 status = "disabled";
263 };
264
265 gpio10: gpio@b2a000 {
266 compatible = "arm,pl061", "arm,primecell";
267 reg = <0xb2a000 0x1000>;
268 interrupts = <0 118 0x4>;
269 gpio-controller;
270 #gpio-cells = <2>;
271 clocks = <&clock HIX5HD2_FIXED_100M>;
272 clock-names = "apb_pclk";
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 status = "disabled";
276 };
277
278 gpio11: gpio@b2b000 {
279 compatible = "arm,pl061", "arm,primecell";
280 reg = <0xb2b000 0x1000>;
281 interrupts = <0 119 0x4>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 clocks = <&clock HIX5HD2_FIXED_100M>;
285 clock-names = "apb_pclk";
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 status = "disabled";
289 };
290
291 gpio12: gpio@b2c000 {
292 compatible = "arm,pl061", "arm,primecell";
293 reg = <0xb2c000 0x1000>;
294 interrupts = <0 120 0x4>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 clocks = <&clock HIX5HD2_FIXED_100M>;
298 clock-names = "apb_pclk";
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 status = "disabled";
302 };
303
304 gpio13: gpio@b2d000 {
305 compatible = "arm,pl061", "arm,primecell";
306 reg = <0xb2d000 0x1000>;
307 interrupts = <0 121 0x4>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 clocks = <&clock HIX5HD2_FIXED_100M>;
311 clock-names = "apb_pclk";
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 status = "disabled";
315 };
316
317 gpio14: gpio@b2e000 {
318 compatible = "arm,pl061", "arm,primecell";
319 reg = <0xb2e000 0x1000>;
320 interrupts = <0 122 0x4>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 clocks = <&clock HIX5HD2_FIXED_100M>;
324 clock-names = "apb_pclk";
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 status = "disabled";
328 };
329
330 gpio15: gpio@b2f000 {
331 compatible = "arm,pl061", "arm,primecell";
332 reg = <0xb2f000 0x1000>;
333 interrupts = <0 123 0x4>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 clocks = <&clock HIX5HD2_FIXED_100M>;
337 clock-names = "apb_pclk";
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 status = "disabled";
341 };
342
343 gpio16: gpio@b30000 {
344 compatible = "arm,pl061", "arm,primecell";
345 reg = <0xb30000 0x1000>;
346 interrupts = <0 124 0x4>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 clocks = <&clock HIX5HD2_FIXED_100M>;
350 clock-names = "apb_pclk";
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 status = "disabled";
354 };
355
356 gpio17: gpio@b31000 {
357 compatible = "arm,pl061", "arm,primecell";
358 reg = <0xb31000 0x1000>;
359 interrupts = <0 125 0x4>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 clocks = <&clock HIX5HD2_FIXED_100M>;
363 clock-names = "apb_pclk";
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 status = "disabled";
367 };
368 }; 134 };
369 135
370 local_timer@00a00600 { 136 local_timer@00a00600 {
@@ -400,72 +166,5 @@
400 #clock-cells = <1>; 166 #clock-cells = <1>;
401 }; 167 };
402 }; 168 };
403
404 /* unremovable emmc as mmcblk0 */
405 mmc: mmc@1830000 {
406 compatible = "snps,dw-mshc";
407 reg = <0x1830000 0x1000>;
408 interrupts = <0 35 4>;
409 clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>;
410 clock-names = "ciu", "biu";
411 };
412
413 sd: mmc@1820000 {
414 compatible = "snps,dw-mshc";
415 reg = <0x1820000 0x1000>;
416 interrupts = <0 34 4>;
417 clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>;
418 clock-names = "ciu","biu";
419 };
420
421 gmac0: ethernet@1840000 {
422 compatible = "hisilicon,hix5hd2-gmac";
423 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
424 interrupts = <0 71 4>;
425 clocks = <&clock HIX5HD2_MAC0_CLK>;
426 status = "disabled";
427 };
428
429 gmac1: ethernet@1841000 {
430 compatible = "hisilicon,hix5hd2-gmac";
431 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
432 interrupts = <0 72 4>;
433 clocks = <&clock HIX5HD2_MAC1_CLK>;
434 status = "disabled";
435 };
436
437 usb0: ehci@1890000 {
438 compatible = "generic-ehci";
439 reg = <0x1890000 0x1000>;
440 interrupts = <0 66 4>;
441 clocks = <&clock HIX5HD2_USB_CLK>;
442 };
443
444 usb1: ohci@1880000 {
445 compatible = "generic-ohci";
446 reg = <0x1880000 0x1000>;
447 interrupts = <0 67 4>;
448 clocks = <&clock HIX5HD2_USB_CLK>;
449 };
450
451 peripheral_ctrl: syscon@a20000 {
452 compatible = "syscon";
453 reg = <0xa20000 0x1000>;
454 };
455
456 sata_phy: phy@1900000 {
457 compatible = "hisilicon,hix5hd2-sata-phy";
458 reg = <0x1900000 0x10000>;
459 #phy-cells = <0>;
460 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
461 hisilicon,power-reg = <0x8 10>;
462 };
463
464 ahci: sata@1900000 {
465 compatible = "hisilicon,hisi-ahci";
466 reg = <0x1900000 0x10000>;
467 interrupts = <0 70 4>;
468 clocks = <&clock HIX5HD2_SATA_CLK>;
469 };
470 }; 169 };
471}; 170};
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