diff options
author | Nishanth Menon <nm@ti.com> | 2014-05-22 16:00:55 -0400 |
---|---|---|
committer | Nishanth Menon <nm@ti.com> | 2014-09-08 11:53:39 -0400 |
commit | 390ddc19e2a56c47b46f11a5ed0a7be8e695dd8a (patch) | |
tree | e6bdc83c0782b270b7ba702bef61f44e99a55636 | |
parent | e3002d1ae16812ba6c1479a25cce77fd0d175838 (diff) |
ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstracted
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/prm44xx.c | 47 |
1 files changed, 38 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index a7f6ea27180a..d4d745e5e64b 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
@@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id) | |||
154 | 154 | ||
155 | u32 omap4_prm_vcvp_read(u8 offset) | 155 | u32 omap4_prm_vcvp_read(u8 offset) |
156 | { | 156 | { |
157 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
158 | |||
159 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
160 | return 0; | ||
161 | |||
157 | return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, | 162 | return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, |
158 | OMAP4430_PRM_DEVICE_INST, offset); | 163 | inst, offset); |
159 | } | 164 | } |
160 | 165 | ||
161 | void omap4_prm_vcvp_write(u32 val, u8 offset) | 166 | void omap4_prm_vcvp_write(u32 val, u8 offset) |
162 | { | 167 | { |
168 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
169 | |||
170 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
171 | return; | ||
172 | |||
163 | omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, | 173 | omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, |
164 | OMAP4430_PRM_DEVICE_INST, offset); | 174 | inst, offset); |
165 | } | 175 | } |
166 | 176 | ||
167 | u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) | 177 | u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) |
168 | { | 178 | { |
179 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
180 | |||
181 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
182 | return 0; | ||
183 | |||
169 | return omap4_prminst_rmw_inst_reg_bits(mask, bits, | 184 | return omap4_prminst_rmw_inst_reg_bits(mask, bits, |
170 | OMAP4430_PRM_PARTITION, | 185 | OMAP4430_PRM_PARTITION, |
171 | OMAP4430_PRM_DEVICE_INST, | 186 | inst, |
172 | offset); | 187 | offset); |
173 | } | 188 | } |
174 | 189 | ||
@@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask) | |||
275 | void omap44xx_prm_reconfigure_io_chain(void) | 290 | void omap44xx_prm_reconfigure_io_chain(void) |
276 | { | 291 | { |
277 | int i = 0; | 292 | int i = 0; |
293 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
294 | |||
295 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
296 | return; | ||
278 | 297 | ||
279 | /* Trigger WUCLKIN enable */ | 298 | /* Trigger WUCLKIN enable */ |
280 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, | 299 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, |
281 | OMAP4430_WUCLK_CTRL_MASK, | 300 | OMAP4430_WUCLK_CTRL_MASK, |
282 | OMAP4430_PRM_DEVICE_INST, | 301 | inst, |
283 | OMAP4_PRM_IO_PMCTRL_OFFSET); | 302 | OMAP4_PRM_IO_PMCTRL_OFFSET); |
284 | omap_test_timeout( | 303 | omap_test_timeout( |
285 | (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | 304 | (((omap4_prm_read_inst_reg(inst, |
286 | OMAP4_PRM_IO_PMCTRL_OFFSET) & | 305 | OMAP4_PRM_IO_PMCTRL_OFFSET) & |
287 | OMAP4430_WUCLK_STATUS_MASK) >> | 306 | OMAP4430_WUCLK_STATUS_MASK) >> |
288 | OMAP4430_WUCLK_STATUS_SHIFT) == 1), | 307 | OMAP4430_WUCLK_STATUS_SHIFT) == 1), |
@@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void) | |||
292 | 311 | ||
293 | /* Trigger WUCLKIN disable */ | 312 | /* Trigger WUCLKIN disable */ |
294 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, | 313 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, |
295 | OMAP4430_PRM_DEVICE_INST, | 314 | inst, |
296 | OMAP4_PRM_IO_PMCTRL_OFFSET); | 315 | OMAP4_PRM_IO_PMCTRL_OFFSET); |
297 | omap_test_timeout( | 316 | omap_test_timeout( |
298 | (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | 317 | (((omap4_prm_read_inst_reg(inst, |
299 | OMAP4_PRM_IO_PMCTRL_OFFSET) & | 318 | OMAP4_PRM_IO_PMCTRL_OFFSET) & |
300 | OMAP4430_WUCLK_STATUS_MASK) >> | 319 | OMAP4430_WUCLK_STATUS_MASK) >> |
301 | OMAP4430_WUCLK_STATUS_SHIFT) == 0), | 320 | OMAP4430_WUCLK_STATUS_SHIFT) == 0), |
@@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void) | |||
316 | */ | 335 | */ |
317 | static void __init omap44xx_prm_enable_io_wakeup(void) | 336 | static void __init omap44xx_prm_enable_io_wakeup(void) |
318 | { | 337 | { |
338 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
339 | |||
340 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
341 | return; | ||
342 | |||
319 | omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, | 343 | omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, |
320 | OMAP4430_GLOBAL_WUEN_MASK, | 344 | OMAP4430_GLOBAL_WUEN_MASK, |
321 | OMAP4430_PRM_DEVICE_INST, | 345 | inst, |
322 | OMAP4_PRM_IO_PMCTRL_OFFSET); | 346 | OMAP4_PRM_IO_PMCTRL_OFFSET); |
323 | } | 347 | } |
324 | 348 | ||
@@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void) | |||
333 | struct prm_reset_src_map *p; | 357 | struct prm_reset_src_map *p; |
334 | u32 r = 0; | 358 | u32 r = 0; |
335 | u32 v; | 359 | u32 v; |
360 | s32 inst = omap4_prmst_get_prm_dev_inst(); | ||
361 | |||
362 | if (inst == PRM_INSTANCE_UNKNOWN) | ||
363 | return 0; | ||
364 | |||
336 | 365 | ||
337 | v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | 366 | v = omap4_prm_read_inst_reg(inst, |
338 | OMAP4_RM_RSTST); | 367 | OMAP4_RM_RSTST); |
339 | 368 | ||
340 | p = omap44xx_prm_reset_src_map; | 369 | p = omap44xx_prm_reset_src_map; |