diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2012-09-11 08:27:20 -0400 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2012-09-21 14:03:44 -0400 |
commit | 383b99610e6084878930d4e4682dfc5e9141b038 (patch) | |
tree | 1a35c3cac8cbb8335ec6dcb632db4ccd7a21dc68 | |
parent | 060f3d191b1d80312d7c90de2f3c3356db413f40 (diff) |
arm: mach-mv78xx0: use IOMEM() for base address definitions
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-mv78xx0 code.
Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r-- | arch/arm/mach-mv78xx0/addr-map.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/common.c | 23 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/irq.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/mpp.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/pcie.c | 12 |
6 files changed, 31 insertions, 24 deletions
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d21..3358f079bcd1 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c | |||
@@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i | |||
47 | * so we don't need to take that into account here. | 47 | * so we don't need to take that into account here. |
48 | */ | 48 | */ |
49 | 49 | ||
50 | return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); | 50 | return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); |
51 | } | 51 | } |
52 | 52 | ||
53 | /* | 53 | /* |
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 3057f7d4329a..c4e3458e0674 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
@@ -130,17 +130,17 @@ static int get_tclk(void) | |||
130 | ****************************************************************************/ | 130 | ****************************************************************************/ |
131 | static struct map_desc mv78xx0_io_desc[] __initdata = { | 131 | static struct map_desc mv78xx0_io_desc[] __initdata = { |
132 | { | 132 | { |
133 | .virtual = MV78XX0_CORE_REGS_VIRT_BASE, | 133 | .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, |
134 | .pfn = 0, | 134 | .pfn = 0, |
135 | .length = MV78XX0_CORE_REGS_SIZE, | 135 | .length = MV78XX0_CORE_REGS_SIZE, |
136 | .type = MT_DEVICE, | 136 | .type = MT_DEVICE, |
137 | }, { | 137 | }, { |
138 | .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), | 138 | .virtual = (unsigned long) MV78XX0_PCIE_IO_VIRT_BASE(0), |
139 | .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), | 139 | .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), |
140 | .length = MV78XX0_PCIE_IO_SIZE * 8, | 140 | .length = MV78XX0_PCIE_IO_SIZE * 8, |
141 | .type = MT_DEVICE, | 141 | .type = MT_DEVICE, |
142 | }, { | 142 | }, { |
143 | .virtual = MV78XX0_REGS_VIRT_BASE, | 143 | .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, |
144 | .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), | 144 | .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), |
145 | .length = MV78XX0_REGS_SIZE, | 145 | .length = MV78XX0_REGS_SIZE, |
146 | .type = MT_DEVICE, | 146 | .type = MT_DEVICE, |
@@ -300,7 +300,8 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) | |||
300 | ****************************************************************************/ | 300 | ****************************************************************************/ |
301 | void __init mv78xx0_uart0_init(void) | 301 | void __init mv78xx0_uart0_init(void) |
302 | { | 302 | { |
303 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, | 303 | orion_uart0_init((unsigned long) UART0_VIRT_BASE, |
304 | UART0_PHYS_BASE, | ||
304 | IRQ_MV78XX0_UART_0, tclk); | 305 | IRQ_MV78XX0_UART_0, tclk); |
305 | } | 306 | } |
306 | 307 | ||
@@ -310,7 +311,8 @@ void __init mv78xx0_uart0_init(void) | |||
310 | ****************************************************************************/ | 311 | ****************************************************************************/ |
311 | void __init mv78xx0_uart1_init(void) | 312 | void __init mv78xx0_uart1_init(void) |
312 | { | 313 | { |
313 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, | 314 | orion_uart1_init((unsigned long) UART1_VIRT_BASE, |
315 | UART1_PHYS_BASE, | ||
314 | IRQ_MV78XX0_UART_1, tclk); | 316 | IRQ_MV78XX0_UART_1, tclk); |
315 | } | 317 | } |
316 | 318 | ||
@@ -320,7 +322,8 @@ void __init mv78xx0_uart1_init(void) | |||
320 | ****************************************************************************/ | 322 | ****************************************************************************/ |
321 | void __init mv78xx0_uart2_init(void) | 323 | void __init mv78xx0_uart2_init(void) |
322 | { | 324 | { |
323 | orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, | 325 | orion_uart2_init((unsigned long) UART2_VIRT_BASE, |
326 | UART2_PHYS_BASE, | ||
324 | IRQ_MV78XX0_UART_2, tclk); | 327 | IRQ_MV78XX0_UART_2, tclk); |
325 | } | 328 | } |
326 | 329 | ||
@@ -329,7 +332,8 @@ void __init mv78xx0_uart2_init(void) | |||
329 | ****************************************************************************/ | 332 | ****************************************************************************/ |
330 | void __init mv78xx0_uart3_init(void) | 333 | void __init mv78xx0_uart3_init(void) |
331 | { | 334 | { |
332 | orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, | 335 | orion_uart3_init((unsigned long) UART3_VIRT_BASE, |
336 | UART3_PHYS_BASE, | ||
333 | IRQ_MV78XX0_UART_3, tclk); | 337 | IRQ_MV78XX0_UART_3, tclk); |
334 | } | 338 | } |
335 | 339 | ||
@@ -338,12 +342,13 @@ void __init mv78xx0_uart3_init(void) | |||
338 | ****************************************************************************/ | 342 | ****************************************************************************/ |
339 | void __init mv78xx0_init_early(void) | 343 | void __init mv78xx0_init_early(void) |
340 | { | 344 | { |
341 | orion_time_set_base(TIMER_VIRT_BASE); | 345 | orion_time_set_base((unsigned long) TIMER_VIRT_BASE); |
342 | } | 346 | } |
343 | 347 | ||
344 | static void mv78xx0_timer_init(void) | 348 | static void mv78xx0_timer_init(void) |
345 | { | 349 | { |
346 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | 350 | orion_time_init((unsigned long) BRIDGE_VIRT_BASE, |
351 | BRIDGE_INT_TIMER1_CLR, | ||
347 | IRQ_MV78XX0_TIMER_1, get_tclk()); | 352 | IRQ_MV78XX0_TIMER_1, get_tclk()); |
348 | } | 353 | } |
349 | 354 | ||
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index a86e79ecfeaf..62405e8dda0e 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
@@ -41,16 +41,16 @@ | |||
41 | */ | 41 | */ |
42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 | 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 | 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 | 44 | #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) |
45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 | 45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 |
46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K | 46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
47 | 47 | ||
48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) | 48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
49 | #define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) | 49 | #define MV78XX0_PCIE_IO_VIRT_BASE(i) IOMEM(0xfe700000 + ((i) << 20)) |
50 | #define MV78XX0_PCIE_IO_SIZE SZ_1M | 50 | #define MV78XX0_PCIE_IO_SIZE SZ_1M |
51 | 51 | ||
52 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 | 52 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
53 | #define MV78XX0_REGS_VIRT_BASE 0xfef00000 | 53 | #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfef00000) |
54 | #define MV78XX0_REGS_SIZE SZ_1M | 54 | #define MV78XX0_REGS_SIZE SZ_1M |
55 | 55 | ||
56 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 | 56 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 |
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index eff9a750bbe2..b5c40c4f524e 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c | |||
@@ -10,6 +10,7 @@ | |||
10 | #include <linux/gpio.h> | 10 | #include <linux/gpio.h> |
11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
12 | #include <linux/irq.h> | 12 | #include <linux/irq.h> |
13 | #include <linux/io.h> | ||
13 | #include <mach/bridge-regs.h> | 14 | #include <mach/bridge-regs.h> |
14 | #include <plat/irq.h> | 15 | #include <plat/irq.h> |
15 | #include "common.h" | 16 | #include "common.h" |
@@ -23,16 +24,16 @@ static int __initdata gpio0_irqs[4] = { | |||
23 | 24 | ||
24 | void __init mv78xx0_init_irq(void) | 25 | void __init mv78xx0_init_irq(void) |
25 | { | 26 | { |
26 | orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); | 27 | orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); |
27 | orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); | 28 | orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); |
28 | orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); | 29 | orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); |
29 | 30 | ||
30 | /* | 31 | /* |
31 | * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask | 32 | * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask |
32 | * registers for core #1 are at an offset of 0x18 from those of | 33 | * registers for core #1 are at an offset of 0x18 from those of |
33 | * core #0.) | 34 | * core #0.) |
34 | */ | 35 | */ |
35 | orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, | 36 | orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, |
36 | mv78xx0_core_index() ? 0x18 : 0, | 37 | mv78xx0_core_index() ? 0x18 : 0, |
37 | IRQ_MV78XX0_GPIO_START, gpio0_irqs); | 38 | IRQ_MV78XX0_GPIO_START, gpio0_irqs); |
38 | } | 39 | } |
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index df50342179e2..4da82f85d1ce 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c | |||
@@ -33,5 +33,6 @@ static unsigned int __init mv78xx0_variant(void) | |||
33 | void __init mv78xx0_mpp_conf(unsigned int *mpp_list) | 33 | void __init mv78xx0_mpp_conf(unsigned int *mpp_list) |
34 | { | 34 | { |
35 | orion_mpp_conf(mpp_list, mv78xx0_variant(), | 35 | orion_mpp_conf(mpp_list, mv78xx0_variant(), |
36 | MPP_MAX, DEV_BUS_VIRT_BASE); | 36 | MPP_MAX, |
37 | (unsigned long) DEV_BUS_VIRT_BASE); | ||
37 | } | 38 | } |
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d68..e2940fbbcd68 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c | |||
@@ -36,8 +36,8 @@ static struct resource pcie_mem_space; | |||
36 | 36 | ||
37 | void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) | 37 | void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) |
38 | { | 38 | { |
39 | *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); | 39 | *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE); |
40 | *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); | 40 | *rev = orion_pcie_rev(PCIE00_VIRT_BASE); |
41 | } | 41 | } |
42 | 42 | ||
43 | static void __init mv78xx0_pcie_preinit(void) | 43 | static void __init mv78xx0_pcie_preinit(void) |
@@ -267,11 +267,11 @@ static struct hw_pci mv78xx0_pci __initdata = { | |||
267 | .map_irq = mv78xx0_pcie_map_irq, | 267 | .map_irq = mv78xx0_pcie_map_irq, |
268 | }; | 268 | }; |
269 | 269 | ||
270 | static void __init add_pcie_port(int maj, int min, unsigned long base) | 270 | static void __init add_pcie_port(int maj, int min, void __iomem *base) |
271 | { | 271 | { |
272 | printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); | 272 | printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); |
273 | 273 | ||
274 | if (orion_pcie_link_up((void __iomem *)base)) { | 274 | if (orion_pcie_link_up(base)) { |
275 | struct pcie_port *pp = &pcie_port[num_pcie_ports++]; | 275 | struct pcie_port *pp = &pcie_port[num_pcie_ports++]; |
276 | 276 | ||
277 | printk("link up\n"); | 277 | printk("link up\n"); |
@@ -279,7 +279,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) | |||
279 | pp->maj = maj; | 279 | pp->maj = maj; |
280 | pp->min = min; | 280 | pp->min = min; |
281 | pp->root_bus_nr = -1; | 281 | pp->root_bus_nr = -1; |
282 | pp->base = (void __iomem *)base; | 282 | pp->base = base; |
283 | spin_lock_init(&pp->conf_lock); | 283 | spin_lock_init(&pp->conf_lock); |
284 | memset(pp->res, 0, sizeof(pp->res)); | 284 | memset(pp->res, 0, sizeof(pp->res)); |
285 | } else { | 285 | } else { |
@@ -293,7 +293,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1) | |||
293 | 293 | ||
294 | if (init_port0) { | 294 | if (init_port0) { |
295 | add_pcie_port(0, 0, PCIE00_VIRT_BASE); | 295 | add_pcie_port(0, 0, PCIE00_VIRT_BASE); |
296 | if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { | 296 | if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) { |
297 | add_pcie_port(0, 1, PCIE01_VIRT_BASE); | 297 | add_pcie_port(0, 1, PCIE01_VIRT_BASE); |
298 | add_pcie_port(0, 2, PCIE02_VIRT_BASE); | 298 | add_pcie_port(0, 2, PCIE02_VIRT_BASE); |
299 | add_pcie_port(0, 3, PCIE03_VIRT_BASE); | 299 | add_pcie_port(0, 3, PCIE03_VIRT_BASE); |