diff options
author | Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 2014-11-13 10:01:15 -0500 |
---|---|---|
committer | Eduardo Valentin <edubezval@gmail.com> | 2014-11-20 09:53:58 -0500 |
commit | 37f9034f99c3c1ba9087357fbbc2b79fc1a30e72 (patch) | |
tree | 4ba6c81b7f86259ae6cb5f0d51a4cc773066dc34 | |
parent | d00671c3ae3f4bfdfbdd1413150ad1a3a135ad1e (diff) |
thermal: exynos: add ->tmu_control method
Add ->tmu_control method to struct exynos_tmu_data and use it
in exynos_tmu_control(). Then add ->tmu_control implementations
for Exynos4210+ and Exynos5440. Finally remove no longer needed
reg->tmu_[ctrl,inten], reg->inten_rise[0,1,2,3]_shift and
reg->inten_fall0_shift abstractions.
There should be no functional changes caused by this patch.
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.c | 81 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.h | 25 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu_data.c | 41 |
3 files changed, 60 insertions, 87 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index f65e6d807afe..938e8e63cff9 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c | |||
@@ -53,6 +53,7 @@ | |||
53 | * @regulator: pointer to the TMU regulator structure. | 53 | * @regulator: pointer to the TMU regulator structure. |
54 | * @reg_conf: pointer to structure to register with core thermal. | 54 | * @reg_conf: pointer to structure to register with core thermal. |
55 | * @tmu_initialize: SoC specific TMU initialization method | 55 | * @tmu_initialize: SoC specific TMU initialization method |
56 | * @tmu_control: SoC specific TMU control method | ||
56 | */ | 57 | */ |
57 | struct exynos_tmu_data { | 58 | struct exynos_tmu_data { |
58 | int id; | 59 | int id; |
@@ -68,6 +69,7 @@ struct exynos_tmu_data { | |||
68 | struct regulator *regulator; | 69 | struct regulator *regulator; |
69 | struct thermal_sensor_conf *reg_conf; | 70 | struct thermal_sensor_conf *reg_conf; |
70 | int (*tmu_initialize)(struct platform_device *pdev); | 71 | int (*tmu_initialize)(struct platform_device *pdev); |
72 | void (*tmu_control)(struct platform_device *pdev, bool on); | ||
71 | }; | 73 | }; |
72 | 74 | ||
73 | /* | 75 | /* |
@@ -221,32 +223,10 @@ static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) | |||
221 | static void exynos_tmu_control(struct platform_device *pdev, bool on) | 223 | static void exynos_tmu_control(struct platform_device *pdev, bool on) |
222 | { | 224 | { |
223 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | 225 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
224 | struct exynos_tmu_platform_data *pdata = data->pdata; | ||
225 | const struct exynos_tmu_registers *reg = pdata->registers; | ||
226 | unsigned int con, interrupt_en; | ||
227 | 226 | ||
228 | mutex_lock(&data->lock); | 227 | mutex_lock(&data->lock); |
229 | clk_enable(data->clk); | 228 | clk_enable(data->clk); |
230 | 229 | data->tmu_control(pdev, on); | |
231 | con = get_con_reg(data, readl(data->base + reg->tmu_ctrl)); | ||
232 | |||
233 | if (on) { | ||
234 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
235 | interrupt_en = | ||
236 | pdata->trigger_enable[3] << reg->inten_rise3_shift | | ||
237 | pdata->trigger_enable[2] << reg->inten_rise2_shift | | ||
238 | pdata->trigger_enable[1] << reg->inten_rise1_shift | | ||
239 | pdata->trigger_enable[0] << reg->inten_rise0_shift; | ||
240 | if (TMU_SUPPORTS(pdata, FALLING_TRIP)) | ||
241 | interrupt_en |= | ||
242 | interrupt_en << reg->inten_fall0_shift; | ||
243 | } else { | ||
244 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
245 | interrupt_en = 0; /* Disable all interrupts */ | ||
246 | } | ||
247 | writel(interrupt_en, data->base + reg->tmu_inten); | ||
248 | writel(con, data->base + reg->tmu_ctrl); | ||
249 | |||
250 | clk_disable(data->clk); | 230 | clk_disable(data->clk); |
251 | mutex_unlock(&data->lock); | 231 | mutex_unlock(&data->lock); |
252 | } | 232 | } |
@@ -388,6 +368,58 @@ static int exynos5440_tmu_initialize(struct platform_device *pdev) | |||
388 | return ret; | 368 | return ret; |
389 | } | 369 | } |
390 | 370 | ||
371 | static void exynos4210_tmu_control(struct platform_device *pdev, bool on) | ||
372 | { | ||
373 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | ||
374 | struct exynos_tmu_platform_data *pdata = data->pdata; | ||
375 | unsigned int con, interrupt_en; | ||
376 | |||
377 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | ||
378 | |||
379 | if (on) { | ||
380 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
381 | interrupt_en = | ||
382 | pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT | | ||
383 | pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT | | ||
384 | pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT | | ||
385 | pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT; | ||
386 | if (TMU_SUPPORTS(pdata, FALLING_TRIP)) | ||
387 | interrupt_en |= | ||
388 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | ||
389 | } else { | ||
390 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
391 | interrupt_en = 0; /* Disable all interrupts */ | ||
392 | } | ||
393 | writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); | ||
394 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | ||
395 | } | ||
396 | |||
397 | static void exynos5440_tmu_control(struct platform_device *pdev, bool on) | ||
398 | { | ||
399 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | ||
400 | struct exynos_tmu_platform_data *pdata = data->pdata; | ||
401 | unsigned int con, interrupt_en; | ||
402 | |||
403 | con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL)); | ||
404 | |||
405 | if (on) { | ||
406 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
407 | interrupt_en = | ||
408 | pdata->trigger_enable[3] << EXYNOS5440_TMU_INTEN_RISE3_SHIFT | | ||
409 | pdata->trigger_enable[2] << EXYNOS5440_TMU_INTEN_RISE2_SHIFT | | ||
410 | pdata->trigger_enable[1] << EXYNOS5440_TMU_INTEN_RISE1_SHIFT | | ||
411 | pdata->trigger_enable[0] << EXYNOS5440_TMU_INTEN_RISE0_SHIFT; | ||
412 | if (TMU_SUPPORTS(pdata, FALLING_TRIP)) | ||
413 | interrupt_en |= | ||
414 | interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT; | ||
415 | } else { | ||
416 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
417 | interrupt_en = 0; /* Disable all interrupts */ | ||
418 | } | ||
419 | writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN); | ||
420 | writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); | ||
421 | } | ||
422 | |||
391 | static int exynos_tmu_read(struct exynos_tmu_data *data) | 423 | static int exynos_tmu_read(struct exynos_tmu_data *data) |
392 | { | 424 | { |
393 | struct exynos_tmu_platform_data *pdata = data->pdata; | 425 | struct exynos_tmu_platform_data *pdata = data->pdata; |
@@ -685,6 +717,7 @@ static int exynos_tmu_probe(struct platform_device *pdev) | |||
685 | switch (data->soc) { | 717 | switch (data->soc) { |
686 | case SOC_ARCH_EXYNOS4210: | 718 | case SOC_ARCH_EXYNOS4210: |
687 | data->tmu_initialize = exynos4210_tmu_initialize; | 719 | data->tmu_initialize = exynos4210_tmu_initialize; |
720 | data->tmu_control = exynos4210_tmu_control; | ||
688 | break; | 721 | break; |
689 | case SOC_ARCH_EXYNOS3250: | 722 | case SOC_ARCH_EXYNOS3250: |
690 | case SOC_ARCH_EXYNOS4412: | 723 | case SOC_ARCH_EXYNOS4412: |
@@ -693,9 +726,11 @@ static int exynos_tmu_probe(struct platform_device *pdev) | |||
693 | case SOC_ARCH_EXYNOS5420: | 726 | case SOC_ARCH_EXYNOS5420: |
694 | case SOC_ARCH_EXYNOS5420_TRIMINFO: | 727 | case SOC_ARCH_EXYNOS5420_TRIMINFO: |
695 | data->tmu_initialize = exynos4412_tmu_initialize; | 728 | data->tmu_initialize = exynos4412_tmu_initialize; |
729 | data->tmu_control = exynos4210_tmu_control; | ||
696 | break; | 730 | break; |
697 | case SOC_ARCH_EXYNOS5440: | 731 | case SOC_ARCH_EXYNOS5440: |
698 | data->tmu_initialize = exynos5440_tmu_initialize; | 732 | data->tmu_initialize = exynos5440_tmu_initialize; |
733 | data->tmu_control = exynos5440_tmu_control; | ||
699 | break; | 734 | break; |
700 | default: | 735 | default: |
701 | ret = -EINVAL; | 736 | ret = -EINVAL; |
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h index f186f4ff44c4..7496b54f2a86 100644 --- a/drivers/thermal/samsung/exynos_tmu.h +++ b/drivers/thermal/samsung/exynos_tmu.h | |||
@@ -68,38 +68,17 @@ enum soc_type { | |||
68 | #define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b) | 68 | #define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b) |
69 | 69 | ||
70 | /** | 70 | /** |
71 | * struct exynos_tmu_register - register descriptors to access registers and | 71 | * struct exynos_tmu_register - register descriptors to access registers. |
72 | * bitfields. The register validity, offsets and bitfield values may vary | 72 | * The register validity may vary slightly across different exynos SOC's. |
73 | * slightly across different exynos SOC's. | ||
74 | * @tmu_ctrl: TMU main controller register. | ||
75 | * @tmu_cur_temp: register containing the current temperature of the TMU. | 73 | * @tmu_cur_temp: register containing the current temperature of the TMU. |
76 | * @tmu_inten: register containing the different threshold interrupt | ||
77 | enable bits. | ||
78 | * @inten_rise0_shift: shift bits of rising 0 interrupt bits. | ||
79 | * @inten_rise1_shift: shift bits of rising 1 interrupt bits. | ||
80 | * @inten_rise2_shift: shift bits of rising 2 interrupt bits. | ||
81 | * @inten_rise3_shift: shift bits of rising 3 interrupt bits. | ||
82 | * @inten_fall0_shift: shift bits of falling 0 interrupt bits. | ||
83 | * @tmu_intstat: Register containing the interrupt status values. | 74 | * @tmu_intstat: Register containing the interrupt status values. |
84 | * @tmu_intclear: Register for clearing the raised interrupt status. | 75 | * @tmu_intclear: Register for clearing the raised interrupt status. |
85 | * @emul_con: TMU emulation controller register. | 76 | * @emul_con: TMU emulation controller register. |
86 | */ | 77 | */ |
87 | struct exynos_tmu_registers { | 78 | struct exynos_tmu_registers { |
88 | u32 tmu_ctrl; | ||
89 | |||
90 | u32 tmu_cur_temp; | 79 | u32 tmu_cur_temp; |
91 | |||
92 | u32 tmu_inten; | ||
93 | u32 inten_rise0_shift; | ||
94 | u32 inten_rise1_shift; | ||
95 | u32 inten_rise2_shift; | ||
96 | u32 inten_rise3_shift; | ||
97 | u32 inten_fall0_shift; | ||
98 | |||
99 | u32 tmu_intstat; | 80 | u32 tmu_intstat; |
100 | |||
101 | u32 tmu_intclear; | 81 | u32 tmu_intclear; |
102 | |||
103 | u32 emul_con; | 82 | u32 emul_con; |
104 | }; | 83 | }; |
105 | 84 | ||
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c index db3b3bc53f76..2bfd4690e0d7 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.c +++ b/drivers/thermal/samsung/exynos_tmu_data.c | |||
@@ -26,13 +26,7 @@ | |||
26 | 26 | ||
27 | #if defined(CONFIG_CPU_EXYNOS4210) | 27 | #if defined(CONFIG_CPU_EXYNOS4210) |
28 | static const struct exynos_tmu_registers exynos4210_tmu_registers = { | 28 | static const struct exynos_tmu_registers exynos4210_tmu_registers = { |
29 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | ||
30 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, | 29 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, |
31 | .tmu_inten = EXYNOS_TMU_REG_INTEN, | ||
32 | .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, | ||
33 | .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, | ||
34 | .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, | ||
35 | .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT, | ||
36 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, | 30 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, |
37 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, | 31 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, |
38 | }; | 32 | }; |
@@ -80,13 +74,7 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = { | |||
80 | 74 | ||
81 | #if defined(CONFIG_SOC_EXYNOS3250) | 75 | #if defined(CONFIG_SOC_EXYNOS3250) |
82 | static const struct exynos_tmu_registers exynos3250_tmu_registers = { | 76 | static const struct exynos_tmu_registers exynos3250_tmu_registers = { |
83 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | ||
84 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, | 77 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, |
85 | .tmu_inten = EXYNOS_TMU_REG_INTEN, | ||
86 | .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, | ||
87 | .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, | ||
88 | .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, | ||
89 | .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT, | ||
90 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, | 78 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, |
91 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, | 79 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, |
92 | .emul_con = EXYNOS_EMUL_CON, | 80 | .emul_con = EXYNOS_EMUL_CON, |
@@ -147,14 +135,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = { | |||
147 | 135 | ||
148 | #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) | 136 | #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) |
149 | static const struct exynos_tmu_registers exynos4412_tmu_registers = { | 137 | static const struct exynos_tmu_registers exynos4412_tmu_registers = { |
150 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | ||
151 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, | 138 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, |
152 | .tmu_inten = EXYNOS_TMU_REG_INTEN, | ||
153 | .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, | ||
154 | .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, | ||
155 | .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, | ||
156 | .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT, | ||
157 | .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT, | ||
158 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, | 139 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, |
159 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, | 140 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, |
160 | .emul_con = EXYNOS_EMUL_CON, | 141 | .emul_con = EXYNOS_EMUL_CON, |
@@ -227,14 +208,7 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = { | |||
227 | 208 | ||
228 | #if defined(CONFIG_SOC_EXYNOS5260) | 209 | #if defined(CONFIG_SOC_EXYNOS5260) |
229 | static const struct exynos_tmu_registers exynos5260_tmu_registers = { | 210 | static const struct exynos_tmu_registers exynos5260_tmu_registers = { |
230 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | ||
231 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, | 211 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, |
232 | .tmu_inten = EXYNOS5260_TMU_REG_INTEN, | ||
233 | .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, | ||
234 | .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, | ||
235 | .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, | ||
236 | .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT, | ||
237 | .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT, | ||
238 | .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT, | 212 | .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT, |
239 | .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR, | 213 | .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR, |
240 | .emul_con = EXYNOS5260_EMUL_CON, | 214 | .emul_con = EXYNOS5260_EMUL_CON, |
@@ -297,15 +271,7 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = { | |||
297 | 271 | ||
298 | #if defined(CONFIG_SOC_EXYNOS5420) | 272 | #if defined(CONFIG_SOC_EXYNOS5420) |
299 | static const struct exynos_tmu_registers exynos5420_tmu_registers = { | 273 | static const struct exynos_tmu_registers exynos5420_tmu_registers = { |
300 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | ||
301 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, | 274 | .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, |
302 | .tmu_inten = EXYNOS_TMU_REG_INTEN, | ||
303 | .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, | ||
304 | .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, | ||
305 | .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, | ||
306 | /* INTEN_RISE3 Not availble in exynos5420 */ | ||
307 | .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT, | ||
308 | .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT, | ||
309 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, | 275 | .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, |
310 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, | 276 | .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, |
311 | .emul_con = EXYNOS_EMUL_CON, | 277 | .emul_con = EXYNOS_EMUL_CON, |
@@ -374,14 +340,7 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = { | |||
374 | 340 | ||
375 | #if defined(CONFIG_SOC_EXYNOS5440) | 341 | #if defined(CONFIG_SOC_EXYNOS5440) |
376 | static const struct exynos_tmu_registers exynos5440_tmu_registers = { | 342 | static const struct exynos_tmu_registers exynos5440_tmu_registers = { |
377 | .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL, | ||
378 | .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP, | 343 | .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP, |
379 | .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN, | ||
380 | .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT, | ||
381 | .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT, | ||
382 | .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT, | ||
383 | .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT, | ||
384 | .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT, | ||
385 | .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ, | 344 | .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ, |
386 | .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ, | 345 | .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ, |
387 | .emul_con = EXYNOS5440_TMU_S0_7_DEBUG, | 346 | .emul_con = EXYNOS5440_TMU_S0_7_DEBUG, |