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authorKukjin Kim <kgene.kim@samsung.com>2013-02-03 20:00:11 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-02-04 13:31:43 -0500
commit37c3adca81b282bdf310d5ed54acbc28ac0b20a3 (patch)
tree4f3aab042ce27c6341c9db6b0e57946f182a046a
parent14cce0e7754e72516af8406a90c7c3eb177632d4 (diff)
ARM: S3C24XX: header mach/regs-mem.h local
Since header mach/regs-mem.h is used only into mach-s3c24xx/, this patch moves the header file in local. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c3
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2410.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2412.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c1
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-mem.h202
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2410.c3
-rw-r--r--arch/arm/mach-s3c24xx/mach-anubis.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-at2440evb.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-bast.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-gta02.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-mini2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-osiris.c2
-rw-r--r--arch/arm/mach-s3c24xx/pm.c3
-rw-r--r--arch/arm/mach-s3c24xx/regs-mem.h54
-rw-r--r--arch/arm/mach-s3c24xx/simtec-pm.c3
-rw-r--r--arch/arm/mach-s3c24xx/sleep-s3c2410.S3
-rw-r--r--arch/arm/mach-s3c24xx/sleep.S1
19 files changed, 65 insertions, 219 deletions
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 89e4e2b7a82e..ddd8280e3875 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -16,11 +16,12 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/regs-mem.h>
20#include <mach/regs-clock.h> 19#include <mach/regs-clock.h>
21 20
22#include <plat/cpu-freq-core.h> 21#include <plat/cpu-freq-core.h>
23 22
23#include "regs-mem.h"
24
24/** 25/**
25 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value 26 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * @cfg: The frequency configuration 27 * @cfg: The frequency configuration
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56e..25d085adc93c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920ff..d2408ba372cb 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84f..0b86e74d104f 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 2d94228d2866..05536254a3f8 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11*/
12
13#ifndef __ASM_ARM_MEMREGS_H
14#define __ASM_ARM_MEMREGS_H
15
16#ifndef S3C2410_MEMREG
17#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#endif
19
20/* bus width, and wait state control */
21#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
22
23/* bank zero config - note, pinstrapped from OM pins! */
24#define S3C2410_BWSCON_DW0_16 (1<<1)
25#define S3C2410_BWSCON_DW0_32 (2<<1)
26
27/* bank one configs */
28#define S3C2410_BWSCON_DW1_8 (0<<4)
29#define S3C2410_BWSCON_DW1_16 (1<<4)
30#define S3C2410_BWSCON_DW1_32 (2<<4)
31#define S3C2410_BWSCON_WS1 (1<<6)
32#define S3C2410_BWSCON_ST1 (1<<7)
33
34/* bank 2 configurations */
35#define S3C2410_BWSCON_DW2_8 (0<<8)
36#define S3C2410_BWSCON_DW2_16 (1<<8)
37#define S3C2410_BWSCON_DW2_32 (2<<8)
38#define S3C2410_BWSCON_WS2 (1<<10)
39#define S3C2410_BWSCON_ST2 (1<<11)
40
41/* bank 3 configurations */
42#define S3C2410_BWSCON_DW3_8 (0<<12)
43#define S3C2410_BWSCON_DW3_16 (1<<12)
44#define S3C2410_BWSCON_DW3_32 (2<<12)
45#define S3C2410_BWSCON_WS3 (1<<14)
46#define S3C2410_BWSCON_ST3 (1<<15)
47
48/* bank 4 configurations */
49#define S3C2410_BWSCON_DW4_8 (0<<16)
50#define S3C2410_BWSCON_DW4_16 (1<<16)
51#define S3C2410_BWSCON_DW4_32 (2<<16)
52#define S3C2410_BWSCON_WS4 (1<<18)
53#define S3C2410_BWSCON_ST4 (1<<19)
54
55/* bank 5 configurations */
56#define S3C2410_BWSCON_DW5_8 (0<<20)
57#define S3C2410_BWSCON_DW5_16 (1<<20)
58#define S3C2410_BWSCON_DW5_32 (2<<20)
59#define S3C2410_BWSCON_WS5 (1<<22)
60#define S3C2410_BWSCON_ST5 (1<<23)
61
62/* bank 6 configurations */
63#define S3C2410_BWSCON_DW6_8 (0<<24)
64#define S3C2410_BWSCON_DW6_16 (1<<24)
65#define S3C2410_BWSCON_DW6_32 (2<<24)
66#define S3C2410_BWSCON_WS6 (1<<26)
67#define S3C2410_BWSCON_ST6 (1<<27)
68
69/* bank 7 configurations */
70#define S3C2410_BWSCON_DW7_8 (0<<28)
71#define S3C2410_BWSCON_DW7_16 (1<<28)
72#define S3C2410_BWSCON_DW7_32 (2<<28)
73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31)
75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
86/* memory set (rom, ram) */
87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
89#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
90#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
91#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
92#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
93#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
94#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
95
96/* bank configuration registers */
97
98#define S3C2410_BANKCON_PMCnorm (0x00)
99#define S3C2410_BANKCON_PMC4 (0x01)
100#define S3C2410_BANKCON_PMC8 (0x02)
101#define S3C2410_BANKCON_PMC16 (0x03)
102
103/* bank configurations for banks 0..7, note banks
104 * 6 and 7 have different configurations depending on
105 * the memory type bits */
106
107#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
108#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
109#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
110#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
111#define S3C2410_BANKCON_Tacp_SHIFT (2)
112
113#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
114#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
115#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
116#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
117#define S3C2410_BANKCON_Tcah_SHIFT (4)
118
119#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
120#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
121#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
122#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
123#define S3C2410_BANKCON_Tcoh_SHIFT (6)
124
125#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
126#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
127#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
128#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
129#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
130#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
131#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
132#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
133#define S3C2410_BANKCON_Tacc_SHIFT (8)
134
135#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
136#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
137#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
138#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
139#define S3C2410_BANKCON_Tcos_SHIFT (11)
140
141#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
142#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
143#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
144#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146
147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
149
150/* next bits only for SDRAM in 6,7 */
151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
153#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
154
155/* control column address select */
156#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
157#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
158#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
159
160#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
161#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
162#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
163#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
164
165/* refresh control */
166
167#define S3C2410_REFRESH_REFEN (1<<23)
168#define S3C2410_REFRESH_SELF (1<<22)
169#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
170
171#define S3C2410_REFRESH_TRP_MASK (3<<20)
172#define S3C2410_REFRESH_TRP_2clk (0<<20)
173#define S3C2410_REFRESH_TRP_3clk (1<<20)
174#define S3C2410_REFRESH_TRP_4clk (2<<20)
175
176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
179#define S3C2410_REFRESH_TSRC_6clk (2<<18)
180#define S3C2410_REFRESH_TSRC_7clk (3<<18)
181
182
183/* mode select register(s) */
184
185#define S3C2410_MRSRB_CL1 (0x00 << 4)
186#define S3C2410_MRSRB_CL2 (0x02 << 4)
187#define S3C2410_MRSRB_CL3 (0x03 << 4)
188
189/* bank size register */
190#define S3C2410_BANKSIZE_128M (0x2 << 0)
191#define S3C2410_BANKSIZE_64M (0x1 << 0)
192#define S3C2410_BANKSIZE_32M (0x0 << 0)
193#define S3C2410_BANKSIZE_16M (0x7 << 0)
194#define S3C2410_BANKSIZE_8M (0x6 << 0)
195#define S3C2410_BANKSIZE_4M (0x5 << 0)
196#define S3C2410_BANKSIZE_2M (0x4 << 0)
197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
200#define S3C2410_BANKSIZE_BURST (1<<7)
201
202#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
index 48ccfcf715fa..4cd13ab6496b 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -19,11 +19,12 @@
19#include <linux/slab.h> 19#include <linux/slab.h>
20 20
21#include <mach/map.h> 21#include <mach/map.h>
22#include <mach/regs-mem.h>
23#include <mach/regs-clock.h> 22#include <mach/regs-clock.h>
24 23
25#include <plat/cpu-freq-core.h> 24#include <plat/cpu-freq-core.h>
26 25
26#include "regs-mem.h"
27
27#define print_ns(x) ((x) / 10), ((x) % 10) 28#define print_ns(x) ((x) / 10), ((x) % 10)
28 29
29/** 30/**
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 113304c48dea..3767d518456f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -34,7 +34,6 @@
34 34
35#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h> 36#include <mach/regs-gpio.h>
37#include <mach/regs-mem.h>
38#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
39#include <linux/platform_data/mtd-nand-s3c2410.h> 38#include <linux/platform_data/mtd-nand-s3c2410.h>
40#include <linux/platform_data/i2c-s3c2410.h> 39#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index f51bbcb58097..2fa05173499d 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -35,7 +35,6 @@
35 35
36#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h> 37#include <mach/regs-gpio.h>
38#include <mach/regs-mem.h>
39#include <mach/regs-lcd.h> 38#include <mach/regs-lcd.h>
40#include <linux/platform_data/mtd-nand-s3c2410.h> 39#include <linux/platform_data/mtd-nand-s3c2410.h>
41#include <linux/platform_data/i2c-s3c2410.h> 40#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 1ed29b456be7..00d57f334b71 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -48,7 +48,6 @@
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <mach/regs-gpio.h> 49#include <mach/regs-gpio.h>
50#include <mach/regs-lcd.h> 50#include <mach/regs-lcd.h>
51#include <mach/regs-mem.h>
52 51
53#include <plat/clock.h> 52#include <plat/clock.h>
54#include <plat/cpu.h> 53#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 1053706c0ea5..fa9bbe6f3446 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -75,7 +75,6 @@
75#include <mach/hardware.h> 75#include <mach/hardware.h>
76#include <mach/regs-gpio.h> 76#include <mach/regs-gpio.h>
77#include <mach/regs-irq.h> 77#include <mach/regs-irq.h>
78#include <mach/regs-mem.h>
79 78
80#include <plat/cpu.h> 79#include <plat/cpu.h>
81#include <plat/devs.h> 80#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 0de85e32082d..ceaaf0b41332 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -36,7 +36,6 @@
36#include <linux/platform_data/i2c-s3c2410.h> 36#include <linux/platform_data/i2c-s3c2410.h>
37 37
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39#include <mach/regs-mem.h>
40#include <mach/regs-lcd.h> 39#include <mach/regs-lcd.h>
41#include <mach/fb.h> 40#include <mach/fb.h>
42 41
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index a31d5b83e5f7..64494ff73ad8 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -40,7 +40,6 @@
40#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <mach/regs-gpio.h> 41#include <mach/regs-gpio.h>
42#include <linux/platform_data/leds-s3c24xx.h> 42#include <linux/platform_data/leds-s3c24xx.h>
43#include <mach/regs-mem.h>
44#include <mach/regs-lcd.h> 43#include <mach/regs-lcd.h>
45#include <mach/irqs.h> 44#include <mach/irqs.h>
46#include <linux/platform_data/mtd-nand-s3c2410.h> 45#include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 1eeeee4169ac..572f1c811adf 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -47,11 +47,11 @@
47 47
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <mach/regs-gpio.h> 49#include <mach/regs-gpio.h>
50#include <mach/regs-mem.h>
51#include <mach/regs-lcd.h> 50#include <mach/regs-lcd.h>
52 51
53#include "common.h" 52#include "common.h"
54#include "osiris.h" 53#include "osiris.h"
54#include "regs-mem.h"
55 55
56/* onboard perihperal map */ 56/* onboard perihperal map */
57 57
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 724755f0b0f5..caa5b7211380 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -38,7 +38,6 @@
38#include <plat/regs-serial.h> 38#include <plat/regs-serial.h>
39#include <mach/regs-clock.h> 39#include <mach/regs-clock.h>
40#include <mach/regs-gpio.h> 40#include <mach/regs-gpio.h>
41#include <mach/regs-mem.h>
42#include <mach/regs-irq.h> 41#include <mach/regs-irq.h>
43 42
44#include <asm/mach/time.h> 43#include <asm/mach/time.h>
@@ -46,6 +45,8 @@
46#include <plat/gpio-cfg.h> 45#include <plat/gpio-cfg.h>
47#include <plat/pm.h> 46#include <plat/pm.h>
48 47
48#include "regs-mem.h"
49
49#define PFX "s3c24xx-pm: " 50#define PFX "s3c24xx-pm: "
50 51
51static struct sleep_save core_save[] = { 52static struct sleep_save core_save[] = {
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h
new file mode 100644
index 000000000000..86b1258368c2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/regs-mem.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
3 * http://www.simtec.co.uk/products/SWLINUX/
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 Memory Control register definitions
10 */
11
12#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
13#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
14
15#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
16
17#define S3C2410_BWSCON S3C2410_MEMREG(0x00)
18#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04)
19#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08)
20#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C)
21#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10)
22#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14)
23#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18)
24#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C)
25#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20)
26#define S3C2410_REFRESH S3C2410_MEMREG(0x24)
27#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28)
28
29#define S3C2410_BWSCON_ST1 (1 << 7)
30#define S3C2410_BWSCON_ST2 (1 << 11)
31#define S3C2410_BWSCON_ST3 (1 << 15)
32#define S3C2410_BWSCON_ST4 (1 << 19)
33#define S3C2410_BWSCON_ST5 (1 << 23)
34
35#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
36
37#define S3C2410_BWSCON_WS (1 << 2)
38
39#define S3C2410_BANKCON_PMC16 (0x3)
40
41#define S3C2410_BANKCON_Tacp_SHIFT (2)
42#define S3C2410_BANKCON_Tcah_SHIFT (4)
43#define S3C2410_BANKCON_Tcoh_SHIFT (6)
44#define S3C2410_BANKCON_Tacc_SHIFT (8)
45#define S3C2410_BANKCON_Tcos_SHIFT (11)
46#define S3C2410_BANKCON_Tacs_SHIFT (13)
47
48#define S3C2410_BANKCON_SDRAM (0x3 << 15)
49
50#define S3C2410_REFRESH_SELF (1 << 22)
51
52#define S3C2410_BANKSIZE_MASK (0x7 << 0)
53
54#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f93171297..38a2f1fdebab 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
@@ -28,12 +28,13 @@
28 28
29#include <mach/map.h> 29#include <mach/map.h>
30#include <mach/regs-gpio.h> 30#include <mach/regs-gpio.h>
31#include <mach/regs-mem.h>
32 31
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
34 33
35#include <plat/pm.h> 34#include <plat/pm.h>
36 35
36#include "regs-mem.h"
37
37#define COPYRIGHT ", Copyright 2005 Simtec Electronics" 38#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
38 39
39/* pm_simtec_init 40/* pm_simtec_init
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..25b212180bf5 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -31,9 +31,10 @@
31 31
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
36 35
36#include "regs-mem.h"
37
37 /* s3c2410_cpu_suspend 38 /* s3c2410_cpu_suspend
38 * 39 *
39 * put the cpu into sleep mode 40 * put the cpu into sleep mode
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index c56612569b40..7f378b662da6 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -31,7 +31,6 @@
31 31
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
36 35
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not 36/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 08:25:18 -0400