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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-12-10 13:37:21 -0500
committerOlof Johansson <olof@lixom.net>2013-12-11 20:15:21 -0500
commit378d0aee3b53bd8549b29dcc75f2bf47ee446e8f (patch)
tree9bc3b735a436e12e01e6317e8dfdeb6594772acd
parent2a82f95c3fb4904a473e205f3510b6e8884dd34d (diff)
ARM: sun7i: dt: Fix interrupt trigger types
The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The GIC can work on several interrupt triggers, and the A20 was actually setting it up to use a rising edge as a trigger, while it was actually a level high trigger, leading to some interrupts that would be completely ignored if the edge was missed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Cc: stable@vger.kernel.org #3.12+ Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi42
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e46cfedde74c..367611a0730b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -170,7 +170,7 @@
170 emac: ethernet@01c0b000 { 170 emac: ethernet@01c0b000 {
171 compatible = "allwinner,sun4i-emac"; 171 compatible = "allwinner,sun4i-emac";
172 reg = <0x01c0b000 0x1000>; 172 reg = <0x01c0b000 0x1000>;
173 interrupts = <0 55 1>; 173 interrupts = <0 55 4>;
174 clocks = <&ahb_gates 17>; 174 clocks = <&ahb_gates 17>;
175 status = "disabled"; 175 status = "disabled";
176 }; 176 };
@@ -186,7 +186,7 @@
186 pio: pinctrl@01c20800 { 186 pio: pinctrl@01c20800 {
187 compatible = "allwinner,sun7i-a20-pinctrl"; 187 compatible = "allwinner,sun7i-a20-pinctrl";
188 reg = <0x01c20800 0x400>; 188 reg = <0x01c20800 0x400>;
189 interrupts = <0 28 1>; 189 interrupts = <0 28 4>;
190 clocks = <&apb0_gates 5>; 190 clocks = <&apb0_gates 5>;
191 gpio-controller; 191 gpio-controller;
192 interrupt-controller; 192 interrupt-controller;
@@ -251,12 +251,12 @@
251 timer@01c20c00 { 251 timer@01c20c00 {
252 compatible = "allwinner,sun4i-timer"; 252 compatible = "allwinner,sun4i-timer";
253 reg = <0x01c20c00 0x90>; 253 reg = <0x01c20c00 0x90>;
254 interrupts = <0 22 1>, 254 interrupts = <0 22 4>,
255 <0 23 1>, 255 <0 23 4>,
256 <0 24 1>, 256 <0 24 4>,
257 <0 25 1>, 257 <0 25 4>,
258 <0 67 1>, 258 <0 67 4>,
259 <0 68 1>; 259 <0 68 4>;
260 clocks = <&osc24M>; 260 clocks = <&osc24M>;
261 }; 261 };
262 262
@@ -273,7 +273,7 @@
273 uart0: serial@01c28000 { 273 uart0: serial@01c28000 {
274 compatible = "snps,dw-apb-uart"; 274 compatible = "snps,dw-apb-uart";
275 reg = <0x01c28000 0x400>; 275 reg = <0x01c28000 0x400>;
276 interrupts = <0 1 1>; 276 interrupts = <0 1 4>;
277 reg-shift = <2>; 277 reg-shift = <2>;
278 reg-io-width = <4>; 278 reg-io-width = <4>;
279 clocks = <&apb1_gates 16>; 279 clocks = <&apb1_gates 16>;
@@ -283,7 +283,7 @@
283 uart1: serial@01c28400 { 283 uart1: serial@01c28400 {
284 compatible = "snps,dw-apb-uart"; 284 compatible = "snps,dw-apb-uart";
285 reg = <0x01c28400 0x400>; 285 reg = <0x01c28400 0x400>;
286 interrupts = <0 2 1>; 286 interrupts = <0 2 4>;
287 reg-shift = <2>; 287 reg-shift = <2>;
288 reg-io-width = <4>; 288 reg-io-width = <4>;
289 clocks = <&apb1_gates 17>; 289 clocks = <&apb1_gates 17>;
@@ -293,7 +293,7 @@
293 uart2: serial@01c28800 { 293 uart2: serial@01c28800 {
294 compatible = "snps,dw-apb-uart"; 294 compatible = "snps,dw-apb-uart";
295 reg = <0x01c28800 0x400>; 295 reg = <0x01c28800 0x400>;
296 interrupts = <0 3 1>; 296 interrupts = <0 3 4>;
297 reg-shift = <2>; 297 reg-shift = <2>;
298 reg-io-width = <4>; 298 reg-io-width = <4>;
299 clocks = <&apb1_gates 18>; 299 clocks = <&apb1_gates 18>;
@@ -303,7 +303,7 @@
303 uart3: serial@01c28c00 { 303 uart3: serial@01c28c00 {
304 compatible = "snps,dw-apb-uart"; 304 compatible = "snps,dw-apb-uart";
305 reg = <0x01c28c00 0x400>; 305 reg = <0x01c28c00 0x400>;
306 interrupts = <0 4 1>; 306 interrupts = <0 4 4>;
307 reg-shift = <2>; 307 reg-shift = <2>;
308 reg-io-width = <4>; 308 reg-io-width = <4>;
309 clocks = <&apb1_gates 19>; 309 clocks = <&apb1_gates 19>;
@@ -313,7 +313,7 @@
313 uart4: serial@01c29000 { 313 uart4: serial@01c29000 {
314 compatible = "snps,dw-apb-uart"; 314 compatible = "snps,dw-apb-uart";
315 reg = <0x01c29000 0x400>; 315 reg = <0x01c29000 0x400>;
316 interrupts = <0 17 1>; 316 interrupts = <0 17 4>;
317 reg-shift = <2>; 317 reg-shift = <2>;
318 reg-io-width = <4>; 318 reg-io-width = <4>;
319 clocks = <&apb1_gates 20>; 319 clocks = <&apb1_gates 20>;
@@ -323,7 +323,7 @@
323 uart5: serial@01c29400 { 323 uart5: serial@01c29400 {
324 compatible = "snps,dw-apb-uart"; 324 compatible = "snps,dw-apb-uart";
325 reg = <0x01c29400 0x400>; 325 reg = <0x01c29400 0x400>;
326 interrupts = <0 18 1>; 326 interrupts = <0 18 4>;
327 reg-shift = <2>; 327 reg-shift = <2>;
328 reg-io-width = <4>; 328 reg-io-width = <4>;
329 clocks = <&apb1_gates 21>; 329 clocks = <&apb1_gates 21>;
@@ -333,7 +333,7 @@
333 uart6: serial@01c29800 { 333 uart6: serial@01c29800 {
334 compatible = "snps,dw-apb-uart"; 334 compatible = "snps,dw-apb-uart";
335 reg = <0x01c29800 0x400>; 335 reg = <0x01c29800 0x400>;
336 interrupts = <0 19 1>; 336 interrupts = <0 19 4>;
337 reg-shift = <2>; 337 reg-shift = <2>;
338 reg-io-width = <4>; 338 reg-io-width = <4>;
339 clocks = <&apb1_gates 22>; 339 clocks = <&apb1_gates 22>;
@@ -343,7 +343,7 @@
343 uart7: serial@01c29c00 { 343 uart7: serial@01c29c00 {
344 compatible = "snps,dw-apb-uart"; 344 compatible = "snps,dw-apb-uart";
345 reg = <0x01c29c00 0x400>; 345 reg = <0x01c29c00 0x400>;
346 interrupts = <0 20 1>; 346 interrupts = <0 20 4>;
347 reg-shift = <2>; 347 reg-shift = <2>;
348 reg-io-width = <4>; 348 reg-io-width = <4>;
349 clocks = <&apb1_gates 23>; 349 clocks = <&apb1_gates 23>;
@@ -353,7 +353,7 @@
353 i2c0: i2c@01c2ac00 { 353 i2c0: i2c@01c2ac00 {
354 compatible = "allwinner,sun4i-i2c"; 354 compatible = "allwinner,sun4i-i2c";
355 reg = <0x01c2ac00 0x400>; 355 reg = <0x01c2ac00 0x400>;
356 interrupts = <0 7 1>; 356 interrupts = <0 7 4>;
357 clocks = <&apb1_gates 0>; 357 clocks = <&apb1_gates 0>;
358 clock-frequency = <100000>; 358 clock-frequency = <100000>;
359 status = "disabled"; 359 status = "disabled";
@@ -362,7 +362,7 @@
362 i2c1: i2c@01c2b000 { 362 i2c1: i2c@01c2b000 {
363 compatible = "allwinner,sun4i-i2c"; 363 compatible = "allwinner,sun4i-i2c";
364 reg = <0x01c2b000 0x400>; 364 reg = <0x01c2b000 0x400>;
365 interrupts = <0 8 1>; 365 interrupts = <0 8 4>;
366 clocks = <&apb1_gates 1>; 366 clocks = <&apb1_gates 1>;
367 clock-frequency = <100000>; 367 clock-frequency = <100000>;
368 status = "disabled"; 368 status = "disabled";
@@ -371,7 +371,7 @@
371 i2c2: i2c@01c2b400 { 371 i2c2: i2c@01c2b400 {
372 compatible = "allwinner,sun4i-i2c"; 372 compatible = "allwinner,sun4i-i2c";
373 reg = <0x01c2b400 0x400>; 373 reg = <0x01c2b400 0x400>;
374 interrupts = <0 9 1>; 374 interrupts = <0 9 4>;
375 clocks = <&apb1_gates 2>; 375 clocks = <&apb1_gates 2>;
376 clock-frequency = <100000>; 376 clock-frequency = <100000>;
377 status = "disabled"; 377 status = "disabled";
@@ -380,7 +380,7 @@
380 i2c3: i2c@01c2b800 { 380 i2c3: i2c@01c2b800 {
381 compatible = "allwinner,sun4i-i2c"; 381 compatible = "allwinner,sun4i-i2c";
382 reg = <0x01c2b800 0x400>; 382 reg = <0x01c2b800 0x400>;
383 interrupts = <0 88 1>; 383 interrupts = <0 88 4>;
384 clocks = <&apb1_gates 3>; 384 clocks = <&apb1_gates 3>;
385 clock-frequency = <100000>; 385 clock-frequency = <100000>;
386 status = "disabled"; 386 status = "disabled";
@@ -389,7 +389,7 @@
389 i2c4: i2c@01c2bc00 { 389 i2c4: i2c@01c2bc00 {
390 compatible = "allwinner,sun4i-i2c"; 390 compatible = "allwinner,sun4i-i2c";
391 reg = <0x01c2bc00 0x400>; 391 reg = <0x01c2bc00 0x400>;
392 interrupts = <0 89 1>; 392 interrupts = <0 89 4>;
393 clocks = <&apb1_gates 15>; 393 clocks = <&apb1_gates 15>;
394 clock-frequency = <100000>; 394 clock-frequency = <100000>;
395 status = "disabled"; 395 status = "disabled";