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authorPhilippe De Muyter <phdm@macqel.be>2010-04-02 11:56:08 -0400
committerGreg Ungerer <gerg@uclinux.org>2010-04-20 23:43:06 -0400
commit3732b68f22857201fa09cb82b128f295096a2375 (patch)
tree14584810aee0a110704fa0c6f5b858b67d32afab
parent6ecaf44e62274cd3496341ee0189bbbc0ae00976 (diff)
m68knommu: fix coldfire tcdrain
Fix tcdrain on coldfire uarts. Currently with coldfire uarts tcdrain returns without waiting for txempty, because (tx)fifosize is 0. Fix that and call uart_update_timeout when setting the baud rate, otherwise tcdrain will wait for an half our :) Also constify mcf_uart_ops. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
-rw-r--r--drivers/serial/mcf.c4
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index ef2293873612..01a8716c5fc5 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -212,5 +212,10 @@ struct mcf_platform_uart {
212#define MCFUART_URF_RXS 0xc0 /* Receiver status */ 212#define MCFUART_URF_RXS 0xc0 /* Receiver status */
213#endif 213#endif
214 214
215#if defined(CONFIG_M5272)
216#define MCFUART_TXFIFOSIZE 25
217#else
218#define MCFUART_TXFIFOSIZE 1
219#endif
215/****************************************************************************/ 220/****************************************************************************/
216#endif /* mcfuart_h */ 221#endif /* mcfuart_h */
diff --git a/drivers/serial/mcf.c b/drivers/serial/mcf.c
index 7bb5fee639e3..b9f7dfe6c5d5 100644
--- a/drivers/serial/mcf.c
+++ b/drivers/serial/mcf.c
@@ -263,6 +263,7 @@ static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
263 } 263 }
264 264
265 spin_lock_irqsave(&port->lock, flags); 265 spin_lock_irqsave(&port->lock, flags);
266 uart_update_timeout(port, termios->c_cflag, baud);
266 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); 267 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
267 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); 268 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
268 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR); 269 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
@@ -379,6 +380,7 @@ static irqreturn_t mcf_interrupt(int irq, void *data)
379static void mcf_config_port(struct uart_port *port, int flags) 380static void mcf_config_port(struct uart_port *port, int flags)
380{ 381{
381 port->type = PORT_MCF; 382 port->type = PORT_MCF;
383 port->fifosize = MCFUART_TXFIFOSIZE;
382 384
383 /* Clear mask, so no surprise interrupts. */ 385 /* Clear mask, so no surprise interrupts. */
384 writeb(0, port->membase + MCFUART_UIMR); 386 writeb(0, port->membase + MCFUART_UIMR);
@@ -424,7 +426,7 @@ static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
424/* 426/*
425 * Define the basic serial functions we support. 427 * Define the basic serial functions we support.
426 */ 428 */
427static struct uart_ops mcf_uart_ops = { 429static const struct uart_ops mcf_uart_ops = {
428 .tx_empty = mcf_tx_empty, 430 .tx_empty = mcf_tx_empty,
429 .get_mctrl = mcf_get_mctrl, 431 .get_mctrl = mcf_get_mctrl,
430 .set_mctrl = mcf_set_mctrl, 432 .set_mctrl = mcf_set_mctrl,