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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-10-29 07:55:44 -0400
committerMark Brown <broonie@kernel.org>2014-10-29 08:31:38 -0400
commit36bcecd0a73eb4a11c9748bc96c2d254d5364d12 (patch)
tree8bd9be21f9c04249f53387928610230171cd754f
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
ASoC: davinci-mcasp: Correct TX start sequence
Follow the sequence described in the TRMs when starting TX. This sequence will make sure that we are not facing with initial channel swap caused by no data available in McASP for transmit. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/davinci/davinci-mcasp.c25
-rw-r--r--sound/soc/davinci/davinci-mcasp.h6
2 files changed, 15 insertions, 16 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 0eed9b1b24e1..e1c1f40dd77f 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -183,31 +183,24 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
183 183
184static void mcasp_start_tx(struct davinci_mcasp *mcasp) 184static void mcasp_start_tx(struct davinci_mcasp *mcasp)
185{ 185{
186 u8 offset = 0, i;
187 u32 cnt; 186 u32 cnt;
188 187
188 /* Start clocks */
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
191 /* Activate serializer(s) */
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
192 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
193 193
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 194 /* wait for XDATA to be cleared */
195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
196 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
197 for (i = 0; i < mcasp->num_serializer; i++) {
198 if (mcasp->serial_dir[i] == TX_MODE) {
199 offset = i;
200 break;
201 }
202 }
203
204 /* wait for TX ready */
205 cnt = 0; 195 cnt = 0;
206 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) & 196 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
207 TXSTATE) && (cnt < 100000)) 197 ~XRDATA) && (cnt < 100000))
208 cnt++; 198 cnt++;
209 199
210 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0); 200 /* Release TX state machine */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
202 /* Release Frame Sync generator */
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
211} 204}
212 205
213static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 206static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
index 98fbc451892a..9737108f0305 100644
--- a/sound/soc/davinci/davinci-mcasp.h
+++ b/sound/soc/davinci/davinci-mcasp.h
@@ -253,6 +253,12 @@
253#define TXFSRST BIT(12) /* Frame Sync Generator Reset */ 253#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
254 254
255/* 255/*
256 * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
257 * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
258 */
259#define XRDATA BIT(5) /* Transmit/Receive data ready */
260
261/*
256 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits 262 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
257 */ 263 */
258#define MUTENA(val) (val) 264#define MUTENA(val) (val)