diff options
| author | Barry Grussling <barry@grussling.com> | 2013-01-08 11:05:53 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-01-10 03:04:34 -0500 |
| commit | 3675c8d7144e91d9a2a1f6f12e576cb92e06f352 (patch) | |
| tree | fb113eb9c6445686b169f57f9bd18ba9f70a2416 | |
| parent | a0376db0f234a8053100bddf26c073be79546b2b (diff) | |
DSA: Convert DSA comments to network-style comments
Convert DSA driver comments to network-style comments as reported by
checkpatch.pl. Fix spelling error.
Signed-off-by: Barry Grussling <barry@grussling.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/dsa/mv88e6060.c | 31 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6123_61_65.c | 113 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6131.c | 102 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx.c | 70 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx.h | 9 |
5 files changed, 93 insertions, 232 deletions
diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c index 325391d19bad..637373cebf78 100644 --- a/drivers/net/dsa/mv88e6060.c +++ b/drivers/net/dsa/mv88e6060.c | |||
| @@ -67,27 +67,19 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds) | |||
| 67 | int i; | 67 | int i; |
| 68 | int ret; | 68 | int ret; |
| 69 | 69 | ||
| 70 | /* | 70 | /* Set all ports to the disabled state. */ |
| 71 | * Set all ports to the disabled state. | ||
| 72 | */ | ||
| 73 | for (i = 0; i < 6; i++) { | 71 | for (i = 0; i < 6; i++) { |
| 74 | ret = REG_READ(REG_PORT(i), 0x04); | 72 | ret = REG_READ(REG_PORT(i), 0x04); |
| 75 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | 73 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 76 | } | 74 | } |
| 77 | 75 | ||
| 78 | /* | 76 | /* Wait for transmit queues to drain. */ |
| 79 | * Wait for transmit queues to drain. | ||
| 80 | */ | ||
| 81 | msleep(2); | 77 | msleep(2); |
| 82 | 78 | ||
| 83 | /* | 79 | /* Reset the switch. */ |
| 84 | * Reset the switch. | ||
| 85 | */ | ||
| 86 | REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); | 80 | REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); |
| 87 | 81 | ||
| 88 | /* | 82 | /* Wait up to one second for reset to complete. */ |
| 89 | * Wait up to one second for reset to complete. | ||
| 90 | */ | ||
| 91 | for (i = 0; i < 1000; i++) { | 83 | for (i = 0; i < 1000; i++) { |
| 92 | ret = REG_READ(REG_GLOBAL, 0x00); | 84 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 93 | if ((ret & 0x8000) == 0x0000) | 85 | if ((ret & 0x8000) == 0x0000) |
| @@ -103,15 +95,13 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds) | |||
| 103 | 95 | ||
| 104 | static int mv88e6060_setup_global(struct dsa_switch *ds) | 96 | static int mv88e6060_setup_global(struct dsa_switch *ds) |
| 105 | { | 97 | { |
| 106 | /* | 98 | /* Disable discarding of frames with excessive collisions, |
| 107 | * Disable discarding of frames with excessive collisions, | ||
| 108 | * set the maximum frame size to 1536 bytes, and mask all | 99 | * set the maximum frame size to 1536 bytes, and mask all |
| 109 | * interrupt sources. | 100 | * interrupt sources. |
| 110 | */ | 101 | */ |
| 111 | REG_WRITE(REG_GLOBAL, 0x04, 0x0800); | 102 | REG_WRITE(REG_GLOBAL, 0x04, 0x0800); |
| 112 | 103 | ||
| 113 | /* | 104 | /* Enable automatic address learning, set the address |
| 114 | * Enable automatic address learning, set the address | ||
| 115 | * database size to 1024 entries, and set the default aging | 105 | * database size to 1024 entries, and set the default aging |
| 116 | * time to 5 minutes. | 106 | * time to 5 minutes. |
| 117 | */ | 107 | */ |
| @@ -124,16 +114,14 @@ static int mv88e6060_setup_port(struct dsa_switch *ds, int p) | |||
| 124 | { | 114 | { |
| 125 | int addr = REG_PORT(p); | 115 | int addr = REG_PORT(p); |
| 126 | 116 | ||
| 127 | /* | 117 | /* Do not force flow control, disable Ingress and Egress |
| 128 | * Do not force flow control, disable Ingress and Egress | ||
| 129 | * Header tagging, disable VLAN tunneling, and set the port | 118 | * Header tagging, disable VLAN tunneling, and set the port |
| 130 | * state to Forwarding. Additionally, if this is the CPU | 119 | * state to Forwarding. Additionally, if this is the CPU |
| 131 | * port, enable Ingress and Egress Trailer tagging mode. | 120 | * port, enable Ingress and Egress Trailer tagging mode. |
| 132 | */ | 121 | */ |
| 133 | REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); | 122 | REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); |
| 134 | 123 | ||
| 135 | /* | 124 | /* Port based VLAN map: give each port its own address |
| 136 | * Port based VLAN map: give each port its own address | ||
| 137 | * database, allow the CPU port to talk to each of the 'real' | 125 | * database, allow the CPU port to talk to each of the 'real' |
| 138 | * ports, and allow each of the 'real' ports to only talk to | 126 | * ports, and allow each of the 'real' ports to only talk to |
| 139 | * the CPU port. | 127 | * the CPU port. |
| @@ -144,8 +132,7 @@ static int mv88e6060_setup_port(struct dsa_switch *ds, int p) | |||
| 144 | ds->phys_port_mask : | 132 | ds->phys_port_mask : |
| 145 | (1 << ds->dst->cpu_port))); | 133 | (1 << ds->dst->cpu_port))); |
| 146 | 134 | ||
| 147 | /* | 135 | /* Port Association Vector: when learning source addresses |
| 148 | * Port Association Vector: when learning source addresses | ||
| 149 | * of packets, add the address to the address database using | 136 | * of packets, add the address to the address database using |
| 150 | * a port bitmap that has only the bit for this port set and | 137 | * a port bitmap that has only the bit for this port set and |
| 151 | * the other bits clear. | 138 | * the other bits clear. |
diff --git a/drivers/net/dsa/mv88e6123_61_65.c b/drivers/net/dsa/mv88e6123_61_65.c index c17c75b9f531..a644fc9fe093 100644 --- a/drivers/net/dsa/mv88e6123_61_65.c +++ b/drivers/net/dsa/mv88e6123_61_65.c | |||
| @@ -51,27 +51,19 @@ static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds) | |||
| 51 | int i; | 51 | int i; |
| 52 | int ret; | 52 | int ret; |
| 53 | 53 | ||
| 54 | /* | 54 | /* Set all ports to the disabled state. */ |
| 55 | * Set all ports to the disabled state. | ||
| 56 | */ | ||
| 57 | for (i = 0; i < 8; i++) { | 55 | for (i = 0; i < 8; i++) { |
| 58 | ret = REG_READ(REG_PORT(i), 0x04); | 56 | ret = REG_READ(REG_PORT(i), 0x04); |
| 59 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | 57 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 60 | } | 58 | } |
| 61 | 59 | ||
| 62 | /* | 60 | /* Wait for transmit queues to drain. */ |
| 63 | * Wait for transmit queues to drain. | ||
| 64 | */ | ||
| 65 | msleep(2); | 61 | msleep(2); |
| 66 | 62 | ||
| 67 | /* | 63 | /* Reset the switch. */ |
| 68 | * Reset the switch. | ||
| 69 | */ | ||
| 70 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | 64 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); |
| 71 | 65 | ||
| 72 | /* | 66 | /* Wait up to one second for reset to complete. */ |
| 73 | * Wait up to one second for reset to complete. | ||
| 74 | */ | ||
| 75 | for (i = 0; i < 1000; i++) { | 67 | for (i = 0; i < 1000; i++) { |
| 76 | ret = REG_READ(REG_GLOBAL, 0x00); | 68 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 77 | if ((ret & 0xc800) == 0xc800) | 69 | if ((ret & 0xc800) == 0xc800) |
| @@ -90,54 +82,45 @@ static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) | |||
| 90 | int ret; | 82 | int ret; |
| 91 | int i; | 83 | int i; |
| 92 | 84 | ||
| 93 | /* | 85 | /* Disable the PHY polling unit (since there won't be any |
| 94 | * Disable the PHY polling unit (since there won't be any | ||
| 95 | * external PHYs to poll), don't discard packets with | 86 | * external PHYs to poll), don't discard packets with |
| 96 | * excessive collisions, and mask all interrupt sources. | 87 | * excessive collisions, and mask all interrupt sources. |
| 97 | */ | 88 | */ |
| 98 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); | 89 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); |
| 99 | 90 | ||
| 100 | /* | 91 | /* Set the default address aging time to 5 minutes, and |
| 101 | * Set the default address aging time to 5 minutes, and | ||
| 102 | * enable address learn messages to be sent to all message | 92 | * enable address learn messages to be sent to all message |
| 103 | * ports. | 93 | * ports. |
| 104 | */ | 94 | */ |
| 105 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | 95 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); |
| 106 | 96 | ||
| 107 | /* | 97 | /* Configure the priority mapping registers. */ |
| 108 | * Configure the priority mapping registers. | ||
| 109 | */ | ||
| 110 | ret = mv88e6xxx_config_prio(ds); | 98 | ret = mv88e6xxx_config_prio(ds); |
| 111 | if (ret < 0) | 99 | if (ret < 0) |
| 112 | return ret; | 100 | return ret; |
| 113 | 101 | ||
| 114 | /* | 102 | /* Configure the upstream port, and configure the upstream |
| 115 | * Configure the upstream port, and configure the upstream | ||
| 116 | * port as the port to which ingress and egress monitor frames | 103 | * port as the port to which ingress and egress monitor frames |
| 117 | * are to be sent. | 104 | * are to be sent. |
| 118 | */ | 105 | */ |
| 119 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); | 106 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); |
| 120 | 107 | ||
| 121 | /* | 108 | /* Disable remote management for now, and set the switch's |
