drm/radeon/si: disable cgcg and pg for now

Coarse grain clockgating causes problems with reclocking on
some cards and powergating (verde only) causes problems with
ring initialization.  The proper fix (restructuring the init
sequences) is too invasive for 3.11 so just disable them for
now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 1d656f7b13f2..6ca904673a4f 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5216,7 +5216,7 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
 static void si_init_cg(struct radeon_device *rdev)
 {
         si_enable_mgcg(rdev, true);
-        si_enable_cgcg(rdev, true);
+        si_enable_cgcg(rdev, false);
         /* disable MC LS on Tahiti */
         if (rdev->family == CHIP_TAHITI)
                 si_enable_mc_ls(rdev, false);
@@ -5237,11 +5237,11 @@ static void si_fini_cg(struct radeon_device *rdev)
 static void si_init_pg(struct radeon_device *rdev)
 {
         bool has_pg = false;
-
+#if 0
         /* only cape verde supports PG */
         if (rdev->family == CHIP_VERDE)
                 has_pg = true;
-
+#endif
         if (has_pg) {
                 si_init_ao_cu_mask(rdev);
                 si_init_dma_pg(rdev);