diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2015-03-31 11:43:12 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-04-27 09:54:54 -0400 |
| commit | 362ff251390f3d1f8fe94666f4fc4e5876381114 (patch) | |
| tree | b151ce9db25774439835463d684f2018201ba182 | |
| parent | 12428327bbd1180b5d8ef83fdf9482b878d0502a (diff) | |
drm/radeon/audio: don't enable packets until the end
Don't enable the audio and avi infoframes and audio stream
until all the state is set up.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 7264ccd337af..9e1cd0cfcd55 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
| @@ -222,10 +222,6 @@ void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, | |||
| 222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, | 222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
| 223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ | 223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
| 224 | ~HDMI_AVI_INFO_LINE_MASK); | 224 | ~HDMI_AVI_INFO_LINE_MASK); |
| 225 | |||
| 226 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, | ||
| 227 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | ||
| 228 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ | ||
| 229 | } | 225 | } |
| 230 | 226 | ||
| 231 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, | 227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
| @@ -370,9 +366,13 @@ void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) | |||
| 370 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, | 366 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
| 371 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); | 367 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
| 372 | 368 | ||
| 369 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, | ||
| 370 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | ||
| 371 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | ||
| 372 | |||
| 373 | /* allow 60958 channel status and send audio packets fields to be updated */ | 373 | /* allow 60958 channel status and send audio packets fields to be updated */ |
| 374 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, | 374 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
| 375 | AFMT_AUDIO_SAMPLE_SEND | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); | 375 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
| 376 | } | 376 | } |
| 377 | 377 | ||
| 378 | 378 | ||
| @@ -398,17 +398,16 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
| 398 | return; | 398 | return; |
| 399 | 399 | ||
| 400 | if (enable) { | 400 | if (enable) { |
| 401 | WREG32(HDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, | ||
| 402 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ | ||
| 403 | |||
| 404 | WREG32(HDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, | ||
| 405 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | ||
| 406 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | ||
| 407 | |||
| 408 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, | 401 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
| 402 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | ||
| 403 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ | ||
| 409 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | 404 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 410 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | 405 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
| 406 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | ||
| 407 | AFMT_AUDIO_SAMPLE_SEND); | ||
| 411 | } else { | 408 | } else { |
| 409 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | ||
| 410 | ~AFMT_AUDIO_SAMPLE_SEND); | ||
| 412 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); | 411 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
| 413 | } | 412 | } |
| 414 | 413 | ||
| @@ -434,6 +433,9 @@ void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) | |||
| 434 | struct radeon_connector_atom_dig *dig_connector; | 433 | struct radeon_connector_atom_dig *dig_connector; |
| 435 | uint32_t val; | 434 | uint32_t val; |
| 436 | 435 | ||
| 436 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | ||
| 437 | AFMT_AUDIO_SAMPLE_SEND); | ||
| 438 | |||
| 437 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, | 439 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
| 438 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); | 440 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
| 439 | 441 | ||
| @@ -457,6 +459,8 @@ void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) | |||
| 457 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ | 459 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
| 458 | } else { | 460 | } else { |
| 459 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); | 461 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
| 462 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | ||
| 463 | ~AFMT_AUDIO_SAMPLE_SEND); | ||
| 460 | } | 464 | } |
| 461 | 465 | ||
| 462 | dig->afmt->enabled = enable; | 466 | dig->afmt->enabled = enable; |
