diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-03-09 10:54:51 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-10 09:41:44 -0400 |
| commit | 3563c32d6532ece53c9dd8905a8e41983ef9952f (patch) | |
| tree | 5c2a00d13913295a2683d1259a55b86629e2f589 | |
| parent | eeb538950367e3966cbf0237ab1a1dc30e059818 (diff) | |
MIPS: unaligned: Surround load/store macros in do {} while statements
It's best to surround such complex macros with do {} while statements
so they can appear as independent logical blocks when used within other
control blocks.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9502/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/unaligned.c | 116 |
1 files changed, 90 insertions, 26 deletions
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 7a5707eea898..ab475903175f 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c | |||
| @@ -110,6 +110,7 @@ extern void show_registers(struct pt_regs *regs); | |||
| 110 | 110 | ||
| 111 | #ifdef __BIG_ENDIAN | 111 | #ifdef __BIG_ENDIAN |
| 112 | #define _LoadHW(addr, value, res, type) \ | 112 | #define _LoadHW(addr, value, res, type) \ |
| 113 | do { \ | ||
| 113 | __asm__ __volatile__ (".set\tnoat\n" \ | 114 | __asm__ __volatile__ (".set\tnoat\n" \ |
| 114 | "1:\t"type##_lb("%0", "0(%2)")"\n" \ | 115 | "1:\t"type##_lb("%0", "0(%2)")"\n" \ |
| 115 | "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ | 116 | "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ |
| @@ -127,10 +128,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 127 | STR(PTR)"\t2b, 4b\n\t" \ | 128 | STR(PTR)"\t2b, 4b\n\t" \ |
| 128 | ".previous" \ | 129 | ".previous" \ |
| 129 | : "=&r" (value), "=r" (res) \ | 130 | : "=&r" (value), "=r" (res) \ |
| 130 | : "r" (addr), "i" (-EFAULT)); | 131 | : "r" (addr), "i" (-EFAULT)); \ |
| 132 | } while(0) | ||
| 131 | 133 | ||
| 132 | #ifndef CONFIG_CPU_MIPSR6 | 134 | #ifndef CONFIG_CPU_MIPSR6 |
| 133 | #define _LoadW(addr, value, res, type) \ | 135 | #define _LoadW(addr, value, res, type) \ |
| 136 | do { \ | ||
| 134 | __asm__ __volatile__ ( \ | 137 | __asm__ __volatile__ ( \ |
| 135 | "1:\t"type##_lwl("%0", "(%2)")"\n" \ | 138 | "1:\t"type##_lwl("%0", "(%2)")"\n" \ |
| 136 | "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ | 139 | "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ |
| @@ -146,10 +149,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 146 | STR(PTR)"\t2b, 4b\n\t" \ | 149 | STR(PTR)"\t2b, 4b\n\t" \ |
| 147 | ".previous" \ | 150 | ".previous" \ |
| 148 | : "=&r" (value), "=r" (res) \ | 151 | : "=&r" (value), "=r" (res) \ |
| 149 | : "r" (addr), "i" (-EFAULT)); | 152 | : "r" (addr), "i" (-EFAULT)); \ |
| 153 | } while(0) | ||
| 154 | |||
| 150 | #else | 155 | #else |
| 151 | /* MIPSR6 has no lwl instruction */ | 156 | /* MIPSR6 has no lwl instruction */ |
| 152 | #define _LoadW(addr, value, res, type) \ | 157 | #define _LoadW(addr, value, res, type) \ |
| 158 | do { \ | ||
| 153 | __asm__ __volatile__ ( \ | 159 | __asm__ __volatile__ ( \ |
| 154 | ".set\tpush\n" \ | 160 | ".set\tpush\n" \ |
| 155 | ".set\tnoat\n\t" \ | 161 | ".set\tnoat\n\t" \ |
| @@ -178,10 +184,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 178 | STR(PTR)"\t4b, 11b\n\t" \ | 184 | STR(PTR)"\t4b, 11b\n\t" \ |
| 179 | ".previous" \ | 185 | ".previous" \ |
| 180 | : "=&r" (value), "=r" (res) \ | 186 | : "=&r" (value), "=r" (res) \ |
| 181 | : "r" (addr), "i" (-EFAULT)); | 187 | : "r" (addr), "i" (-EFAULT)); \ |
| 188 | } while(0) | ||
| 189 | |||
| 182 | #endif /* CONFIG_CPU_MIPSR6 */ | 190 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 183 | 191 | ||
| 184 | #define _LoadHWU(addr, value, res, type) \ | 192 | #define _LoadHWU(addr, value, res, type) \ |
| 193 | do { \ | ||
| 185 | __asm__ __volatile__ ( \ | 194 | __asm__ __volatile__ ( \ |
| 186 | ".set\tnoat\n" \ | 195 | ".set\tnoat\n" \ |
| 187 | "1:\t"type##_lbu("%0", "0(%2)")"\n" \ | 196 | "1:\t"type##_lbu("%0", "0(%2)")"\n" \ |
| @@ -201,10 +210,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 201 | STR(PTR)"\t2b, 4b\n\t" \ | 210 | STR(PTR)"\t2b, 4b\n\t" \ |
| 202 | ".previous" \ | 211 | ".previous" \ |
| 203 | : "=&r" (value), "=r" (res) \ | 212 | : "=&r" (value), "=r" (res) \ |
| 204 | : "r" (addr), "i" (-EFAULT)); | 213 | : "r" (addr), "i" (-EFAULT)); \ |
| 214 | } while(0) | ||
| 205 | 215 | ||
| 206 | #ifndef CONFIG_CPU_MIPSR6 | 216 | #ifndef CONFIG_CPU_MIPSR6 |
| 207 | #define _LoadWU(addr, value, res, type) \ | 217 | #define _LoadWU(addr, value, res, type) \ |
| 218 | do { \ | ||
| 208 | __asm__ __volatile__ ( \ | 219 | __asm__ __volatile__ ( \ |
| 209 | "1:\t"type##_lwl("%0", "(%2)")"\n" \ | 220 | "1:\t"type##_lwl("%0", "(%2)")"\n" \ |
| 210 | "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ | 221 | "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ |
| @@ -222,9 +233,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 222 | STR(PTR)"\t2b, 4b\n\t" \ | 233 | STR(PTR)"\t2b, 4b\n\t" \ |
| 223 | ".previous" \ | 234 | ".previous" \ |
| 224 | : "=&r" (value), "=r" (res) \ | 235 | : "=&r" (value), "=r" (res) \ |
| 225 | : "r" (addr), "i" (-EFAULT)); | 236 | : "r" (addr), "i" (-EFAULT)); \ |
| 237 | } while(0) | ||
| 226 | 238 | ||
| 227 | #define _LoadDW(addr, value, res) \ | 239 | #define _LoadDW(addr, value, res) \ |
| 240 | do { \ | ||
| 228 | __asm__ __volatile__ ( \ | 241 | __asm__ __volatile__ ( \ |
| 229 | "1:\tldl\t%0, (%2)\n" \ | 242 | "1:\tldl\t%0, (%2)\n" \ |
| 230 | "2:\tldr\t%0, 7(%2)\n\t" \ | 243 | "2:\tldr\t%0, 7(%2)\n\t" \ |
| @@ -240,10 +253,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 240 | STR(PTR)"\t2b, 4b\n\t" \ | 253 | STR(PTR)"\t2b, 4b\n\t" \ |
| 241 | ".previous" \ | 254 | ".previous" \ |
| 242 | : "=&r" (value), "=r" (res) \ | 255 | : "=&r" (value), "=r" (res) \ |
| 243 | : "r" (addr), "i" (-EFAULT)); | 256 | : "r" (addr), "i" (-EFAULT)); \ |
| 257 | } while(0) | ||
| 258 | |||
| 244 | #else | 259 | #else |
| 245 | /* MIPSR6 has not lwl and ldl instructions */ | 260 | /* MIPSR6 has not lwl and ldl instructions */ |
| 246 | #define _LoadWU(addr, value, res, type) \ | 261 | #define _LoadWU(addr, value, res, type) \ |
| 262 | do { \ | ||
| 247 | __asm__ __volatile__ ( \ | 263 | __asm__ __volatile__ ( \ |
| 248 | ".set\tpush\n\t" \ | 264 | ".set\tpush\n\t" \ |
| 249 | ".set\tnoat\n\t" \ | 265 | ".set\tnoat\n\t" \ |
| @@ -272,9 +288,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 272 | STR(PTR)"\t4b, 11b\n\t" \ | 288 | STR(PTR)"\t4b, 11b\n\t" \ |
| 273 | ".previous" \ | 289 | ".previous" \ |
| 274 | : "=&r" (value), "=r" (res) \ | 290 | : "=&r" (value), "=r" (res) \ |
| 275 | : "r" (addr), "i" (-EFAULT)); | 291 | : "r" (addr), "i" (-EFAULT)); \ |
| 292 | } while(0) | ||
| 276 | 293 | ||
| 277 | #define _LoadDW(addr, value, res) \ | 294 | #define _LoadDW(addr, value, res) \ |
| 295 | do { \ | ||
| 278 | __asm__ __volatile__ ( \ | 296 | __asm__ __volatile__ ( \ |
| 279 | ".set\tpush\n\t" \ | 297 | ".set\tpush\n\t" \ |
| 280 | ".set\tnoat\n\t" \ | 298 | ".set\tnoat\n\t" \ |
| @@ -319,11 +337,14 @@ extern void show_registers(struct pt_regs *regs); | |||
| 319 | STR(PTR)"\t8b, 11b\n\t" \ | 337 | STR(PTR)"\t8b, 11b\n\t" \ |
| 320 | ".previous" \ | 338 | ".previous" \ |
| 321 | : "=&r" (value), "=r" (res) \ | 339 | : "=&r" (value), "=r" (res) \ |
| 322 | : "r" (addr), "i" (-EFAULT)); | 340 | : "r" (addr), "i" (-EFAULT)); \ |
| 341 | } while(0) | ||
| 342 | |||
| 323 | #endif /* CONFIG_CPU_MIPSR6 */ | 343 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 324 | 344 | ||
| 325 | 345 | ||
| 326 | #define _StoreHW(addr, value, res, type) \ | 346 | #define _StoreHW(addr, value, res, type) \ |
| 347 | do { \ | ||
| 327 | __asm__ __volatile__ ( \ | 348 | __asm__ __volatile__ ( \ |
| 328 | ".set\tnoat\n" \ | 349 | ".set\tnoat\n" \ |
| 329 | "1:\t"type##_sb("%1", "1(%2)")"\n" \ | 350 | "1:\t"type##_sb("%1", "1(%2)")"\n" \ |
| @@ -342,10 +363,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 342 | STR(PTR)"\t2b, 4b\n\t" \ | 363 | STR(PTR)"\t2b, 4b\n\t" \ |
| 343 | ".previous" \ | 364 | ".previous" \ |
| 344 | : "=r" (res) \ | 365 | : "=r" (res) \ |
| 345 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 366 | : "r" (value), "r" (addr), "i" (-EFAULT));\ |
| 367 | } while(0) | ||
| 346 | 368 | ||
| 347 | #ifndef CONFIG_CPU_MIPSR6 | 369 | #ifndef CONFIG_CPU_MIPSR6 |
| 348 | #define _StoreW(addr, value, res, type) \ | 370 | #define _StoreW(addr, value, res, type) \ |
| 371 | do { \ | ||
| 349 | __asm__ __volatile__ ( \ | 372 | __asm__ __volatile__ ( \ |
| 350 | "1:\t"type##_swl("%1", "(%2)")"\n" \ | 373 | "1:\t"type##_swl("%1", "(%2)")"\n" \ |
| 351 | "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ | 374 | "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ |
| @@ -361,9 +384,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 361 | STR(PTR)"\t2b, 4b\n\t" \ | 384 | STR(PTR)"\t2b, 4b\n\t" \ |
| 362 | ".previous" \ | 385 | ".previous" \ |
| 363 | : "=r" (res) \ | 386 | : "=r" (res) \ |
| 364 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 387 | : "r" (value), "r" (addr), "i" (-EFAULT)); \ |
| 388 | } while(0) | ||
| 365 | 389 | ||
| 366 | #define _StoreDW(addr, value, res) \ | 390 | #define _StoreDW(addr, value, res) \ |
| 391 | do { \ | ||
| 367 | __asm__ __volatile__ ( \ | 392 | __asm__ __volatile__ ( \ |
| 368 | "1:\tsdl\t%1,(%2)\n" \ | 393 | "1:\tsdl\t%1,(%2)\n" \ |
| 369 | "2:\tsdr\t%1, 7(%2)\n\t" \ | 394 | "2:\tsdr\t%1, 7(%2)\n\t" \ |
| @@ -379,10 +404,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 379 | STR(PTR)"\t2b, 4b\n\t" \ | 404 | STR(PTR)"\t2b, 4b\n\t" \ |
| 380 | ".previous" \ | 405 | ".previous" \ |
| 381 | : "=r" (res) \ | 406 | : "=r" (res) \ |
| 382 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 407 | : "r" (value), "r" (addr), "i" (-EFAULT)); \ |
| 408 | } while(0) | ||
| 409 | |||
| 383 | #else | 410 | #else |
| 384 | /* MIPSR6 has no swl and sdl instructions */ | 411 | /* MIPSR6 has no swl and sdl instructions */ |
| 385 | #define _StoreW(addr, value, res, type) \ | 412 | #define _StoreW(addr, value, res, type) \ |
| 413 | do { \ | ||
| 386 | __asm__ __volatile__ ( \ | 414 | __asm__ __volatile__ ( \ |
| 387 | ".set\tpush\n\t" \ | 415 | ".set\tpush\n\t" \ |
| 388 | ".set\tnoat\n\t" \ | 416 | ".set\tnoat\n\t" \ |
| @@ -409,9 +437,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 409 | ".previous" \ | 437 | ".previous" \ |
| 410 | : "=&r" (res) \ | 438 | : "=&r" (res) \ |
| 411 | : "r" (value), "r" (addr), "i" (-EFAULT) \ | 439 | : "r" (value), "r" (addr), "i" (-EFAULT) \ |
| 412 | : "memory"); | 440 | : "memory"); \ |
| 441 | } while(0) | ||
| 413 | 442 | ||
| 414 | #define StoreDW(addr, value, res) \ | 443 | #define StoreDW(addr, value, res) \ |
| 444 | do { \ | ||
| 415 | __asm__ __volatile__ ( \ | 445 | __asm__ __volatile__ ( \ |
| 416 | ".set\tpush\n\t" \ | 446 | ".set\tpush\n\t" \ |
| 417 | ".set\tnoat\n\t" \ | 447 | ".set\tnoat\n\t" \ |
| @@ -451,12 +481,15 @@ extern void show_registers(struct pt_regs *regs); | |||
| 451 | ".previous" \ | 481 | ".previous" \ |
| 452 | : "=&r" (res) \ | 482 | : "=&r" (res) \ |
| 453 | : "r" (value), "r" (addr), "i" (-EFAULT) \ | 483 | : "r" (value), "r" (addr), "i" (-EFAULT) \ |
| 454 | : "memory"); | 484 | : "memory"); \ |
| 485 | } while(0) | ||
| 486 | |||
| 455 | #endif /* CONFIG_CPU_MIPSR6 */ | 487 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 456 | 488 | ||
| 457 | #else /* __BIG_ENDIAN */ | 489 | #else /* __BIG_ENDIAN */ |
| 458 | 490 | ||
| 459 | #define _LoadHW(addr, value, res, type) \ | 491 | #define _LoadHW(addr, value, res, type) \ |
| 492 | do { \ | ||
| 460 | __asm__ __volatile__ (".set\tnoat\n" \ | 493 | __asm__ __volatile__ (".set\tnoat\n" \ |
| 461 | "1:\t"type##_lb("%0", "1(%2)")"\n" \ | 494 | "1:\t"type##_lb("%0", "1(%2)")"\n" \ |
| 462 | "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ | 495 | "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ |
| @@ -474,10 +507,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 474 | STR(PTR)"\t2b, 4b\n\t" \ | 507 | STR(PTR)"\t2b, 4b\n\t" \ |
| 475 | ".previous" \ | 508 | ".previous" \ |
| 476 | : "=&r" (value), "=r" (res) \ | 509 | : "=&r" (value), "=r" (res) \ |
| 477 | : "r" (addr), "i" (-EFAULT)); | 510 | : "r" (addr), "i" (-EFAULT)); \ |
| 511 | } while(0) | ||
| 478 | 512 | ||
| 479 | #ifndef CONFIG_CPU_MIPSR6 | 513 | #ifndef CONFIG_CPU_MIPSR6 |
| 480 | #define _LoadW(addr, value, res, type) \ | 514 | #define _LoadW(addr, value, res, type) \ |
| 515 | do { \ | ||
| 481 | __asm__ __volatile__ ( \ | 516 | __asm__ __volatile__ ( \ |
| 482 | "1:\t"type##_lwl("%0", "3(%2)")"\n" \ | 517 | "1:\t"type##_lwl("%0", "3(%2)")"\n" \ |
| 483 | "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ | 518 | "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ |
| @@ -493,10 +528,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 493 | STR(PTR)"\t2b, 4b\n\t" \ | 528 | STR(PTR)"\t2b, 4b\n\t" \ |
| 494 | ".previous" \ | 529 | ".previous" \ |
| 495 | : "=&r" (value), "=r" (res) \ | 530 | : "=&r" (value), "=r" (res) \ |
| 496 | : "r" (addr), "i" (-EFAULT)); | 531 | : "r" (addr), "i" (-EFAULT)); \ |
| 532 | } while(0) | ||
| 533 | |||
| 497 | #else | 534 | #else |
| 498 | /* MIPSR6 has no lwl instruction */ | 535 | /* MIPSR6 has no lwl instruction */ |
| 499 | #define _LoadW(addr, value, res, type) \ | 536 | #define _LoadW(addr, value, res, type) \ |
| 537 | do { \ | ||
| 500 | __asm__ __volatile__ ( \ | 538 | __asm__ __volatile__ ( \ |
| 501 | ".set\tpush\n" \ | 539 | ".set\tpush\n" \ |
| 502 | ".set\tnoat\n\t" \ | 540 | ".set\tnoat\n\t" \ |
| @@ -525,11 +563,14 @@ extern void show_registers(struct pt_regs *regs); | |||
| 525 | STR(PTR)"\t4b, 11b\n\t" \ | 563 | STR(PTR)"\t4b, 11b\n\t" \ |
| 526 | ".previous" \ | 564 | ".previous" \ |
| 527 | : "=&r" (value), "=r" (res) \ | 565 | : "=&r" (value), "=r" (res) \ |
| 528 | : "r" (addr), "i" (-EFAULT)); | 566 | : "r" (addr), "i" (-EFAULT)); \ |
| 567 | } while(0) | ||
| 568 | |||
| 529 | #endif /* CONFIG_CPU_MIPSR6 */ | 569 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 530 | 570 | ||
| 531 | 571 | ||
| 532 | #define _LoadHWU(addr, value, res, type) \ | 572 | #define _LoadHWU(addr, value, res, type) \ |
| 573 | do { \ | ||
| 533 | __asm__ __volatile__ ( \ | 574 | __asm__ __volatile__ ( \ |
| 534 | ".set\tnoat\n" \ | 575 | ".set\tnoat\n" \ |
| 535 | "1:\t"type##_lbu("%0", "1(%2)")"\n" \ | 576 | "1:\t"type##_lbu("%0", "1(%2)")"\n" \ |
| @@ -549,10 +590,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 549 | STR(PTR)"\t2b, 4b\n\t" \ | 590 | STR(PTR)"\t2b, 4b\n\t" \ |
| 550 | ".previous" \ | 591 | ".previous" \ |
| 551 | : "=&r" (value), "=r" (res) \ | 592 | : "=&r" (value), "=r" (res) \ |
| 552 | : "r" (addr), "i" (-EFAULT)); | 593 | : "r" (addr), "i" (-EFAULT)); \ |
| 594 | } while(0) | ||
| 553 | 595 | ||
| 554 | #ifndef CONFIG_CPU_MIPSR6 | 596 | #ifndef CONFIG_CPU_MIPSR6 |
| 555 | #define _LoadWU(addr, value, res, type) \ | 597 | #define _LoadWU(addr, value, res, type) \ |
| 598 | do { \ | ||
| 556 | __asm__ __volatile__ ( \ | 599 | __asm__ __volatile__ ( \ |
| 557 | "1:\t"type##_lwl("%0", "3(%2)")"\n" \ | 600 | "1:\t"type##_lwl("%0", "3(%2)")"\n" \ |
| 558 | "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ | 601 | "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ |
| @@ -570,9 +613,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 570 | STR(PTR)"\t2b, 4b\n\t" \ | 613 | STR(PTR)"\t2b, 4b\n\t" \ |
| 571 | ".previous" \ | 614 | ".previous" \ |
| 572 | : "=&r" (value), "=r" (res) \ | 615 | : "=&r" (value), "=r" (res) \ |
| 573 | : "r" (addr), "i" (-EFAULT)); | 616 | : "r" (addr), "i" (-EFAULT)); \ |
| 617 | } while(0) | ||
| 574 | 618 | ||
| 575 | #define _LoadDW(addr, value, res) \ | 619 | #define _LoadDW(addr, value, res) \ |
| 620 | do { \ | ||
| 576 | __asm__ __volatile__ ( \ | 621 | __asm__ __volatile__ ( \ |
| 577 | "1:\tldl\t%0, 7(%2)\n" \ | 622 | "1:\tldl\t%0, 7(%2)\n" \ |
| 578 | "2:\tldr\t%0, (%2)\n\t" \ | 623 | "2:\tldr\t%0, (%2)\n\t" \ |
| @@ -588,10 +633,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 588 | STR(PTR)"\t2b, 4b\n\t" \ | 633 | STR(PTR)"\t2b, 4b\n\t" \ |
| 589 | ".previous" \ | 634 | ".previous" \ |
| 590 | : "=&r" (value), "=r" (res) \ | 635 | : "=&r" (value), "=r" (res) \ |
| 591 | : "r" (addr), "i" (-EFAULT)); | 636 | : "r" (addr), "i" (-EFAULT)); \ |
| 637 | } while(0) | ||
| 638 | |||
| 592 | #else | 639 | #else |
| 593 | /* MIPSR6 has not lwl and ldl instructions */ | 640 | /* MIPSR6 has not lwl and ldl instructions */ |
| 594 | #define _LoadWU(addr, value, res, type) \ | 641 | #define _LoadWU(addr, value, res, type) \ |
| 642 | do { \ | ||
| 595 | __asm__ __volatile__ ( \ | 643 | __asm__ __volatile__ ( \ |
| 596 | ".set\tpush\n\t" \ | 644 | ".set\tpush\n\t" \ |
| 597 | ".set\tnoat\n\t" \ | 645 | ".set\tnoat\n\t" \ |
| @@ -620,9 +668,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 620 | STR(PTR)"\t4b, 11b\n\t" \ | 668 | STR(PTR)"\t4b, 11b\n\t" \ |
| 621 | ".previous" \ | 669 | ".previous" \ |
| 622 | : "=&r" (value), "=r" (res) \ | 670 | : "=&r" (value), "=r" (res) \ |
| 623 | : "r" (addr), "i" (-EFAULT)); | 671 | : "r" (addr), "i" (-EFAULT)); \ |
| 672 | } while(0) | ||
| 624 | 673 | ||
| 625 | #define _LoadDW(addr, value, res) \ | 674 | #define _LoadDW(addr, value, res) \ |
| 675 | do { \ | ||
| 626 | __asm__ __volatile__ ( \ | 676 | __asm__ __volatile__ ( \ |
| 627 | ".set\tpush\n\t" \ | 677 | ".set\tpush\n\t" \ |
| 628 | ".set\tnoat\n\t" \ | 678 | ".set\tnoat\n\t" \ |
| @@ -667,10 +717,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 667 | STR(PTR)"\t8b, 11b\n\t" \ | 717 | STR(PTR)"\t8b, 11b\n\t" \ |
| 668 | ".previous" \ | 718 | ".previous" \ |
| 669 | : "=&r" (value), "=r" (res) \ | 719 | : "=&r" (value), "=r" (res) \ |
| 670 | : "r" (addr), "i" (-EFAULT)); | 720 | : "r" (addr), "i" (-EFAULT)); \ |
| 721 | } while(0) | ||
| 671 | #endif /* CONFIG_CPU_MIPSR6 */ | 722 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 672 | 723 | ||
| 673 | #define _StoreHW(addr, value, res, type) \ | 724 | #define _StoreHW(addr, value, res, type) \ |
| 725 | do { \ | ||
| 674 | __asm__ __volatile__ ( \ | 726 | __asm__ __volatile__ ( \ |
| 675 | ".set\tnoat\n" \ | 727 | ".set\tnoat\n" \ |
| 676 | "1:\t"type##_sb("%1", "0(%2)")"\n" \ | 728 | "1:\t"type##_sb("%1", "0(%2)")"\n" \ |
| @@ -689,9 +741,12 @@ extern void show_registers(struct pt_regs *regs); | |||
| 689 | STR(PTR)"\t2b, 4b\n\t" \ | 741 | STR(PTR)"\t2b, 4b\n\t" \ |
| 690 | ".previous" \ | 742 | ".previous" \ |
| 691 | : "=r" (res) \ | 743 | : "=r" (res) \ |
| 692 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 744 | : "r" (value), "r" (addr), "i" (-EFAULT));\ |
| 745 | } while(0) | ||
| 746 | |||
| 693 | #ifndef CONFIG_CPU_MIPSR6 | 747 | #ifndef CONFIG_CPU_MIPSR6 |
| 694 | #define _StoreW(addr, value, res, type) \ | 748 | #define _StoreW(addr, value, res, type) \ |
| 749 | do { \ | ||
| 695 | __asm__ __volatile__ ( \ | 750 | __asm__ __volatile__ ( \ |
| 696 | "1:\t"type##_swl("%1", "3(%2)")"\n" \ | 751 | "1:\t"type##_swl("%1", "3(%2)")"\n" \ |
| 697 | "2:\t"type##_swr("%1", "(%2)")"\n\t"\ | 752 | "2:\t"type##_swr("%1", "(%2)")"\n\t"\ |
| @@ -707,9 +762,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 707 | STR(PTR)"\t2b, 4b\n\t" \ | 762 | STR(PTR)"\t2b, 4b\n\t" \ |
| 708 | ".previous" \ | 763 | ".previous" \ |
| 709 | : "=r" (res) \ | 764 | : "=r" (res) \ |
| 710 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 765 | : "r" (value), "r" (addr), "i" (-EFAULT)); \ |
| 766 | } while(0) | ||
| 711 | 767 | ||
| 712 | #define _StoreDW(addr, value, res) \ | 768 | #define _StoreDW(addr, value, res) \ |
| 769 | do { \ | ||
| 713 | __asm__ __volatile__ ( \ | 770 | __asm__ __volatile__ ( \ |
| 714 | "1:\tsdl\t%1, 7(%2)\n" \ | 771 | "1:\tsdl\t%1, 7(%2)\n" \ |
| 715 | "2:\tsdr\t%1, (%2)\n\t" \ | 772 | "2:\tsdr\t%1, (%2)\n\t" \ |
| @@ -725,10 +782,13 @@ extern void show_registers(struct pt_regs *regs); | |||
| 725 | STR(PTR)"\t2b, 4b\n\t" \ | 782 | STR(PTR)"\t2b, 4b\n\t" \ |
| 726 | ".previous" \ | 783 | ".previous" \ |
| 727 | : "=r" (res) \ | 784 | : "=r" (res) \ |
| 728 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 785 | : "r" (value), "r" (addr), "i" (-EFAULT)); \ |
| 786 | } while(0) | ||
| 787 | |||
| 729 | #else | 788 | #else |
| 730 | /* MIPSR6 has no swl and sdl instructions */ | 789 | /* MIPSR6 has no swl and sdl instructions */ |
| 731 | #define _StoreW(addr, value, res, type) \ | 790 | #define _StoreW(addr, value, res, type) \ |
| 791 | do { \ | ||
| 732 | __asm__ __volatile__ ( \ | 792 | __asm__ __volatile__ ( \ |
| 733 | ".set\tpush\n\t" \ | 793 | ".set\tpush\n\t" \ |
| 734 | ".set\tnoat\n\t" \ | 794 | ".set\tnoat\n\t" \ |
| @@ -755,9 +815,11 @@ extern void show_registers(struct pt_regs *regs); | |||
| 755 | ".previous" \ | 815 | ".previous" \ |
| 756 | : "=&r" (res) \ | 816 | : "=&r" (res) \ |
| 757 | : "r" (value), "r" (addr), "i" (-EFAULT) \ | 817 | : "r" (value), "r" (addr), "i" (-EFAULT) \ |
| 758 | : "memory"); | 818 | : "memory"); \ |
| 819 | } while(0) | ||
| 759 | 820 | ||
| 760 | #define _StoreDW(addr, value, res) \ | 821 | #define _StoreDW(addr, value, res) \ |
| 822 | do { \ | ||
| 761 | __asm__ __volatile__ ( \ | 823 | __asm__ __volatile__ ( \ |
| 762 | ".set\tpush\n\t" \ | 824 | ".set\tpush\n\t" \ |
| 763 | ".set\tnoat\n\t" \ | 825 | ".set\tnoat\n\t" \ |
| @@ -797,7 +859,9 @@ extern void show_registers(struct pt_regs *regs); | |||
| 797 | ".previous" \ | 859 | ".previous" \ |
| 798 | : "=&r" (res) \ | 860 | : "=&r" (res) \ |
| 799 | : "r" (value), "r" (addr), "i" (-EFAULT) \ | 861 | : "r" (value), "r" (addr), "i" (-EFAULT) \ |
| 800 | : "memory"); | 862 | : "memory"); \ |
| 863 | } while(0) | ||
| 864 | |||
| 801 | #endif /* CONFIG_CPU_MIPSR6 */ | 865 | #endif /* CONFIG_CPU_MIPSR6 */ |
| 802 | #endif | 866 | #endif |
| 803 | 867 | ||