diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-12-17 23:23:23 -0500 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-12-18 15:23:46 -0500 |
| commit | 3533bf6b15a0885344367aa2a4b3e2c8e496520f (patch) | |
| tree | 57db6d61bdf5ea88ed32d67ffe331db535a09d7b | |
| parent | ee65b38890fd98ba927aa2a69c5cc2b2cc1c9c38 (diff) | |
ath9k: Fix regulatory compliance
To comply with ETSI regulations, make sure that
the CCA registers are programmed with the threshold
values from the EEPROM/Caldata. A new field is used
to indicate if the card has been calibrated with the
required threshold information.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 32 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 4 |
2 files changed, 35 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index d9e09bf178aa..c8d22eccfef8 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
| @@ -4121,6 +4121,37 @@ static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) | |||
| 4121 | } | 4121 | } |
| 4122 | } | 4122 | } |
| 4123 | 4123 | ||
| 4124 | static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, | ||
| 4125 | bool is2ghz) | ||
| 4126 | { | ||
| 4127 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | ||
| 4128 | const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = { | ||
| 4129 | AR_PHY_CCA_CTRL_0, | ||
| 4130 | AR_PHY_CCA_CTRL_1, | ||
| 4131 | AR_PHY_CCA_CTRL_2, | ||
| 4132 | }; | ||
| 4133 | int chain; | ||
| 4134 | u32 val; | ||
| 4135 | |||
| 4136 | if (is2ghz) { | ||
| 4137 | if (!(eep->base_ext1.misc_enable & BIT(2))) | ||
| 4138 | return; | ||
| 4139 | } else { | ||
| 4140 | if (!(eep->base_ext1.misc_enable & BIT(3))) | ||
| 4141 | return; | ||
| 4142 | } | ||
| 4143 | |||
| 4144 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | ||
| 4145 | if (!(ah->caps.tx_chainmask & BIT(chain))) | ||
| 4146 | continue; | ||
| 4147 | |||
| 4148 | val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; | ||
| 4149 | REG_RMW_FIELD(ah, cca_ctrl[chain], | ||
| 4150 | AR_PHY_EXT_CCA0_THRESH62_1, val); | ||
| 4151 | } | ||
| 4152 | |||
| 4153 | } | ||
| 4154 | |||
| 4124 | static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, | 4155 | static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, |
| 4125 | struct ath9k_channel *chan) | 4156 | struct ath9k_channel *chan) |
| 4126 | { | 4157 | { |
| @@ -4135,6 +4166,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, | |||
| 4135 | if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah)) | 4166 | if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah)) |
| 4136 | ar9003_hw_internal_regulator_apply(ah); | 4167 | ar9003_hw_internal_regulator_apply(ah); |
| 4137 | ar9003_hw_apply_tuning_caps(ah); | 4168 | ar9003_hw_apply_tuning_caps(ah); |
| 4169 | ar9003_hw_apply_minccapwr_thresh(ah, chan); | ||
| 4138 | ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); | 4170 | ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); |
| 4139 | ar9003_hw_thermometer_apply(ah); | 4171 | ar9003_hw_thermometer_apply(ah); |
| 4140 | ar9003_hw_thermo_cal_apply(ah); | 4172 | ar9003_hw_thermo_cal_apply(ah); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index bbbfc4dc59eb..1b441715ba39 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
| @@ -270,7 +270,7 @@ | |||
| 270 | #define AR_PHY_AGC (AR_AGC_BASE + 0x14) | 270 | #define AR_PHY_AGC (AR_AGC_BASE + 0x14) |
| 271 | #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18) | 271 | #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18) |
| 272 | #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) | 272 | #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) |
| 273 | #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) | 273 | #define AR_PHY_CCA_CTRL_0 (AR_AGC_BASE + 0x20) |
| 274 | #define AR_PHY_RESTART (AR_AGC_BASE + 0x24) | 274 | #define AR_PHY_RESTART (AR_AGC_BASE + 0x24) |
| 275 | 275 | ||
| 276 | /* | 276 | /* |
| @@ -398,6 +398,8 @@ | |||
| 398 | #define AR9280_PHY_CCA_THRESH62_S 12 | 398 | #define AR9280_PHY_CCA_THRESH62_S 12 |
| 399 | #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF | 399 | #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF |
| 400 | #define AR_PHY_EXT_CCA0_THRESH62_S 0 | 400 | #define AR_PHY_EXT_CCA0_THRESH62_S 0 |
| 401 | #define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF | ||
| 402 | #define AR_PHY_EXT_CCA0_THRESH62_1_S 0 | ||
| 401 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F | 403 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F |
| 402 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 | 404 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 |
| 403 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 | 405 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 |
