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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-03 08:46:31 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-08-25 10:27:33 -0400
commit351a4ffea259a11deebe0eb169c46ccbfc3abd36 (patch)
tree8f8e32b8f0b0261280567dbb3576a71636d6f4c6
parent572e85e3aa58f11671759e9cfa6b9b5d79b131fd (diff)
ARM: at91: Remove rstc and shdwnc global base addresses
Now that there's no user left for the global variables holding the reset and shutdown controllers base address, we can remove these variables and their associated mapping function. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c2
-rw-r--r--arch/arm/mach-at91/generic.h6
-rw-r--r--arch/arm/mach-at91/setup.c18
7 files changed, 0 insertions, 34 deletions
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 601f2c708767..dbb069f4a0a6 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -343,8 +343,6 @@ static void __init at91sam9260_map_io(void)
343 343
344static void __init at91sam9260_ioremap_registers(void) 344static void __init at91sam9260_ioremap_registers(void)
345{ 345{
346 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
347 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
348 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512); 346 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
349 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 347 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
350 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 348 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 5e8ac0d271b8..80cae8728316 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -302,8 +302,6 @@ static void __init at91sam9261_map_io(void)
302 302
303static void __init at91sam9261_ioremap_registers(void) 303static void __init at91sam9261_ioremap_registers(void)
304{ 304{
305 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
306 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
307 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512); 305 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
308 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 306 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
309 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 307 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index bcc8b04d3cfb..37bb02ce8b62 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -322,8 +322,6 @@ static void __init at91sam9263_map_io(void)
322 322
323static void __init at91sam9263_ioremap_registers(void) 323static void __init at91sam9263_ioremap_registers(void)
324{ 324{
325 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
326 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
327 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512); 325 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
328 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512); 326 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
329 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 327 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 665d378877a3..7a329703f31a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -372,8 +372,6 @@ static void __init at91sam9g45_map_io(void)
372 372
373static void __init at91sam9g45_ioremap_registers(void) 373static void __init at91sam9g45_ioremap_registers(void)
374{ 374{
375 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
376 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
377 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512); 375 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
378 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512); 376 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
379 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 377 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 5a18a76ac9e3..1644aa250eba 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -312,8 +312,6 @@ static void __init at91sam9rl_map_io(void)
312 312
313static void __init at91sam9rl_ioremap_registers(void) 313static void __init at91sam9rl_ioremap_registers(void)
314{ 314{
315 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
316 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
317 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512); 315 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
318 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 316 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
319 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 317 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 5d5e55237c41..f42b0490ad98 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -64,12 +64,6 @@ extern void at91_irq_resume(void);
64/* idle */ 64/* idle */
65extern void at91sam9_idle(void); 65extern void at91sam9_idle(void);
66 66
67/* reset */
68extern void at91_ioremap_rstc(u32 base_addr);
69
70/* shutdown */
71extern void at91_ioremap_shdwc(u32 base_addr);
72
73/* Matrix */ 67/* Matrix */
74extern void at91_ioremap_matrix(u32 base_addr); 68extern void at91_ioremap_matrix(u32 base_addr);
75 69
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index a46df6759c92..bf9b03df11f6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -320,24 +320,6 @@ void __init at91_map_io(void)
320 at91_boot_soc.map_io(); 320 at91_boot_soc.map_io();
321} 321}
322 322
323void __iomem *at91_shdwc_base = NULL;
324
325void __init at91_ioremap_shdwc(u32 base_addr)
326{
327 at91_shdwc_base = ioremap(base_addr, 16);
328 if (!at91_shdwc_base)
329 panic(pr_fmt("Impossible to ioremap at91_shdwc_base\n"));
330}
331
332void __iomem *at91_rstc_base;
333
334void __init at91_ioremap_rstc(u32 base_addr)
335{
336 at91_rstc_base = ioremap(base_addr, 16);
337 if (!at91_rstc_base)
338 panic(pr_fmt("Impossible to ioremap at91_rstc_base\n"));
339}
340
341void __iomem *at91_matrix_base; 323void __iomem *at91_matrix_base;
342EXPORT_SYMBOL_GPL(at91_matrix_base); 324EXPORT_SYMBOL_GPL(at91_matrix_base);
343 325