drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag

Some asic revisions need to disable PG when UVD is active.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index b13448f13ee8..dc599060a9a4 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
         radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
 
         if (pi->enable_gfx_power_gating) {
-                sumo_gfx_powergating_enable(rdev, true);
+                if (!pi->disable_gfx_power_gating_in_uvd ||
+                    !r600_is_uvd_state(new_rps->class, new_rps->class2))
+                        sumo_gfx_powergating_enable(rdev, true);
         }
 }