diff options
| author | Christoph Fritz <chf.fritz@googlemail.com> | 2014-07-13 21:36:18 -0400 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-07-23 04:48:24 -0400 |
| commit | 33753cd2ba41c72a0756edc5dc094d91602deda5 (patch) | |
| tree | d5032941d081863132623b1383fc9c16495b91f9 | |
| parent | 23d9cec07c589276561c13b180577c0b87930140 (diff) | |
ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable()
This patch adds bch8 ecc software fallback which is mostly used by
omap3s because they lack hardware elm support.
Fixes: 0611c41934ab35ce84dea34ab291897ad3cbc7be (ARM: OMAP2+: gpmc:
update gpmc_hwecc_bch_capable() for new platforms and ECC schemes)
Cc: <stable@vger.kernel.org> # 3.15.x+
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap2/gpmc-nand.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 17cd39360afe..93914d220069 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -50,6 +50,16 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) | |||
| 50 | soc_is_omap54xx() || soc_is_dra7xx()) | 50 | soc_is_omap54xx() || soc_is_dra7xx()) |
| 51 | return 1; | 51 | return 1; |
| 52 | 52 | ||
| 53 | if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW || | ||
| 54 | ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) { | ||
| 55 | if (cpu_is_omap24xx()) | ||
| 56 | return 0; | ||
| 57 | else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0)) | ||
| 58 | return 0; | ||
| 59 | else | ||
| 60 | return 1; | ||
| 61 | } | ||
| 62 | |||
| 53 | /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes | 63 | /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes |
| 54 | * which require H/W based ECC error detection */ | 64 | * which require H/W based ECC error detection */ |
| 55 | if ((cpu_is_omap34xx() || cpu_is_omap3630()) && | 65 | if ((cpu_is_omap34xx() || cpu_is_omap3630()) && |
| @@ -57,14 +67,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) | |||
| 57 | (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) | 67 | (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) |
| 58 | return 0; | 68 | return 0; |
| 59 | 69 | ||
| 60 | /* | ||
| 61 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 | ||
| 62 | * and AM33xx derivates. Other chips may be added if confirmed to work. | ||
| 63 | */ | ||
| 64 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) && | ||
| 65 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) | ||
| 66 | return 0; | ||
| 67 | |||
| 68 | /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ | 70 | /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ |
| 69 | if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) | 71 | if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) |
| 70 | return 1; | 72 | return 1; |
