diff options
author | Andrew Bresticker <abrestic@chromium.org> | 2014-05-22 11:55:35 -0400 |
---|---|---|
committer | Chris Ball <chris@printf.net> | 2014-05-23 08:48:55 -0400 |
commit | 3145351a6f4026fa9e9f8c7a0ba85a877377e0e3 (patch) | |
tree | eec15cbe8690f8373199b2453239e3b7a40e5ba7 | |
parent | c5ee249069367fa0529de007f7119a157ce4a4ad (diff) |
mmc: tegra: disable UHS modes
Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised
in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support
these modes, they require Tegra-specific tuning and calibration routines
which the driver does not support yet.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
-rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 985247649f46..4375cd4704c6 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c | |||
@@ -32,11 +32,17 @@ | |||
32 | 32 | ||
33 | /* Tegra SDHOST controller vendor register definitions */ | 33 | /* Tegra SDHOST controller vendor register definitions */ |
34 | #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 | 34 | #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 |
35 | #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 | ||
36 | #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 | ||
35 | #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 | 37 | #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 |
38 | #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 | ||
36 | 39 | ||
37 | #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) | 40 | #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) |
38 | #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) | 41 | #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) |
39 | #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) | 42 | #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) |
43 | #define NVQUIRK_DISABLE_SDR50 BIT(3) | ||
44 | #define NVQUIRK_DISABLE_SDR104 BIT(4) | ||
45 | #define NVQUIRK_DISABLE_DDR50 BIT(5) | ||
40 | 46 | ||
41 | struct sdhci_tegra_soc_data { | 47 | struct sdhci_tegra_soc_data { |
42 | const struct sdhci_pltfm_data *pdata; | 48 | const struct sdhci_pltfm_data *pdata; |
@@ -100,20 +106,25 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) | |||
100 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 106 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
101 | struct sdhci_tegra *tegra_host = pltfm_host->priv; | 107 | struct sdhci_tegra *tegra_host = pltfm_host->priv; |
102 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; | 108 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
109 | u32 misc_ctrl; | ||
103 | 110 | ||
104 | sdhci_reset(host, mask); | 111 | sdhci_reset(host, mask); |
105 | 112 | ||
106 | if (!(mask & SDHCI_RESET_ALL)) | 113 | if (!(mask & SDHCI_RESET_ALL)) |
107 | return; | 114 | return; |
108 | 115 | ||
116 | misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
109 | /* Erratum: Enable SDHCI spec v3.00 support */ | 117 | /* Erratum: Enable SDHCI spec v3.00 support */ |
110 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { | 118 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) |
111 | u32 misc_ctrl; | ||
112 | |||
113 | misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
114 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; | 119 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; |
115 | sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); | 120 | /* Don't advertise UHS modes which aren't supported yet */ |
116 | } | 121 | if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) |
122 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; | ||
123 | if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) | ||
124 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; | ||
125 | if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) | ||
126 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; | ||
127 | sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); | ||
117 | } | 128 | } |
118 | 129 | ||
119 | static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) | 130 | static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) |
@@ -170,7 +181,9 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { | |||
170 | 181 | ||
171 | static struct sdhci_tegra_soc_data soc_data_tegra30 = { | 182 | static struct sdhci_tegra_soc_data soc_data_tegra30 = { |
172 | .pdata = &sdhci_tegra30_pdata, | 183 | .pdata = &sdhci_tegra30_pdata, |
173 | .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, | 184 | .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | |
185 | NVQUIRK_DISABLE_SDR50 | | ||
186 | NVQUIRK_DISABLE_SDR104, | ||
174 | }; | 187 | }; |
175 | 188 | ||
176 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | 189 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
@@ -184,6 +197,9 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | |||
184 | 197 | ||
185 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { | 198 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { |
186 | .pdata = &sdhci_tegra114_pdata, | 199 | .pdata = &sdhci_tegra114_pdata, |
200 | .nvquirks = NVQUIRK_DISABLE_SDR50 | | ||
201 | NVQUIRK_DISABLE_DDR50 | | ||
202 | NVQUIRK_DISABLE_SDR104, | ||
187 | }; | 203 | }; |
188 | 204 | ||
189 | static const struct of_device_id sdhci_tegra_dt_match[] = { | 205 | static const struct of_device_id sdhci_tegra_dt_match[] = { |