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authorMatt Carlson <mcarlson@broadcom.com>2010-12-06 03:28:50 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-06 14:03:46 -0500
commit3110f5f5545a645c50ef66b1f705d08dfd1df404 (patch)
tree0de70162efdc0094ec52af362730712271967730
parent8fc2f9956127d2b85280c07e69aeb08b9bd85150 (diff)
tg3: Move EEE definitions into mdio.h
In commit 52b02d04c801fff51ca49ad033210846d1713253 entitled "tg3: Add EEE support", Ben Hutchings had commented that the EEE advertisement register will be in a standard location. This patch moves that definition into mdio.h and changes the code to use it. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c16
-rw-r--r--drivers/net/tg3.h3
-rw-r--r--include/linux/mdio.h5
3 files changed, 13 insertions, 11 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b8ae5e19ced5..1e7a135de7b3 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -32,6 +32,7 @@
32#include <linux/etherdevice.h> 32#include <linux/etherdevice.h>
33#include <linux/skbuff.h> 33#include <linux/skbuff.h>
34#include <linux/ethtool.h> 34#include <linux/ethtool.h>
35#include <linux/mdio.h>
35#include <linux/mii.h> 36#include <linux/mii.h>
36#include <linux/phy.h> 37#include <linux/phy.h>
37#include <linux/brcmphy.h> 38#include <linux/brcmphy.h>
@@ -1781,7 +1782,8 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1781 1782
1782 tw32(TG3_CPMU_EEE_CTRL, eeectl); 1783 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783 1784
1784 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val); 1785 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1786 TG3_CL45_D7_EEERES_STAT, &val);
1785 1787
1786 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || 1788 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) 1789 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
@@ -2987,16 +2989,14 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
2987 if (tp->link_config.autoneg == AUTONEG_ENABLE) { 2989 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2988 /* Advertise 100-BaseTX EEE ability */ 2990 /* Advertise 100-BaseTX EEE ability */
2989 if (tp->link_config.advertising & 2991 if (tp->link_config.advertising &
2990 (ADVERTISED_100baseT_Half | 2992 ADVERTISED_100baseT_Full)
2991 ADVERTISED_100baseT_Full)) 2993 val |= MDIO_AN_EEE_ADV_100TX;
2992 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2993 /* Advertise 1000-BaseT EEE ability */ 2994 /* Advertise 1000-BaseT EEE ability */
2994 if (tp->link_config.advertising & 2995 if (tp->link_config.advertising &
2995 (ADVERTISED_1000baseT_Half | 2996 ADVERTISED_1000baseT_Full)
2996 ADVERTISED_1000baseT_Full)) 2997 val |= MDIO_AN_EEE_ADV_1000T;
2997 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
2998 } 2998 }
2999 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val); 2999 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3000 3000
3001 /* Turn off SM_DSP clock. */ 3001 /* Turn off SM_DSP clock. */
3002 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | 3002 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 59b0e096149e..6e72c6bd2675 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2172,9 +2172,6 @@
2172#define MII_TG3_TEST1_CRC_EN 0x8000 2172#define MII_TG3_TEST1_CRC_EN 0x8000
2173 2173
2174/* Clause 45 expansion registers */ 2174/* Clause 45 expansion registers */
2175#define TG3_CL45_D7_EEEADV_CAP 0x003c
2176#define TG3_CL45_D7_EEEADV_CAP_100TX 0x0002
2177#define TG3_CL45_D7_EEEADV_CAP_1000T 0x0004
2178#define TG3_CL45_D7_EEERES_STAT 0x803e 2175#define TG3_CL45_D7_EEERES_STAT 0x803e
2179#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2176#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2180#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2177#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index c779b49a1fda..b1494aced217 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -55,6 +55,7 @@
55#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ 55#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
56#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ 56#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
57#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ 57#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
58#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
58 59
59/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ 60/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
60#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ 61#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -235,6 +236,10 @@
235#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ 236#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
236#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ 237#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
237 238
239/* AN EEE Advertisement register. */
240#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
241#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
242
238/* LASI RX_ALARM control/status registers. */ 243/* LASI RX_ALARM control/status registers. */
239#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ 244#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
240#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ 245#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */