i2c: riic: add driver

Tested with a r7s72100 genmai board acessing an eeprom.

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

4 files changed, 467 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/i2c/i2c-riic.txt b/Documentation/devicetree/bindings/i2c/i2c-riic.txt
new file mode 100644
index 000000000000..0bcc4716c319
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-riic.txt
@@ -0,0 +1,29 @@
+Device tree configuration for Renesas RIIC driver
+
+Required properties:
+- compatible      : "renesas,riic-<soctype>". "renesas,riic-rz" as fallback
+- reg             : address start and address range size of device
+- interrupts      : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
+- clock-frequency : frequency of bus clock in Hz
+- #address-cells  : should be <1>
+- #size-cells     : should be <0>
+
+Pinctrl properties might be needed, too. See there.
+
+Example:
+
+        i2c0: i2c@fcfee000 {
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee000 0x44>;
+                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 158 IRQ_TYPE_EDGE_RISING>,
+                             <0 159 IRQ_TYPE_EDGE_RISING>,
+                             <0 160 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 161 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 162 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 163 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <100000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 3b26129f6055..8e8332d5ac73 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -648,6 +648,16 @@ config I2C_PXA_SLAVE
           is necessary for systems where the PXA may be a target on the
           I2C bus.
 
+config I2C_RIIC
+        tristate "Renesas RIIC adapter"
+        depends on ARCH_SHMOBILE || COMPILE_TEST
+        help
+          If you say yes to this option, support will be included for the
+          Renesas RIIC I2C interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-riic.
+
 config HAVE_S3C2410_I2C
         bool
         help
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index c73eb0ea788e..dca041b1b99d 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_I2C_PNX)		+= i2c-pnx.o
 obj-$(CONFIG_I2C_PUV3)          += i2c-puv3.o
 obj-$(CONFIG_I2C_PXA)           += i2c-pxa.o
 obj-$(CONFIG_I2C_PXA_PCI)       += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_RIIC)          += i2c-riic.o
 obj-$(CONFIG_I2C_S3C2410)       += i2c-s3c2410.o
 obj-$(CONFIG_I2C_S6000)         += i2c-s6000.o
 obj-$(CONFIG_I2C_SH7760)        += i2c-sh7760.o
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
new file mode 100644
index 000000000000..9e1f8bacfb39
--- /dev/null
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -0,0 +1,427 @@
+/*
+ * Renesas RIIC driver
+ *
+ * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+/*
+ * This i2c core has a lot of interrupts, namely 8. We use their chaining as
+ * some kind of state machine.
+ *
+ * 1) The main xfer routine kicks off a transmission by putting the start bit
+ * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
+ * since we need to send the slave address + RW bit in every case.
+ *
+ * 2) TIE sends slave address + RW bit and selects how to continue.
+ *
+ * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
+ * are done, we switch over to the transmission done interrupt (TEIE) and mark
+ * the message as completed (includes sending STOP) there.
+ *
+ * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
+ * needed to start clocking, then we keep receiving until we are done. Note
+ * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
+ * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
+ * message to create the final NACK as sketched in the datasheet. This caused
+ * some subtle races (when byte n was processed and byte n+1 was already
+ * waiting), though, and I started with the safe approach.
+ *
+ * 4) If we got a NACK somewhere, we flag the error and stop the transmission
+ * via NAKIE.
+ *
+ * Also check the comments in the interrupt routines for some gory details.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define RIIC_ICCR1      0x00
+#define RIIC_ICCR2      0x04
+#define RIIC_ICMR1      0x08
+#define RIIC_ICMR3      0x10
+#define RIIC_ICSER      0x18
+#define RIIC_ICIER      0x1c
+#define RIIC_ICSR2      0x24
+#define RIIC_ICBRL      0x34
+#define RIIC_ICBRH      0x38
+#define RIIC_ICDRT      0x3c
+#define RIIC_ICDRR      0x40
+
+#define ICCR1_ICE       0x80
+#define ICCR1_IICRST    0x40
+#define ICCR1_SOWP      0x10
+
+#define ICCR2_BBSY      0x80
+#define ICCR2_SP        0x08
+#define ICCR2_RS        0x04
+#define ICCR2_ST        0x02
+
+#define ICMR1_CKS_MASK  0x70
+#define ICMR1_BCWP      0x08
+#define ICMR1_CKS(_x)   ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
+
+#define ICMR3_RDRFS     0x20
+#define ICMR3_ACKWP     0x10
+#define ICMR3_ACKBT     0x08
+
+#define ICIER_TIE       0x80
+#define ICIER_TEIE      0x40
+#define ICIER_RIE       0x20
+#define ICIER_NAKIE     0x10
+
+#define ICSR2_NACKF     0x10
+
+/* ICBRx (@ PCLK 33MHz) */
+#define ICBR_RESERVED   0xe0 /* Should be 1 on writes */
+#define ICBRL_SP100K    (19 | ICBR_RESERVED)
+#define ICBRH_SP100K    (16 | ICBR_RESERVED)
+#define ICBRL_SP400K    (21 | ICBR_RESERVED)
+#define ICBRH_SP400K    (9 | ICBR_RESERVED)
+
+#define RIIC_INIT_MSG   -1
+
+struct riic_dev {
+        void __iomem *base;
+        u8 *buf;
+        struct i2c_msg *msg;
+        int bytes_left;
+        int err;
+        int is_last;
+        struct completion msg_done;
+        struct i2c_adapter adapter;
+        struct clk *clk;
+};
+
+struct riic_irq_desc {
+        int res_num;
+        irq_handler_t isr;
+        char *name;
+};
+
+static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
+{
+        writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
+}
+
+static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+        struct riic_dev *riic = i2c_get_adapdata(adap);
+        unsigned long time_left;
+        int i, ret;
+        u8 start_bit;