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authorDave Airlie <airlied@redhat.com>2013-07-05 01:55:12 -0400
committerDave Airlie <airlied@redhat.com>2013-07-05 01:55:12 -0400
commit30f83b371645e310c12087ece4eb255781036260 (patch)
treee3798d2bbb7c9c8de9308225746406d3401f6309
parent6d35dea107834eb549c1fba28fea6ec39c81d0ba (diff)
parentbf03d1b293cc556df53545e318110505014d805e (diff)
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- GF117 acceleration support - GK110 acceleration-with-blob-ucode support, and initial work towards fixing our own ucode to be suitable. - Large cleanups of fermi/kepler context handling * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (22 commits) drm/nva3/disp: Fix HDMI audio regression drm/nv50-/disp: Use output specific mask in interrupt drm/nouveau: use vmalloc for pgt allocation drm/nvc0-/gr: remove some more of the hardcoded register writes drm/nvc0-/gr: factor out yet more unknown magic into versioned functions drm/nvd7/devinit: use fermi class, not tesla drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16 drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode drm/nvf0/gr: build cs ucode for GK110 drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs drm/nvf0/gr: fix ddx shaders locking up on me drm/nvc0/devinit: minor typo drm/nvf0/gr: enable support, if external cs ucode is available drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding drm/nvf0/ce: enable support drm/nvf0/fifo: enable support drm/nvd7/gr: initial support drm/nvc0-/gr: generate cs register lists from grctx data drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs drm/nve0-/gr: some new gpc registers can have multiple copies ...
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile16
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c20
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c12
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c4514
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c823
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c99
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c370
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c290
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c515
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c2924
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c1018
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c328
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc118
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc118
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h620
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc42
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h475
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc141
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h672
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc42
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h475
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc69
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc81
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h1137
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc40
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h921
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc127
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h1223
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc40
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h918
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc50
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c1619
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h223
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c144
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c110
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c141
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c167
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c165
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nve0.c1105
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nve4.c354
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c248
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/graph.h10
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/vm/base.c6
48 files changed, 11568 insertions, 10986 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index b59cfd79bd79..d939a1da3203 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -200,7 +200,13 @@ nouveau-y += core/engine/fifo/nve0.o
200nouveau-y += core/engine/graph/ctxnv40.o 200nouveau-y += core/engine/graph/ctxnv40.o
201nouveau-y += core/engine/graph/ctxnv50.o 201nouveau-y += core/engine/graph/ctxnv50.o
202nouveau-y += core/engine/graph/ctxnvc0.o 202nouveau-y += core/engine/graph/ctxnvc0.o
203nouveau-y += core/engine/graph/ctxnve0.o 203nouveau-y += core/engine/graph/ctxnvc1.o
204nouveau-y += core/engine/graph/ctxnvc3.o
205nouveau-y += core/engine/graph/ctxnvc8.o
206nouveau-y += core/engine/graph/ctxnvd7.o
207nouveau-y += core/engine/graph/ctxnvd9.o
208nouveau-y += core/engine/graph/ctxnve4.o
209nouveau-y += core/engine/graph/ctxnvf0.o
204nouveau-y += core/engine/graph/nv04.o 210nouveau-y += core/engine/graph/nv04.o
205nouveau-y += core/engine/graph/nv10.o 211nouveau-y += core/engine/graph/nv10.o
206nouveau-y += core/engine/graph/nv20.o 212nouveau-y += core/engine/graph/nv20.o
@@ -212,7 +218,13 @@ nouveau-y += core/engine/graph/nv35.o
212nouveau-y += core/engine/graph/nv40.o 218nouveau-y += core/engine/graph/nv40.o
213nouveau-y += core/engine/graph/nv50.o 219nouveau-y += core/engine/graph/nv50.o
214nouveau-y += core/engine/graph/nvc0.o 220nouveau-y += core/engine/graph/nvc0.o
215nouveau-y += core/engine/graph/nve0.o 221nouveau-y += core/engine/graph/nvc1.o
222nouveau-y += core/engine/graph/nvc3.o
223nouveau-y += core/engine/graph/nvc8.o
224nouveau-y += core/engine/graph/nvd7.o
225nouveau-y += core/engine/graph/nvd9.o
226nouveau-y += core/engine/graph/nve4.o
227nouveau-y += core/engine/graph/nvf0.o
216nouveau-y += core/engine/mpeg/nv31.o 228nouveau-y += core/engine/mpeg/nv31.o
217nouveau-y += core/engine/mpeg/nv40.o 229nouveau-y += core/engine/mpeg/nv40.o
218nouveau-y += core/engine/mpeg/nv50.o 230nouveau-y += core/engine/mpeg/nv50.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index 1df3578a5315..418f51f50d7a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 76 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 77 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
78 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 78 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
79 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 79 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
80 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 80 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
81 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 81 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device)
104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
105 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 105 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
106 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 106 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
107 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 107 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
108 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 108 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
109 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 109 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
110 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 110 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -133,7 +133,7 @@ nvc0_identify(struct nouveau_device *device)
133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
134 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 134 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
135 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 135 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
136 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 136 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
137 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 137 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
138 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 138 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
139 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 139 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -161,7 +161,7 @@ nvc0_identify(struct nouveau_device *device)
161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
162 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 162 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
163 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 163 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
164 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 164 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
165 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 165 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
166 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 166 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
167 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 167 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -190,7 +190,7 @@ nvc0_identify(struct nouveau_device *device)
190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
191 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 191 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
192 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 192 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
193 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 193 device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
194 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 194 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
195 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 195 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
196 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 196 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device)
219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
220 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 220 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
221 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 221 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
222 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 222 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
223 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 223 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
224 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 224 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
225 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 225 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device)
247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
248 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 248 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
249 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 249 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
250 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 250 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
251 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 251 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
252 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 252 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
253 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 253 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device)
276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
277 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 277 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
278 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 278 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
279 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 279 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
280 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 280 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
281 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 281 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
282 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 282 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -291,7 +291,7 @@ nvc0_identify(struct nouveau_device *device)
291 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 291 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
292 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 292 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
293 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 293 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
294 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 294 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
295 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; 295 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
296 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 296 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
297 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 297 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
305 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; 305 device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
306 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 306 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
307 device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; 307 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
308 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 308 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
309 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 309 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
310 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 310 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 4e6ef62e88c8..7aca1877add4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 76 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 77 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
78 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 78 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
79 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 79 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
80 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; 80 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
81 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; 81 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
@@ -105,7 +105,7 @@ nve0_identify(struct nouveau_device *device)
105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
106 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 106 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
107 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 107 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
108 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 108 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
109 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 109 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
110 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; 110 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
111 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; 111 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
@@ -135,7 +135,7 @@ nve0_identify(struct nouveau_device *device)
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
140 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; 140 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
141 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; 141 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
@@ -163,16 +163,14 @@ nve0_identify(struct nouveau_device *device)
163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
166#if 0
167 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 166 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
168 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 167 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
169 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; 168 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
170#endif
171 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; 169 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
172#if 0
173 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; 170 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
174 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; 171 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
175 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; 172 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
173#if 0
176 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; 174 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
177 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; 175 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
178 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 176 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
index f065fc248adf..db8c6fd46278 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
@@ -55,6 +55,10 @@ nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
55 nv_wr32(priv, 0x61c510 + soff, 0x00000000); 55 nv_wr32(priv, 0x61c510 + soff, 0x00000000);
56 nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); 56 nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);
57 57
58 nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
59 nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
60 nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
61
58 /* ??? */ 62 /* ??? */
59 nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ 63 nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
60 nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ 64 nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 8b42f45c2b1d..7ffe2f309f12 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1107 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; 1107 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1108 u32 hval, hreg = 0x614200 + (head * 0x800); 1108 u32 hval, hreg = 0x614200 + (head * 0x800);
1109 u32 oval, oreg; 1109 u32 oval, oreg;
1110 u32 mask;
1110 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp); 1111 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
1111 if (conf != ~0) { 1112 if (conf != ~0) {
1112 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { 1113 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
@@ -1133,6 +1134,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1133 oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800; 1134 oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1134 oval = 0x00000000; 1135 oval = 0x00000000;
1135 hval = 0x00000000; 1136 hval = 0x00000000;
1137 mask = 0xffffffff;
1136 } else 1138 } else
1137 if (!outp.location) { 1139 if (!outp.location) {
1138 if (outp.type == DCB_OUTPUT_DP) 1140 if (outp.type == DCB_OUTPUT_DP)
@@ -1140,14 +1142,16 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1140 oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800; 1142 oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1141 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; 1143 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
1142 hval = 0x00000000; 1144 hval = 0x00000000;
1145 mask = 0x00000707;
1143 } else { 1146 } else {
1144 oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800; 1147 oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
1145 oval = 0x00000001; 1148 oval = 0x00000001;
1146 hval = 0x00000001; 1149 hval = 0x00000001;
1150 mask = 0x00000707;
1147 } 1151 }
1148 1152
1149 nv_mask(priv, hreg, 0x0000000f, hval); 1153 nv_mask(priv, hreg, 0x0000000f, hval);
1150 nv_mask(priv, oreg, 0x00000707, oval); 1154 nv_mask(priv, oreg, mask, oval);
1151 } 1155 }
1152} 1156}
1153 1157
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 0338e66bc620..09644fa9602c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -221,8 +221,10 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
221 } 221 }
222 } 222 }
223 223
224 if (i == FIFO_ENGINE_NR) 224 if (i == FIFO_ENGINE_NR) {
225 nv_error(priv, "unsupported engines 0x%08x\n", args->engine);
225 return -ENODEV; 226 return -ENODEV;
227 }
226 228
227 ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, 229 ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
228 priv->user.bar.offset, 0x200, 230 priv->user.bar.offset, 0x200,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 3be7b950eece..64dca260912f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -24,3456 +24,1220 @@
24 24
25#include "nvc0.h" 25#include "nvc0.h"
26 26
27void 27struct nvc0_graph_init
28nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data) 28nvc0_grctx_init_icmd[] = {
29{ 29 { 0x001000, 1, 0x01, 0x00000004 },
30 nv_wr32(priv, 0x400204, data); 30 { 0x0000a9, 1, 0x01, 0x0000ffff },
31 nv_wr32(priv, 0x400200, icmd); 31 { 0x000038, 1, 0x01, 0x0fac6881 },
32 while (nv_rd32(priv, 0x400700) & 2) {} 32 { 0x00003d, 1, 0x01, 0x00000001 },
33} 33 { 0x0000e8, 8, 0x01, 0x00000400 },
34 { 0x000078, 8, 0x01, 0x00000300 },
35 { 0x000050, 1, 0x01, 0x00000011 },
36 { 0x000058, 8, 0x01, 0x00000008 },
37 { 0x000208, 8, 0x01, 0x00000001 },
38 { 0x000081, 1, 0x01, 0x00000001 },
39 { 0x000085, 1, 0x01, 0x00000004 },
40 { 0x000088, 1, 0x01, 0x00000400 },
41 { 0x000090, 1, 0x01, 0x00000300 },
42 { 0x000098, 1, 0x01, 0x00001001 },
43 { 0x0000e3, 1, 0x01, 0x00000001 },
44 { 0x0000da, 1, 0x01, 0x00000001 },
45 { 0x0000f8, 1, 0x01, 0x00000003 },
46 { 0x0000fa, 1, 0x01, 0x00000001 },
47 { 0x00009f, 4, 0x01, 0x0000ffff },
48 { 0x0000b1, 1, 0x01, 0x00000001 },
49 { 0x0000b2, 40, 0x01, 0x00000000 },
50 { 0x000210, 8, 0x01, 0x00000040 },
51 { 0x000218, 8, 0x01, 0x0000c080 },
52 { 0x0000ad, 1, 0x01, 0x0000013e },
53 { 0x0000e1, 1, 0x01, 0x00000010 },
54 { 0x000290, 16, 0x01, 0x00000000 },
55 { 0x0003b0, 16, 0x01, 0x00000000 },
56 { 0x0002a0, 16, 0x01, 0x00000000 },
57 { 0x000420, 16, 0x01, 0x00000000 },
58 { 0x0002b0, 16, 0x01, 0x00000000 },
59 { 0x000430, 16, 0x01, 0x00000000 },
60 { 0x0002c0, 16, 0x01, 0x00000000 },
61 { 0x0004d0, 16, 0x01, 0x00000000 },
62 { 0x000720, 16, 0x01, 0x00000000 },
63 { 0x0008c0, 16, 0x01, 0x00000000 },
64 { 0x000890, 16, 0x01, 0x00000000 },
65 { 0x0008e0, 16, 0x01, 0x00000000 },
66 { 0x0008a0, 16, 0x01, 0x00000000 },
67 { 0x0008f0, 16, 0x01, 0x00000000 },
68 { 0x00094c, 1, 0x01, 0x000000ff },
69 { 0x00094d, 1, 0x01, 0xffffffff },
70 { 0x00094e, 1, 0x01, 0x00000002 },
71 { 0x0002ec, 1, 0x01, 0x00000001 },
72 { 0x000303, 1, 0x01, 0x00000001 },
73 { 0x0002e6, 1, 0x01, 0x00000001 },
74 { 0x000466, 1, 0x01, 0x00000052 },
75 { 0x000301, 1, 0x01, 0x3f800000 },
76 { 0x000304, 1, 0x01, 0x30201000 },
77 { 0x000305, 1, 0x01, 0x70605040 },
78 { 0x000306, 1, 0x01, 0xb8a89888 },
79 { 0x000307, 1, 0x01, 0xf8e8d8c8 },
80 { 0x00030a, 1, 0x01, 0x00ffff00 },
81 { 0x00030b, 1, 0x01, 0x0000001a },
82 { 0x00030c, 1, 0x01, 0x00000001 },
83 { 0x000318, 1, 0x01, 0x00000001 },
84 { 0x000340, 1, 0x01, 0x00000000 },
85 { 0x000375, 1, 0x01, 0x00000001 },
86 { 0x000351, 1, 0x01, 0x00000100 },
87 { 0x00037d, 1, 0x01, 0x00000006 },
88 { 0x0003a0, 1, 0x01, 0x00000002 },
89 { 0x0003aa, 1, 0x01, 0x00000001 },
90 { 0x0003a9, 1, 0x01, 0x00000001 },
91 { 0x000380, 1, 0x01, 0x00000001 },
92 { 0x000360, 1, 0x01, 0x00000040 },
93 { 0x000366, 2, 0x01, 0x00000000 },
94 { 0x000368, 1, 0x01, 0x00001fff },
95 { 0x000370, 2, 0x01, 0x00000000 },
96 { 0x000372, 1, 0x01, 0x003fffff },
97 { 0x00037a, 1, 0x01, 0x00000012 },
98 { 0x0005e0, 5, 0x01, 0x00000022 },
99 { 0x000619, 1, 0x01, 0x00000003 },
100 { 0x000811, 1, 0x01, 0x00000003 },
101 { 0x000812, 1, 0x01, 0x00000004 },
102 { 0x000813, 1, 0x01, 0x00000006 },
103 { 0x000814, 1, 0x01, 0x00000008 },
104 { 0x000815, 1, 0x01, 0x0000000b },
105 { 0x000800, 6, 0x01, 0x00000001 },
106 { 0x000632, 1, 0x01, 0x00000001 },
107 { 0x000633, 1, 0x01, 0x00000002 },
108 { 0x000634, 1, 0x01, 0x00000003 },
109 { 0x000635, 1, 0x01, 0x00000004 },
110 { 0x000654, 1, 0x01, 0x3f800000 },
111 { 0x000657, 1, 0x01, 0x3f800000 },
112 { 0x000655, 2, 0x01, 0x3f800000 },
113 { 0x0006cd, 1, 0x01, 0x3f800000 },
114 { 0x0007f5, 1, 0x01, 0x3f800000 },
115 { 0x0007dc, 1, 0x01, 0x39291909 },
116 { 0x0007dd, 1, 0x01, 0x79695949 },
117 { 0x0007de, 1, 0x01, 0xb9a99989 },
118 { 0x0007df, 1, 0x01, 0xf9e9d9c9 },
119 { 0x0007e8, 1, 0x01, 0x00003210 },
120 { 0x0007e9, 1, 0x01, 0x00007654 },
121 { 0x0007ea, 1, 0x01, 0x00000098 },
122 { 0x0007ec, 1, 0x01, 0x39291909 },
123 { 0x0007ed, 1, 0x01, 0x79695949 },
124 { 0x0007ee, 1, 0x01, 0xb9a99989 },
125 { 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
126 { 0x0007f0, 1, 0x01, 0x00003210 },
127 { 0x0007f1, 1, 0x01, 0x00007654 },
128 { 0x0007f2, 1, 0x01, 0x00000098 },
129 { 0x0005a5, 1, 0x01, 0x00000001 },
130 { 0x000980, 128, 0x01, 0x00000000 },
131 { 0x000468, 1, 0x01, 0x00000004 },
132 { 0x00046c, 1, 0x01, 0x00000001 },
133 { 0x000470, 96, 0x01, 0x00000000 },
134 { 0x000510, 16, 0x01, 0x3f800000 },
135 { 0x000520, 1, 0x01, 0x000002b6 },
136 { 0x000529, 1, 0x01, 0x00000001 },
137 { 0x000530, 16, 0x01, 0xffff0000 },
138 { 0x000585, 1, 0x01, 0x0000003f },
139 { 0x000576, 1, 0x01, 0x00000003 },
140 { 0x000586, 1, 0x01, 0x00000040 },
141 { 0x000582, 2, 0x01, 0x00000080 },
142 { 0x0005c2, 1, 0x01, 0x00000001 },
143 { 0x000638, 1, 0x01, 0x00000001 },
144 { 0x000639, 1, 0x01, 0x00000001 },
145 { 0x00063a, 1, 0x01, 0x00000002 },
146 { 0x00063b, 2, 0x01, 0x00000001 },
147 { 0x00063d, 1, 0x01, 0x00000002 },
148 { 0x00063e, 1, 0x01, 0x00000001 },
149 { 0x0008b8, 8, 0x01, 0x00000001 },
150 { 0x000900, 8, 0x01, 0x00000001 },
151 { 0x000908, 8, 0x01, 0x00000002 },
152 { 0x000910, 16, 0x01, 0x00000001 },
153 { 0x000920, 8, 0x01, 0x00000002 },
154 { 0x000928, 8, 0x01, 0x00000001 },
155 { 0x000648, 9, 0x01, 0x00000001 },
156 { 0x000658, 1, 0x01, 0x0000000f },
157 { 0x0007ff, 1, 0x01, 0x0000000a },
158 { 0x00066a, 1, 0x01, 0x40000000 },
159 { 0x00066b, 1, 0x01, 0x10000000 },
160 { 0x00066c, 2, 0x01, 0xffff0000 },
161 { 0x0007af, 2, 0x01, 0x00000008 },
162 { 0x0007f6, 1, 0x01, 0x00000001 },
163 { 0x0006b2, 1, 0x01, 0x00000055 },
164 { 0x0007ad, 1, 0x01, 0x00000003 },
165 { 0x000937, 1, 0x01, 0x00000001 },
166 { 0x000971, 1, 0x01, 0x00000008 },
167 { 0x000972, 1, 0x01, 0x00000040 },
168 { 0x000973, 1, 0x01, 0x0000012c },
169 { 0x00097c, 1, 0x01, 0x00000040 },
170 { 0x000979, 1, 0x01, 0x00000003 },
171 { 0x000975, 1, 0x01, 0x00000020 },
172 { 0x000976, 1, 0x01, 0x00000001 },
173 { 0x000977, 1, 0x01, 0x00000020 },
174 { 0x000978, 1, 0x01, 0x00000001 },
175 { 0x000957, 1, 0x01, 0x00000003 },
176 { 0x00095e, 1, 0x01, 0x20164010 },
177 { 0x00095f, 1, 0x01, 0x00000020 },
178 { 0x000683, 1, 0x01, 0x00000006 },
179 { 0x000685, 1, 0x01, 0x003fffff },
180 { 0x000687, 1, 0x01, 0x00000c48 },
181 { 0x0006a0, 1, 0x01, 0x00000005 },
182 { 0x000840, 1, 0x01, 0x00300008 },
183 { 0x000841, 1, 0x01, 0x04000080 },
184 { 0x000842, 1, 0x01, 0x00300008 },
185 { 0x000843, 1, 0x01, 0x04000080 },
186 { 0x000818, 8, 0x01, 0x00000000 },
187 { 0x000848, 16, 0x01, 0x00000000 },
188 { 0x000738, 1, 0x01, 0x00000000 },
189 { 0x0006aa, 1, 0x01, 0x00000001 },
190 { 0x0006ab, 1, 0x01, 0x00000002 },
191 { 0x0006ac, 1, 0x01, 0x00000080 },
192 { 0x0006ad, 2, 0x01, 0x00000100 },
193 { 0x0006b1, 1, 0x01, 0x00000011 },
194 { 0x0006bb, 1, 0x01, 0x000000cf },
195 { 0x0006ce, 1, 0x01, 0x2a712488 },
196 { 0x000739, 1, 0x01, 0x4085c000 },
197 { 0x00073a, 1, 0x01, 0x00000080 },
198 { 0x000786, 1, 0x01, 0x80000100 },
199 { 0x00073c, 1, 0x01, 0x00010100 },
200 { 0x00073d, 1, 0x01, 0x02800000 },
201 { 0x000787, 1, 0x01, 0x000000cf },
202 { 0x00078c, 1, 0x01, 0x00000008 },
203 { 0x000792, 1, 0x01, 0x00000001 },
204 { 0x000794, 1, 0x01, 0x00000001 },
205 { 0x000795, 2, 0x01, 0x00000001 },
206 { 0x000797, 1, 0x01, 0x000000cf },
207 { 0x000836, 1, 0x01, 0x00000001 },
208 { 0x00079a, 1, 0x01, 0x00000002 },
209 { 0x000833, 1, 0x01, 0x04444480 },
210 { 0x0007a1, 1, 0x01, 0x00000001 },
211 { 0x0007a3, 1, 0x01, 0x00000001 },
212 { 0x0007a4, 2, 0x01, 0x00000001 },
213 { 0x000831, 1, 0x01, 0x00000004 },
214 { 0x00080c, 1, 0x01, 0x00000002 },
215 { 0x00080d, 2, 0x01, 0x00000100 },
216 { 0x00080f, 1, 0x01, 0x00000001 },
217 { 0x000823, 1, 0x01, 0x00000002 },
218 { 0x000824, 2, 0x01, 0x00000100 },
219 { 0x000826, 1, 0x01, 0x00000001 },
220 { 0x00095d, 1, 0x01, 0x00000001 },
221 { 0x00082b, 1, 0x01, 0x00000004 },
222 { 0x000942, 1, 0x01, 0x00010001 },
223 { 0x000943, 1, 0x01, 0x00000001 },
224 { 0x000944, 1, 0x01, 0x00000022 },
225 { 0x0007c5, 1, 0x01, 0x00010001 },
226 { 0x000834, 1, 0x01, 0x00000001 },
227 { 0x0007c7, 1, 0x01, 0x00000001 },
228 { 0x00c1b0, 8, 0x01, 0x0000000f },
229 { 0x00c1b8, 1, 0x01, 0x0fac6881 },
230 { 0x00c1b9, 1, 0x01, 0x00fac688 },
231 { 0x01e100, 1, 0x01, 0x00000001 },
232 { 0x001000, 1, 0x01, 0x00000002 },
233 { 0x0006aa, 1, 0x01, 0x00000001 },
234 { 0x0006ad, 2, 0x01, 0x00000100 },
235 { 0x0006b1, 1, 0x01, 0x00000011 },
236 { 0x00078c, 1, 0x01, 0x00000008 },
237 { 0x000792, 1, 0x01, 0x00000001 },
238 { 0x000794, 1, 0x01, 0x00000001 },
239 { 0x000795, 2, 0x01, 0x00000001 },
240 { 0x000797, 1, 0x01, 0x000000cf },
241 { 0x00079a, 1, 0x01, 0x00000002 },
242 { 0x000833, 1, 0x01, 0x04444480 },
243 { 0x0007a1, 1, 0x01, 0x00000001 },
244 { 0x0007a3, 1, 0x01, 0x00000001 },
245 { 0x0007a4, 2, 0x01, 0x00000001 },
246 { 0x000831, 1, 0x01, 0x00000004 },
247 { 0x01e100, 1, 0x01, 0x00000001 },
248 { 0x001000, 1, 0x01, 0x00000014 },
249 { 0x000351, 1, 0x01, 0x00000100 },
250 { 0x000957, 1, 0x01, 0x00000003 },
251 { 0x00095d, 1, 0x01, 0x00000001 },
252 { 0x00082b, 1, 0x01, 0x00000004 },
253 { 0x000942, 1, 0x01, 0x00010001 },
254 { 0x000943, 1, 0x01, 0x00000001 },
255 { 0x0007c5, 1, 0x01, 0x00010001 },
256 { 0x000834, 1, 0x01, 0x00000001 },
257 { 0x0007c7, 1, 0x01, 0x00000001 },
258 { 0x01e100, 1, 0x01, 0x00000001 },
259 { 0x001000, 1, 0x01, 0x00000001 },
260 { 0x00080c, 1, 0x01, 0x00000002 },
261 { 0x00080d, 2, 0x01, 0x00000100 },
262 { 0x00080f, 1, 0x01, 0x00000001 },
263 { 0x000823, 1, 0x01, 0x00000002 },
264 { 0x000824, 2, 0x01, 0x00000100 },
265 { 0x000826, 1, 0x01, 0x00000001 },
266 { 0x01e100, 1, 0x01, 0x00000001 },
267 {}
268};
269
270struct nvc0_graph_init
271nvc0_grctx_init_9097[] = {
272 { 0x000800, 8, 0x40, 0x00000000 },
273 { 0x000804, 8, 0x40, 0x00000000 },
274 { 0x000808, 8, 0x40, 0x00000400 },
275 { 0x00080c, 8, 0x40, 0x00000300 },
276 { 0x000810, 1, 0x04, 0x000000cf },
277 { 0x000850, 7, 0x40, 0x00000000 },
278 { 0x000814, 8, 0x40, 0x00000040 },
279 { 0x000818, 8, 0x40, 0x00000001 },
280 { 0x00081c, 8, 0x40, 0x00000000 },
281 { 0x000820, 8, 0x40, 0x00000000 },
282 { 0x002700, 8, 0x20, 0x00000000 },
283 { 0x002704, 8, 0x20, 0x00000000 },
284 { 0x002708, 8, 0x20, 0x00000000 },
285 { 0x00270c, 8, 0x20, 0x00000000 },
286 { 0x002710, 8, 0x20, 0x00014000 },
287 { 0x002714, 8, 0x20, 0x00000040 },
288 { 0x001c00, 16, 0x10, 0x00000000 },
289 { 0x001c04, 16, 0x10, 0x00000000 },
290 { 0x001c08, 16, 0x10, 0x00000000 },
291 { 0x001c0c, 16, 0x10, 0x00000000 },
292 { 0x001d00, 16, 0x10, 0x00000000 },
293 { 0x001d04, 16, 0x10, 0x00000000 },
294 { 0x001d08, 16, 0x10, 0x00000000 },
295 { 0x001d0c, 16, 0x10, 0x00000000 },
296 { 0x001f00, 16, 0x08, 0x00000000 },
297 { 0x001f04, 16, 0x08, 0x00000000 },
298 { 0x001f80, 16, 0x08, 0x00000000 },
299 { 0x001f84, 16, 0x08, 0x00000000 },
300 { 0x002200, 5, 0x10, 0x00000022 },
301 { 0x002000, 1, 0x04, 0x00000000 },
302 { 0x002040, 1, 0x04, 0x00000011 },
303 { 0x002080, 1, 0x04, 0x00000020 },
304 { 0x0020c0, 1, 0x04, 0x00000030 },
305 { 0x002100, 1, 0x04, 0x00000040 },
306 { 0x002140, 1, 0x04, 0x00000051 },
307 { 0x00200c, 6, 0x40, 0x00000001 },
308 { 0x002010, 1, 0x04, 0x00000000 },
309 { 0x002050, 1, 0x04, 0x00000000 },
310 { 0x002090, 1, 0x04, 0x00000001 },
311 { 0x0020d0, 1, 0x04, 0x00000002 },
312 { 0x002110, 1, 0x04, 0x00000003 },
313 { 0x002150, 1, 0x04, 0x00000004 },
314 { 0x000380, 4, 0x20, 0x00000000 },
315 { 0x000384, 4, 0x20, 0x00000000 },
316 { 0x000388, 4, 0x20, 0x00000000 },
317 { 0x00038c, 4, 0x20, 0x00000000 },
318 { 0x000700, 4, 0x10, 0x00000000 },
319 { 0x000704, 4, 0x10, 0x00000000 },
320 { 0x000708, 4, 0x10, 0x00000000 },
321 { 0x002800, 128, 0x04, 0x00000000 },
322 { 0x000a00, 16, 0x20, 0x00000000 },
323 { 0x000a04, 16, 0x20, 0x00000000 },
324 { 0x000a08, 16, 0x20, 0x00000000 },
325 { 0x000a0c, 16, 0x20, 0x00000000 },
326 { 0x000a10, 16, 0x20, 0x00000000 },
327 { 0x000a14, 16, 0x20, 0x00000000 },
328 { 0x000c00, 16, 0x10, 0x00000000 },
329 { 0x000c04, 16, 0x10, 0x00000000 },
330 { 0x000c08, 16, 0x10, 0x00000000 },
331 { 0x000c0c, 16, 0x10, 0x3f800000 },
332 { 0x000d00, 8, 0x08, 0xffff0000 },
333 { 0x000d04, 8, 0x08, 0xffff0000 },
334 { 0x000e00, 16, 0x10, 0x00000000 },
335 { 0x000e04, 16, 0x10, 0xffff0000 },
336 { 0x000e08, 16, 0x10, 0xffff0000 },
337 { 0x000d40, 4, 0x08, 0x00000000 },
338 { 0x000d44, 4, 0x08, 0x00000000 },
339 { 0x001e00, 8, 0x20, 0x00000001 },
340 { 0x001e04, 8, 0x20, 0x00000001 },
341 { 0x001e08, 8, 0x20, 0x00000002 },
342 { 0x001e0c, 8, 0x20, 0x00000001 },
343 { 0x001e10, 8, 0x20, 0x00000001 },
344 { 0x001e14, 8, 0x20, 0x00000002 },
345 { 0x001e18, 8, 0x20, 0x00000001 },
346 { 0x003400, 128, 0x04, 0x00000000 },
347 { 0x00030c, 1, 0x04, 0x00000001 },
348 { 0x001944, 1, 0x04, 0x00000000 },
349 { 0x001514, 1, 0x04, 0x00000000 },
350 { 0x000d68, 1, 0x04, 0x0000ffff },
351 { 0x00121c, 1, 0x04, 0x0fac6881 },
352 { 0x000fac, 1, 0x04, 0x00000001 },
353 { 0x001538, 1, 0x04, 0x00000001 },
354 { 0x000fe0, 2, 0x04, 0x00000000 },
355 { 0x000fe8, 1, 0x04, 0x00000014 },
356 { 0x000fec, 1, 0x04, 0x00000040 },
357 { 0x000ff0, 1, 0x04, 0x00000000 },
358 { 0x00179c, 1, 0x04, 0x00000000 },
359 { 0x001228, 1, 0x04, 0x00000400 },
360 { 0x00122c, 1, 0x04, 0x00000300 },
361 { 0x001230, 1, 0x04, 0x00010001 },
362 { 0x0007f8, 1, 0x04, 0x00000000 },
363 { 0x0015b4, 1, 0x04, 0x00000001 },
364 { 0x0015cc, 1, 0x04, 0x00000000 },
365 { 0x001534, 1, 0x04, 0x00000000 },
366 { 0x000fb0, 1, 0x04, 0x00000000 },
367 { 0x0015d0, 1, 0x04, 0x00000000 },
368 { 0x00153c, 1, 0x04, 0x00000000 },
369 { 0x0016b4, 1, 0x04, 0x00000003 },
370 { 0x000fbc, 4, 0x04, 0x0000ffff },
371 { 0x000df8, 2, 0x04, 0x00000000 },
372 { 0x001948, 1, 0x04, 0x00000000 },
373 { 0x001970, 1, 0x04, 0x00000001 },
374 { 0x00161c, 1, 0x04, 0x000009f0 },
375 { 0x000dcc, 1, 0x04, 0x00000010 },
376 { 0x00163c, 1, 0x04, 0x00000000 },
377 { 0x0015e4, 1, 0x04, 0x00000000 },
378 { 0x001160, 32, 0x04, 0x25e00040 },
379 { 0x001880, 32, 0x04, 0x00000000 },
380 { 0x000f84, 2, 0x04, 0x00000000 },
381 { 0x0017c8, 2, 0x04, 0x00000000 },
382 { 0x0017d0, 1, 0x04, 0x000000ff },
383 { 0x0017d4, 1, 0x04, 0xffffffff },
384 { 0x0017d8, 1, 0x04, 0x00000002 },
385 { 0x0017dc, 1, 0x04, 0x00000000 },
386 { 0x0015f4, 2, 0x04, 0x00000000 },
387 { 0x001434, 2, 0x04, 0x00000000 },
388 { 0x000d74, 1, 0x04, 0x00000000 },
389 { 0x000dec, 1, 0x04, 0x00000001 },
390 { 0x0013a4, 1, 0x04, 0x00000000 },
391 { 0x001318, 1, 0x04, 0x00000001 },
392 { 0x001644, 1, 0x04, 0x00000000 },
393 { 0x000748, 1, 0x04, 0x00000000 },
394 { 0x000de8, 1, 0x04, 0x00000000 },
395 { 0x001648, 1, 0x04, 0x00000000 },
396 { 0x0012a4, 1, 0x04, 0x00000000 },
397 { 0x001120, 4, 0x04, 0x00000000 },
398 { 0x001118, 1, 0x04, 0x00000000 },
399 { 0x00164c, 1, 0x04, 0x00000000 },
400 { 0x001658, 1, 0x04, 0x00000000 },
401 { 0x001910, 1, 0x04, 0x00000290 },
402 { 0x001518, 1, 0x04, 0x00000000 },
403 { 0x00165c, 1, 0x04, 0x00000001 },
404 { 0x001520, 1, 0x04, 0x00000000 },
405 { 0x001604, 1, 0x04, 0x00000000 },
406 { 0x001570, 1, 0x04, 0x00000000 },
407 { 0x0013b0, 2, 0x04, 0x3f800000 },
408 { 0x00020c, 1, 0x04, 0x00000000 },
409 { 0x001670, 1, 0x04, 0x30201000 },
410 { 0x001674, 1, 0x04, 0x70605040 },
411 { 0x001678, 1, 0x04, 0xb8a89888 },
412 { 0x00167c, 1, 0x04, 0xf8e8d8c8 },
413 { 0x00166c, 1, 0x04, 0x00000000 },
414 { 0x001680, 1, 0x04, 0x00ffff00 },
415 { 0x0012d0, 1, 0x04, 0x00000003 },
416 { 0x0012d4, 1, 0x04, 0x00000002 },
417 { 0x001684, 2, 0x04, 0x00000000 },
418 { 0x000dac, 2, 0x04, 0x00001b02 },
419 { 0x000db4, 1, 0x04, 0x00000000 },
420 { 0x00168c, 1, 0x04, 0x00000000 },
421 { 0x0015bc, 1, 0x04, 0x00000000 },
422 { 0x00156c, 1, 0x04, 0x00000000 },
423 { 0x00187c, 1, 0x04, 0x00000000 },
424 { 0x001110, 1, 0x04, 0x00000001 },
425 { 0x000dc0, 3, 0x04, 0x00000000 },
426 { 0x001234, 1, 0x04, 0x00000000 },
427 { 0x001690, 1, 0x04, 0x00000000 },
428 { 0x0012ac, 1, 0x04, 0x00000001 },
429 { 0x0002c4, 1, 0x04, 0x00000000 },
430 { 0x000790, 5, 0x04, 0x00000000 },
431 { 0x00077c, 1, 0x04, 0x00000000 },
432 { 0x001000, 1, 0x04, 0x00000010 },
433 { 0x0010fc, 1, 0x04, 0x00000000 },
434 { 0x001290, 1, 0x04, 0x00000000 },
435 { 0x000218, 1, 0x04, 0x00000010 },
436 { 0x0012d8, 1, 0x04, 0x00000000 },
437 { 0x0012dc, 1, 0x04, 0x00000010 },
438 { 0x000d94, 1, 0x04, 0x00000001 },
439 { 0x00155c, 2, 0x04, 0x00000000 },
440 { 0x001564, 1, 0x04, 0x00001fff },
441 { 0x001574, 2, 0x04, 0x00000000 },
442 { 0x00157c, 1, 0x04, 0x003fffff },
443 { 0x001354, 1, 0x04, 0x00000000 },
444 { 0x001664, 1, 0x04, 0x00000000 },
445 { 0x001610, 1, 0x04, 0x00000012 },
446 { 0x001608, 2, 0x04, 0x00000000 },
447 { 0x00162c, 1, 0x04, 0x00000003 },
448 { 0x000210, 1, 0x04, 0x00000000 },
449 { 0x000320, 1, 0x04, 0x00000000 },
450 { 0x000324, 6, 0x04, 0x3f800000 },
451 { 0x000750, 1, 0x04, 0x00000000 },
452 { 0x000760, 1, 0x04, 0x39291909 },
453 { 0x000764, 1, 0x04, 0x79695949 },
454 { 0x000768, 1, 0x04, 0xb9a99989 },
455 { 0x00076c, 1, 0x04, 0xf9e9d9c9 },
456 { 0x000770, 1, 0x04, 0x30201000 },
457 { 0x000774, 1, 0x04, 0x70605040 },
458 { 0x000778, 1, 0x04, 0x00009080 },
459 { 0x000780, 1, 0x04, 0x39291909 },
460 { 0x000784, 1, 0x04, 0x79695949 },
461 { 0x000788, 1, 0x04, 0xb9a99989 },
462 { 0x00078c, 1, 0x04, 0xf9e9d9c9 },
463 { 0x0007d0, 1, 0x04, 0x30201000 },
464 { 0x0007d4, 1, 0x04, 0x70605040 },
465 { 0x0007d8, 1, 0x04, 0x00009080 },
466 { 0x00037c, 1, 0x04, 0x00000001 },
467 { 0x000740, 2, 0x04, 0x00000000 },
468 { 0x002600, 1, 0x04, 0x00000000 },
469 { 0x001918, 1, 0x04, 0x00000000 },
470 { 0x00191c, 1, 0x04, 0x00000900 },
471 { 0x001920, 1, 0x04, 0x00000405 },
472 { 0x001308, 1, 0x04, 0x00000001 },
473 { 0x001924, 1, 0x04, 0x00000000 },
474 { 0x0013ac, 1, 0x04, 0x00000000 },
475 { 0x00192c, 1, 0x04, 0x00000001 },
476 { 0x00193c, 1, 0x04, 0x00002c1c },
477 { 0x000d7c, 1, 0x04, 0x00000000 },
478 { 0x000f8c, 1, 0x04, 0x00000000 },
479 { 0x0002c0, 1, 0x04, 0x00000001 },
480 { 0x001510, 1, 0x04, 0x00000000 },
481 { 0x001940, 1, 0x04, 0x00000000 },
482 { 0x000ff4, 2, 0x04, 0x00000000 },
483 { 0x00194c, 2, 0x04, 0x00000000 },
484 { 0x001968, 1, 0x04, 0x00000000 },
485 { 0x001590, 1, 0x04, 0x0000003f },
486 { 0x0007e8, 4, 0x04, 0x00000000 },
487 { 0x00196c, 1, 0x04, 0x00000011 },
488 { 0x00197c, 1, 0x04, 0x00000000 },
489 { 0x000fcc, 2, 0x04, 0x00000000 },
490 { 0x0002d8, 1, 0x04, 0x00000040 },
491 { 0x001980, 1, 0x04, 0x00000080 },
492 { 0x001504, 1, 0x04, 0x00000080 },
493 { 0x001984, 1, 0x04, 0x00000000 },
494 { 0x000300, 1, 0x04, 0x00000001 },
495 { 0x0013a8, 1, 0x04, 0x00000000 },
496 { 0x0012ec, 1, 0x04, 0x00000000 },
497 { 0x001310, 1, 0x04, 0x00000000 },
498 { 0x001314, 1, 0x04, 0x00000001 },
499 { 0x001380, 1, 0x04, 0x00000000 },
500 { 0x001384, 4, 0x04, 0x00000001 },
501 { 0x001394, 1, 0x04, 0x00000000 },
502 { 0x00139c, 1, 0x04, 0x00000000 },
503 { 0x001398, 1, 0x04, 0x00000000 },
504 { 0x001594, 1, 0x04, 0x00000000 },
505 { 0x001598, 4, 0x04, 0x00000001 },
506 { 0x000f54, 3, 0x04, 0x00000000 },
507 { 0x0019bc, 1, 0x04, 0x00000000 },
508 { 0x000f9c, 2, 0x04, 0x00000000 },
509 { 0x0012cc, 1, 0x04, 0x00000000 },
510 { 0x0012e8, 1, 0x04, 0x00000000 },
511 { 0x00130c, 1, 0x04, 0x00000001 },
512 { 0x001360, 8, 0x04, 0x00000000 },
513 { 0x00133c, 2, 0x04, 0x00000001 },
514 { 0x001344, 1, 0x04, 0x00000002 },
515 { 0x001348, 2, 0x04, 0x00000001 },
516 { 0x001350, 1, 0x04, 0x00000002 },
517 { 0x001358, 1, 0x04, 0x00000001 },
518 { 0x0012e4, 1, 0x04, 0x00000000 },
519 { 0x00131c, 1, 0x04, 0x00000000 },
520 { 0x001320, 3, 0x04, 0x00000000 },
521 { 0x0019c0, 1, 0x04, 0x00000000 },
522 { 0x001140, 1, 0x04, 0x00000000 },
523 { 0x0019c4, 1, 0x04, 0x00000000 },
524 { 0x0019c8, 1, 0x04, 0x00001500 },
525 { 0x00135c, 1, 0x04, 0x00000000 },
526 { 0x000f90, 1, 0x04, 0x00000000 },
527 { 0x0019e0, 8, 0x04, 0x00000001 },
528 { 0x0019cc, 1, 0x04, 0x00000001 },
529 { 0x0015b8, 1, 0x04, 0x00000000 },
530 { 0x001a00, 1, 0x04, 0x00001111 },
531 { 0x001a04, 7, 0x04, 0x00000000 },
532 { 0x000d6c, 2, 0x04, 0xffff0000 },
533 { 0x0010f8, 1, 0x04, 0x00001010 },
534 { 0x000d80, 5, 0x04, 0x00000000 },
535 { 0x000da0, 1, 0x04, 0x00000000 },
536 { 0x001508, 1, 0x04, 0x80000000 },
537 { 0x00150c, 1, 0x04, 0x40000000 },
538 { 0x001668, 1, 0x04, 0x00000000 },
539 { 0x000318, 2, 0x04, 0x00000008 },
540 { 0x000d9c, 1, 0x04, 0x00000001 },
541 { 0x0007dc, 1, 0x04, 0x00000000 },
542 { 0x00074c, 1, 0x04, 0x00000055 },
543 { 0x001420, 1, 0x04, 0x00000003 },
544 { 0x0017bc, 2, 0x04, 0x00000000 },
545 { 0x0017c4, 1, 0x04, 0x00000001 },
546 { 0x001008, 1, 0x04, 0x00000008 },
547 { 0x00100c, 1, 0x04, 0x00000040 },
548 { 0x001010, 1, 0x04, 0x0000012c },
549 { 0x000d60, 1, 0x04, 0x00000040 },
550 { 0x00075c, 1, 0x04, 0x00000003 },
551 { 0x001018, 1, 0x04, 0x00000020 },
552 { 0x00101c, 1, 0x04, 0x00000001 },
553 { 0x001020, 1, 0x04, 0x00000020 },
554 { 0x001024, 1, 0x04, 0x00000001 },
555 { 0x001444, 3, 0x04, 0x00000000 },
556 { 0x000360, 1, 0x04, 0x20164010 },
557 { 0x000364, 1, 0x04, 0x00000020 },
558 { 0x000368, 1, 0x04, 0x00000000 },
559 { 0x000de4, 1, 0x04, 0x00000000 },
560 { 0x000204, 1, 0x04, 0x00000006 },
561 { 0x000208, 1, 0x04, 0x00000000 },
562 { 0x0002cc, 1, 0x04, 0x003fffff },
563 { 0x0002d0, 1, 0x04, 0x00000c48 },
564 { 0x001220, 1, 0x04, 0x00000005 },
565 { 0x000fdc, 1, 0x04, 0x00000000 },
566 { 0x000f98, 1, 0x04, 0x00300008 },
567 { 0x001284, 1, 0x04, 0x04000080 },
568 { 0x001450, 1, 0x04, 0x00300008 },
569 { 0x001454, 1, 0x04, 0x04000080 },
570 { 0x000214, 1, 0x04, 0x00000000 },
571 {}
572};
573
574struct nvc0_graph_init
575nvc0_grctx_init_902d[] = {
576 { 0x000200, 1, 0x04, 0x000000cf },
577 { 0x000204, 1, 0x04, 0x00000001 },
578 { 0x000208, 1, 0x04, 0x00000020 },
579 { 0x00020c, 1, 0x04, 0x00000001 },
580 { 0x000210, 1, 0x04, 0x00000000 },
581 { 0x000214, 1, 0x04, 0x00000080 },
582 { 0x000218, 2, 0x04, 0x00000100 },
583 { 0x000220, 2, 0x04, 0x00000000 },
584 { 0x000230, 1, 0x04, 0x000000cf },
585 { 0x000234, 1, 0x04, 0x00000001 },
586 { 0x000238, 1, 0x04, 0x00000020 },
587 { 0x00023c, 1, 0x04, 0x00000001 },
588 { 0x000244, 1, 0x04, 0x00000080 },
589 { 0x000248, 2, 0x04, 0x00000100 },
590 {}
591};
592
593struct nvc0_graph_init
594nvc0_grctx_init_9039[] = {
595 { 0x00030c, 3, 0x04, 0x00000000 },
596 { 0x000320, 1, 0x04, 0x00000000 },
597 { 0x000238, 2, 0x04, 0x00000000 },
598 { 0x000318, 2, 0x04, 0x00000000 },
599 {}
600};
601
602struct nvc0_graph_init
603nvc0_grctx_init_90c0[] = {
604 { 0x00270c, 8, 0x20, 0x00000000 },
605 { 0x00030c, 1, 0x04, 0x00000001 },
606 { 0x001944, 1, 0x04, 0x00000000 },
607 { 0x000758, 1, 0x04, 0x00000100 },
608 { 0x0002c4, 1, 0x04, 0x00000000 },
609 { 0x000790, 5, 0x04, 0x00000000 },
610 { 0x00077c, 1, 0x04, 0x00000000 },
611 { 0x000204, 3, 0x04, 0x00000000 },
612 { 0x000214, 1, 0x04, 0x00000000 },
613 { 0x00024c, 1, 0x04, 0x00000000 },
614 { 0x000d94, 1, 0x04, 0x00000001 },
615 { 0x001608, 2, 0x04, 0x00000000 },
616 { 0x001664, 1, 0x04, 0x00000000 },
617 {}
618};
619
620struct nvc0_graph_init
621nvc0_grctx_init_base[] = {
622 { 0x400204, 2, 0x04, 0x00000000 },
623 {}
624};
625
626struct nvc0_graph_init
627nvc0_grctx_init_unk40xx[] = {
628 { 0x404004, 10, 0x04, 0x00000000 },
629 { 0x404044, 1, 0x04, 0x00000000 },
630 { 0x404094, 1, 0x04, 0x00000000 },
631 { 0x404098, 12, 0x04, 0x00000000 },
632 { 0x4040c8, 1, 0x04, 0xf0000087 },
633 { 0x4040d0, 6, 0x04, 0x00000000 },
634 { 0x4040e8, 1, 0x04, 0x00001000 },
635 { 0x4040f8, 1, 0x04, 0x00000000 },
636 { 0x404130, 1, 0x04, 0x00000000 },
637 { 0x404134, 1, 0x04, 0x00000000 },
638 { 0x404138, 1, 0x04, 0x20000040 },
639 { 0x404150, 1, 0x04, 0x0000002e },
640 { 0x404154, 1, 0x04, 0x00000400 },
641 { 0x404158, 1, 0x04, 0x00000200 },
642 { 0x404164, 1, 0x04, 0x00000055 },
643 { 0x404168, 1, 0x04, 0x00000000 },
644 { 0x404174, 1, 0x04, 0x00000000 },
645 { 0x404178, 2, 0x04, 0x00000000 },
646 { 0x404200, 8, 0x04, 0x00000000 },
647 {}
648};
649
650struct nvc0_graph_init
651nvc0_grctx_init_unk44xx[] = {
652 { 0x404404, 14, 0x04, 0x00000000 },
653 { 0x404460, 2, 0x04, 0x00000000 },
654 { 0x404468, 1, 0x04, 0x00ffffff },
655 { 0x40446c, 1, 0x04, 0x00000000 },
656 { 0x404480, 1, 0x04, 0x00000001 },
657 { 0x404498, 1, 0x04, 0x00000001 },
658 {}
659};
660
661struct nvc0_graph_init
662nvc0_grctx_init_unk46xx[] = {
663 { 0x404604, 1, 0x04, 0x00000015 },
664 { 0x404608, 1, 0x04, 0x00000000 },
665 { 0x40460c, 1, 0x04, 0x00002e00 },
666 { 0x404610, 1, 0x04, 0x00000100 },
667 { 0x404618, 8, 0x04, 0x00000000 },
668 { 0x404638, 1, 0x04, 0x00000004 },
669 { 0x40463c, 8, 0x04, 0x00000000 },
670 { 0x40465c, 1, 0x04, 0x007f0100 },
671 { 0x404660, 7, 0x04, 0x00000000 },
672 { 0x40467c, 1, 0x04, 0x00000002 },
673 { 0x404680, 8, 0x04, 0x00000000 },
674 { 0x4046a0, 1, 0x04, 0x007f0080 },
675 { 0x4046a4, 18, 0x04, 0x00000000 },
676 { 0x4046f0, 2, 0x04, 0x00000000 },
677 {}
678};
679
680struct nvc0_graph_init
681nvc0_grctx_init_unk47xx[] = {
682 { 0x404700, 13, 0x04, 0x00000000 },
683 { 0x404734, 1, 0x04, 0x00000100 },
684 { 0x404738, 8, 0x04, 0x00000000 },
685 {}
686};
687
688struct nvc0_graph_init
689nvc0_grctx_init_unk58xx[] = {
690 { 0x405800, 1, 0x04, 0x078000bf },
691 { 0x405830, 1, 0x04, 0x02180000 },
692 { 0x405834, 2, 0x04, 0x00000000 },
693 { 0x405854, 1, 0x04, 0x00000000 },
694 { 0x405870, 4, 0x04, 0x00000001 },
695 { 0x405a00, 2, 0x04, 0x00000000 },
696 { 0x405a18, 1, 0x04, 0x00000000 },
697 {}
698};
699
700struct nvc0_graph_init
701nvc0_grctx_init_unk60xx[] = {
702 { 0x406020, 1, 0x04, 0x000103c1 },
703 { 0x406028, 4, 0x04, 0x00000001 },
704 {}
705};
706
707struct nvc0_graph_init
708nvc0_grctx_init_unk64xx[] = {
709 { 0x4064a8, 1, 0x04, 0x00000000 },
710 { 0x4064ac, 1, 0x04, 0x00003fff },
711 { 0x4064b4, 2, 0x04, 0x00000000 },
712 {}
713};
714
715struct nvc0_graph_init
716nvc0_grctx_init_unk78xx[] = {
717 { 0x407804, 1, 0x04, 0x00000023 },
718 { 0x40780c, 1, 0x04, 0x0a418820 },
719 { 0x407810, 1, 0x04, 0x062080e6 },
720 { 0x407814, 1, 0x04, 0x020398a4 },
721 { 0x407818, 1, 0x04, 0x0e629062 },
722 { 0x40781c, 1, 0x04, 0x0a418820 },
723 { 0x407820, 1, 0x04, 0x000000e6 },
724 { 0x4078bc, 1, 0x04, 0x00000103 },
725 {}
726};
727
728struct nvc0_graph_init
729nvc0_grctx_init_unk80xx[] = {
730 { 0x408000, 2, 0x04, 0x00000000 },
731 { 0x408008, 1, 0x04, 0x00000018 },
732 { 0x40800c, 2, 0x04, 0x00000000 },
733 { 0x408014, 1, 0x04, 0x00000069 },
734 { 0x408018, 1, 0x04, 0xe100e100 },
735 { 0x408064, 1, 0x04, 0x00000000 },
736 {}
737};
738
739struct nvc0_graph_init
740nvc0_grctx_init_rop[] = {
741 { 0x408800, 1, 0x04, 0x02802a3c },
742 { 0x408804, 1, 0x04, 0x00000040 },
743 { 0x408808, 1, 0x04, 0x0003e00d },
744 { 0x408900, 1, 0x04, 0x3080b801 },
745 { 0x408904, 1, 0x04, 0x02000001 },
746 { 0x408908, 1, 0x04, 0x00c80929 },
747 { 0x408980, 1, 0x04, 0x0000011d },
748 {}
749};
750
751struct nvc0_graph_init
752nvc0_grctx_init_gpc_0[] = {
753 { 0x418380, 1, 0x04, 0x00000016 },
754 { 0x418400, 1, 0x04, 0x38004e00 },
755 { 0x418404, 1, 0x04, 0x71e0ffff },
756 { 0x418408, 1, 0x04, 0x00000000 },
757 { 0x41840c, 1, 0x04, 0x00001008 },
758 { 0x418410, 1, 0x04, 0x0fff0fff },
759 { 0x418414, 1, 0x04, 0x00200fff },
760 { 0x418450, 6, 0x04, 0x00000000 },
761 { 0x418468, 1, 0x04, 0x00000001 },
762 { 0x41846c, 2, 0x04, 0x00000000 },
763 { 0x418600, 1, 0x04, 0x0000001f },
764 { 0x418684, 1, 0x04, 0x0000000f },
765 { 0x418700, 1, 0x04, 0x00000002 },
766 { 0x418704, 1, 0x04, 0x00000080 },
767 { 0x418708, 1, 0x04, 0x00000000 },
768 { 0x41870c, 1, 0x04, 0x07c80000 },
769 { 0x418710, 1, 0x04, 0x00000000 },
770 { 0x418800, 1, 0x04, 0x0006860a },
771 { 0x418808, 3, 0x04, 0x00000000 },
772 { 0x418828, 1, 0x04, 0x00008442 },
773 { 0x418830, 1, 0x04, 0x00000001 },
774 { 0x4188d8, 1, 0x04, 0x00000008 },
775 { 0x4188e0, 1, 0x04, 0x01000000 },
776 { 0x4188e8, 5, 0x04, 0x00000000 },
777 { 0x4188fc, 1, 0x04, 0x00100000 },
778 { 0x41891c, 1, 0x04, 0x00ff00ff },
779 { 0x418924, 1, 0x04, 0x00000000 },
780 { 0x418928, 1, 0x04, 0x00ffff00 },
781 { 0x41892c, 1, 0x04, 0x0000ff00 },
782 { 0x418b00, 1, 0x04, 0x00000000 },
783 { 0x418b08, 1, 0x04, 0x0a418820 },
784 { 0x418b0c, 1, 0x04, 0x062080e6 },
785 { 0x418b10, 1, 0x04, 0x020398a4 },
786 { 0x418b14, 1, 0x04, 0x0e629062 },
787 { 0x418b18, 1, 0x04, 0x0a418820 },
788 { 0x418b1c, 1, 0x04, 0x000000e6 },
789 { 0x418bb8, 1, 0x04, 0x00000103 },
790 { 0x418c08, 1, 0x04, 0x00000001 },
791 { 0x418c10, 8, 0x04, 0x00000000 },
792 { 0x418c80, 1, 0x04, 0x20200004 },
793 { 0x418c8c, 1, 0x04, 0x00000001 },
794 { 0x419000, 1, 0x04, 0x00000780 },
795 { 0x419004, 2, 0x04, 0x00000000 },
796 { 0x419014, 1, 0x04, 0x00000004 },
797 {}
798};
799
800struct nvc0_graph_init
801nvc0_grctx_init_gpc_1[] = {
802 { 0x418a00, 3, 0x04, 0x00000000 },
803 { 0x418a0c, 1, 0x04, 0x00010000 },
804 { 0x418a10, 3, 0x04, 0x00000000 },
805 { 0x418a20, 3, 0x04, 0x00000000 },
806 { 0x418a2c, 1, 0x04, 0x00010000 },
807 { 0x418a30, 3, 0x04, 0x00000000 },
808 { 0x418a40, 3, 0x04, 0x00000000 },
809 { 0x418a4c, 1, 0x04, 0x00010000 },
810 { 0x418a50, 3, 0x04, 0x00000000 },
811 { 0x418a60, 3, 0x04, 0x00000000 },
812 { 0x418a6c, 1, 0x04, 0x00010000 },
813 { 0x418a70, 3, 0x04, 0x00000000 },
814 { 0x418a80, 3, 0x04, 0x00000000 },
815 { 0x418a8c, 1, 0x04, 0x00010000 },
816 { 0x418a90, 3, 0x04, 0x00000000 },
817 { 0x418aa0, 3, 0x04, 0x00000000 },
818 { 0x418aac, 1, 0x04, 0x00010000 },
819 { 0x418ab0, 3, 0x04, 0x00000000 },
820 { 0x418ac0, 3, 0x04, 0x00000000 },
821 { 0x418acc, 1, 0x04, 0x00010000 },
822 { 0x418ad0, 3, 0x04, 0x00000000 },
823 { 0x418ae0, 3, 0x04, 0x00000000 },
824 { 0x418aec, 1, 0x04, 0x00010000 },
825 { 0x418af0, 3, 0x04, 0x00000000 },
826 {}
827};
828
829struct nvc0_graph_init
830nvc0_grctx_init_tpc[] = {
831 { 0x419818, 1, 0x04, 0x00000000 },
832 { 0x41983c, 1, 0x04, 0x00038bc7 },
833 { 0x419848, 1, 0x04, 0x00000000 },
834 { 0x419864, 1, 0x04, 0x0000012a },
835 { 0x419888, 1, 0x04, 0x00000000 },
836 { 0x419a00, 1, 0x04, 0x000001f0 },
837 { 0x419a04, 1, 0x04, 0x00000001 },
838 { 0x419a08, 1, 0x04, 0x00000023 },
839 { 0x419a0c, 1, 0x04, 0x00020000 },
840 { 0x419a10, 1, 0x04, 0x00000000 },
841 { 0x419a14, 1, 0x04, 0x00000200 },
842 { 0x419b00, 1, 0x04, 0x0a418820 },
843 { 0x419b04, 1, 0x04, 0x062080e6 },
844 { 0x419b08, 1, 0x04, 0x020398a4 },
845 { 0x419b0c, 1, 0x04, 0x0e629062 },
846 { 0x419b10, 1, 0x04, 0x0a418820 },
847 { 0x419b14, 1, 0x04, 0x000000e6 },
848 { 0x419bd0, 1, 0x04, 0x00900103 },
849 { 0x419be0, 1, 0x04, 0x00000001 },
850 { 0x419be4, 1, 0x04, 0x00000000 },
851 { 0x419c00, 1, 0x04, 0x00000002 },
852 { 0x419c04, 1, 0x04, 0x00000006 },
853 { 0x419c08, 1, 0x04, 0x00000002 },
854 { 0x419c20, 1, 0x04, 0x00000000 },
855 { 0x419cb0, 1, 0x04, 0x00060048 },
856 { 0x419ce8, 1, 0x04, 0x00000000 },
857 { 0x419cf4, 1, 0x04, 0x00000183 },
858 { 0x419d20, 1, 0x04, 0x02180000 },
859 { 0x419d24, 1, 0x04, 0x00001fff },
860 { 0x419e04, 3, 0x04, 0x00000000 },
861 { 0x419e10, 1, 0x04, 0x00000002 },
862 { 0x419e44, 1, 0x04, 0x001beff2 },
863 { 0x419e48, 1, 0x04, 0x00000000 },
864 { 0x419e4c, 1, 0x04, 0x0000000f },
865 { 0x419e50, 17, 0x04, 0x00000000 },
866 { 0x419e98, 1, 0x04, 0x00000000 },
867 { 0x419f50, 2, 0x04, 0x00000000 },
868 {}
869};
34 870
35int 871void
36nvc0_grctx_init(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 872nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
37{ 873{
38 struct nouveau_bar *bar = nouveau_bar(priv); 874 int gpc, tpc;
39 struct nouveau_gpuobj *chan; 875 u32 offset;
40 u32 size = (0x80000 + priv->size + 4095) & ~4095;
41 int ret, i;
42
43 /* allocate memory to for a "channel", which we'll use to generate
44 * the default context values
45 */
46 ret = nouveau_gpuobj_new(nv_object(priv), NULL, size, 0x1000,
47 NVOBJ_FLAG_ZERO_ALLOC, &info->chan);
48 chan = info->chan;
49 if (ret) {
50 nv_error(priv, "failed to allocate channel memory, %d\n", ret);
51 return ret;
52 }
53
54 /* PGD pointer */
55 nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));
56 nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));
57 nv_wo32(chan, 0x0208, 0xffffffff);
58 nv_wo32(chan, 0x020c, 0x000000ff);
59
60 /* PGT[0] pointer */
61 nv_wo32(chan, 0x1000, 0x00000000);
62 nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);
63
64 /* identity-map the whole "channel" into its own vm */
65 for (i = 0; i < size / 4096; i++) {
66 u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;
67 nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));
68 nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));
69 }
70
71 /* context pointer (virt) */
72 nv_wo32(chan, 0x0210, 0x00080004);
73 nv_wo32(chan, 0x0214, 0x00000000);
74
75 bar->flush(bar);
76 876
77 nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); 877 mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
78 nv_wr32(priv, 0x100cbc, 0x80000001); 878 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
79 nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); 879 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
80
81 /* setup default state for mmio list construction */
82 info->data = priv->mmio_data;
83 info->mmio = priv->mmio_list;
84 info->addr = 0x2000 + (i * 8);
85 info->priv = priv;
86 info->buffer_nr = 0;
87 880
88 if (priv->firmware) { 881 mmio_list(0x408004, 0x00000000, 8, 0);
89 nv_wr32(priv, 0x409840, 0x00000030); 882 mmio_list(0x408008, 0x80000018, 0, 0);
90 nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); 883 mmio_list(0x40800c, 0x00000000, 8, 1);
91 nv_wr32(priv, 0x409504, 0x00000003); 884 mmio_list(0x408010, 0x80000000, 0, 0);
92 if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) 885 mmio_list(0x418810, 0x80000000, 12, 2);
93 nv_error(priv, "load_ctx timeout\n"); 886 mmio_list(0x419848, 0x10000000, 12, 2);
887 mmio_list(0x419004, 0x00000000, 8, 1);
888 mmio_list(0x419008, 0x00000000, 0, 0);
889 mmio_list(0x418808, 0x00000000, 8, 0);
890 mmio_list(0x41880c, 0x80000018, 0, 0);
94 891
95 nv_wo32(chan, 0x8001c, 1); 892 mmio_list(0x405830, 0x02180000, 0, 0);
96 nv_wo32(chan, 0x80020, 0);
97 nv_wo32(chan, 0x80028, 0);
98 nv_wo32(chan, 0x8002c, 0);
99 bar->flush(bar);
100 return 0;
101 }
102 893
103 /* HUB_FUC(SET_CHAN) */ 894 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
104 nv_wr32(priv, 0x409840, 0x80000000); 895 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
105 nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); 896 u32 addr = TPC_UNIT(gpc, tpc, 0x0520);
106 nv_wr32(priv, 0x409504, 0x00000001); 897 mmio_list(addr, 0x02180000 | offset, 0, 0);
107 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { 898 offset += 0x0324;
108 nv_error(priv, "HUB_SET_CHAN timeout\n"); 899 }
109 nvc0_graph_ctxctl_debug(priv);
110 nouveau_gpuobj_ref(NULL, &info->chan);
111 return -EBUSY;
112 } 900 }
113
114 return 0;
115} 901}
116 902
117void 903void
118nvc0_grctx_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) 904nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
119{ 905{
120 info->buffer[info->buffer_nr] = info->addr;
121 info->buffer[info->buffer_nr] += (align - 1);
122 info->buffer[info->buffer_nr] &= ~(align - 1);
123 info->addr = info->buffer[info->buffer_nr++] + size;
124
125 info->data->size = size;
126 info->data->align = align;
127 info->data->access = access;
128 info->data++;
129} 906}
130 907
131void 908void
132nvc0_grctx_mmio(struct nvc0_grctx *info, u32 addr, u32 data, u32 shift, u32 buf) 909nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
133{ 910{
134 struct nvc0_graph_priv *priv = info->priv; 911 int gpc, tpc, id;
135
136 info->mmio->addr = addr;
137 info->mmio->data = data;
138 info->mmio->shift = shift;
139 info->mmio->buffer = buf;
140 info->mmio++;
141 912
142 if (shift) 913 for (tpc = 0, id = 0; tpc < 4; tpc++) {
143 data |= info->buffer[buf] >> shift; 914 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
144 nv_wr32(priv, addr, data); 915 if (tpc < priv->tpc_nr[gpc]) {
145} 916 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
146 917 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
147int 918 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
148nvc0_grctx_fini(struct nvc0_grctx *info) 919 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
149{ 920 id++;
150 struct nvc0_graph_priv *priv = info->priv; 921 }
151 int i;
152
153 /* trigger a context unload by unsetting the "next channel valid" bit
154 * and faking a context switch interrupt
155 */
156 nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
157 nv_wr32(priv, 0x409000, 0x00000100);
158 if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
159 nv_error(priv, "grctx template channel unload timeout\n");
160 return -EBUSY;
161 }
162
163 priv->data = kmalloc(priv->size, GFP_KERNEL);
164 if (priv->data) {
165 for (i = 0; i < priv->size; i += 4)
166 priv->data[i / 4] = nv_ro32(info->chan, 0x80000 + i);
167 }
168
169 nouveau_gpuobj_ref(NULL, &info->chan);
170 return priv->data ? 0 : -ENOMEM;
171}
172 922
173static void 923 nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
174nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) 924 nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
175{ 925 }
176 u32 fermi = nvc0_graph_class(priv);
177 u32 mthd;
178
179 nv_mthd(priv, 0x9097, 0x0800, 0x00000000);
180 nv_mthd(priv, 0x9097, 0x0840, 0x00000000);
181 nv_mthd(priv, 0x9097, 0x0880, 0x00000000);
182 nv_mthd(priv, 0x9097, 0x08c0, 0x00000000);
183 nv_mthd(priv, 0x9097, 0x0900, 0x00000000);
184 nv_mthd(priv, 0x9097, 0x0940, 0x00000000);
185 nv_mthd(priv, 0x9097, 0x0980, 0x00000000);
186 nv_mthd(priv, 0x9097, 0x09c0, 0x00000000);
187 nv_mthd(priv, 0x9097, 0x0804, 0x00000000);
188 nv_mthd(priv, 0x9097, 0x0844, 0x00000000);
189 nv_mthd(priv, 0x9097, 0x0884, 0x00000000);
190 nv_mthd(priv, 0x9097, 0x08c4, 0x00000000);
191 nv_mthd(priv, 0x9097, 0x0904, 0x00000000);
192 nv_mthd(priv, 0x9097, 0x0944, 0x00000000);
193 nv_mthd(priv, 0x9097, 0x0984, 0x00000000);
194 nv_mthd(priv, 0x9097, 0x09c4, 0x00000000);
195 nv_mthd(priv, 0x9097, 0x0808, 0x00000400);
196 nv_mthd(priv, 0x9097, 0x0848, 0x00000400);
197 nv_mthd(priv, 0x9097, 0x0888, 0x00000400);
198 nv_mthd(priv, 0x9097, 0x08c8, 0x00000400);
199 nv_mthd(priv, 0x9097, 0x0908, 0x00000400);
200 nv_mthd(priv, 0x9097, 0x0948, 0x00000400);
201 nv_mthd(priv, 0x9097, 0x0988, 0x00000400);
202 nv_mthd(priv, 0x9097, 0x09c8, 0x00000400);
203 nv_mthd(priv, 0x9097, 0x080c, 0x00000300);
204 nv_mthd(priv, 0x9097, 0x084c, 0x00000300);
205 nv_mthd(priv, 0x9097, 0x088c, 0x00000300);
206 nv_mthd(priv, 0x9097, 0x08cc, 0x00000300);
207 nv_mthd(priv, 0x9097, 0x090c, 0x00000300);
208 nv_mthd(priv, 0x9097, 0x094c, 0x00000300);
209 nv_mthd(priv, 0x9097, 0x098c, 0x00000300);
210 nv_mthd(priv, 0x9097, 0x09cc, 0x00000300);
211 nv_mthd(priv, 0x9097, 0x0810, 0x000000cf);
212 nv_mthd(priv, 0x9097, 0x0850, 0x00000000);
213 nv_mthd(priv, 0x9097, 0x0890, 0x00000000);
214 nv_mthd(priv, 0x9097, 0x08d0, 0x00000000);
215 nv_mthd(priv, 0x9097, 0x0910, 0x00000000);
216 nv_mthd(priv, 0x9097, 0x0950, 0x00000000);
217 nv_mthd(priv, 0x9097, 0x0990, 0x00000000);
218 nv_mthd(priv, 0x9097, 0x09d0, 0x00000000);
219 nv_mthd(priv, 0x9097, 0x0814, 0x00000040);
220 nv_mthd(priv, 0x9097, 0x0854, 0x00000040);
221 nv_mthd(priv, 0x9097, 0x0894, 0x00000040);
222 nv_mthd(priv, 0x9097, 0x08d4, 0x00000040);
223 nv_mthd(priv, 0x9097, 0x0914, 0x00000040);
224 nv_mthd(priv, 0x9097, 0x0954, 0x00000040);
225 nv_mthd(priv, 0x9097, 0x0994, 0x00000040);
226 nv_mthd(priv, 0x9097, 0x09d4, 0x00000040);
227 nv_mthd(priv, 0x9097, 0x0818, 0x00000001);
228 nv_mthd(priv, 0x9097, 0x0858, 0x00000001);
229 nv_mthd(priv, 0x9097, 0x0898, 0x00000001);
230 nv_mthd(priv, 0x9097, 0x08d8, 0x00000001);
231 nv_mthd(priv, 0x9097, 0x0918, 0x00000001);
232 nv_mthd(priv, 0x9097, 0x0958, 0x00000001);
233 nv_mthd(priv, 0x9097, 0x0998, 0x00000001);
234 nv_mthd(priv, 0x9097, 0x09d8, 0x00000001);
235 nv_mthd(priv, 0x9097, 0x081c, 0x00000000);
236 nv_mthd(priv, 0x9097, 0x085c, 0x00000000);
237 nv_mthd(priv, 0x9097, 0x089c, 0x00000000);
238 nv_mthd(priv, 0x9097, 0x08dc, 0x00000000);
239 nv_mthd(priv, 0x9097, 0x091c, 0x00000000);
240 nv_mthd(priv, 0x9097, 0x095c, 0x00000000);
241 nv_mthd(priv, 0x9097, 0x099c, 0x00000000);
242 nv_mthd(priv, 0x9097, 0x09dc, 0x00000000);
243 nv_mthd(priv, 0x9097, 0x0820, 0x00000000);
244 nv_mthd(priv, 0x9097, 0x0860, 0x00000000);
245 nv_mthd(priv, 0x9097, 0x08a0, 0x00000000);
246 nv_mthd(priv, 0x9097, 0x08e0, 0x00000000);
247 nv_mthd(priv, 0x9097, 0x0920, 0x00000000);
248 nv_mthd(priv, 0x9097, 0x0960, 0x00000000);
249 nv_mthd(priv, 0x9097, 0x09a0, 0x00000000);
250 nv_mthd(priv, 0x9097, 0x09e0, 0x00000000);
251 nv_mthd(priv, 0x9097, 0x2700, 0x00000000);
252 nv_mthd(priv, 0x9097, 0x2720, 0x00000000);
253 nv_mthd(priv, 0x9097, 0x2740, 0x00000000);
254 nv_mthd(priv, 0x9097, 0x2760, 0x00000000);
255 nv_mthd(priv, 0x9097, 0x2780, 0x00000000);
256 nv_mthd(priv, 0x9097, 0x27a0, 0x00000000);
257 nv_mthd(priv, 0x9097, 0x27c0, 0x00000000);
258 nv_mthd(priv, 0x9097, 0x27e0, 0x00000000);
259 nv_mthd(priv, 0x9097, 0x2704, 0x00000000);
260 nv_mthd(priv, 0x9097, 0x2724, 0x00000000);
261 nv_mthd(priv, 0x9097, 0x2744, 0x00000000);
262 nv_mthd(priv, 0x9097, 0x2764, 0x00000000);
263 nv_mthd(priv, 0x9097, 0x2784, 0x00000000);
264 nv_mthd(priv, 0x9097, 0x27a4, 0x00000000);
265 nv_mthd(priv, 0x9097, 0x27c4, 0x00000000);
266 nv_mthd(priv, 0x9097, 0x27e4, 0x00000000);
267 nv_mthd(priv, 0x9097, 0x2708, 0x00000000);
268 nv_mthd(priv, 0x9097, 0x2728, 0x00000000);
269 nv_mthd(priv, 0x9097, 0x2748, 0x00000000);
270 nv_mthd(priv, 0x9097, 0x2768, 0x00000000);
271 nv_mthd(priv, 0x9097, 0x2788, 0x00000000);
272 nv_mthd(priv, 0x9097, 0x27a8, 0x00000000);
273 nv_mthd(priv, 0x9097, 0x27c8, 0x00000000);
274 nv_mthd(priv, 0x9097, 0x27e8, 0x00000000);
275 nv_mthd(priv, 0x9097, 0x270c, 0x00000000);
276 nv_mthd(priv, 0x9097, 0x272c, 0x00000000);
277 nv_mthd(priv, 0x9097, 0x274c, 0x00000000);
278 nv_mthd(priv, 0x9097, 0x276c, 0x00000000);
279 nv_mthd(priv, 0x9097, 0x278c, 0x00000000);
280 nv_mthd(priv, 0x9097, 0x27ac, 0x00000000);
281 nv_mthd(priv, 0x9097, 0x27cc, 0x00000000);
282 nv_mthd(priv, 0x9097, 0x27ec, 0x00000000);
283 nv_mthd(priv, 0x9097, 0x2710, 0x00014000);
284 nv_mthd(priv, 0x9097, 0x2730, 0x00014000);
285 nv_mthd(priv, 0x9097, 0x2750, 0x00014000);
286 nv_mthd(priv, 0x9097, 0x2770, 0x00014000);
287 nv_mthd(priv, 0x9097, 0x2790, 0x00014000);
288 nv_mthd(priv, 0x9097, 0x27b0, 0x00014000);
289 nv_mthd(priv, 0x9097, 0x27d0, 0x00014000);
290 nv_mthd(priv, 0x9097, 0x27f0, 0x00014000);
291 nv_mthd(priv, 0x9097, 0x2714, 0x00000040);
292 nv_mthd(priv, 0x9097, 0x2734, 0x00000040);
293 nv_mthd(priv, 0x9097, 0x2754, 0x00000040);
294 nv_mthd(priv, 0x9097, 0x2774, 0x00000040);
295 nv_mthd(priv, 0x9097, 0x2794, 0x00000040);
296 nv_mthd(priv, 0x9097, 0x27b4, 0x00000040);
297 nv_mthd(priv, 0x9097, 0x27d4, 0x00000040);
298 nv_mthd(priv, 0x9097, 0x27f4, 0x00000040);
299 nv_mthd(priv, 0x9097, 0x1c00, 0x00000000);
300 nv_mthd(priv, 0x9097, 0x1c10, 0x00000000);
301 nv_mthd(priv, 0x9097, 0x1c20, 0x00000000);
302 nv_mthd(priv, 0x9097, 0x1c30, 0x00000000);
303 nv_mthd(priv, 0x9097, 0x1c40, 0x00000000);
304 nv_mthd(priv, 0x9097, 0x1c50, 0x00000000);
305 nv_mthd(priv, 0x9097, 0x1c60, 0x00000000);
306 nv_mthd(priv, 0x9097, 0x1c70, 0x00000000);
307 nv_mthd(priv, 0x9097, 0x1c80, 0x00000000);
308 nv_mthd(priv, 0x9097, 0x1c90, 0x00000000);
309 nv_mthd(priv, 0x9097, 0x1ca0, 0x00000000);
310 nv_mthd(priv, 0x9097, 0x1cb0, 0x00000000);
311 nv_mthd(priv, 0x9097, 0x1cc0, 0x00000000);
312 nv_mthd(priv, 0x9097, 0x1cd0, 0x00000000);
313 nv_mthd(priv, 0x9097, 0x1ce0, 0x00000000);
314 nv_mthd(priv, 0x9097, 0x1cf0, 0x00000000);
315 nv_mthd(priv, 0x9097, 0x1c04, 0x00000000);
316 nv_mthd(priv, 0x9097, 0x1c14, 0x00000000);
317 nv_mthd(priv, 0x9097, 0x1c24, 0x00000000);
318 nv_mthd(priv, 0x9097, 0x1c34, 0x00000000);
319 nv_mthd(priv, 0x9097, 0x1c44, 0x00000000);
320 nv_mthd(priv, 0x9097, 0x1c54, 0x00000000);
321 nv_mthd(priv, 0x9097, 0x1c64, 0x00000000);
322 nv_mthd(priv, 0x9097, 0x1c74, 0x00000000);
323 nv_mthd(priv, 0x9097, 0x1c84, 0x00000000);
324 nv_mthd(priv, 0x9097, 0x1c94, 0x00000000);
325 nv_mthd(priv, 0x9097, 0x1ca4, 0x00000000);
326 nv_mthd(priv, 0x9097, 0x1cb4, 0x00000000);
327 nv_mthd(priv, 0x9097, 0x1cc4, 0x00000000);
328 nv_mthd(priv, 0x9097, 0x1cd4, 0x00000000);
329 nv_mthd(priv, 0x9097, 0x1ce4, 0x00000000);
330 nv_mthd(priv, 0x9097, 0x1cf4, 0x00000000);
331 nv_mthd(priv, 0x9097, 0x1c08, 0x00000000);
332 nv_mthd(priv, 0x9097, 0x1c18, 0x00000000);
333 nv_mthd(priv, 0x9097, 0x1c28, 0x00000000);
334 nv_mthd(priv, 0x9097, 0x1c38, 0x00000000);
335 nv_mthd(priv, 0x9097, 0x1c48, 0x00000000);
336 nv_mthd(priv, 0x9097, 0x1c58, 0x00000000);
337 nv_mthd(priv, 0x9097, 0x1c68, 0x00000000);
338 nv_mthd(priv, 0x9097, 0x1c78, 0x00000000);
339 nv_mthd(priv, 0x9097, 0x1c88, 0x00000000);
340 nv_mthd(priv, 0x9097, 0x1c98, 0x00000000);
341 nv_mthd(priv, 0x9097, 0x1ca8, 0x00000000);
342 nv_mthd(priv, 0x9097, 0x1cb8, 0x00000000);
343 nv_mthd(priv, 0x9097, 0x1cc8, 0x00000000);
344 nv_mthd(priv, 0x9097, 0x1cd8, 0x00000000);
345 nv_mthd(priv, 0x9097, 0x1ce8, 0x00000000);
346 nv_mthd(priv, 0x9097, 0x1cf8, 0x00000000);
347 nv_mthd(priv, 0x9097, 0x1c0c, 0x00000000);
348 nv_mthd(priv, 0x9097, 0x1c1c, 0x00000000);
349 nv_mthd(priv, 0x9097, 0x1c2c, 0x00000000);
350 nv_mthd(priv, 0x9097, 0x1c3c, 0x00000000);
351 nv_mthd(priv, 0x9097, 0x1c4c, 0x00000000);
352 nv_mthd(priv, 0x9097, 0x1c5c, 0x00000000);
353 nv_mthd(priv, 0x9097, 0x1c6c, 0x00000000);
354 nv_mthd(priv, 0x9097, 0x1c7c, 0x00000000);
355 nv_mthd(priv, 0x9097, 0x1c8c, 0x00000000);
356 nv_mthd(priv, 0x9097, 0x1c9c, 0x00000000);
357 nv_mthd(priv, 0x9097, 0x1cac, 0x00000000);
358 nv_mthd(priv, 0x9097, 0x1cbc, 0x00000000);
359 nv_mthd(priv, 0x9097, 0x1ccc, 0x00000000);
360 nv_mthd(priv, 0x9097, 0x1cdc, 0x00000000);
361 nv_mthd(priv, 0x9097, 0x1cec, 0x00000000);
362 nv_mthd(priv, 0x9097, 0x1cfc, 0x00000000);
363 nv_mthd(priv, 0x9097, 0x1d00, 0x00000000);
364 nv_mthd(priv, 0x9097, 0x1d10, 0x00000000);
365 nv_mthd(priv, 0x9097, 0x1d20, 0x00000000);
366 nv_mthd(priv, 0x9097, 0x1d30, 0x00000000);
367 nv_mthd(priv, 0x9097, 0x1d40, 0x00000000);
368 nv_mthd(priv, 0x9097, 0x1d50, 0x00000000);
369 nv_mthd(priv, 0x9097, 0x1d60, 0x00000000);
370 nv_mthd(priv, 0x9097, 0x1d70, 0x00000000);
371 nv_mthd(priv, 0x9097, 0x1d80, 0x00000000);
372 nv_mthd(priv, 0x9097, 0x1d90, 0x00000000);
373 nv_mthd(priv, 0x9097, 0x1da0, 0x00000000);
374 nv_mthd(priv, 0x9097, 0x1db0, 0x00000000);
375 nv_mthd(priv, 0x9097, 0x1dc0, 0x00000000);
376 nv_mthd(priv, 0x9097, 0x1dd0, 0x00000000);
377 nv_mthd(priv, 0x9097, 0x1de0, 0x00000000);
378 nv_mthd(priv, 0x9097, 0x1df0, 0x00000000);
379 nv_mthd(priv, 0x9097, 0x1d04, 0x00000000);
380 nv_mthd(priv, 0x9097, 0x1d14, 0x00000000);
381 nv_mthd(priv, 0x9097, 0x1d24, 0x00000000);
382 nv_mthd(priv, 0x9097, 0x1d34, 0x00000000);
383 nv_mthd(priv, 0x9097, 0x1d44, 0x00000000);
384 nv_mthd(priv, 0x9097, 0x1d54, 0x00000000);
385 nv_mthd(priv, 0x9097, 0x1d64, 0x00000000);
386 nv_mthd(priv, 0x9097, 0x1d74, 0x00000000);
387 nv_mthd(priv, 0x9097, 0x1d84, 0x00000000);
388 nv_mthd(priv, 0x9097, 0x1d94, 0x00000000);
389 nv_mthd(priv, 0x9097, 0x1da4, 0x00000000);
390 nv_mthd(priv, 0x9097, 0x1db4, 0x00000000);
391 nv_mthd(priv, 0x9097, 0x1dc4, 0x00000000);
392 nv_mthd(priv, 0x9097, 0x1dd4, 0x00000000);
393 nv_mthd(priv, 0x9097, 0x1de4, 0x00000000);
394 nv_mthd(priv, 0x9097, 0x1df4, 0x00000000);
395 nv_mthd(priv, 0x9097, 0x1d08, 0x00000000);
396 nv_mthd(priv, 0x9097, 0x1d18, 0x00000000);
397 nv_mthd(priv, 0x9097, 0x1d28, 0x00000000);
398 nv_mthd(priv, 0x9097, 0x1d38, 0x00000000);
399 nv_mthd(priv, 0x9097, 0x1d48, 0x00000000);
400 nv_mthd(priv, 0x9097, 0x1d58, 0x00000000);
401 nv_mthd(priv, 0x9097, 0x1d68, 0x00000000);
402 nv_mthd(priv, 0x9097, 0x1d78, 0x00000000);
403 nv_mthd(priv, 0x9097, 0x1d88, 0x00000000);
404 nv_mthd(priv, 0x9097, 0x1d98, 0x00000000);
405 nv_mthd(priv, 0x9097, 0x1da8, 0x00000000);
406 nv_mthd(priv, 0x9097, 0x1db8, 0x00000000);
407 nv_mthd(priv, 0x9097, 0x1dc8, 0x00000000);
408 nv_mthd(priv, 0x9097, 0x1dd8, 0x00000000);
409 nv_mthd(priv, 0x9097, 0x1de8, 0x00000000);
410 nv_mthd(priv, 0x9097, 0x1df8, 0x00000000);
411 nv_mthd(priv, 0x9097, 0x1d0c, 0x00000000);
412 nv_mthd(priv, 0x9097, 0x1d1c, 0x00000000);
413 nv_mthd(priv, 0x9097, 0x1d2c, 0x00000000);
414 nv_mthd(priv, 0x9097, 0x1d3c, 0x00000000);
415 nv_mthd(priv, 0x9097, 0x1d4c, 0x00000000);
416 nv_mthd(priv, 0x9097, 0x1d5c, 0x00000000);
417 nv_mthd(priv, 0x9097, 0x1d6c, 0x00000000);
418 nv_mthd(priv, 0x9097, 0x1d7c, 0x00000000);
419 nv_mthd(priv, 0x9097, 0x1d8c, 0x00000000);
420 nv_mthd(priv, 0x9097, 0x1d9c, 0x00000000);
421 nv_mthd(priv, 0x9097, 0x1dac, 0x00000000);
422 nv_mthd(priv, 0x9097, 0x1dbc, 0x00000000);
423 nv_mthd(priv, 0x9097, 0x1dcc, 0x00000000);
424 nv_mthd(priv, 0x9097, 0x1ddc, 0x00000000);
425 nv_mthd(priv, 0x9097, 0x1dec, 0x00000000);
426 nv_mthd(priv, 0x9097, 0x1dfc, 0x00000000);
427 nv_mthd(priv, 0x9097, 0x1f00, 0x00000000);
428 nv_mthd(priv, 0x9097, 0x1f08, 0x00000000);
429 nv_mthd(priv, 0x9097, 0x1f10, 0x00000000);
430 nv_mthd(priv, 0x9097, 0x1f18, 0x00000000);
431 nv_mthd(priv, 0x9097, 0x1f20, 0x00000000);
432 nv_mthd(priv, 0x9097, 0x1f28, 0x00000000);
433 nv_mthd(priv, 0x9097, 0x1f30, 0x00000000);
434 nv_mthd(priv, 0x9097, 0x1f38, 0x00000000);
435 nv_mthd(priv, 0x9097, 0x1f40, 0x00000000);
436 nv_mthd(priv, 0x9097, 0x1f48, 0x00000000);
437 nv_mthd(priv, 0x9097, 0x1f50, 0x00000000);
438 nv_mthd(priv, 0x9097, 0x1f58, 0x00000000);
439 nv_mthd(priv, 0x9097, 0x1f60, 0x00000000);
440 nv_mthd(priv, 0x9097, 0x1f68, 0x00000000);
441 nv_mthd(priv, 0x9097, 0x1f70, 0x00000000);
442 nv_mthd(priv, 0x9097, 0x1f78, 0x00000000);
443 nv_mthd(priv, 0x9097, 0x1f04, 0x00000000);
444 nv_mthd(priv, 0x9097, 0x1f0c, 0x00000000);
445 nv_mthd(priv, 0x9097, 0x1f14, 0x00000000);
446 nv_mthd(priv, 0x9097, 0x1f1c, 0x00000000);
447 nv_mthd(priv, 0x9097, 0x1f24, 0x00000000);
448 nv_mthd(priv, 0x9097, 0x1f2c, 0x00000000);
449 nv_mthd(priv, 0x9097, 0x1f34, 0x00000000);
450 nv_mthd(priv, 0x9097, 0x1f3c, 0x00000000);
451 nv_mthd(priv, 0x9097, 0x1f44, 0x00000000);
452 nv_mthd(priv, 0x9097, 0x1f4c, 0x00000000);
453 nv_mthd(priv, 0x9097, 0x1f54, 0x00000000);
454 nv_mthd(priv, 0x9097, 0x1f5c, 0x00000000);
455 nv_mthd(priv, 0x9097, 0x1f64, 0x00000000);
456 nv_mthd(priv, 0x9097, 0x1f6c, 0x00000000);
457 nv_mthd(priv, 0x9097, 0x1f74, 0x00000000);
458 nv_mthd(priv, 0x9097, 0x1f7c, 0x00000000);
459 nv_mthd(priv, 0x9097, 0x1f80, 0x00000000);
460 nv_mthd(priv, 0x9097, 0x1f88, 0x00000000);
461 nv_mthd(priv, 0x9097, 0x1f90, 0x00000000);
462 nv_mthd(priv, 0x9097, 0x1f98, 0x00000000);
463 nv_mthd(priv, 0x9097, 0x1fa0, 0x00000000);
464 nv_mthd(priv, 0x9097, 0x1fa8, 0x00000000);
465 nv_mthd(priv, 0x9097, 0x1fb0, 0x00000000);
466 nv_mthd(priv, 0x9097, 0x1fb8, 0x00000000);
467 nv_mthd(priv, 0x9097, 0x1fc0, 0x00000000);
468 nv_mthd(priv, 0x9097, 0x1fc8, 0x00000000);
469 nv_mthd(priv, 0x9097, 0x1fd0, 0x00000000);
470 nv_mthd(priv, 0x9097, 0x1fd8, 0x00000000);
471 nv_mthd(priv, 0x9097, 0x1fe0, 0x00000000);
472 nv_mthd(priv, 0x9097, 0x1fe8, 0x00000000);
473 nv_mthd(priv, 0x9097, 0x1ff0, 0x00000000);
474 nv_mthd(priv, 0x9097, 0x1ff8, 0x00000000);
475 nv_mthd(priv, 0x9097, 0x1f84, 0x00000000);
476 nv_mthd(priv, 0x9097, 0x1f8c, 0x00000000);
477 nv_mthd(priv, 0x9097, 0x1f94, 0x00000000);
478 nv_mthd(priv, 0x9097, 0x1f9c, 0x00000000);
479 nv_mthd(priv, 0x9097, 0x1fa4, 0x00000000);
480 nv_mthd(priv, 0x9097, 0x1fac, 0x00000000);
481 nv_mthd(priv, 0x9097, 0x1fb4, 0x00000000);
482 nv_mthd(priv, 0x9097, 0x1fbc, 0x00000000);
483 nv_mthd(priv, 0x9097, 0x1fc4, 0x00000000);
484 nv_mthd(priv, 0x9097, 0x1fcc, 0x00000000);
485 nv_mthd(priv, 0x9097, 0x1fd4, 0x00000000);
486 nv_mthd(priv, 0x9097, 0x1fdc, 0x00000000);
487 nv_mthd(priv, 0x9097, 0x1fe4, 0x00000000);
488 nv_mthd(priv, 0x9097, 0x1fec, 0x00000000);
489 nv_mthd(priv, 0x9097, 0x1ff4, 0x00000000);
490 nv_mthd(priv, 0x9097, 0x1ffc, 0x00000000);
491 nv_mthd(priv, 0x9097, 0x2200, 0x00000022);
492 nv_mthd(priv, 0x9097, 0x2210, 0x00000022);
493 nv_mthd(priv, 0x9097, 0x2220, 0x00000022);
494 nv_mthd(priv, 0x9097, 0x2230, 0x00000022);
495 nv_mthd(priv, 0x9097, 0x2240, 0x00000022);
496 nv_mthd(priv, 0x9097, 0x2000, 0x00000000);
497 nv_mthd(priv, 0x9097, 0x2040, 0x00000011);
498 nv_mthd(priv, 0x9097, 0x2080, 0x00000020);
499 nv_mthd(priv, 0x9097, 0x20c0, 0x00000030);
500 nv_mthd(priv, 0x9097, 0x2100, 0x00000040);
501 nv_mthd(priv, 0x9097, 0x2140, 0x00000051);
502 nv_mthd(priv, 0x9097, 0x200c, 0x00000001);
503 nv_mthd(priv, 0x9097, 0x204c, 0x00000001);
504 nv_mthd(priv, 0x9097, 0x208c, 0x00000001);
505 nv_mthd(priv, 0x9097, 0x20cc, 0x00000001);
506 nv_mthd(priv, 0x9097, 0x210c, 0x00000001);
507 nv_mthd(priv, 0x9097, 0x214c, 0x00000001);
508 nv_mthd(priv, 0x9097, 0x2010, 0x00000000);
509 nv_mthd(priv, 0x9097, 0x2050, 0x00000000);
510 nv_mthd(priv, 0x9097, 0x2090, 0x00000001);
511 nv_mthd(priv, 0x9097, 0x20d0, 0x00000002);
512 nv_mthd(priv, 0x9097, 0x2110, 0x00000003);
513 nv_mthd(priv, 0x9097, 0x2150, 0x00000004);
514 nv_mthd(priv, 0x9097, 0x0380, 0x00000000);
515 nv_mthd(priv, 0x9097, 0x03a0, 0x00000000);
516 nv_mthd(priv, 0x9097, 0x03c0, 0x00000000);
517 nv_mthd(priv, 0x9097, 0x03e0, 0x00000000);
518 nv_mthd(priv, 0x9097, 0x0384, 0x00000000);
519 nv_mthd(priv, 0x9097, 0x03a4, 0x00000000);
520 nv_mthd(priv, 0x9097, 0x03c4, 0x00000000);
521 nv_mthd(priv, 0x9097, 0x03e4, 0x00000000);
522 nv_mthd(priv, 0x9097, 0x0388, 0x00000000);
523 nv_mthd(priv, 0x9097, 0x03a8, 0x00000000);
524 nv_mthd(priv, 0x9097, 0x03c8, 0x00000000);
525 nv_mthd(priv, 0x9097, 0x03e8, 0x00000000);
526 nv_mthd(priv, 0x9097, 0x038c, 0x00000000);
527 nv_mthd(priv, 0x9097, 0x03ac, 0x00000000);
528 nv_mthd(priv, 0x9097, 0x03cc, 0x00000000);
529 nv_mthd(priv, 0x9097, 0x03ec, 0x00000000);
530 nv_mthd(priv, 0x9097, 0x0700, 0x00000000);
531 nv_mthd(priv, 0x9097, 0x0710, 0x00000000);
532 nv_mthd(priv, 0x9097, 0x0720, 0x00000000);
533 nv_mthd(priv, 0x9097, 0x0730, 0x00000000);
534 nv_mthd(priv, 0x9097, 0x0704, 0x00000000);
535 nv_mthd(priv, 0x9097, 0x0714, 0x00000000);
536 nv_mthd(priv, 0x9097, 0x0724, 0x00000000);
537 nv_mthd(priv, 0x9097, 0x0734, 0x00000000);
538 nv_mthd(priv, 0x9097, 0x0708, 0x00000000);
539 nv_mthd(priv, 0x9097, 0x0718, 0x00000000);
540 nv_mthd(priv, 0x9097, 0x0728, 0x00000000);
541 nv_mthd(priv, 0x9097, 0x0738, 0x00000000);
542 nv_mthd(priv, 0x9097, 0x2800, 0x00000000);
543 nv_mthd(priv, 0x9097, 0x2804, 0x00000000);
544 nv_mthd(priv, 0x9097, 0x2808, 0x00000000);
545 nv_mthd(priv, 0x9097, 0x280c, 0x00000000);
546 nv_mthd(priv, 0x9097, 0x2810, 0x00000000);
547 nv_mthd(priv, 0x9097, 0x2814, 0x00000000);
548 nv_mthd(priv, 0x9097, 0x2818, 0x00000000);
549 nv_mthd(priv, 0x9097, 0x281c, 0x00000000);
550 nv_mthd(priv, 0x9097, 0x2820, 0x00000000);
551 nv_mthd(priv, 0x9097, 0x2824, 0x00000000);
552 nv_mthd(priv, 0x9097, 0x2828, 0x00000000);
553 nv_mthd(priv, 0x9097, 0x282c, 0x00000000);
554 nv_mthd(priv, 0x9097, 0x2830, 0x00000000);
555 nv_mthd(priv, 0x9097, 0x2834, 0x00000000);
556 nv_mthd(priv, 0x9097, 0x2838, 0x00000000);
557 nv_mthd(priv, 0x9097, 0x283c, 0x00000000);
558 nv_mthd(priv, 0x9097, 0x2840, 0x00000000);
559 nv_mthd(priv, 0x9097, 0x2844, 0x00000000);
560 nv_mthd(priv, 0x9097, 0x2848, 0x00000000);
561 nv_mthd(priv, 0x9097, 0x284c, 0x00000000);
562 nv_mthd(priv, 0x9097, 0x2850, 0x00000000);
563 nv_mthd(priv, 0x9097, 0x2854, 0x00000000);
564 nv_mthd(priv, 0x9097, 0x2858, 0x00000000);
565 nv_mthd(priv, 0x9097, 0x285c, 0x00000000);
566 nv_mthd(priv, 0x9097, 0x2860, 0x00000000);
567 nv_mthd(priv, 0x9097, 0x2864, 0x00000000);
568 nv_mthd(priv, 0x9097, 0x2868, 0x00000000);
569 nv_mthd(priv, 0x9097, 0x286c, 0x00000000);
570 nv_mthd(priv, 0x9097, 0x2870, 0x00000000);
571 nv_mthd(priv, 0x9097, 0x2874, 0x00000000);
572 nv_mthd(priv, 0x9097, 0x2878, 0x00000000);
573 nv_mthd(priv, 0x9097, 0x287c, 0x00000000);
574 nv_mthd(priv, 0x9097, 0x2880, 0x00000000);
575 nv_mthd(priv, 0x9097, 0x2884, 0x00000000);
576 nv_mthd(priv, 0x9097, 0x2888, 0x00000000);
577 nv_mthd(priv, 0x9097, 0x288c, 0x00000000);
578 nv_mthd(priv, 0x9097, 0x2890, 0x00000000);
579 nv_mthd(priv, 0x9097, 0x2894, 0x00000000);
580 nv_mthd(priv, 0x9097, 0x2898, 0x00000000);
581 nv_mthd(priv, 0x9097, 0x289c, 0x00000000);
582 nv_mthd(priv, 0x9097, 0x28a0, 0x00000000);
583 nv_mthd(priv, 0x9097, 0x28a4, 0x00000000);
584 nv_mthd(priv, 0x9097, 0x28a8, 0x00000000);
585 nv_mthd(priv, 0x9097, 0x28ac, 0x00000000);
586 nv_mthd(priv, 0x9097, 0x28b0, 0x00000000);
587 nv_mthd(priv, 0x9097, 0x28b4, 0x00000000);
588 nv_mthd(priv, 0x9097, 0x28b8, 0x00000000);
589 nv_mthd(priv, 0x9097, 0x28bc, 0x00000000);
590 nv_mthd(priv, 0x9097, 0x28c0, 0x00000000);
591 nv_mthd(priv, 0x9097, 0x28c4, 0x00000000);
592 nv_mthd(priv, 0x9097, 0x28c8, 0x00000000);
593 nv_mthd(priv, 0x9097, 0x28cc, 0x00000000);
594 nv_mthd(priv, 0x9097, 0x28d0, 0x00000000);
595 nv_mthd(priv, 0x9097, 0x28d4, 0x00000000);
596 nv_mthd(priv, 0x9097, 0x28d8, 0x00000000);
597 nv_mthd(priv, 0x9097, 0x28dc, 0x00000000);
598 nv_mthd(priv, 0x9097, 0x28e0, 0x00000000);
599 nv_mthd(priv, 0x9097, 0x28e4, 0x00000000);
600 nv_mthd(priv, 0x9097, 0x28e8, 0x00000000);
601 nv_mthd(priv, 0x9097, 0x28ec, 0x00000000);
602 nv_mthd(priv, 0x9097, 0x28f0, 0x00000000);
603 nv_mthd(priv, 0x9097, 0x28f4, 0x00000000);
604 nv_mthd(priv, 0x9097, 0x28f8, 0x00000000);
605 nv_mthd(priv, 0x9097, 0x28fc, 0x00000000);
606 nv_mthd(priv, 0x9097, 0x2900, 0x00000000);
607 nv_mthd(priv, 0x9097, 0x2904, 0x00000000);
608 nv_mthd(priv, 0x9097, 0x2908, 0x00000000);
609 nv_mthd(priv, 0x9097, 0x290c, 0x00000000);
610 nv_mthd(priv, 0x9097, 0x2910, 0x00000000);
611 nv_mthd(priv, 0x9097, 0x2914, 0x00000000);
612 nv_mthd(priv, 0x9097, 0x2918, 0x00000000);
613 nv_mthd(priv, 0x9097, 0x291c, 0x00000000);
614 nv_mthd(priv, 0x9097, 0x2920, 0x00000000);
615 nv_mthd(priv, 0x9097, 0x2924, 0x00000000);
616 nv_mthd(priv, 0x9097, 0x2928, 0x00000000);
617 nv_mthd(priv, 0x9097, 0x292c, 0x00000000);
618 nv_mthd(priv, 0x9097, 0x2930, 0x00000000);
619 nv_mthd(priv, 0x9097, 0x2934, 0x00000000);
620 nv_mthd(priv, 0x9097, 0x2938, 0x00000000);
621 nv_mthd(priv, 0x9097, 0x293c, 0x00000000);
622 nv_mthd(priv, 0x9097, 0x2940, 0x00000000);
623 nv_mthd(priv, 0x9097, 0x2944, 0x00000000);
624 nv_mthd(priv, 0x9097, 0x2948, 0x00000000);
625 nv_mthd(priv, 0x9097, 0x294c, 0x00000000);
626 nv_mthd(priv, 0x9097, 0x2950, 0x00000000);
627 nv_mthd(priv, 0x9097, 0x2954, 0x00000000);
628 nv_mthd(priv, 0x9097, 0x2958, 0x00000000);
629 nv_mthd(priv, 0x9097, 0x295c, 0x00000000);
630 nv_mthd(priv, 0x9097, 0x2960, 0x00000000);
631 nv_mthd(priv, 0x9097, 0x2964, 0x00000000);
632 nv_mthd(priv, 0x9097, 0x2968, 0x00000000);
633 nv_mthd(priv, 0x9097, 0x296c, 0x00000000);
634 nv_mthd(priv, 0x9097, 0x2970, 0x00000000);
635 nv_mthd(priv, 0x9097, 0x2974, 0x00000000);
636 nv_mthd(priv, 0x9097, 0x2978, 0x00000000);
637 nv_mthd(priv, 0x9097, 0x297c, 0x00000000);
638 nv_mthd(priv, 0x9097, 0x2980, 0x00000000);
639 nv_mthd(priv, 0x9097, 0x2984, 0x00000000);
640 nv_mthd(priv, 0x9097, 0x2988, 0x00000000);
641 nv_mthd(priv, 0x9097, 0x298c, 0x00000000);
642 nv_mthd(priv, 0x9097, 0x2990, 0x00000000);
643 nv_mthd(priv, 0x9097, 0x2994, 0x00000000);
644 nv_mthd(priv, 0x9097, 0x2998, 0x00000000);
645 nv_mthd(priv, 0x9097, 0x299c, 0x00000000);
646 nv_mthd(priv, 0x9097, 0x29a0, 0x00000000);
647 nv_mthd(priv, 0x9097, 0x29a4, 0x00000000);
648 nv_mthd(priv, 0x9097, 0x29a8, 0x00000000);
649 nv_mthd(priv, 0x9097, 0x29ac, 0x00000000);
650 nv_mthd(priv, 0x9097, 0x29b0, 0x00000000);
651 nv_mthd(priv, 0x9097, 0x29b4, 0x00000000);
652 nv_mthd(priv, 0x9097, 0x29b8, 0x00000000);
653 nv_mthd(priv, 0x9097, 0x29bc, 0x00000000);
654 nv_mthd(priv, 0x9097, 0x29c0, 0x00000000);
655 nv_mthd(priv, 0x9097, 0x29c4, 0x00000000);
656 nv_mthd(priv, 0x9097, 0x29c8, 0x00000000);
657 nv_mthd(priv, 0x9097, 0x29cc, 0x00000000);
658 nv_mthd(priv, 0x9097, 0x29d0, 0x00000000);
659 nv_mthd(priv, 0x9097, 0x29d4, 0x00000000);
660 nv_mthd(priv, 0x9097, 0x29d8, 0x00000000);
661 nv_mthd(priv, 0x9097, 0x29dc, 0x00000000);
662 nv_mthd(priv, 0x9097, 0x29e0, 0x00000000);
663 nv_mthd(priv, 0x9097, 0x29e4, 0x00000000);
664 nv_mthd(priv, 0x9097, 0x29e8, 0x00000000);
665 nv_mthd(priv, 0x9097, 0x29ec, 0x00000000);
666 nv_mthd(priv, 0x9097, 0x29f0, 0x00000000);
667 nv_mthd(priv, 0x9097, 0x29f4, 0x00000000);
668 nv_mthd(priv, 0x9097, 0x29f8, 0x00000000);
669 nv_mthd(priv, 0x9097, 0x29fc, 0x00000000);
670 nv_mthd(priv, 0x9097, 0x0a00, 0x00000000);
671 nv_mthd(priv, 0x9097, 0x0a20, 0x00000000);
672 nv_mthd(priv, 0x9097, 0x0a40, 0x00000000);
673 nv_mthd(priv, 0x9097, 0x0a60, 0x00000000);
674 nv_mthd(priv, 0x9097, 0x0a80, 0x00000000);
675 nv_mthd(priv, 0x9097, 0x0aa0, 0x00000000);
676 nv_mthd(priv, 0x9097, 0x0ac0, 0x00000000);
677 nv_mthd(priv, 0x9097, 0x0ae0, 0x00000000);
678 nv_mthd(priv, 0x9097, 0x0b00, 0x00000000);
679 nv_mthd(priv, 0x9097, 0x0b20, 0x00000000);
680 nv_mthd(priv, 0x9097, 0x0b40, 0x00000000);
681 nv_mthd(priv, 0x9097, 0x0b60, 0x00000000);
682 nv_mthd(priv, 0x9097, 0x0b80, 0x00000000);
683 nv_mthd(priv, 0x9097, 0x0ba0, 0x00000000);
684 nv_mthd(priv, 0x9097, 0x0bc0, 0x00000000);
685 nv_mthd(priv, 0x9097, 0x0be0, 0x00000000);
686 nv_mthd(priv, 0x9097, 0x0a04, 0x00000000);
687 nv_mthd(priv, 0x9097, 0x0a24, 0x00000000);
688 nv_mthd(priv, 0x9097, 0x0a44, 0x00000000);
689 nv_mthd(priv, 0x9097, 0x0a64, 0x00000000);
690 nv_mthd(priv, 0x9097, 0x0a84, 0x00000000);
691 nv_mthd(priv, 0x9097, 0x0aa4, 0x00000000);
692 nv_mthd(priv, 0x9097, 0x0ac4, 0x00000000);
693 nv_mthd(priv, 0x9097, 0x0ae4, 0x00000000);
694 nv_mthd(priv, 0x9097, 0x0b04, 0x00000000);
695 nv_mthd(priv, 0x9097, 0x0b24, 0x00000000);
696 nv_mthd(priv, 0x9097, 0x0b44, 0x00000000);
697 nv_mthd(priv, 0x9097, 0x0b64, 0x00000000);
698 nv_mthd(priv, 0x9097, 0x0b84, 0x00000000);
699 nv_mthd(priv, 0x9097, 0x0ba4, 0x00000000);
700 nv_mthd(priv, 0x9097, 0x0bc4, 0x00000000);
701 nv_mthd(priv, 0x9097, 0x0be4, 0x00000000);
702 nv_mthd(priv, 0x9097, 0x0a08, 0x00000000);
703 nv_mthd(priv, 0x9097, 0x0a28, 0x00000000);
704 nv_mthd(priv, 0x9097, 0x0a48, 0x00000000);
705 nv_mthd(priv, 0x9097, 0x0a68, 0x00000000);
706 nv_mthd(priv, 0x9097, 0x0a88, 0x00000000);
707 nv_mthd(priv, 0x9097, 0x0aa8, 0x00000000);
708 nv_mthd(priv, 0x9097, 0x0ac8, 0x00000000);
709 nv_mthd(priv, 0x9097, 0x0ae8, 0x00000000);
710 nv_mthd(priv, 0x9097, 0x0b08, 0x00000000);
711 nv_mthd(priv, 0x9097, 0x0b28, 0x00000000);
712 nv_mthd(priv, 0x9097, 0x0b48, 0x00000000);
713 nv_mthd(priv, 0x9097, 0x0b68, 0x00000000);
714 nv_mthd(priv, 0x9097, 0x0b88, 0x00000000);
715 nv_mthd(priv, 0x9097, 0x0ba8, 0x00000000);
716 nv_mthd(priv, 0x9097, 0x0bc8, 0x00000000);
717 nv_mthd(priv, 0x9097, 0x0be8, 0x00000000);
718 nv_mthd(priv, 0x9097, 0x0a0c, 0x00000000);
719 nv_mthd(priv, 0x9097, 0x0a2c, 0x00000000);
720 nv_mthd(priv, 0x9097, 0x0a4c, 0x00000000);
721 nv_mthd(priv, 0x9097, 0x0a6c, 0x00000000);
722 nv_mthd(priv, 0x9097, 0x0a8c, 0x00000000);
723 nv_mthd(priv, 0x9097, 0x0aac, 0x00000000);
724 nv_mthd(priv, 0x9097, 0x0acc, 0x00000000);
725 nv_mthd(priv, 0x9097, 0x0aec, 0x00000000);
726 nv_mthd(priv, 0x9097, 0x0b0c, 0x00000000);
727 nv_mthd(priv, 0x9097, 0x0b2c, 0x00000000);
728 nv_mthd(priv, 0x9097, 0x0b4c, 0x00000000);
729 nv_mthd(priv, 0x9097, 0x0b6c, 0x00000000);
730 nv_mthd(priv, 0x9097, 0x0b8c, 0x00000000);
731 nv_mthd(priv, 0x9097, 0x0bac, 0x00000000);
732 nv_mthd(priv, 0x9097, 0x0bcc, 0x00000000);
733 nv_mthd(priv, 0x9097, 0x0bec, 0x00000000);
734 nv_mthd(priv, 0x9097, 0x0a10, 0x00000000);
735 nv_mthd(priv, 0x9097, 0x0a30, 0x00000000);
736 nv_mthd(priv, 0x9097, 0x0a50, 0x00000000);
737 nv_mthd(priv, 0x9097, 0x0a70, 0x00000000);
738 nv_mthd(priv, 0x9097, 0x0a90, 0x00000000);
739 nv_mthd(priv, 0x9097, 0x0ab0, 0x00000000);
740 nv_mthd(priv, 0x9097, 0x0ad0, 0x00000000);
741 nv_mthd(priv, 0x9097, 0x0af0, 0x00000000);
742 nv_mthd(priv, 0x9097, 0x0b10, 0x00000000);
743 nv_mthd(priv, 0x9097, 0x0b30, 0x00000000);
744 nv_mthd(priv, 0x9097, 0x0b50, 0x00000000);
745 nv_mthd(priv, 0x9097, 0x0b70, 0x00000000);
746 nv_mthd(priv, 0x9097, 0x0b90, 0x00000000);
747 nv_mthd(priv, 0x9097, 0x0bb0, 0x00000000);
748 nv_mthd(priv, 0x9097, 0x0bd0, 0x00000000);
749 nv_mthd(priv, 0x9097, 0x0bf0, 0x00000000);
750 nv_mthd(priv, 0x9097, 0x0a14, 0x00000000);
751 nv_mthd(priv, 0x9097, 0x0a34, 0x00000000);
752 nv_mthd(priv, 0x9097, 0x0a54, 0x00000000);
753 nv_mthd(priv, 0x9097, 0x0a74, 0x00000000);
754 nv_mthd(priv, 0x9097, 0x0a94, 0x00000000);
755 nv_mthd(priv, 0x9097, 0x0ab4, 0x00000000);
756 nv_mthd(priv, 0x9097, 0x0ad4, 0x00000000);
757 nv_mthd(priv, 0x9097, 0x0af4, 0x00000000);
758 nv_mthd(priv, 0x9097, 0x0b14, 0x00000000);
759 nv_mthd(priv, 0x9097, 0x0b34, 0x00000000);
760 nv_mthd(priv, 0x9097, 0x0b54, 0x00000000);
761 nv_mthd(priv, 0x9097, 0x0b74, 0x00000000);
762 nv_mthd(priv, 0x9097, 0x0b94, 0x00000000);
763 nv_mthd(priv, 0x9097, 0x0bb4, 0x00000000);
764 nv_mthd(priv, 0x9097, 0x0bd4, 0x00000000);
765 nv_mthd(priv, 0x9097, 0x0bf4, 0x00000000);
766 nv_mthd(priv, 0x9097, 0x0c00, 0x00000000);
767 nv_mthd(priv, 0x9097, 0x0c10, 0x00000000);
768 nv_mthd(priv, 0x9097, 0x0c20, 0x00000000);
769 nv_mthd(priv, 0x9097, 0x0c30, 0x00000000);
770 nv_mthd(priv, 0x9097, 0x0c40, 0x00000000);
771 nv_mthd(priv, 0x9097, 0x0c50, 0x00000000);
772 nv_mthd(priv, 0x9097, 0x0c60, 0x00000000);
773 nv_mthd(priv, 0x9097, 0x0c70, 0x00000000);
774 nv_mthd(priv, 0x9097, 0x0c80, 0x00000000);
775 nv_mthd(priv, 0x9097, 0x0c90, 0x00000000);
776 nv_mthd(priv, 0x9097, 0x0ca0, 0x00000000);
777 nv_mthd(priv, 0x9097, 0x0cb0, 0x00000000);
778 nv_mthd(priv, 0x9097, 0x0cc0, 0x00000000);
779 nv_mthd(priv, 0x9097, 0x0cd0, 0x00000000);
780 nv_mthd(priv, 0x9097, 0x0ce0, 0x00000000);
781 nv_mthd(priv, 0x9097, 0x0cf0, 0x00000000);
782 nv_mthd(priv, 0x9097, 0x0c04, 0x00000000);
783 nv_mthd(priv, 0x9097, 0x0c14, 0x00000000);
784 nv_mthd(priv, 0x9097, 0x0c24, 0x00000000);
785 nv_mthd(priv, 0x9097, 0x0c34, 0x00000000);
786 nv_mthd(priv, 0x9097, 0x0c44, 0x00000000);
787 nv_mthd(priv, 0x9097, 0x0c54, 0x00000000);
788 nv_mthd(priv, 0x9097, 0x0c64, 0x00000000);
789 nv_mthd(priv, 0x9097, 0x0c74, 0x00000000);
790 nv_mthd(priv, 0x9097, 0x0c84, 0x00000000);
791 nv_mthd(priv, 0x9097, 0x0c94, 0x00000000);
792 nv_mthd(priv, 0x9097, 0x0ca4, 0x00000000);
793 nv_mthd(priv, 0x9097, 0x0cb4, 0x00000000);
794 nv_mthd(priv, 0x9097, 0x0cc4, 0x00000000);
795 nv_mthd(priv, 0x9097, 0x0cd4, 0x00000000);
796 nv_mthd(priv, 0x9097, 0x0ce4, 0x00000000);
797 nv_mthd(priv, 0x9097, 0x0cf4, 0x00000000);
798 nv_mthd(priv, 0x9097, 0x0c08, 0x00000000);
799 nv_mthd(priv, 0x9097, 0x0c18, 0x00000000);
800 nv_mthd(priv, 0x9097, 0x0c28, 0x00000000);
801 nv_mthd(priv, 0x9097, 0x0c38, 0x00000000);
802 nv_mthd(priv, 0x9097, 0x0c48, 0x00000000);
803 nv_mthd(priv, 0x9097, 0x0c58, 0x00000000);
804 nv_mthd(priv, 0x9097, 0x0c68, 0x00000000);
805 nv_mthd(priv, 0x9097, 0x0c78, 0x00000000);
806 nv_mthd(priv, 0x9097, 0x0c88, 0x00000000);
807 nv_mthd(priv, 0x9097, 0x0c98, 0x00000000);
808 nv_mthd(priv, 0x9097, 0x0ca8, 0x00000000);
809 nv_mthd(priv, 0x9097, 0x0cb8, 0x00000000);
810 nv_mthd(priv, 0x9097, 0x0cc8, 0x00000000);
811 nv_mthd(priv, 0x9097, 0x0cd8, 0x00000000);
812 nv_mthd(priv, 0x9097, 0x0ce8, 0x00000000);
813 nv_mthd(priv, 0x9097, 0x0cf8, 0x00000000);
814 nv_mthd(priv, 0x9097, 0x0c0c, 0x3f800000);
815 nv_mthd(priv, 0x9097, 0x0c1c, 0x3f800000);
816 nv_mthd(priv, 0x9097, 0x0c2c, 0x3f800000);
817 nv_mthd(priv, 0x9097, 0x0c3c, 0x3f800000);
818 nv_mthd(priv, 0x9097, 0x0c4c, 0x3f800000);
819 nv_mthd(priv, 0x9097, 0x0c5c, 0x3f800000);
820 nv_mthd(priv, 0x9097, 0x0c6c, 0x3f800000);
821 nv_mthd(priv, 0x9097, 0x0c7c, 0x3f800000);
822 nv_mthd(priv, 0x9097, 0x0c8c, 0x3f800000);
823 nv_mthd(priv, 0x9097, 0x0c9c, 0x3f800000);
824 nv_mthd(priv, 0x9097, 0x0cac, 0x3f800000);
825 nv_mthd(priv, 0x9097, 0x0cbc, 0x3f800000);
826 nv_mthd(priv, 0x9097, 0x0ccc, 0x3f800000);
827 nv_mthd(priv, 0x9097, 0x0cdc, 0x3f800000);
828 nv_mthd(priv, 0x9097, 0x0cec, 0x3f800000);
829 nv_mthd(priv, 0x9097, 0x0cfc, 0x3f800000);
830 nv_mthd(priv, 0x9097, 0x0d00, 0xffff0000);
831 nv_mthd(priv, 0x9097, 0x0d08, 0xffff0000);
832 nv_mthd(priv, 0x9097, 0x0d10, 0xffff0000);
833 nv_mthd(priv, 0x9097, 0x0d18, 0xffff0000);
834 nv_mthd(priv, 0x9097, 0x0d20, 0xffff0000);
835 nv_mthd(priv, 0x9097, 0x0d28, 0xffff0000);
836 nv_mthd(priv, 0x9097, 0x0d30, 0xffff0000);
837 nv_mthd(priv, 0x9097, 0x0d38, 0xffff0000);
838 nv_mthd(priv, 0x9097, 0x0d04, 0xffff0000);
839 nv_mthd(priv, 0x9097, 0x0d0c, 0xffff0000);
840 nv_mthd(priv, 0x9097, 0x0d14, 0xffff0000);
841 nv_mthd(priv, 0x9097, 0x0d1c, 0xffff0000);
842 nv_mthd(priv, 0x9097, 0x0d24, 0xffff0000);
843 nv_mthd(priv, 0x9097, 0x0d2c, 0xffff0000);
844 nv_mthd(priv, 0x9097, 0x0d34, 0xffff0000);
845 nv_mthd(priv, 0x9097, 0x0d3c, 0xffff0000);
846 nv_mthd(priv, 0x9097, 0x0e00, 0x00000000);
847 nv_mthd(priv, 0x9097, 0x0e10, 0x00000000);
848 nv_mthd(priv, 0x9097, 0x0e20, 0x00000000);
849 nv_mthd(priv, 0x9097, 0x0e30, 0x00000000);
850 nv_mthd(priv, 0x9097, 0x0e40, 0x00000000);
851 nv_mthd(priv, 0x9097, 0x0e50, 0x00000000);
852 nv_mthd(priv, 0x9097, 0x0e60, 0x00000000);
853 nv_mthd(priv, 0x9097, 0x0e70, 0x00000000);
854 nv_mthd(priv, 0x9097, 0x0e80, 0x00000000);
855 nv_mthd(priv, 0x9097, 0x0e90, 0x00000000);
856 nv_mthd(priv, 0x9097, 0x0ea0, 0x00000000);
857 nv_mthd(priv, 0x9097, 0x0eb0, 0x00000000);
858 nv_mthd(priv, 0x9097, 0x0ec0, 0x00000000);
859 nv_mthd(priv, 0x9097, 0x0ed0, 0x00000000);
860 nv_mthd(priv, 0x9097, 0x0ee0, 0x00000000);
861 nv_mthd(priv, 0x9097, 0x0ef0, 0x00000000);
862 nv_mthd(priv, 0x9097, 0x0e04, 0xffff0000);
863 nv_mthd(priv, 0x9097, 0x0e14, 0xffff0000);
864 nv_mthd(priv, 0x9097, 0x0e24, 0xffff0000);
865 nv_mthd(priv, 0x9097, 0x0e34, 0xffff0000);
866 nv_mthd(priv, 0x9097, 0x0e44, 0xffff0000);
867 nv_mthd(priv, 0x9097, 0x0e54, 0xffff0000);
868 nv_mthd(priv, 0x9097, 0x0e64, 0xffff0000);
869 nv_mthd(priv, 0x9097, 0x0e74, 0xffff0000);
870 nv_mthd(priv, 0x9097, 0x0e84, 0xffff0000);
871 nv_mthd(priv, 0x9097, 0x0e94, 0xffff0000);
872 nv_mthd(priv, 0x9097, 0x0ea4, 0xffff0000);
873 nv_mthd(priv, 0x9097, 0x0eb4, 0xffff0000);
874 nv_mthd(priv, 0x9097, 0x0ec4, 0xffff0000);
875 nv_mthd(priv, 0x9097, 0x0ed4, 0xffff0000);
876 nv_mthd(priv, 0x9097, 0x0ee4, 0xffff0000);
877 nv_mthd(priv, 0x9097, 0x0ef4, 0xffff0000);
878 nv_mthd(priv, 0x9097, 0x0e08, 0xffff0000);
879 nv_mthd(priv, 0x9097, 0x0e18, 0xffff0000);
880 nv_mthd(priv, 0x9097, 0x0e28, 0xffff0000);
881 nv_mthd(priv, 0x9097, 0x0e38, 0xffff0000);
882 nv_mthd(priv, 0x9097, 0x0e48, 0xffff0000);
883 nv_mthd(priv, 0x9097, 0x0e58, 0xffff0000);
884 nv_mthd(priv, 0x9097, 0x0e68, 0xffff0000);
885 nv_mthd(priv, 0x9097, 0x0e78, 0xffff0000);
886 nv_mthd(priv, 0x9097, 0x0e88, 0xffff0000);
887 nv_mthd(priv, 0x9097, 0x0e98, 0xffff0000);
888 nv_mthd(priv, 0x9097, 0x0ea8, 0xffff0000);
889 nv_mthd(priv, 0x9097, 0x0eb8, 0xffff0000);
890 nv_mthd(priv, 0x9097, 0x0ec8, 0xffff0000);
891 nv_mthd(priv, 0x9097, 0x0ed8, 0xffff0000);
892 nv_mthd(priv, 0x9097, 0x0ee8, 0xffff0000);
893 nv_mthd(priv, 0x9097, 0x0ef8, 0xffff0000);
894 nv_mthd(priv, 0x9097, 0x0d40, 0x00000000);
895 nv_mthd(priv, 0x9097, 0x0d48, 0x00000000);
896 nv_mthd(priv, 0x9097, 0x0d50, 0x00000000);
897 nv_mthd(priv, 0x9097, 0x0d58, 0x00000000);
898 nv_mthd(priv, 0x9097, 0x0d44, 0x00000000);
899 nv_mthd(priv, 0x9097, 0x0d4c, 0x00000000);
900 nv_mthd(priv, 0x9097, 0x0d54, 0x00000000);
901 nv_mthd(priv, 0x9097, 0x0d5c, 0x00000000);
902 nv_mthd(priv, 0x9097, 0x1e00, 0x00000001);
903 nv_mthd(priv, 0x9097, 0x1e20, 0x00000001);
904 nv_mthd(priv, 0x9097, 0x1e40, 0x00000001);
905 nv_mthd(priv, 0x9097, 0x1e60, 0x00000001);
906 nv_mthd(priv, 0x9097, 0x1e80, 0x00000001);
907 nv_mthd(priv, 0x9097, 0x1ea0, 0x00000001);
908 nv_mthd(priv, 0x9097, 0x1ec0, 0x00000001);
909 nv_mthd(priv, 0x9097, 0x1ee0, 0x00000001);
910 nv_mthd(priv, 0x9097, 0x1e04, 0x00000001);
911 nv_mthd(priv, 0x9097, 0x1e24, 0x00000001);
912 nv_mthd(priv, 0x9097, 0x1e44, 0x00000001);
913 nv_mthd(priv, 0x9097, 0x1e64, 0x00000001);
914 nv_mthd(priv, 0x9097, 0x1e84, 0x00000001);
915 nv_mthd(priv, 0x9097, 0x1ea4, 0x00000001);
916 nv_mthd(priv, 0x9097, 0x1ec4, 0x00000001);
917 nv_mthd(priv, 0x9097, 0x1ee4, 0x00000001);
918 nv_mthd(priv, 0x9097, 0x1e08, 0x00000002);
919 nv_mthd(priv, 0x9097, 0x1e28, 0x00000002);
920 nv_mthd(priv, 0x9097, 0x1e48, 0x00000002);
921 nv_mthd(priv, 0x9097, 0x1e68, 0x00000002);
922 nv_mthd(priv, 0x9097, 0x1e88, 0x00000002);
923 nv_mthd(priv, 0x9097, 0x1ea8, 0x00000002);
924 nv_mthd(priv, 0x9097, 0x1ec8, 0x00000002);
925 nv_mthd(priv, 0x9097, 0x1ee8, 0x00000002);
926 nv_mthd(priv, 0x9097, 0x1e0c, 0x00000001);
927 nv_mthd(priv, 0x9097, 0x1e2c, 0x00000001);
928 nv_mthd(priv, 0x9097, 0x1e4c, 0x00000001);
929 nv_mthd(priv, 0x9097, 0x1e6c, 0x00000001);
930 nv_mthd(priv, 0x9097, 0x1e8c, 0x00000001);
931 nv_mthd(priv, 0x9097, 0x1eac, 0x00000001);
932 nv_mthd(priv, 0x9097, 0x1ecc, 0x00000001);
933 nv_mthd(priv, 0x9097, 0x1eec, 0x00000001);
934 nv_mthd(priv, 0x9097, 0x1e10, 0x00000001);
935 nv_mthd(priv, 0x9097, 0x1e30, 0x00000001);
936 nv_mthd(priv, 0x9097, 0x1e50, 0x00000001);
937 nv_mthd(priv, 0x9097, 0x1e70, 0x00000001);
938 nv_mthd(priv, 0x9097, 0x1e90, 0x00000001);
939 nv_mthd(priv, 0x9097, 0x1eb0, 0x00000001);
940 nv_mthd(priv, 0x9097, 0x1ed0, 0x00000001);
941 nv_mthd(priv, 0x9097, 0x1ef0, 0x00000001);
942 nv_mthd(priv, 0x9097, 0x1e14, 0x00000002);
943 nv_mthd(priv, 0x9097, 0x1e34, 0x00000002);
944 nv_mthd(priv, 0x9097, 0x1e54, 0x00000002);
945 nv_mthd(priv, 0x9097, 0x1e74, 0x00000002);
946 nv_mthd(priv, 0x9097, 0x1e94, 0x00000002);
947 nv_mthd(priv, 0x9097, 0x1eb4, 0x00000002);
948 nv_mthd(priv, 0x9097, 0x1ed4, 0x00000002);
949 nv_mthd(priv, 0x9097, 0x1ef4, 0x00000002);
950 nv_mthd(priv, 0x9097, 0x1e18, 0x00000001);
951 nv_mthd(priv, 0x9097, 0x1e38, 0x00000001);
952 nv_mthd(priv, 0x9097, 0x1e58, 0x00000001);
953 nv_mthd(priv, 0x9097, 0x1e78, 0x00000001);
954 nv_mthd(priv, 0x9097, 0x1e98, 0x00000001);
955 nv_mthd(priv, 0x9097, 0x1eb8, 0x00000001);
956 nv_mthd(priv, 0x9097, 0x1ed8, 0x00000001);
957 nv_mthd(priv, 0x9097, 0x1ef8, 0x00000001);
958 if (fermi == 0x9097) {
959 for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4)
960 nv_mthd(priv, 0x9097, mthd, 0x00000000);
961 } 926 }
962 nv_mthd(priv, 0x9097, 0x030c, 0x00000001);
963 nv_mthd(priv, 0x9097, 0x1944, 0x00000000);
964 nv_mthd(priv, 0x9097, 0x1514, 0x00000000);
965 nv_mthd(priv, 0x9097, 0x0d68, 0x0000ffff);
966 nv_mthd(priv, 0x9097, 0x121c, 0x0fac6881);
967 nv_mthd(priv, 0x9097, 0x0fac, 0x00000001);
968 nv_mthd(priv, 0x9097, 0x1538, 0x00000001);
969 nv_mthd(priv, 0x9097, 0x0fe0, 0x00000000);
970 nv_mthd(priv, 0x9097, 0x0fe4, 0x00000000);
971 nv_mthd(priv, 0x9097, 0x0fe8, 0x00000014);
972 nv_mthd(priv, 0x9097, 0x0fec, 0x00000040);
973 nv_mthd(priv, 0x9097, 0x0ff0, 0x00000000);
974 nv_mthd(priv, 0x9097, 0x179c, 0x00000000);
975 nv_mthd(priv, 0x9097, 0x1228, 0x00000400);
976 nv_mthd(priv, 0x9097, 0x122c, 0x00000300);
977 nv_mthd(priv, 0x9097, 0x1230, 0x00010001);
978 nv_mthd(priv, 0x9097, 0x07f8, 0x00000000);
979 nv_mthd(priv, 0x9097, 0x15b4, 0x00000001);
980 nv_mthd(priv, 0x9097, 0x15cc, 0x00000000);
981 nv_mthd(priv, 0x9097, 0x1534, 0x00000000);
982 nv_mthd(priv, 0x9097, 0x0fb0, 0x00000000);
983 nv_mthd(priv, 0x9097, 0x15d0, 0x00000000);
984 nv_mthd(priv, 0x9097, 0x153c, 0x00000000);
985 nv_mthd(priv, 0x9097, 0x16b4, 0x00000003);
986 nv_mthd(priv, 0x9097, 0x0fbc, 0x0000ffff);
987 nv_mthd(priv, 0x9097, 0x0fc0, 0x0000ffff);
988 nv_mthd(priv, 0x9097, 0x0fc4, 0x0000ffff);
989 nv_mthd(priv, 0x9097, 0x0fc8, 0x0000ffff);
990 nv_mthd(priv, 0x9097, 0x0df8, 0x00000000);
991 nv_mthd(priv, 0x9097, 0x0dfc, 0x00000000);
992 nv_mthd(priv, 0x9097, 0x1948, 0x00000000);
993 nv_mthd(priv, 0x9097, 0x1970, 0x00000001);
994 nv_mthd(priv, 0x9097, 0x161c, 0x000009f0);
995 nv_mthd(priv, 0x9097, 0x0dcc, 0x00000010);
996 nv_mthd(priv, 0x9097, 0x163c, 0x00000000);
997 nv_mthd(priv, 0x9097, 0x15e4, 0x00000000);
998 nv_mthd(priv, 0x9097, 0x1160, 0x25e00040);
999 nv_mthd(priv, 0x9097, 0x1164, 0x25e00040);
1000 nv_mthd(priv, 0x9097, 0x1168, 0x25e00040);
1001 nv_mthd(priv, 0x9097, 0x116c, 0x25e00040);
1002 nv_mthd(priv, 0x9097, 0x1170, 0x25e00040);
1003 nv_mthd(priv, 0x9097, 0x1174, 0x25e00040);
1004 nv_mthd(priv, 0x9097, 0x1178, 0x25e00040);
1005 nv_mthd(priv, 0x9097, 0x117c, 0x25e00040);
1006 nv_mthd(priv, 0x9097, 0x1180, 0x25e00040);
1007 nv_mthd(priv, 0x9097, 0x1184, 0x25e00040);
1008 nv_mthd(priv, 0x9097, 0x1188, 0x25e00040);
1009 nv_mthd(priv, 0x9097, 0x118c, 0x25e00040);
1010 nv_mthd(priv, 0x9097, 0x1190, 0x25e00040);
1011 nv_mthd(priv, 0x9097, 0x1194, 0x25e00040);
1012 nv_mthd(priv, 0x9097, 0x1198, 0x25e00040);
1013 nv_mthd(priv, 0x9097, 0x119c, 0x25e00040);
1014 nv_mthd(priv, 0x9097, 0x11a0, 0x25e00040);
1015 nv_mthd(priv, 0x9097, 0x11a4, 0x25e00040);
1016 nv_mthd(priv, 0x9097, 0x11a8, 0x25e00040);
1017 nv_mthd(priv, 0x9097, 0x11ac, 0x25e00040);
1018 nv_mthd(priv, 0x9097, 0x11b0, 0x25e00040);
1019 nv_mthd(priv, 0x9097, 0x11b4, 0x25e00040);
1020 nv_mthd(priv, 0x9097, 0x11b8, 0x25e00040);
1021 nv_mthd(priv, 0x9097, 0x11bc, 0x25e00040);
1022 nv_mthd(priv, 0x9097, 0x11c0, 0x25e00040);
1023 nv_mthd(priv, 0x9097, 0x11c4, 0x25e00040);
1024 nv_mthd(priv, 0x9097, 0x11c8, 0x25e00040);
1025 nv_mthd(priv, 0x9097, 0x11cc, 0x25e00040);
1026 nv_mthd(priv, 0x9097, 0x11d0, 0x25e00040);
1027 nv_mthd(priv, 0x9097, 0x11d4, 0x25e00040);
1028 nv_mthd(priv, 0x9097, 0x11d8, 0x25e00040);
1029 nv_mthd(priv, 0x9097, 0x11dc, 0x25e00040);
1030 nv_mthd(priv, 0x9097, 0x1880, 0x00000000);
1031 nv_mthd(priv, 0x9097, 0x1884, 0x00000000);
1032 nv_mthd(priv, 0x9097, 0x1888, 0x00000000);
1033 nv_mthd(priv, 0x9097, 0x188c, 0x00000000);
1034 nv_mthd(priv, 0x9097, 0x1890, 0x00000000);
1035 nv_mthd(priv, 0x9097, 0x1894, 0x00000000);
1036 nv_mthd(priv, 0x9097, 0x1898, 0x00000000);
1037 nv_mthd(priv, 0x9097, 0x189c, 0x00000000);
1038 nv_mthd(priv, 0x9097, 0x18a0, 0x00000000);
1039 nv_mthd(priv, 0x9097, 0x18a4, 0x00000000);
1040 nv_mthd(priv, 0x9097, 0x18a8, 0x00000000);
1041 nv_mthd(priv, 0x9097, 0x18ac, 0x00000000);
1042 nv_mthd(priv, 0x9097, 0x18b0, 0x00000000);
1043 nv_mthd(priv, 0x9097, 0x18b4, 0x00000000);
1044 nv_mthd(priv, 0x9097, 0x18b8, 0x00000000);
1045 nv_mthd(priv, 0x9097, 0x18bc, 0x00000000);
1046 nv_mthd(priv, 0x9097, 0x18c0, 0x00000000);
1047 nv_mthd(priv, 0x9097, 0x18c4, 0x00000000);
1048 nv_mthd(priv, 0x9097, 0x18c8, 0x00000000);
1049 nv_mthd(priv, 0x9097, 0x18cc, 0x00000000);
1050 nv_mthd(priv, 0x9097, 0x18d0, 0x00000000);
1051 nv_mthd(priv, 0x9097, 0x18d4, 0x00000000);
1052 nv_mthd(priv, 0x9097, 0x18d8, 0x00000000);
1053 nv_mthd(priv, 0x9097, 0x18dc, 0x00000000);
1054 nv_mthd(priv, 0x9097, 0x18e0, 0x00000000);
1055 nv_mthd(priv, 0x9097, 0x18e4, 0x00000000);
1056 nv_mthd(priv, 0x9097, 0x18e8, 0x00000000);
1057 nv_mthd(priv, 0x9097, 0x18ec, 0x00000000);
1058 nv_mthd(priv, 0x9097, 0x18f0, 0x00000000);
1059 nv_mthd(priv, 0x9097, 0x18f4, 0x00000000);
1060 nv_mthd(priv, 0x9097, 0x18f8, 0x00000000);
1061 nv_mthd(priv, 0x9097, 0x18fc, 0x00000000);
1062 nv_mthd(priv, 0x9097, 0x0f84, 0x00000000);
1063 nv_mthd(priv, 0x9097, 0x0f88, 0x00000000);
1064 nv_mthd(priv, 0x9097, 0x17c8, 0x00000000);
1065 nv_mthd(priv, 0x9097, 0x17cc, 0x00000000);
1066 nv_mthd(priv, 0x9097, 0x17d0, 0x000000ff);
1067 nv_mthd(priv, 0x9097, 0x17d4, 0xffffffff);
1068 nv_mthd(priv, 0x9097, 0x17d8, 0x00000002);
1069 nv_mthd(priv, 0x9097, 0x17dc, 0x00000000);
1070 nv_mthd(priv, 0x9097, 0x15f4, 0x00000000);
1071 nv_mthd(priv, 0x9097, 0x15f8, 0x00000000);
1072 nv_mthd(priv, 0x9097, 0x1434, 0x00000000);
1073 nv_mthd(priv, 0x9097, 0x1438, 0x00000000);
1074 nv_mthd(priv, 0x9097, 0x0d74, 0x00000000);
1075 nv_mthd(priv, 0x9097, 0x0dec, 0x00000001);
1076 nv_mthd(priv, 0x9097, 0x13a4, 0x00000000);
1077 nv_mthd(priv, 0x9097, 0x1318, 0x00000001);
1078 nv_mthd(priv, 0x9097, 0x1644, 0x00000000);
1079 nv_mthd(priv, 0x9097, 0x0748, 0x00000000);
1080 nv_mthd(priv, 0x9097, 0x0de8, 0x00000000);
1081 nv_mthd(priv, 0x9097, 0x1648, 0x00000000);
1082 nv_mthd(priv, 0x9097, 0x12a4, 0x00000000);
1083 nv_mthd(priv, 0x9097, 0x1120, 0x00000000);
1084 nv_mthd(priv, 0x9097, 0x1124, 0x00000000);
1085 nv_mthd(priv, 0x9097, 0x1128, 0x00000000);
1086 nv_mthd(priv, 0x9097, 0x112c, 0x00000000);
1087 nv_mthd(priv, 0x9097, 0x1118, 0x00000000);
1088 nv_mthd(priv, 0x9097, 0x164c, 0x00000000);
1089 nv_mthd(priv, 0x9097, 0x1658, 0x00000000);
1090 nv_mthd(priv, 0x9097, 0x1910, 0x00000290);
1091 nv_mthd(priv, 0x9097, 0x1518, 0x00000000);
1092 nv_mthd(priv, 0x9097, 0x165c, 0x00000001);
1093 nv_mthd(priv, 0x9097, 0x1520, 0x00000000);
1094 nv_mthd(priv, 0x9097, 0x1604, 0x00000000);
1095 nv_mthd(priv, 0x9097, 0x1570, 0x00000000);
1096 nv_mthd(priv, 0x9097, 0x13b0, 0x3f800000);
1097 nv_mthd(priv, 0x9097, 0x13b4, 0x3f800000);
1098 nv_mthd(priv, 0x9097, 0x020c, 0x00000000);
1099 nv_mthd(priv, 0x9097, 0x1670, 0x30201000);
1100 nv_mthd(priv, 0x9097, 0x1674, 0x70605040);
1101 nv_mthd(priv, 0x9097, 0x1678, 0xb8a89888);
1102 nv_mthd(priv, 0x9097, 0x167c, 0xf8e8d8c8);
1103 nv_mthd(priv, 0x9097, 0x166c, 0x00000000);
1104 nv_mthd(priv, 0x9097, 0x1680, 0x00ffff00);
1105 nv_mthd(priv, 0x9097, 0x12d0, 0x00000003);
1106 nv_mthd(priv, 0x9097, 0x12d4, 0x00000002);
1107 nv_mthd(priv, 0x9097, 0x1684, 0x00000000);
1108 nv_mthd(priv, 0x9097, 0x1688, 0x00000000);
1109 nv_mthd(priv, 0x9097, 0x0dac, 0x00001b02);
1110 nv_mthd(priv, 0x9097, 0x0db0, 0x00001b02);
1111 nv_mthd(priv, 0x9097, 0x0db4, 0x00000000);
1112 nv_mthd(priv, 0x9097, 0x168c, 0x00000000);
1113 nv_mthd(priv, 0x9097, 0x15bc, 0x00000000);
1114 nv_mthd(priv, 0x9097, 0x156c, 0x00000000);
1115 nv_mthd(priv, 0x9097, 0x187c, 0x00000000);
1116 nv_mthd(priv, 0x9097, 0x1110, 0x00000001);
1117 nv_mthd(priv, 0x9097, 0x0dc0, 0x00000000);
1118 nv_mthd(priv, 0x9097, 0x0dc4, 0x00000000);
1119 nv_mthd(priv, 0x9097, 0x0dc8, 0x00000000);
1120 nv_mthd(priv, 0x9097, 0x1234, 0x00000000);
1121 nv_mthd(priv, 0x9097, 0x1690, 0x00000000);
1122 nv_mthd(priv, 0x9097, 0x12ac, 0x00000001);
1123 nv_mthd(priv, 0x9097, 0x02c4, 0x00000000);
1124 nv_mthd(priv, 0x9097, 0x0790, 0x00000000);
1125 nv_mthd(priv, 0x9097, 0x0794, 0x00000000);
1126 nv_mthd(priv, 0x9097, 0x0798, 0x00000000);
1127 nv_mthd(priv, 0x9097, 0x079c, 0x00000000);
1128 nv_mthd(priv, 0x9097, 0x07a0, 0x00000000);
1129 nv_mthd(priv, 0x9097, 0x077c, 0x00000000);
1130 nv_mthd(priv, 0x9097, 0x1000, 0x00000010);
1131 nv_mthd(priv, 0x9097, 0x10fc, 0x00000000);
1132 nv_mthd(priv, 0x9097, 0x1290, 0x00000000);
1133 nv_mthd(priv, 0x9097, 0x0218, 0x00000010);
1134 nv_mthd(priv, 0x9097, 0x12d8, 0x00000000);
1135 nv_mthd(priv, 0x9097, 0x12dc, 0x00000010);
1136 nv_mthd(priv, 0x9097, 0x0d94, 0x00000001);
1137 nv_mthd(priv, 0x9097, 0x155c, 0x00000000);
1138 nv_mthd(priv, 0x9097, 0x1560, 0x00000000);
1139 nv_mthd(priv, 0x9097, 0x1564, 0x00001fff);
1140 nv_mthd(priv, 0x9097, 0x1574, 0x00000000);
1141 nv_mthd(priv, 0x9097, 0x1578, 0x00000000);
1142 nv_mthd(priv, 0x9097, 0x157c, 0x003fffff);
1143 nv_mthd(priv, 0x9097, 0x1354, 0x00000000);
1144 nv_mthd(priv, 0x9097, 0x1664, 0x00000000);
1145 nv_mthd(priv, 0x9097, 0x1610, 0x00000012);
1146 nv_mthd(priv, 0x9097, 0x1608, 0x00000000);
1147 nv_mthd(priv, 0x9097, 0x160c, 0x00000000);
1148 nv_mthd(priv, 0x9097, 0x162c, 0x00000003);
1149 nv_mthd(priv, 0x9097, 0x0210, 0x00000000);
1150 nv_mthd(priv, 0x9097, 0x0320, 0x00000000);
1151 nv_mthd(priv, 0x9097, 0x0324, 0x3f800000);
1152 nv_mthd(priv, 0x9097, 0x0328, 0x3f800000);
1153 nv_mthd(priv, 0x9097, 0x032c, 0x3f800000);
1154 nv_mthd(priv, 0x9097, 0x0330, 0x3f800000);
1155 nv_mthd(priv, 0x9097, 0x0334, 0x3f800000);
1156 nv_mthd(priv, 0x9097, 0x0338, 0x3f800000);
1157 nv_mthd(priv, 0x9097, 0x0750, 0x00000000);
1158 nv_mthd(priv, 0x9097, 0x0760, 0x39291909);
1159 nv_mthd(priv, 0x9097, 0x0764, 0x79695949);
1160 nv_mthd(priv, 0x9097, 0x0768, 0xb9a99989);
1161 nv_mthd(priv, 0x9097, 0x076c, 0xf9e9d9c9);
1162 nv_mthd(priv, 0x9097, 0x0770, 0x30201000);
1163 nv_mthd(priv, 0x9097, 0x0774, 0x70605040);
1164 nv_mthd(priv, 0x9097, 0x0778, 0x00009080);
1165 nv_mthd(priv, 0x9097, 0x0780, 0x39291909);
1166 nv_mthd(priv, 0x9097, 0x0784, 0x79695949);
1167 nv_mthd(priv, 0x9097, 0x0788, 0xb9a99989);
1168 nv_mthd(priv, 0x9097, 0x078c, 0xf9e9d9c9);
1169 nv_mthd(priv, 0x9097, 0x07d0, 0x30201000);
1170 nv_mthd(priv, 0x9097, 0x07d4, 0x70605040);
1171 nv_mthd(priv, 0x9097, 0x07d8, 0x00009080);
1172 nv_mthd(priv, 0x9097, 0x037c, 0x00000001);
1173 nv_mthd(priv, 0x9097, 0x0740, 0x00000000);
1174 nv_mthd(priv, 0x9097, 0x0744, 0x00000000);
1175 nv_mthd(priv, 0x9097, 0x2600, 0x00000000);
1176 nv_mthd(priv, 0x9097, 0x1918, 0x00000000);
1177 nv_mthd(priv, 0x9097, 0x191c, 0x00000900);
1178 nv_mthd(priv, 0x9097, 0x1920, 0x00000405);
1179 nv_mthd(priv, 0x9097, 0x1308, 0x00000001);
1180 nv_mthd(priv, 0x9097, 0x1924, 0x00000000);
1181 nv_mthd(priv, 0x9097, 0x13ac, 0x00000000);
1182 nv_mthd(priv, 0x9097, 0x192c, 0x00000001);
1183 nv_mthd(priv, 0x9097, 0x193c, 0x00002c1c);
1184 nv_mthd(priv, 0x9097, 0x0d7c, 0x00000000);
1185 nv_mthd(priv, 0x9097, 0x0f8c, 0x00000000);
1186 nv_mthd(priv, 0x9097, 0x02c0, 0x00000001);
1187 nv_mthd(priv, 0x9097, 0x1510, 0x00000000);
1188 nv_mthd(priv, 0x9097, 0x1940, 0x00000000);
1189 nv_mthd(priv, 0x9097, 0x0ff4, 0x00000000);
1190 nv_mthd(priv, 0x9097, 0x0ff8, 0x00000000);
1191 nv_mthd(priv, 0x9097, 0x194c, 0x00000000);
1192 nv_mthd(priv, 0x9097, 0x1950, 0x00000000);
1193 nv_mthd(priv, 0x9097, 0x1968, 0x00000000);
1194 nv_mthd(priv, 0x9097, 0x1590, 0x0000003f);
1195 nv_mthd(priv, 0x9097, 0x07e8, 0x00000000);
1196 nv_mthd(priv, 0x9097, 0x07ec, 0x00000000);
1197 nv_mthd(priv, 0x9097, 0x07f0, 0x00000000);
1198 nv_mthd(priv, 0x9097, 0x07f4, 0x00000000);
1199 nv_mthd(priv, 0x9097, 0x196c, 0x00000011);
1200 nv_mthd(priv, 0x9097, 0x197c, 0x00000000);
1201 nv_mthd(priv, 0x9097, 0x0fcc, 0x00000000);
1202 nv_mthd(priv, 0x9097, 0x0fd0, 0x00000000);
1203 nv_mthd(priv, 0x9097, 0x02d8, 0x00000040);
1204 nv_mthd(priv, 0x9097, 0x1980, 0x00000080);
1205 nv_mthd(priv, 0x9097, 0x1504, 0x00000080);
1206 nv_mthd(priv, 0x9097, 0x1984, 0x00000000);
1207 nv_mthd(priv, 0x9097, 0x0300, 0x00000001);
1208 nv_mthd(priv, 0x9097, 0x13a8, 0x00000000);
1209 nv_mthd(priv, 0x9097, 0x12ec, 0x00000000);
1210 nv_mthd(priv, 0x9097, 0x1310, 0x00000000);
1211 nv_mthd(priv, 0x9097, 0x1314, 0x00000001);
1212 nv_mthd(priv, 0x9097, 0x1380, 0x00000000);
1213 nv_mthd(priv, 0x9097, 0x1384, 0x00000001);
1214 nv_mthd(priv, 0x9097, 0x1388, 0x00000001);
1215 nv_mthd(priv, 0x9097, 0x138c, 0x00000001);
1216 nv_mthd(priv, 0x9097, 0x1390, 0x00000001);
1217 nv_mthd(priv, 0x9097, 0x1394, 0x00000000);
1218 nv_mthd(priv, 0x9097, 0x139c, 0x00000000);
1219 nv_mthd(priv, 0x9097, 0x1398, 0x00000000);
1220 nv_mthd(priv, 0x9097, 0x1594, 0x00000000);
1221 nv_mthd(priv, 0x9097, 0x1598, 0x00000001);
1222 nv_mthd(priv, 0x9097, 0x159c, 0x00000001);
1223 nv_mthd(priv, 0x9097, 0x15a0, 0x00000001);
1224 nv_mthd(priv, 0x9097, 0x15a4, 0x00000001);
1225 nv_mthd(priv, 0x9097, 0x0f54, 0x00000000);
1226 nv_mthd(priv, 0x9097, 0x0f58, 0x00000000);
1227 nv_mthd(priv, 0x9097, 0x0f5c, 0x00000000);
1228 nv_mthd(priv, 0x9097, 0x19bc, 0x00000000);
1229 nv_mthd(priv, 0x9097, 0x0f9c, 0x00000000);
1230 nv_mthd(priv, 0x9097, 0x0fa0, 0x00000000);
1231 nv_mthd(priv, 0x9097, 0x12cc, 0x00000000);
1232 nv_mthd(priv, 0x9097, 0x12e8, 0x00000000);
1233 nv_mthd(priv, 0x9097, 0x130c, 0x00000001);
1234 nv_mthd(priv, 0x9097, 0x1360, 0x00000000);
1235 nv_mthd(priv, 0x9097, 0x1364, 0x00000000);
1236 nv_mthd(priv, 0x9097, 0x1368, 0x00000000);
1237 nv_mthd(priv, 0x9097, 0x136c, 0x00000000);
1238 nv_mthd(priv, 0x9097, 0x1370, 0x00000000);
1239 nv_mthd(priv, 0x9097, 0x1374, 0x00000000);
1240 nv_mthd(priv, 0x9097, 0x1378, 0x00000000);
1241 nv_mthd(priv, 0x9097, 0x137c, 0x00000000);
1242 nv_mthd(priv, 0x9097, 0x133c, 0x00000001);
1243 nv_mthd(priv, 0x9097, 0x1340, 0x00000001);
1244 nv_mthd(priv, 0x9097, 0x1344, 0x00000002);
1245 nv_mthd(priv, 0x9097, 0x1348, 0x00000001);
1246 nv_mthd(priv, 0x9097, 0x134c, 0x00000001);
1247 nv_mthd(priv, 0x9097, 0x1350, 0x00000002);
1248 nv_mthd(priv, 0x9097, 0x1358, 0x00000001);
1249 nv_mthd(priv, 0x9097, 0x12e4, 0x00000000);
1250 nv_mthd(priv, 0x9097, 0x131c, 0x00000000);
1251 nv_mthd(priv, 0x9097, 0x1320, 0x00000000);
1252 nv_mthd(priv, 0x9097, 0x1324, 0x00000000);
1253 nv_mthd(priv, 0x9097, 0x1328, 0x00000000);
1254 nv_mthd(priv, 0x9097, 0x19c0, 0x00000000);
1255 nv_mthd(priv, 0x9097, 0x1140, 0x00000000);
1256 nv_mthd(priv, 0x9097, 0x19c4, 0x00000000);
1257 nv_mthd(priv, 0x9097, 0x19c8, 0x00001500);
1258 nv_mthd(priv, 0x9097, 0x135c, 0x00000000);
1259 nv_mthd(priv, 0x9097, 0x0f90, 0x00000000);
1260 nv_mthd(priv, 0x9097, 0x19e0, 0x00000001);
1261 nv_mthd(priv, 0x9097, 0x19e4, 0x00000001);
1262 nv_mthd(priv, 0x9097, 0x19e8, 0x00000001);
1263 nv_mthd(priv, 0x9097, 0x19ec, 0x00000001);
1264 nv_mthd(priv, 0x9097, 0x19f0, 0x00000001);
1265 nv_mthd(priv, 0x9097, 0x19f4, 0x00000001);
1266 nv_mthd(priv, 0x9097, 0x19f8, 0x00000001);
1267 nv_mthd(priv, 0x9097, 0x19fc, 0x00000001);
1268 nv_mthd(priv, 0x9097, 0x19cc, 0x00000001);
1269 nv_mthd(priv, 0x9097, 0x15b8, 0x00000000);
1270 nv_mthd(priv, 0x9097, 0x1a00, 0x00001111);
1271 nv_mthd(priv, 0x9097, 0x1a04, 0x00000000);
1272 nv_mthd(priv, 0x9097, 0x1a08, 0x00000000);
1273 nv_mthd(priv, 0x9097, 0x1a0c, 0x00000000);
1274 nv_mthd(priv, 0x9097, 0x1a10, 0x00000000);
1275 nv_mthd(priv, 0x9097, 0x1a14, 0x00000000);
1276 nv_mthd(priv, 0x9097, 0x1a18, 0x00000000);
1277 nv_mthd(priv, 0x9097, 0x1a1c, 0x00000000);
1278 nv_mthd(priv, 0x9097, 0x0d6c, 0xffff0000);
1279 nv_mthd(priv, 0x9097, 0x0d70, 0xffff0000);
1280 nv_mthd(priv, 0x9097, 0x10f8, 0x00001010);
1281 nv_mthd(priv, 0x9097, 0x0d80, 0x00000000);
1282 nv_mthd(priv, 0x9097, 0x0d84, 0x00000000);
1283 nv_mthd(priv, 0x9097, 0x0d88, 0x00000000);
1284 nv_mthd(priv, 0x9097, 0x0d8c, 0x00000000);
1285 nv_mthd(priv, 0x9097, 0x0d90, 0x00000000);
1286 nv_mthd(priv, 0x9097, 0x0da0, 0x00000000);
1287 nv_mthd(priv, 0x9097, 0x1508, 0x80000000);
1288 nv_mthd(priv, 0x9097, 0x150c, 0x40000000);
1289 nv_mthd(priv, 0x9097, 0x1668, 0x00000000);
1290 nv_mthd(priv, 0x9097, 0x0318, 0x00000008);
1291 nv_mthd(priv, 0x9097, 0x031c, 0x00000008);
1292 nv_mthd(priv, 0x9097, 0x0d9c, 0x00000001);
1293 nv_mthd(priv, 0x9097, 0x07dc, 0x00000000);
1294 nv_mthd(priv, 0x9097, 0x074c, 0x00000055);
1295 nv_mthd(priv, 0x9097, 0x1420, 0x00000003);
1296 nv_mthd(priv, 0x9097, 0x17bc, 0x00000000);
1297 nv_mthd(priv, 0x9097, 0x17c0, 0x00000000);
1298 nv_mthd(priv, 0x9097, 0x17c4, 0x00000001);
1299 nv_mthd(priv, 0x9097, 0x1008, 0x00000008);
1300 nv_mthd(priv, 0x9097, 0x100c, 0x00000040);
1301 nv_mthd(priv, 0x9097, 0x1010, 0x0000012c);
1302 nv_mthd(priv, 0x9097, 0x0d60, 0x00000040);
1303 nv_mthd(priv, 0x9097, 0x075c, 0x00000003);
1304 nv_mthd(priv, 0x9097, 0x1018, 0x00000020);
1305 nv_mthd(priv, 0x9097, 0x101c, 0x00000001);
1306 nv_mthd(priv, 0x9097, 0x1020, 0x00000020);
1307 nv_mthd(priv, 0x9097, 0x1024, 0x00000001);
1308 nv_mthd(priv, 0x9097, 0x1444, 0x00000000);
1309 nv_mthd(priv, 0x9097, 0x1448, 0x00000000);
1310 nv_mthd(priv, 0x9097, 0x144c, 0x00000000);
1311 nv_mthd(priv, 0x9097, 0x0360, 0x20164010);
1312 nv_mthd(priv, 0x9097, 0x0364, 0x00000020);
1313 nv_mthd(priv, 0x9097, 0x0368, 0x00000000);
1314 nv_mthd(priv, 0x9097, 0x0de4, 0x00000000);
1315 nv_mthd(priv, 0x9097, 0x0204, 0x00000006);
1316 nv_mthd(priv, 0x9097, 0x0208, 0x00000000);
1317 nv_mthd(priv, 0x9097, 0x02cc, 0x003fffff);
1318 nv_mthd(priv, 0x9097, 0x02d0, 0x00000c48);
1319 nv_mthd(priv, 0x9097, 0x1220, 0x00000005);
1320 nv_mthd(priv, 0x9097, 0x0fdc, 0x00000000);
1321 nv_mthd(priv, 0x9097, 0x0f98, 0x00300008);
1322 nv_mthd(priv, 0x9097, 0x1284, 0x04000080);
1323 nv_mthd(priv, 0x9097, 0x1450, 0x00300008);
1324 nv_mthd(priv, 0x9097, 0x1454, 0x04000080);
1325 nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
1326} 927}
1327 928
1328static void 929void
1329nvc0_grctx_generate_9197(struct nvc0_graph_priv *priv) 930nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
1330{ 931{
1331 u32 fermi = nvc0_graph_class(priv); 932 u32 tmp[GPC_MAX / 8] = {}, i = 0;
1332 u32 mthd; 933 for (i = 0; i < priv->gpc_nr; i++)
1333 934 tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4);
1334 if (fermi == 0x9197) { 935 for (i = 0; i < 4; i++) {
1335 for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4) 936 nv_wr32(priv, 0x406028 + (i * 4), tmp[i]);
1336 nv_mthd(priv, 0x9197, mthd, 0x00000000); 937 nv_wr32(priv, 0x405870 + (i * 4), tmp[i]);
1337 } 938 }
1338 nv_mthd(priv, 0x9197, 0x02e4, 0x0000b001);
1339} 939}
1340 940
1341static void 941void
1342nvc0_grctx_generate_9297(struct nvc0_graph_priv *priv) 942nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
1343{ 943{
1344 u32 fermi = nvc0_graph_class(priv); 944 u8 tpcnr[GPC_MAX], data[TPC_MAX];
1345 u32 mthd; 945 int gpc, tpc, i;
1346 946
1347 if (fermi == 0x9297) { 947 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1348 for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4) 948 memset(data, 0x1f, sizeof(data));
1349 nv_mthd(priv, 0x9297, mthd, 0x00000000); 949
950 gpc = -1;
951 for (tpc = 0; tpc < priv->tpc_total; tpc++) {
952 do {
953 gpc = (gpc + 1) % priv->gpc_nr;
954 } while (!tpcnr[gpc]);
955 tpcnr[gpc]--;
956 data[tpc] = gpc;
1350 } 957 }
1351 nv_mthd(priv, 0x9297, 0x036c, 0x00000000);
1352 nv_mthd(priv, 0x9297, 0x0370, 0x00000000);
1353 nv_mthd(priv, 0x9297, 0x07a4, 0x00000000);
1354 nv_mthd(priv, 0x9297, 0x07a8, 0x00000000);
1355 nv_mthd(priv, 0x9297, 0x0374, 0x00000000);
1356 nv_mthd(priv, 0x9297, 0x0378, 0x00000020);
1357}
1358
1359static void
1360nvc0_grctx_generate_902d(struct nvc0_graph_priv *priv)
1361{
1362 nv_mthd(priv, 0x902d, 0x0200, 0x000000cf);
1363 nv_mthd(priv, 0x902d, 0x0204, 0x00000001);
1364 nv_mthd(priv, 0x902d, 0x0208, 0x00000020);
1365 nv_mthd(priv, 0x902d, 0x020c, 0x00000001);
1366 nv_mthd(priv, 0x902d, 0x0210, 0x00000000);
1367 nv_mthd(priv, 0x902d, 0x0214, 0x00000080);
1368 nv_mthd(priv, 0x902d, 0x0218, 0x00000100);
1369 nv_mthd(priv, 0x902d, 0x021c, 0x00000100);
1370 nv_mthd(priv, 0x902d, 0x0220, 0x00000000);
1371 nv_mthd(priv, 0x902d, 0x0224, 0x00000000);
1372 nv_mthd(priv, 0x902d, 0x0230, 0x000000cf);
1373 nv_mthd(priv, 0x902d, 0x0234, 0x00000001);
1374 nv_mthd(priv, 0x902d, 0x0238, 0x00000020);
1375 nv_mthd(priv, 0x902d, 0x023c, 0x00000001);
1376 nv_mthd(priv, 0x902d, 0x0244, 0x00000080);
1377 nv_mthd(priv, 0x902d, 0x0248, 0x00000100);
1378 nv_mthd(priv, 0x902d, 0x024c, 0x00000100);
1379}
1380 958
1381static void 959 for (i = 0; i < 4; i++)
1382nvc0_grctx_generate_9039(struct nvc0_graph_priv *priv) 960 nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
1383{
1384 nv_mthd(priv, 0x9039, 0x030c, 0x00000000);
1385 nv_mthd(priv, 0x9039, 0x0310, 0x00000000);
1386 nv_mthd(priv, 0x9039, 0x0314, 0x00000000);
1387 nv_mthd(priv, 0x9039, 0x0320, 0x00000000);
1388 nv_mthd(priv, 0x9039, 0x0238, 0x00000000);
1389 nv_mthd(priv, 0x9039, 0x023c, 0x00000000);
1390 nv_mthd(priv, 0x9039, 0x0318, 0x00000000);
1391 nv_mthd(priv, 0x9039, 0x031c, 0x00000000);
1392} 961}
1393 962
1394static void 963void
1395nvc0_grctx_generate_90c0(struct nvc0_graph_priv *priv) 964nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
1396{ 965{
1397 int i; 966 u32 data[6] = {}, data2[2] = {};
1398 967 u8 tpcnr[GPC_MAX];
1399 for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) { 968 u8 shift, ntpcv;
1400 nv_mthd(priv, 0x90c0, 0x2700 + (i * 0x40), 0x00000000); 969 int gpc, tpc, i;
1401 nv_mthd(priv, 0x90c0, 0x2720 + (i * 0x40), 0x00000000); 970
1402 nv_mthd(priv, 0x90c0, 0x2704 + (i * 0x40), 0x00000000); 971 /* calculate first set of magics */
1403 nv_mthd(priv, 0x90c0, 0x2724 + (i * 0x40), 0x00000000); 972 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1404 nv_mthd(priv, 0x90c0, 0x2708 + (i * 0x40), 0x00000000); 973
1405 nv_mthd(priv, 0x90c0, 0x2728 + (i * 0x40), 0x00000000); 974 gpc = -1;
1406 } 975 for (tpc = 0; tpc < priv->tpc_total; tpc++) {
1407 nv_mthd(priv, 0x90c0, 0x270c, 0x00000000); 976 do {
1408 nv_mthd(priv, 0x90c0, 0x272c, 0x00000000); 977 gpc = (gpc + 1) % priv->gpc_nr;
1409 nv_mthd(priv, 0x90c0, 0x274c, 0x00000000); 978 } while (!tpcnr[gpc]);
1410 nv_mthd(priv, 0x90c0, 0x276c, 0x00000000); 979 tpcnr[gpc]--;
1411 nv_mthd(priv, 0x90c0, 0x278c, 0x00000000); 980
1412 nv_mthd(priv, 0x90c0, 0x27ac, 0x00000000); 981 data[tpc / 6] |= gpc << ((tpc % 6) * 5);
1413 nv_mthd(priv, 0x90c0, 0x27cc, 0x00000000);
1414 nv_mthd(priv, 0x90c0, 0x27ec, 0x00000000);
1415 for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
1416 nv_mthd(priv, 0x90c0, 0x2710 + (i * 0x40), 0x00014000);
1417 nv_mthd(priv, 0x90c0, 0x2730 + (i * 0x40), 0x00014000);
1418 }
1419 for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
1420 nv_mthd(priv, 0x90c0, 0x2714 + (i * 0x40), 0x00000040);
1421 nv_mthd(priv, 0x90c0, 0x2734 + (i * 0x40), 0x00000040);
1422 } 982 }
1423 nv_mthd(priv, 0x90c0, 0x030c, 0x00000001);
1424 nv_mthd(priv, 0x90c0, 0x1944, 0x00000000);
1425 nv_mthd(priv, 0x90c0, 0x0758, 0x00000100);
1426 nv_mthd(priv, 0x90c0, 0x02c4, 0x00000000);
1427 nv_mthd(priv, 0x90c0, 0x0790, 0x00000000);
1428 nv_mthd(priv, 0x90c0, 0x0794, 0x00000000);
1429 nv_mthd(priv, 0x90c0, 0x0798, 0x00000000);
1430 nv_mthd(priv, 0x90c0, 0x079c, 0x00000000);
1431 nv_mthd(priv, 0x90c0, 0x07a0, 0x00000000);
1432 nv_mthd(priv, 0x90c0, 0x077c, 0x00000000);
1433 nv_mthd(priv, 0x90c0, 0x0204, 0x00000000);
1434 nv_mthd(priv, 0x90c0, 0x0208, 0x00000000);
1435 nv_mthd(priv, 0x90c0, 0x020c, 0x00000000);
1436 nv_mthd(priv, 0x90c0, 0x0214, 0x00000000);
1437 nv_mthd(priv, 0x90c0, 0x024c, 0x00000000);
1438 nv_mthd(priv, 0x90c0, 0x0d94, 0x00000001);
1439 nv_mthd(priv, 0x90c0, 0x1608, 0x00000000);
1440 nv_mthd(priv, 0x90c0, 0x160c, 0x00000000);
1441 nv_mthd(priv, 0x90c0, 0x1664, 0x00000000);
1442}
1443 983
1444static void 984 for (; tpc < 32; tpc++)
1445nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) 985 data[tpc / 6] |= 7 << ((tpc % 6) * 5);
1446{
1447 int i;
1448 986
1449 nv_wr32(priv, 0x404004, 0x00000000); 987 /* and the second... */
1450 nv_wr32(priv, 0x404008, 0x00000000); 988 shift = 0;
1451 nv_wr32(priv, 0x40400c, 0x00000000); 989 ntpcv = priv->tpc_total;
1452 nv_wr32(priv, 0x404010, 0x00000000); 990 while (!(ntpcv & (1 << 4))) {
1453 nv_wr32(priv, 0x404014, 0x00000000); 991 ntpcv <<= 1;
1454 nv_wr32(priv, 0x404018, 0x00000000); 992 shift++;
1455 nv_wr32(priv, 0x40401c, 0x00000000);
1456 nv_wr32(priv, 0x404020, 0x00000000);
1457 nv_wr32(priv, 0x404024, 0x00000000);
1458 nv_wr32(priv, 0x404028, 0x00000000);
1459 switch (nv_device(priv)->chipset) {
1460 case 0xd9:
1461 case 0xd7:
1462 nv_wr32(priv, 0x40402c, 0x00000000);
1463 break;
1464 case 0xc0:
1465 case 0xc3:
1466 case 0xc4:
1467 case 0xc1:
1468 case 0xc8:
1469 case 0xce:
1470 case 0xcf:
1471 break;
1472 default:
1473 BUG_ON(1);
1474 break;
1475 }
1476 nv_wr32(priv, 0x404044, 0x00000000);
1477 nv_wr32(priv, 0x404094, 0x00000000);
1478 nv_wr32(priv, 0x404098, 0x00000000);
1479 nv_wr32(priv, 0x40409c, 0x00000000);
1480 nv_wr32(priv, 0x4040a0, 0x00000000);
1481 nv_wr32(priv, 0x4040a4, 0x00000000);
1482 nv_wr32(priv, 0x4040a8, 0x00000000);
1483 nv_wr32(priv, 0x4040ac, 0x00000000);
1484 nv_wr32(priv, 0x4040b0, 0x00000000);
1485 nv_wr32(priv, 0x4040b4, 0x00000000);
1486 nv_wr32(priv, 0x4040b8, 0x00000000);
1487 nv_wr32(priv, 0x4040bc, 0x00000000);
1488 nv_wr32(priv, 0x4040c0, 0x00000000);
1489 nv_wr32(priv, 0x4040c4, 0x00000000);
1490 nv_wr32(priv, 0x4040c8, 0xf0000087);
1491 nv_wr32(priv, 0x4040d0, 0x00000000);
1492 nv_wr32(priv, 0x4040d4, 0x00000000);
1493 nv_wr32(priv, 0x4040d8, 0x00000000);
1494 nv_wr32(priv, 0x4040dc, 0x00000000);
1495 nv_wr32(priv, 0x4040e0, 0x00000000);
1496 nv_wr32(priv, 0x4040e4, 0x00000000);
1497 nv_wr32(priv, 0x4040e8, 0x00001000);
1498 nv_wr32(priv, 0x4040f8, 0x00000000);
1499 nv_wr32(priv, 0x404130, 0x00000000);
1500 nv_wr32(priv, 0x404134, 0x00000000);
1501 nv_wr32(priv, 0x404138, 0x20000040);
1502 nv_wr32(priv, 0x404150, 0x0000002e);
1503 nv_wr32(priv, 0x404154, 0x00000400);
1504 nv_wr32(priv, 0x404158, 0x00000200);
1505 nv_wr32(priv, 0x404164, 0x00000055);
1506 nv_wr32(priv, 0x404168, 0x00000000);
1507 switch (nv_device(priv)->chipset) {
1508 case 0xd9:
1509 case 0xd7:
1510 break;
1511 case 0xc0:
1512 case 0xc3:
1513 case 0xc4:
1514 case 0xc1:
1515 case 0xc8:
1516 case 0xce:
1517 case 0xcf:
1518 nv_wr32(priv, 0x404174, 0x00000000);
1519 break;
1520 default:
1521 BUG_ON(1);
1522 break;
1523 } 993 }
1524 nv_wr32(priv, 0x404178, 0x00000000);
1525 nv_wr32(priv, 0x40417c, 0x00000000);
1526 for (i = 0; i < 8; i++)
1527 nv_wr32(priv, 0x404200 + (i * 4), 0x00000000); /* subc */
1528}
1529 994
1530static void 995 data2[0] = (ntpcv << 16);
1531nvc0_grctx_generate_macro(struct nvc0_graph_priv *priv) 996 data2[0] |= (shift << 21);
1532{ 997 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
1533 nv_wr32(priv, 0x404404, 0x00000000); 998 for (i = 1; i < 7; i++)
1534 nv_wr32(priv, 0x404408, 0x00000000); 999 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
1535 nv_wr32(priv, 0x40440c, 0x00000000);
1536 nv_wr32(priv, 0x404410, 0x00000000);
1537 nv_wr32(priv, 0x404414, 0x00000000);
1538 nv_wr32(priv, 0x404418, 0x00000000);
1539 nv_wr32(priv, 0x40441c, 0x00000000);
1540 nv_wr32(priv, 0x404420, 0x00000000);
1541 nv_wr32(priv, 0x404424, 0x00000000);
1542 nv_wr32(priv, 0x404428, 0x00000000);
1543 nv_wr32(priv, 0x40442c, 0x00000000);
1544 nv_wr32(priv, 0x404430, 0x00000000);
1545 nv_wr32(priv, 0x404434, 0x00000000);
1546 nv_wr32(priv, 0x404438, 0x00000000);
1547 nv_wr32(priv, 0x404460, 0x00000000);
1548 nv_wr32(priv, 0x404464, 0x00000000);
1549 nv_wr32(priv, 0x404468, 0x00ffffff);
1550 nv_wr32(priv, 0x40446c, 0x00000000);
1551 nv_wr32(priv, 0x404480, 0x00000001);
1552 nv_wr32(priv, 0x404498, 0x00000001);
1553}
1554
1555static void
1556nvc0_grctx_generate_m2mf(struct nvc0_graph_priv *priv)
1557{
1558 nv_wr32(priv, 0x404604, 0x00000015);
1559 nv_wr32(priv, 0x404608, 0x00000000);
1560 nv_wr32(priv, 0x40460c, 0x00002e00);
1561 nv_wr32(priv, 0x404610, 0x00000100);
1562 nv_wr32(priv, 0x404618, 0x00000000);
1563 nv_wr32(priv, 0x40461c, 0x00000000);
1564 nv_wr32(priv, 0x404620, 0x00000000);
1565 nv_wr32(priv, 0x404624, 0x00000000);
1566 nv_wr32(priv, 0x404628, 0x00000000);
1567 nv_wr32(priv, 0x40462c, 0x00000000);
1568 nv_wr32(priv, 0x404630, 0x00000000);
1569 nv_wr32(priv, 0x404634, 0x00000000);
1570 nv_wr32(priv, 0x404638, 0x00000004);
1571 nv_wr32(priv, 0x40463c, 0x00000000);
1572 nv_wr32(priv, 0x404640, 0x00000000);
1573 nv_wr32(priv, 0x404644, 0x00000000);
1574 nv_wr32(priv, 0x404648, 0x00000000);
1575 nv_wr32(priv, 0x40464c, 0x00000000);
1576 nv_wr32(priv, 0x404650, 0x00000000);
1577 nv_wr32(priv, 0x404654, 0x00000000);
1578 nv_wr32(priv, 0x404658, 0x00000000);
1579 nv_wr32(priv, 0x40465c, 0x007f0100);
1580 nv_wr32(priv, 0x404660, 0x00000000);
1581 nv_wr32(priv, 0x404664, 0x00000000);
1582 nv_wr32(priv, 0x404668, 0x00000000);
1583 nv_wr32(priv, 0x40466c, 0x00000000);
1584 nv_wr32(priv, 0x404670, 0x00000000);
1585 nv_wr32(priv, 0x404674, 0x00000000);
1586 nv_wr32(priv, 0x404678, 0x00000000);
1587 nv_wr32(priv, 0x40467c, 0x00000002);
1588 nv_wr32(priv, 0x404680, 0x00000000);
1589 nv_wr32(priv, 0x404684, 0x00000000);
1590 nv_wr32(priv, 0x404688, 0x00000000);
1591 nv_wr32(priv, 0x40468c, 0x00000000);
1592 nv_wr32(priv, 0x404690, 0x00000000);
1593 nv_wr32(priv, 0x404694, 0x00000000);
1594 nv_wr32(priv, 0x404698, 0x00000000);
1595 nv_wr32(priv, 0x40469c, 0x00000000);
1596 nv_wr32(priv, 0x4046a0, 0x007f0080);
1597 nv_wr32(priv, 0x4046a4, 0x00000000);
1598 nv_wr32(priv, 0x4046a8, 0x00000000);
1599 nv_wr32(priv, 0x4046ac, 0x00000000);
1600 nv_wr32(priv, 0x4046b0, 0x00000000);
1601 nv_wr32(priv, 0x4046b4, 0x00000000);
1602 nv_wr32(priv, 0x4046b8, 0x00000000);
1603 nv_wr32(priv, 0x4046bc, 0x00000000);
1604 nv_wr32(priv, 0x4046c0, 0x00000000);
1605 nv_wr32(priv, 0x4046c4, 0x00000000);
1606 nv_wr32(priv, 0x4046c8, 0x00000000);
1607 nv_wr32(priv, 0x4046cc, 0x00000000);
1608 nv_wr32(priv, 0x4046d0, 0x00000000);
1609 nv_wr32(priv, 0x4046d4, 0x00000000);
1610 nv_wr32(priv, 0x4046d8, 0x00000000);
1611 nv_wr32(priv, 0x4046dc, 0x00000000);
1612 nv_wr32(priv, 0x4046e0, 0x00000000);
1613 nv_wr32(priv, 0x4046e4, 0x00000000);
1614 nv_wr32(priv, 0x4046e8, 0x00000000);
1615 nv_wr32(priv, 0x4046f0, 0x00000000);
1616 nv_wr32(priv, 0x4046f4, 0x00000000);
1617}
1618 1000
1619static void 1001 /* GPC_BROADCAST */
1620nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv) 1002 nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
1621{ 1003 priv->magic_not_rop_nr);
1622 nv_wr32(priv, 0x404700, 0x00000000); 1004 for (i = 0; i < 6; i++)
1623 nv_wr32(priv, 0x404704, 0x00000000); 1005 nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
1624 nv_wr32(priv, 0x404708, 0x00000000);
1625 nv_wr32(priv, 0x40470c, 0x00000000);
1626 nv_wr32(priv, 0x404710, 0x00000000);
1627 nv_wr32(priv, 0x404714, 0x00000000);
1628 nv_wr32(priv, 0x404718, 0x00000000);
1629 nv_wr32(priv, 0x40471c, 0x00000000);
1630 nv_wr32(priv, 0x404720, 0x00000000);
1631 nv_wr32(priv, 0x404724, 0x00000000);
1632 nv_wr32(priv, 0x404728, 0x00000000);
1633 nv_wr32(priv, 0x40472c, 0x00000000);
1634 nv_wr32(priv, 0x404730, 0x00000000);
1635 nv_wr32(priv, 0x404734, 0x00000100);
1636 nv_wr32(priv, 0x404738, 0x00000000);
1637 nv_wr32(priv, 0x40473c, 0x00000000);
1638 nv_wr32(priv, 0x404740, 0x00000000);
1639 nv_wr32(priv, 0x404744, 0x00000000);
1640 nv_wr32(priv, 0x404748, 0x00000000);
1641 nv_wr32(priv, 0x40474c, 0x00000000);
1642 nv_wr32(priv, 0x404750, 0x00000000);
1643 nv_wr32(priv, 0x404754, 0x00000000);
1644}
1645 1006
1646static void 1007 /* GPC_BROADCAST.TP_BROADCAST */
1647nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) 1008 nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
1648{ 1009 priv->magic_not_rop_nr | data2[0]);
1649 switch (nv_device(priv)->chipset) { 1010 nv_wr32(priv, 0x419be4, data2[1]);
1650 case 0xc1: 1011 for (i = 0; i < 6; i++)
1651 nv_wr32(priv, 0x405800, 0x0f8000bf); 1012 nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
1652 nv_wr32(priv, 0x405830, 0x02180218); 1013
1653 nv_wr32(priv, 0x405834, 0x00000000); 1014 /* UNK78xx */
1654 break; 1015 nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
1655 case 0xd9: 1016 priv->magic_not_rop_nr);
1656 case 0xd7: 1017 for (i = 0; i < 6; i++)
1657 nv_wr32(priv, 0x405800, 0x0f8000bf); 1018 nv_wr32(priv, 0x40780c + (i * 4), data[i]);
1658 nv_wr32(priv, 0x405830, 0x02180218);
1659 nv_wr32(priv, 0x405834, 0x08000000);
1660 break;
1661 case 0xc0:
1662 case 0xc3:
1663 case 0xc4:
1664 case 0xc8:
1665 case 0xce:
1666 case 0xcf:
1667 nv_wr32(priv, 0x405800, 0x078000bf);
1668 nv_wr32(priv, 0x405830, 0x02180000);
1669 nv_wr32(priv, 0x405834, 0x00000000);
1670 break;
1671 default:
1672 BUG_ON(1);
1673 break;
1674 }
1675 nv_wr32(priv, 0x405838, 0x00000000);
1676 nv_wr32(priv, 0x405854, 0x00000000);
1677 nv_wr32(priv, 0x405870, 0x00000001);
1678 nv_wr32(priv, 0x405874, 0x00000001);
1679 nv_wr32(priv, 0x405878, 0x00000001);
1680 nv_wr32(priv, 0x40587c, 0x00000001);
1681 nv_wr32(priv, 0x405a00, 0x00000000);
1682 nv_wr32(priv, 0x405a04, 0x00000000);
1683 nv_wr32(priv, 0x405a18, 0x00000000);
1684} 1019}
1685 1020
1686static void 1021void
1687nvc0_grctx_generate_unk60xx(struct nvc0_graph_priv *priv) 1022nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
1688{ 1023{
1689 nv_wr32(priv, 0x406020, 0x000103c1); 1024 u64 tpc_mask = 0, tpc_set = 0;
1690 nv_wr32(priv, 0x406028, 0x00000001); 1025 u8 tpcnr[GPC_MAX];
1691 nv_wr32(priv, 0x40602c, 0x00000001); 1026 int gpc, tpc;
1692 nv_wr32(priv, 0x406030, 0x00000001); 1027 int i, a, b;
1693 nv_wr32(priv, 0x406034, 0x00000001); 1028
1694} 1029 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1030 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
1031 tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
1032
1033 for (i = 0, gpc = -1, b = -1; i < 32; i++) {
1034 a = (i * (priv->tpc_total - 1)) / 32;
1035 if (a != b) {
1036 b = a;
1037 do {
1038 gpc = (gpc + 1) % priv->gpc_nr;
1039 } while (!tpcnr[gpc]);
1040 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
1695 1041
1696static void 1042 tpc_set |= 1 << ((gpc * 8) + tpc);
1697nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) 1043 }
1698{
1699 1044
1700 nv_wr32(priv, 0x4064a8, 0x00000000); 1045 nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
1701 nv_wr32(priv, 0x4064ac, 0x00003fff); 1046 nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
1702 nv_wr32(priv, 0x4064b4, 0x00000000); 1047 if (priv->gpc_nr > 4) {
1703 nv_wr32(priv, 0x4064b8, 0x00000000); 1048 nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
1704 switch (nv_device(priv)->chipset) { 1049 nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
1705 case 0xd9: 1050 }
1706 case 0xd7:
1707 nv_wr32(priv, 0x4064bc, 0x00000000);
1708 nv_wr32(priv, 0x4064c0, 0x80140078);
1709 nv_wr32(priv, 0x4064c4, 0x0086ffff);
1710 break;
1711 case 0xc0:
1712 case 0xc3:
1713 case 0xc4:
1714 case 0xc1:
1715 case 0xc8:
1716 case 0xce:
1717 case 0xcf:
1718 break;
1719 default:
1720 BUG_ON(1);
1721 break;
1722 } 1051 }
1723} 1052}
1724 1053
1725static void 1054void
1726nvc0_grctx_generate_tpbus(struct nvc0_graph_priv *priv) 1055nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
1727{ 1056{
1728 nv_wr32(priv, 0x407804, 0x00000023); 1057 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
1729 nv_wr32(priv, 0x40780c, 0x0a418820); 1058 int i;
1730 nv_wr32(priv, 0x407810, 0x062080e6);
1731 nv_wr32(priv, 0x407814, 0x020398a4);
1732 nv_wr32(priv, 0x407818, 0x0e629062);
1733 nv_wr32(priv, 0x40781c, 0x0a418820);
1734 nv_wr32(priv, 0x407820, 0x000000e6);
1735 nv_wr32(priv, 0x4078bc, 0x00000103);
1736}
1737 1059
1738static void 1060 nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
1739nvc0_grctx_generate_ccache(struct nvc0_graph_priv *priv)
1740{
1741 nv_wr32(priv, 0x408000, 0x00000000);
1742 nv_wr32(priv, 0x408004, 0x00000000);
1743 nv_wr32(priv, 0x408008, 0x00000018);
1744 nv_wr32(priv, 0x40800c, 0x00000000);
1745 nv_wr32(priv, 0x408010, 0x00000000);
1746 nv_wr32(priv, 0x408014, 0x00000069);
1747 nv_wr32(priv, 0x408018, 0xe100e100);
1748 nv_wr32(priv, 0x408064, 0x00000000);
1749}
1750 1061
1751static void 1062 for (i = 0; oclass->hub[i]; i++)
1752nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) 1063 nvc0_graph_mmio(priv, oclass->hub[i]);
1753{ 1064 for (i = 0; oclass->gpc[i]; i++)
1754 /* ROPC_BROADCAST */ 1065 nvc0_graph_mmio(priv, oclass->gpc[i]);
1755 nv_wr32(priv, 0x408800, 0x02802a3c);
1756 nv_wr32(priv, 0x408804, 0x00000040);
1757 switch (nv_device(priv)->chipset) {
1758 case 0xc0:
1759 case 0xc3:
1760 case 0xc4:
1761 case 0xc8:
1762 case 0xce:
1763 case 0xcf:
1764 nv_wr32(priv, 0x408808, 0x0003e00d);
1765 nv_wr32(priv, 0x408900, 0x3080b801);
1766 nv_wr32(priv, 0x408904, 0x02000001);
1767 nv_wr32(priv, 0x408908, 0x00c80929);
1768 break;
1769 case 0xc1:
1770 nv_wr32(priv, 0x408808, 0x1003e005);
1771 nv_wr32(priv, 0x408900, 0x3080b801);
1772 nv_wr32(priv, 0x408904, 0x62000001);
1773 nv_wr32(priv, 0x408908, 0x00c80929);
1774 break;
1775 case 0xd9:
1776 case 0xd7:
1777 nv_wr32(priv, 0x408808, 0x1043e005);
1778 nv_wr32(priv, 0x408900, 0x3080b801);
1779 nv_wr32(priv, 0x408904, 0x1043e005);
1780 nv_wr32(priv, 0x408908, 0x00c8102f);
1781 break;
1782 default:
1783 BUG_ON(1);
1784 break;
1785 }
1786 nv_wr32(priv, 0x408980, 0x0000011d);
1787}
1788 1066
1789static void 1067 nv_wr32(priv, 0x404154, 0x00000000);
1790nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1791{
1792 int i;
1793 1068
1794 /* GPC_BROADCAST */ 1069 oclass->mods(priv, info);
1795 nv_wr32(priv, 0x418380, 0x00000016); 1070 oclass->unkn(priv);
1796 nv_wr32(priv, 0x418400, 0x38004e00);
1797 nv_wr32(priv, 0x418404, 0x71e0ffff);
1798 switch (nv_device(priv)->chipset) {
1799 case 0xd9:
1800 case 0xd7:
1801 break;
1802 case 0xc0:
1803 case 0xc3:
1804 case 0xc4:
1805 case 0xc1:
1806 case 0xc8:
1807 case 0xce:
1808 case 0xcf:
1809 nv_wr32(priv, 0x418408, 0x00000000);
1810 break;
1811 default:
1812 BUG_ON(1);
1813 break;
1814 }
1815 nv_wr32(priv, 0x41840c, 0x00001008);
1816 nv_wr32(priv, 0x418410, 0x0fff0fff);
1817 switch (nv_device(priv)->chipset) {
1818 case 0xd9:
1819 case 0xd7:
1820 nv_wr32(priv, 0x418414, 0x02200fff);
1821 break;
1822 case 0xc0:
1823 case 0xc3:
1824 case 0xc4:
1825 case 0xc1:
1826 case 0xc8:
1827 case 0xce:
1828 case 0xcf:
1829 nv_wr32(priv, 0x418414, 0x00200fff);
1830 break;
1831 default:
1832 BUG_ON(1);
1833 break;
1834 }
1835 nv_wr32(priv, 0x418450, 0x00000000);
1836 nv_wr32(priv, 0x418454, 0x00000000);
1837 nv_wr32(priv, 0x418458, 0x00000000);
1838 nv_wr32(priv, 0x41845c, 0x00000000);
1839 nv_wr32(priv, 0x418460, 0x00000000);
1840 nv_wr32(priv, 0x418464, 0x00000000);
1841 nv_wr32(priv, 0x418468, 0x00000001);
1842 nv_wr32(priv, 0x41846c, 0x00000000);
1843 nv_wr32(priv, 0x418470, 0x00000000);
1844 nv_wr32(priv, 0x418600, 0x0000001f);
1845 nv_wr32(priv, 0x418684, 0x0000000f);
1846 nv_wr32(priv, 0x418700, 0x00000002);
1847 nv_wr32(priv, 0x418704, 0x00000080);
1848 nv_wr32(priv, 0x418708, 0x00000000);
1849 switch (nv_device(priv)->chipset) {
1850 case 0xd9:
1851 case 0xd7:
1852 nv_wr32(priv, 0x41870c, 0x00000000);
1853 break;
1854 case 0xc0:
1855 case 0xc3:
1856 case 0xc4:
1857 case 0xc1:
1858 case 0xc8:
1859 case 0xce:
1860 case 0xcf:
1861 nv_wr32(priv, 0x41870c, 0x07c80000);
1862 break;
1863 default:
1864 BUG_ON(1);
1865 break;
1866 }
1867 nv_wr32(priv, 0x418710, 0x00000000);
1868 switch (nv_device(priv)->chipset) {
1869 case 0xd9:
1870 case 0xd7:
1871 nv_wr32(priv, 0x418800, 0x7006860a);
1872 break;
1873 case 0xc0:
1874 case 0xc3:
1875 case 0xc4:
1876 case 0xc1:
1877 case 0xc8:
1878 case 0xce:
1879 case 0xcf:
1880 nv_wr32(priv, 0x418800, 0x0006860a);
1881 break;
1882 default:
1883 BUG_ON(1);
1884 break;
1885 }
1886 nv_wr32(priv, 0x418808, 0x00000000);
1887 nv_wr32(priv, 0x41880c, 0x00000000);
1888 nv_wr32(priv, 0x418810, 0x00000000);
1889 nv_wr32(priv, 0x418828, 0x00008442);
1890 switch (nv_device(priv)->chipset) {
1891 case 0xc1:
1892 case 0xd9:
1893 case 0xd7:
1894 nv_wr32(priv, 0x418830, 0x10000001);
1895 break;
1896 case 0xc0:
1897 case 0xc3:
1898 case 0xc4:
1899 case 0xc8:
1900 case 0xce:
1901 case 0xcf:
1902 nv_wr32(priv, 0x418830, 0x00000001);
1903 break;
1904 default:
1905 BUG_ON(1);
1906 break;
1907 }
1908 nv_wr32(priv, 0x4188d8, 0x00000008);
1909 nv_wr32(priv, 0x4188e0, 0x01000000);
1910 nv_wr32(priv, 0x4188e8, 0x00000000);
1911 nv_wr32(priv, 0x4188ec, 0x00000000);
1912 nv_wr32(priv, 0x4188f0, 0x00000000);
1913 nv_wr32(priv, 0x4188f4, 0x00000000);
1914 nv_wr32(priv, 0x4188f8, 0x00000000);
1915 switch (nv_device(priv)->chipset) {
1916 case 0xc1:
1917 nv_wr32(priv, 0x4188fc, 0x00100018);
1918 break;
1919 case 0xd9:
1920 case 0xd7:
1921 nv_wr32(priv, 0x4188fc, 0x20100008);
1922 break;
1923 case 0xc0:
1924 case 0xc3:
1925 case 0xc4:
1926 case 0xc8:
1927 case 0xce:
1928 case 0xcf:
1929 nv_wr32(priv, 0x4188fc, 0x00100000);
1930 break;
1931 default:
1932 BUG_ON(1);
1933 break;
1934 }
1935 nv_wr32(priv, 0x41891c, 0x00ff00ff);
1936 nv_wr32(priv, 0x418924, 0x00000000);
1937 nv_wr32(priv, 0x418928, 0x00ffff00);
1938 nv_wr32(priv, 0x41892c, 0x0000ff00);
1939 for (i = 0; i < 8; i++) {
1940 nv_wr32(priv, 0x418a00 + (i * 0x20), 0x00000000);
1941 nv_wr32(priv, 0x418a04 + (i * 0x20), 0x00000000);
1942 nv_wr32(priv, 0x418a08 + (i * 0x20), 0x00000000);
1943 nv_wr32(priv, 0x418a0c + (i * 0x20), 0x00010000);
1944 nv_wr32(priv, 0x418a10 + (i * 0x20), 0x00000000);
1945 nv_wr32(priv, 0x418a14 + (i * 0x20), 0x00000000);
1946 nv_wr32(priv, 0x418a18 + (i * 0x20), 0x00000000);
1947 }
1948 switch (nv_device(priv)->chipset) {
1949 case 0xd9:
1950 case 0xd7:
1951 nv_wr32(priv, 0x418b00, 0x00000006);
1952 break;
1953 case 0xc0:
1954 case 0xc3:
1955 case 0xc4:
1956 case 0xc1:
1957 case 0xc8:
1958 case 0xce:
1959 case 0xcf:
1960 nv_wr32(priv, 0x418b00, 0x00000000);
1961 break;
1962 default:
1963 BUG_ON(1);
1964 break;
1965 }
1966 nv_wr32(priv, 0x418b08, 0x0a418820);
1967 nv_wr32(priv, 0x418b0c, 0x062080e6);
1968 nv_wr32(priv, 0x418b10, 0x020398a4);
1969 nv_wr32(priv, 0x418b14, 0x0e629062);
1970 nv_wr32(priv, 0x418b18, 0x0a418820);
1971 nv_wr32(priv, 0x418b1c, 0x000000e6);
1972 nv_wr32(priv, 0x418bb8, 0x00000103);
1973 nv_wr32(priv, 0x418c08, 0x00000001);
1974 nv_wr32(priv, 0x418c10, 0x00000000);
1975 nv_wr32(priv, 0x418c14, 0x00000000);
1976 nv_wr32(priv, 0x418c18, 0x00000000);
1977 nv_wr32(priv, 0x418c1c, 0x00000000);
1978 nv_wr32(priv, 0x418c20, 0x00000000);
1979 nv_wr32(priv, 0x418c24, 0x00000000);
1980 nv_wr32(priv, 0x418c28, 0x00000000);
1981 nv_wr32(priv, 0x418c2c, 0x00000000);
1982 switch (nv_device(priv)->chipset) {
1983 case 0xc1:
1984 case 0xd9:
1985 case 0xd7:
1986 nv_wr32(priv, 0x418c6c, 0x00000001);
1987 break;
1988 case 0xc0:
1989 case 0xc3:
1990 case 0xc4:
1991 case 0xc8:
1992 case 0xce:
1993 case 0xcf:
1994 break;
1995 default:
1996 BUG_ON(1);
1997 break;
1998 }
1999 nv_wr32(priv, 0x418c80, 0x20200004);
2000 nv_wr32(priv, 0x418c8c, 0x00000001);
2001 nv_wr32(priv, 0x419000, 0x00000780);
2002 nv_wr32(priv, 0x419004, 0x00000000);
2003 nv_wr32(priv, 0x419008, 0x00000000);
2004 nv_wr32(priv, 0x419014, 0x00000004);
2005}
2006 1071
2007static void 1072 nvc0_grctx_generate_tpcid(priv);
2008nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) 1073 nvc0_grctx_generate_r406028(priv);
2009{ 1074 nvc0_grctx_generate_r4060a8(priv);
2010 /* GPC_BROADCAST.TP_BROADCAST */ 1075 nvc0_grctx_generate_r418bb8(priv);
2011 nv_wr32(priv, 0x419818, 0x00000000); 1076 nvc0_grctx_generate_r406800(priv);
2012 nv_wr32(priv, 0x41983c, 0x00038bc7); 1077
2013 nv_wr32(priv, 0x419848, 0x00000000); 1078 nvc0_graph_icmd(priv, oclass->icmd);
2014 switch (nv_device(priv)->chipset) { 1079 nv_wr32(priv, 0x404154, 0x00000400);
2015 case 0xc1: 1080 nvc0_graph_mthd(priv, oclass->mthd);
2016 case 0xd9: 1081 nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
2017 case 0xd7:
2018 nv_wr32(priv, 0x419864, 0x00000129);
2019 break;
2020 case 0xc0:
2021 case 0xc3:
2022 case 0xc4:
2023 case 0xc8:
2024 case 0xce:
2025 case 0xcf:
2026 nv_wr32(priv, 0x419864, 0x0000012a);
2027 break;
2028 default:
2029 BUG_ON(1);
2030 break;
2031 }
2032 nv_wr32(priv, 0x419888, 0x00000000);
2033 nv_wr32(priv, 0x419a00, 0x000001f0);
2034 nv_wr32(priv, 0x419a04, 0x00000001);
2035 nv_wr32(priv, 0x419a08, 0x00000023);
2036 nv_wr32(priv, 0x419a0c, 0x00020000);
2037 nv_wr32(priv, 0x419a10, 0x00000000);
2038 nv_wr32(priv, 0x419a14, 0x00000200);
2039 switch (nv_device(priv)->chipset) {
2040 case 0xc0:
2041 break;
2042 case 0xc3:
2043 case 0xc4:
2044 case 0xc1:
2045 case 0xc8:
2046 case 0xce:
2047 case 0xcf:
2048 case 0xd9:
2049 case 0xd7:
2050 nv_wr32(priv, 0x419a1c, 0x00000000);
2051 nv_wr32(priv, 0x419a20, 0x00000800);
2052 break;
2053 default:
2054 BUG_ON(1);
2055 break;
2056 }
2057 switch (nv_device(priv)->chipset) {
2058 case 0xc0:
2059 case 0xc8:
2060 break;
2061 case 0xd9:
2062 case 0xd7:
2063 nv_wr32(priv, 0x00419ac4, 0x0017f440);
2064 break;
2065 case 0xc3:
2066 case 0xc4:
2067 case 0xc1:
2068 case 0xce:
2069 case 0xcf:
2070 nv_wr32(priv, 0x00419ac4, 0x0007f440);
2071 break;
2072 default:
2073 BUG_ON(1);
2074 break;
2075 }
2076 nv_wr32(priv, 0x419b00, 0x0a418820);
2077 nv_wr32(priv, 0x419b04, 0x062080e6);
2078 nv_wr32(priv, 0x419b08, 0x020398a4);
2079 nv_wr32(priv, 0x419b0c, 0x0e629062);
2080 nv_wr32(priv, 0x419b10, 0x0a418820);
2081 nv_wr32(priv, 0x419b14, 0x000000e6);
2082 nv_wr32(priv, 0x419bd0, 0x00900103);
2083 switch (nv_device(priv)->chipset) {
2084 case 0xc1:
2085 case 0xd9:
2086 case 0xd7:
2087 nv_wr32(priv, 0x419be0, 0x00400001);
2088 break;
2089 case 0xc0:
2090 case 0xc3:
2091 case 0xc4:
2092 case 0xc8:
2093 case 0xce:
2094 case 0xcf:
2095 nv_wr32(priv, 0x419be0, 0x00000001);
2096 break;
2097 default:
2098 BUG_ON(1);
2099 break;
2100 }
2101 nv_wr32(priv, 0x419be4, 0x00000000);
2102 switch (nv_device(priv)->chipset) {
2103 case 0xd9:
2104 case 0xd7:
2105 nv_wr32(priv, 0x419c00, 0x0000000a);
2106 break;
2107 case 0xc0:
2108 case 0xc3:
2109 case 0xc4:
2110 case 0xc1:
2111 case 0xc8:
2112 case 0xce:
2113 case 0xcf:
2114 nv_wr32(priv, 0x419c00, 0x00000002);
2115 break;
2116 default:
2117 BUG_ON(1);
2118 break;
2119 }
2120 nv_wr32(priv, 0x419c04, 0x00000006);
2121 nv_wr32(priv, 0x419c08, 0x00000002);
2122 nv_wr32(priv, 0x419c20, 0x00000000);
2123 switch (nv_device(priv)->chipset) {
2124 case 0xc3:
2125 case 0xc4:
2126 case 0xc1:
2127 case 0xce:
2128 case 0xcf:
2129 nv_wr32(priv, 0x419cb0, 0x00020048);
2130 break;
2131 case 0xd9:
2132 case 0xd7:
2133 nv_wr32(priv, 0x419c24, 0x00084210);
2134 nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
2135 nv_wr32(priv, 0x419cb0, 0x00020048);
2136 break;
2137 case 0xc0:
2138 case 0xc8:
2139 nv_wr32(priv, 0x419cb0, 0x00060048);
2140 break;
2141 default:
2142 BUG_ON(1);
2143 break;
2144 }
2145 nv_wr32(priv, 0x419ce8, 0x00000000);
2146 nv_wr32(priv, 0x419cf4, 0x00000183);
2147 switch (nv_device(priv)->chipset) {
2148 case 0xc1:
2149 case 0xd9:
2150 case 0xd7:
2151 nv_wr32(priv, 0x419d20, 0x12180000);
2152 break;
2153 case 0xc0:
2154 case 0xc3:
2155 case 0xc4:
2156 case 0xc8:
2157 case 0xce:
2158 case 0xcf:
2159 nv_wr32(priv, 0x419d20, 0x02180000);
2160 break;
2161 default:
2162 BUG_ON(1);
2163 break;
2164 }
2165 nv_wr32(priv, 0x419d24, 0x00001fff);
2166 switch (nv_device(priv)->chipset) {
2167 case 0xc1:
2168 case 0xd9:
2169 case 0xd7:
2170 nv_wr32(priv, 0x419d44, 0x02180218);
2171 break;
2172 case 0xc0:
2173 case 0xc3:
2174 case 0xc4:
2175 case 0xc8:
2176 case 0xce:
2177 case 0xcf:
2178 break;
2179 default:
2180 BUG_ON(1);
2181 break;
2182 }
2183 nv_wr32(priv, 0x419e04, 0x00000000);
2184 nv_wr32(priv, 0x419e08, 0x00000000);
2185 nv_wr32(priv, 0x419e0c, 0x00000000);
2186 nv_wr32(priv, 0x419e10, 0x00000002);
2187 nv_wr32(priv, 0x419e44, 0x001beff2);
2188 nv_wr32(priv, 0x419e48, 0x00000000);
2189 nv_wr32(priv, 0x419e4c, 0x0000000f);
2190 nv_wr32(priv, 0x419e50, 0x00000000);
2191 nv_wr32(priv, 0x419e54, 0x00000000);
2192 nv_wr32(priv, 0x419e58, 0x00000000);
2193 nv_wr32(priv, 0x419e5c, 0x00000000);
2194 nv_wr32(priv, 0x419e60, 0x00000000);
2195 nv_wr32(priv, 0x419e64, 0x00000000);
2196 nv_wr32(priv, 0x419e68, 0x00000000);
2197 nv_wr32(priv, 0x419e6c, 0x00000000);
2198 nv_wr32(priv, 0x419e70, 0x00000000);
2199 nv_wr32(priv, 0x419e74, 0x00000000);
2200 nv_wr32(priv, 0x419e78, 0x00000000);
2201 nv_wr32(priv, 0x419e7c, 0x00000000);
2202 nv_wr32(priv, 0x419e80, 0x00000000);
2203 nv_wr32(priv, 0x419e84, 0x00000000);
2204 nv_wr32(priv, 0x419e88, 0x00000000);
2205 nv_wr32(priv, 0x419e8c, 0x00000000);
2206 nv_wr32(priv, 0x419e90, 0x00000000);
2207 nv_wr32(priv, 0x419e98, 0x00000000);
2208 switch (nv_device(priv)->chipset) {
2209 case 0xc0:
2210 case 0xc8:
2211 break;
2212 case 0xd9:
2213 case 0xd7:
2214 nv_wr32(priv, 0x419ee0, 0x00010110);
2215 break;
2216 case 0xc3:
2217 case 0xc4:
2218 case 0xc1:
2219 case 0xce:
2220 case 0xcf:
2221 nv_wr32(priv, 0x419ee0, 0x00011110);
2222 break;
2223 default:
2224 BUG_ON(1);
2225 break;
2226 }
2227 switch (nv_device(priv)->chipset) {
2228 case 0xc0:
2229 case 0xc8:
2230 nv_wr32(priv, 0x419f50, 0x00000000);
2231 nv_wr32(priv, 0x419f54, 0x00000000);
2232 break;
2233 case 0xc3:
2234 case 0xc4:
2235 case 0xc1:
2236 case 0xce:
2237 case 0xcf:
2238 case 0xd9:
2239 case 0xd7:
2240 nv_wr32(priv, 0x419f30, 0x00000000);
2241 nv_wr32(priv, 0x419f34, 0x00000000);
2242 nv_wr32(priv, 0x419f38, 0x00000000);
2243 nv_wr32(priv, 0x419f3c, 0x00000000);
2244 nv_wr32(priv, 0x419f40, 0x00000000);
2245 nv_wr32(priv, 0x419f44, 0x00000000);
2246 nv_wr32(priv, 0x419f48, 0x00000000);
2247 nv_wr32(priv, 0x419f4c, 0x00000000);
2248 nv_wr32(priv, 0x419f50, 0x00000000);
2249 nv_wr32(priv, 0x419f54, 0x00000000);
2250 nv_wr32(priv, 0x419f58, 0x00000000);
2251 break;
2252 break;
2253 default:
2254 BUG_ON(1);
2255 break;
2256 }
2257} 1082}
2258 1083
2259int 1084int
2260nvc0_grctx_generate(struct nvc0_graph_priv *priv) 1085nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2261{ 1086{
1087 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
1088 struct nouveau_bar *bar = nouveau_bar(priv);
1089 struct nouveau_gpuobj *chan;
2262 struct nvc0_grctx info; 1090 struct nvc0_grctx info;
2263 int ret, i, gpc, tpc, id; 1091 int ret, i;
2264 u32 fermi = nvc0_graph_class(priv);
2265 u32 r000260, tmp;
2266 1092
2267 ret = nvc0_grctx_init(priv, &info); 1093 /* allocate memory to for a "channel", which we'll use to generate
2268 if (ret) 1094 * the default context values
1095 */
1096 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
1097 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
1098 if (ret) {
1099 nv_error(priv, "failed to allocate channel memory, %d\n", ret);
2269 return ret; 1100 return ret;
2270
2271 r000260 = nv_rd32(priv, 0x000260);
2272 nv_wr32(priv, 0x000260, r000260 & ~1);
2273 nv_wr32(priv, 0x400208, 0x00000000);
2274
2275 nvc0_grctx_generate_dispatch(priv);
2276 nvc0_grctx_generate_macro(priv);
2277 nvc0_grctx_generate_m2mf(priv);
2278 nvc0_grctx_generate_unk47xx(priv);
2279 nvc0_grctx_generate_shaders(priv);
2280 nvc0_grctx_generate_unk60xx(priv);
2281 nvc0_grctx_generate_unk64xx(priv);
2282 nvc0_grctx_generate_tpbus(priv);
2283 nvc0_grctx_generate_ccache(priv);
2284 nvc0_grctx_generate_rop(priv);
2285 nvc0_grctx_generate_gpc(priv);
2286 nvc0_grctx_generate_tp(priv);
2287
2288 nv_wr32(priv, 0x404154, 0x00000000);
2289
2290 /* generate per-context mmio list data */
2291 mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
2292 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
2293 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
2294 mmio_list(0x408004, 0x00000000, 8, 0);
2295 mmio_list(0x408008, 0x80000018, 0, 0);
2296 mmio_list(0x40800c, 0x00000000, 8, 1);
2297 mmio_list(0x408010, 0x80000000, 0, 0);
2298 mmio_list(0x418810, 0x80000000, 12, 2);
2299 mmio_list(0x419848, 0x10000000, 12, 2);
2300 mmio_list(0x419004, 0x00000000, 8, 1);
2301 mmio_list(0x419008, 0x00000000, 0, 0);
2302 mmio_list(0x418808, 0x00000000, 8, 0);
2303 mmio_list(0x41880c, 0x80000018, 0, 0);
2304 switch (nv_device(priv)->chipset) {
2305 case 0xc1:
2306 case 0xd9:
2307 case 0xd7:
2308 tmp = 0x02180000;
2309 mmio_list(0x405830, 0x00000218 | tmp, 0, 0);
2310 mmio_list(0x4064c4, 0x0086ffff, 0, 0);
2311 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
2312 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
2313 u32 reg = TPC_UNIT(gpc, tpc, 0x0520);
2314 mmio_list(reg, 0x10000000 | tmp, 0, 0);
2315 tmp += 0x0324;
2316 }
2317 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
2318 u32 reg = TPC_UNIT(gpc, tpc, 0x0544);
2319 mmio_list(reg, tmp, 0, 0);
2320 tmp += 0x0324;
2321 }
2322 }
2323 break;
2324 break;
2325 case 0xc0:
2326 case 0xc3:
2327 case 0xc4:
2328 case 0xc8:
2329 case 0xce:
2330 case 0xcf:
2331 tmp = 0x02180000;
2332 mmio_list(0x405830, tmp, 0, 0);
2333 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
2334 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
2335 u32 reg = TPC_UNIT(gpc, tpc, 0x0520);
2336 mmio_list(reg, tmp, 0, 0);
2337 tmp += 0x0324;
2338 }
2339 }
2340 break;
2341 default:
2342 BUG_ON(1);
2343 break;
2344 }
2345
2346 for (tpc = 0, id = 0; tpc < 4; tpc++) {
2347 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
2348 if (tpc < priv->tpc_nr[gpc]) {
2349 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
2350 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
2351 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
2352 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
2353 id++;
2354 }
2355
2356 nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
2357 nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
2358 }
2359 } 1101 }
2360 1102
2361 tmp = 0; 1103 /* PGD pointer */
2362 for (i = 0; i < priv->gpc_nr; i++) 1104 nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));
2363 tmp |= priv->tpc_nr[i] << (i * 4); 1105 nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));
2364 nv_wr32(priv, 0x406028, tmp); 1106 nv_wo32(chan, 0x0208, 0xffffffff);
2365 nv_wr32(priv, 0x405870, tmp); 1107 nv_wo32(chan, 0x020c, 0x000000ff);
2366
2367 nv_wr32(priv, 0x40602c, 0x00000000);
2368 nv_wr32(priv, 0x405874, 0x00000000);
2369 nv_wr32(priv, 0x406030, 0x00000000);
2370 nv_wr32(priv, 0x405878, 0x00000000);
2371 nv_wr32(priv, 0x406034, 0x00000000);
2372 nv_wr32(priv, 0x40587c, 0x00000000);
2373
2374 if (1) {
2375 u8 tpcnr[GPC_MAX], data[TPC_MAX];
2376
2377 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
2378 memset(data, 0x1f, sizeof(data));
2379 1108
2380 gpc = -1; 1109 /* PGT[0] pointer */
2381 for (tpc = 0; tpc < priv->tpc_total; tpc++) { 1110 nv_wo32(chan, 0x1000, 0x00000000);
2382 do { 1111 nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);
2383 gpc = (gpc + 1) % priv->gpc_nr;
2384 } while (!tpcnr[gpc]);
2385 tpcnr[gpc]--;
2386 data[tpc] = gpc;
2387 }
2388 1112
2389 for (i = 0; i < 4; i++) 1113 /* identity-map the whole "channel" into its own vm */
2390 nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); 1114 for (i = 0; i < chan->size / 4096; i++) {
1115 u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;
1116 nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));
1117 nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));
2391 } 1118 }
2392 1119
2393 if (1) { 1120 /* context pointer (virt) */
2394 u32 data[6] = {}, data2[2] = {}; 1121 nv_wo32(chan, 0x0210, 0x00080004);
2395 u8 tpcnr[GPC_MAX]; 1122 nv_wo32(chan, 0x0214, 0x00000000);
2396 u8 shift, ntpcv;
2397
2398 /* calculate first set of magics */
2399 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
2400 1123
2401 gpc = -1; 1124 bar->flush(bar);
2402 for (tpc = 0; tpc < priv->tpc_total; tpc++) {
2403 do {
2404 gpc = (gpc + 1) % priv->gpc_nr;
2405 } while (!tpcnr[gpc]);
2406 tpcnr[gpc]--;
2407 1125
2408 data[tpc / 6] |= gpc << ((tpc % 6) * 5); 1126 nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
2409 } 1127 nv_wr32(priv, 0x100cbc, 0x80000001);
1128 nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
2410 1129
2411 for (; tpc < 32; tpc++) 1130 /* setup default state for mmio list construction */
2412 data[tpc / 6] |= 7 << ((tpc % 6) * 5); 1131 info.priv = priv;
1132 info.data = priv->mmio_data;
1133 info.mmio = priv->mmio_list;
1134 info.addr = 0x2000 + (i * 8);
1135 info.buffer_nr = 0;
2413 1136
2414 /* and the second... */ 1137 /* make channel current */
2415 shift = 0; 1138 if (priv->firmware) {
2416 ntpcv = priv->tpc_total; 1139 nv_wr32(priv, 0x409840, 0x00000030);
2417 while (!(ntpcv & (1 << 4))) { 1140 nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
2418 ntpcv <<= 1; 1141 nv_wr32(priv, 0x409504, 0x00000003);
2419 shift++; 1142 if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
2420 } 1143 nv_error(priv, "load_ctx timeout\n");
2421 1144
2422 data2[0] = (ntpcv << 16); 1145 nv_wo32(chan, 0x8001c, 1);
2423 data2[0] |= (shift << 21); 1146 nv_wo32(chan, 0x80020, 0);
2424 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 1147 nv_wo32(chan, 0x80028, 0);
2425 for (i = 1; i < 7; i++) 1148 nv_wo32(chan, 0x8002c, 0);
2426 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 1149 bar->flush(bar);
2427 1150 } else {
2428 /* GPC_BROADCAST */ 1151 nv_wr32(priv, 0x409840, 0x80000000);
2429 nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | 1152 nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
2430 priv->magic_not_rop_nr); 1153 nv_wr32(priv, 0x409504, 0x00000001);
2431 for (i = 0; i < 6; i++) 1154 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000))
2432 nv_wr32(priv, 0x418b08 + (i * 4), data[i]); 1155 nv_error(priv, "HUB_SET_CHAN timeout\n");
2433
2434 /* GPC_BROADCAST.TP_BROADCAST */
2435 nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
2436 priv->magic_not_rop_nr |
2437 data2[0]);
2438 nv_wr32(priv, 0x419be4, data2[1]);
2439 for (i = 0; i < 6; i++)
2440 nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
2441
2442 /* UNK78xx */
2443 nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
2444 priv->magic_not_rop_nr);
2445 for (i = 0; i < 6; i++)
2446 nv_wr32(priv, 0x40780c + (i * 4), data[i]);
2447 } 1156 }
2448 1157
2449 if (1) { 1158 oclass->main(priv, &info);
2450 u32 tpc_mask = 0, tpc_set = 0;
2451 u8 tpcnr[GPC_MAX], a, b;
2452
2453 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
2454 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
2455 tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
2456 1159
2457 for (i = 0, gpc = -1, b = -1; i < 32; i++) { 1160 /* trigger a context unload by unsetting the "next channel valid" bit
2458 a = (i * (priv->tpc_total - 1)) / 32; 1161 * and faking a context switch interrupt
2459 if (a != b) { 1162 */
2460 b = a; 1163 nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
2461 do { 1164 nv_wr32(priv, 0x409000, 0x00000100);
2462 gpc = (gpc + 1) % priv->gpc_nr; 1165 if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
2463 } while (!tpcnr[gpc]); 1166 nv_error(priv, "grctx template channel unload timeout\n");
2464 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; 1167 ret = -EBUSY;
2465 1168 goto done;
2466 tpc_set |= 1 << ((gpc * 8) + tpc);
2467 }
2468
2469 nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set);
2470 nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask);
2471 }
2472 }
2473
2474 nv_wr32(priv, 0x400208, 0x80000000);
2475
2476 nv_icmd(priv, 0x00001000, 0x00000004);
2477 nv_icmd(priv, 0x000000a9, 0x0000ffff);
2478 nv_icmd(priv, 0x00000038, 0x0fac6881);
2479 nv_icmd(priv, 0x0000003d, 0x00000001);
2480 nv_icmd(priv, 0x000000e8, 0x00000400);
2481 nv_icmd(priv, 0x000000e9, 0x00000400);
2482 nv_icmd(priv, 0x000000ea, 0x00000400);
2483 nv_icmd(priv, 0x000000eb, 0x00000400);
2484 nv_icmd(priv, 0x000000ec, 0x00000400);
2485 nv_icmd(priv, 0x000000ed, 0x00000400);
2486 nv_icmd(priv, 0x000000ee, 0x00000400);
2487 nv_icmd(priv, 0x000000ef, 0x00000400);
2488 nv_icmd(priv, 0x00000078, 0x00000300);
2489 nv_icmd(priv, 0x00000079, 0x00000300);
2490 nv_icmd(priv, 0x0000007a, 0x00000300);
2491 nv_icmd(priv, 0x0000007b, 0x00000300);
2492 nv_icmd(priv, 0x0000007c, 0x00000300);
2493 nv_icmd(priv, 0x0000007d, 0x00000300);
2494 nv_icmd(priv, 0x0000007e, 0x00000300);
2495 nv_icmd(priv, 0x0000007f, 0x00000300);
2496 nv_icmd(priv, 0x00000050, 0x00000011);
2497 nv_icmd(priv, 0x00000058, 0x00000008);
2498 nv_icmd(priv, 0x00000059, 0x00000008);
2499 nv_icmd(priv, 0x0000005a, 0x00000008);
2500 nv_icmd(priv, 0x0000005b, 0x00000008);
2501 nv_icmd(priv, 0x0000005c, 0x00000008);
2502 nv_icmd(priv, 0x0000005d, 0x00000008);
2503 nv_icmd(priv, 0x0000005e, 0x00000008);
2504 nv_icmd(priv, 0x0000005f, 0x00000008);
2505 nv_icmd(priv, 0x00000208, 0x00000001);
2506 nv_icmd(priv, 0x00000209, 0x00000001);
2507 nv_icmd(priv, 0x0000020a, 0x00000001);
2508 nv_icmd(priv, 0x0000020b, 0x00000001);
2509 nv_icmd(priv, 0x0000020c, 0x00000001);
2510 nv_icmd(priv, 0x0000020d, 0x00000001);
2511 nv_icmd(priv, 0x0000020e, 0x00000001);
2512 nv_icmd(priv, 0x0000020f, 0x00000001);
2513 nv_icmd(priv, 0x00000081, 0x00000001);
2514 nv_icmd(priv, 0x00000085, 0x00000004);
2515 nv_icmd(priv, 0x00000088, 0x00000400);
2516 nv_icmd(priv, 0x00000090, 0x00000300);
2517 nv_icmd(priv, 0x00000098, 0x00001001);
2518 nv_icmd(priv, 0x000000e3, 0x00000001);
2519 nv_icmd(priv, 0x000000da, 0x00000001);
2520 nv_icmd(priv, 0x000000f8, 0x00000003);
2521 nv_icmd(priv, 0x000000fa, 0x00000001);
2522 nv_icmd(priv, 0x0000009f, 0x0000ffff);
2523 nv_icmd(priv, 0x000000a0, 0x0000ffff);
2524 nv_icmd(priv, 0x000000a1, 0x0000ffff);
2525 nv_icmd(priv, 0x000000a2, 0x0000ffff);
2526 nv_icmd(priv, 0x000000b1, 0x00000001);
2527 nv_icmd(priv, 0x000000b2, 0x00000000);
2528 nv_icmd(priv, 0x000000b3, 0x00000000);
2529 nv_icmd(priv, 0x000000b4, 0x00000000);
2530 nv_icmd(priv, 0x000000b5, 0x00000000);
2531 nv_icmd(priv, 0x000000b6, 0x00000000);
2532 nv_icmd(priv, 0x000000b7, 0x00000000);
2533 nv_icmd(priv, 0x000000b8, 0x00000000);
2534 nv_icmd(priv, 0x000000b9, 0x00000000);
2535 nv_icmd(priv, 0x000000ba, 0x00000000);
2536 nv_icmd(priv, 0x000000bb, 0x00000000);
2537 nv_icmd(priv, 0x000000bc, 0x00000000);
2538 nv_icmd(priv, 0x000000bd, 0x00000000);
2539 nv_icmd(priv, 0x000000be, 0x00000000);
2540 nv_icmd(priv, 0x000000bf, 0x00000000);
2541 nv_icmd(priv, 0x000000c0, 0x00000000);
2542 nv_icmd(priv, 0x000000c1, 0x00000000);
2543 nv_icmd(priv, 0x000000c2, 0x00000000);
2544 nv_icmd(priv, 0x000000c3, 0x00000000);
2545 nv_icmd(priv, 0x000000c4, 0x00000000);
2546 nv_icmd(priv, 0x000000c5, 0x00000000);
2547 nv_icmd(priv, 0x000000c6, 0x00000000);
2548 nv_icmd(priv, 0x000000c7, 0x00000000);
2549 nv_icmd(priv, 0x000000c8, 0x00000000);
2550 nv_icmd(priv, 0x000000c9, 0x00000000);
2551 nv_icmd(priv, 0x000000ca, 0x00000000);
2552 nv_icmd(priv, 0x000000cb, 0x00000000);
2553 nv_icmd(priv, 0x000000cc, 0x00000000);
2554 nv_icmd(priv, 0x000000cd, 0x00000000);
2555 nv_icmd(priv, 0x000000ce, 0x00000000);
2556 nv_icmd(priv, 0x000000cf, 0x00000000);
2557 nv_icmd(priv, 0x000000d0, 0x00000000);
2558 nv_icmd(priv, 0x000000d1, 0x00000000);
2559 nv_icmd(priv, 0x000000d2, 0x00000000);
2560 nv_icmd(priv, 0x000000d3, 0x00000000);
2561 nv_icmd(priv, 0x000000d4, 0x00000000);
2562 nv_icmd(priv, 0x000000d5, 0x00000000);
2563 nv_icmd(priv, 0x000000d6, 0x00000000);
2564 nv_icmd(priv, 0x000000d7, 0x00000000);
2565 nv_icmd(priv, 0x000000d8, 0x00000000);
2566 nv_icmd(priv, 0x000000d9, 0x00000000);
2567 nv_icmd(priv, 0x00000210, 0x00000040);
2568 nv_icmd(priv, 0x00000211, 0x00000040);
2569 nv_icmd(priv, 0x00000212, 0x00000040);
2570 nv_icmd(priv, 0x00000213, 0x00000040);
2571 nv_icmd(priv, 0x00000214, 0x00000040);
2572 nv_icmd(priv, 0x00000215, 0x00000040);
2573 nv_icmd(priv, 0x00000216, 0x00000040);
2574 nv_icmd(priv, 0x00000217, 0x00000040);
2575 switch (nv_device(priv)->chipset) {
2576 case 0xd9:
2577 case 0xd7:
2578 for (i = 0x400; i <= 0x417; i++)
2579 nv_icmd(priv, i, 0x00000040);
2580 break;
2581 case 0xc0:
2582 case 0xc3:
2583 case 0xc4:
2584 case 0xc1:
2585 case 0xc8:
2586 case 0xce:
2587 case 0xcf:
2588 break;
2589 default:
2590 BUG_ON(1);
2591 break;
2592 }
2593 nv_icmd(priv, 0x00000218, 0x0000c080);
2594 nv_icmd(priv, 0x00000219, 0x0000c080);
2595 nv_icmd(priv, 0x0000021a, 0x0000c080);
2596 nv_icmd(priv, 0x0000021b, 0x0000c080);
2597 nv_icmd(priv, 0x0000021c, 0x0000c080);
2598 nv_icmd(priv, 0x0000021d, 0x0000c080);
2599 nv_icmd(priv, 0x0000021e, 0x0000c080);
2600 nv_icmd(priv, 0x0000021f, 0x0000c080);
2601 switch (nv_device(priv)->chipset) {
2602 case 0xd9:
2603 case 0xd7:
2604 for (i = 0x440; i <= 0x457; i++)
2605 nv_icmd(priv, i, 0x0000c080);
2606 break;
2607 case 0xc0:
2608 case 0xc3:
2609 case 0xc4:
2610 case 0xc1:
2611 case 0xc8:
2612 case 0xce:
2613 case 0xcf:
2614 break;
2615 default:
2616 BUG_ON(1);
2617 break;
2618 }
2619 nv_icmd(priv, 0x000000ad, 0x0000013e);
2620 nv_icmd(priv, 0x000000e1, 0x00000010);
2621 nv_icmd(priv, 0x00000290, 0x00000000);
2622 nv_icmd(priv, 0x00000291, 0x00000000);
2623 nv_icmd(priv, 0x00000292, 0x00000000);
2624 nv_icmd(priv, 0x00000293, 0x00000000);
2625 nv_icmd(priv, 0x00000294, 0x00000000);
2626 nv_icmd(priv, 0x00000295, 0x00000000);
2627 nv_icmd(priv, 0x00000296, 0x00000000);
2628 nv_icmd(priv, 0x00000297, 0x00000000);
2629 nv_icmd(priv, 0x00000298, 0x00000000);
2630 nv_icmd(priv, 0x00000299, 0x00000000);
2631 nv_icmd(priv, 0x0000029a, 0x00000000);
2632 nv_icmd(priv, 0x0000029b, 0x00000000);
2633 nv_icmd(priv, 0x0000029c, 0x00000000);
2634 nv_icmd(priv, 0x0000029d, 0x00000000);
2635 nv_icmd(priv, 0x0000029e, 0x00000000);
2636 nv_icmd(priv, 0x0000029f, 0x00000000);
2637 nv_icmd(priv, 0x000003b0, 0x00000000);
2638 nv_icmd(priv, 0x000003b1, 0x00000000);
2639 nv_icmd(priv, 0x000003b2, 0x00000000);
2640 nv_icmd(priv, 0x000003b3, 0x00000000);
2641 nv_icmd(priv, 0x000003b4, 0x00000000);
2642 nv_icmd(priv, 0x000003b5, 0x00000000);
2643 nv_icmd(priv, 0x000003b6, 0x00000000);
2644 nv_icmd(priv, 0x000003b7, 0x00000000);
2645 nv_icmd(priv, 0x000003b8, 0x00000000);
2646 nv_icmd(priv, 0x000003b9, 0x00000000);
2647 nv_icmd(priv, 0x000003ba, 0x00000000);
2648 nv_icmd(priv, 0x000003bb, 0x00000000);
2649 nv_icmd(priv, 0x000003bc, 0x00000000);
2650 nv_icmd(priv, 0x000003bd, 0x00000000);
2651 nv_icmd(priv, 0x000003be, 0x00000000);
2652 nv_icmd(priv, 0x000003bf, 0x00000000);
2653 nv_icmd(priv, 0x000002a0, 0x00000000);
2654 nv_icmd(priv, 0x000002a1, 0x00000000);
2655 nv_icmd(priv, 0x000002a2, 0x00000000);
2656 nv_icmd(priv, 0x000002a3, 0x00000000);
2657 nv_icmd(priv, 0x000002a4, 0x00000000);
2658 nv_icmd(priv, 0x000002a5, 0x00000000);
2659 nv_icmd(priv, 0x000002a6, 0x00000000);
2660 nv_icmd(priv, 0x000002a7, 0x00000000);
2661 nv_icmd(priv, 0x000002a8, 0x00000000);
2662 nv_icmd(priv, 0x000002a9, 0x00000000);
2663 nv_icmd(priv, 0x000002aa, 0x00000000);
2664 nv_icmd(priv, 0x000002ab, 0x00000000);
2665 nv_icmd(priv, 0x000002ac, 0x00000000);
2666 nv_icmd(priv, 0x000002ad, 0x00000000);
2667 nv_icmd(priv, 0x000002ae, 0x00000000);
2668 nv_icmd(priv, 0x000002af, 0x00000000);
2669 nv_icmd(priv, 0x00000420, 0x00000000);
2670 nv_icmd(priv, 0x00000421, 0x00000000);
2671 nv_icmd(priv, 0x00000422, 0x00000000);
2672 nv_icmd(priv, 0x00000423, 0x00000000);
2673 nv_icmd(priv, 0x00000424, 0x00000000);
2674 nv_icmd(priv, 0x00000425, 0x00000000);
2675 nv_icmd(priv, 0x00000426, 0x00000000);
2676 nv_icmd(priv, 0x00000427, 0x00000000);
2677 nv_icmd(priv, 0x00000428, 0x00000000);
2678 nv_icmd(priv, 0x00000429, 0x00000000);
2679 nv_icmd(priv, 0x0000042a, 0x00000000);
2680 nv_icmd(priv, 0x0000042b, 0x00000000);
2681 nv_icmd(priv, 0x0000042c, 0x00000000);
2682 nv_icmd(priv, 0x0000042d, 0x00000000);
2683 nv_icmd(priv, 0x0000042e, 0x00000000);
2684 nv_icmd(priv, 0x0000042f, 0x00000000);
2685 nv_icmd(priv, 0x000002b0, 0x00000000);
2686 nv_icmd(priv, 0x000002b1, 0x00000000);
2687 nv_icmd(priv, 0x000002b2, 0x00000000);
2688 nv_icmd(priv, 0x000002b3, 0x00000000);
2689 nv_icmd(priv, 0x000002b4, 0x00000000);
2690 nv_icmd(priv, 0x000002b5, 0x00000000);
2691 nv_icmd(priv, 0x000002b6, 0x00000000);
2692 nv_icmd(priv, 0x000002b7, 0x00000000);
2693 nv_icmd(priv, 0x000002b8, 0x00000000);
2694 nv_icmd(priv, 0x000002b9, 0x00000000);
2695 nv_icmd(priv, 0x000002ba, 0x00000000);
2696 nv_icmd(priv, 0x000002bb, 0x00000000);
2697 nv_icmd(priv, 0x000002bc, 0x00000000);
2698 nv_icmd(priv, 0x000002bd, 0x00000000);
2699 nv_icmd(priv, 0x000002be, 0x00000000);
2700 nv_icmd(priv, 0x000002bf, 0x00000000);
2701 nv_icmd(priv, 0x00000430, 0x00000000);
2702 nv_icmd(priv, 0x00000431, 0x00000000);
2703 nv_icmd(priv, 0x00000432, 0x00000000);
2704 nv_icmd(priv, 0x00000433, 0x00000000);
2705 nv_icmd(priv, 0x00000434, 0x00000000);
2706 nv_icmd(priv, 0x00000435, 0x00000000);
2707 nv_icmd(priv, 0x00000436, 0x00000000);
2708 nv_icmd(priv, 0x00000437, 0x00000000);
2709 nv_icmd(priv, 0x00000438, 0x00000000);
2710 nv_icmd(priv, 0x00000439, 0x00000000);
2711 nv_icmd(priv, 0x0000043a, 0x00000000);
2712 nv_icmd(priv, 0x0000043b, 0x00000000);
2713 nv_icmd(priv, 0x0000043c, 0x00000000);
2714 nv_icmd(priv, 0x0000043d, 0x00000000);
2715 nv_icmd(priv, 0x0000043e, 0x00000000);
2716 nv_icmd(priv, 0x0000043f, 0x00000000);
2717 nv_icmd(priv, 0x000002c0, 0x00000000);
2718 nv_icmd(priv, 0x000002c1, 0x00000000);
2719 nv_icmd(priv, 0x000002c2, 0x00000000);
2720 nv_icmd(priv, 0x000002c3, 0x00000000);
2721 nv_icmd(priv, 0x000002c4, 0x00000000);
2722 nv_icmd(priv, 0x000002c5, 0x00000000);
2723 nv_icmd(priv, 0x000002c6, 0x00000000);
2724 nv_icmd(priv, 0x000002c7, 0x00000000);
2725 nv_icmd(priv, 0x000002c8, 0x00000000);
2726 nv_icmd(priv, 0x000002c9, 0x00000000);
2727 nv_icmd(priv, 0x000002ca, 0x00000000);
2728 nv_icmd(priv, 0x000002cb, 0x00000000);
2729 nv_icmd(priv, 0x000002cc, 0x00000000);
2730 nv_icmd(priv, 0x000002cd, 0x00000000);
2731 nv_icmd(priv, 0x000002ce, 0x00000000);
2732 nv_icmd(priv, 0x000002cf, 0x00000000);
2733 nv_icmd(priv, 0x000004d0, 0x00000000);
2734 nv_icmd(priv, 0x000004d1, 0x00000000);
2735 nv_icmd(priv, 0x000004d2, 0x00000000);
2736 nv_icmd(priv, 0x000004d3, 0x00000000);
2737 nv_icmd(priv, 0x000004d4, 0x00000000);
2738 nv_icmd(priv, 0x000004d5, 0x00000000);
2739 nv_icmd(priv, 0x000004d6, 0x00000000);
2740 nv_icmd(priv, 0x000004d7, 0x00000000);
2741 nv_icmd(priv, 0x000004d8, 0x00000000);
2742 nv_icmd(priv, 0x000004d9, 0x00000000);
2743 nv_icmd(priv, 0x000004da, 0x00000000);
2744 nv_icmd(priv, 0x000004db, 0x00000000);
2745 nv_icmd(priv, 0x000004dc, 0x00000000);
2746 nv_icmd(priv, 0x000004dd, 0x00000000);
2747 nv_icmd(priv, 0x000004de, 0x00000000);
2748 nv_icmd(priv, 0x000004df, 0x00000000);
2749 nv_icmd(priv, 0x00000720, 0x00000000);
2750 nv_icmd(priv, 0x00000721, 0x00000000);
2751 nv_icmd(priv, 0x00000722, 0x00000000);
2752 nv_icmd(priv, 0x00000723, 0x00000000);
2753 nv_icmd(priv, 0x00000724, 0x00000000);
2754 nv_icmd(priv, 0x00000725, 0x00000000);
2755 nv_icmd(priv, 0x00000726, 0x00000000);
2756 nv_icmd(priv, 0x00000727, 0x00000000);
2757 nv_icmd(priv, 0x00000728, 0x00000000);
2758 nv_icmd(priv, 0x00000729, 0x00000000);
2759 nv_icmd(priv, 0x0000072a, 0x00000000);
2760 nv_icmd(priv, 0x0000072b, 0x00000000);
2761 nv_icmd(priv, 0x0000072c, 0x00000000);
2762 nv_icmd(priv, 0x0000072d, 0x00000000);
2763 nv_icmd(priv, 0x0000072e, 0x00000000);
2764 nv_icmd(priv, 0x0000072f, 0x00000000);
2765 nv_icmd(priv, 0x000008c0, 0x00000000);
2766 nv_icmd(priv, 0x000008c1, 0x00000000);
2767 nv_icmd(priv, 0x000008c2, 0x00000000);
2768 nv_icmd(priv, 0x000008c3, 0x00000000);
2769 nv_icmd(priv, 0x000008c4, 0x00000000);
2770 nv_icmd(priv, 0x000008c5, 0x00000000);
2771 nv_icmd(priv, 0x000008c6, 0x00000000);
2772 nv_icmd(priv, 0x000008c7, 0x00000000);
2773 nv_icmd(priv, 0x000008c8, 0x00000000);
2774 nv_icmd(priv, 0x000008c9, 0x00000000);
2775 nv_icmd(priv, 0x000008ca, 0x00000000);
2776 nv_icmd(priv, 0x000008cb, 0x00000000);
2777 nv_icmd(priv, 0x000008cc, 0x00000000);
2778 nv_icmd(priv, 0x000008cd, 0x00000000);
2779 nv_icmd(priv, 0x000008ce, 0x00000000);
2780 nv_icmd(priv, 0x000008cf, 0x00000000);
2781 nv_icmd(priv, 0x00000890, 0x00000000);
2782 nv_icmd(priv, 0x00000891, 0x00000000);
2783 nv_icmd(priv, 0x00000892, 0x00000000);
2784 nv_icmd(priv, 0x00000893, 0x00000000);
2785 nv_icmd(priv, 0x00000894, 0x00000000);
2786 nv_icmd(priv, 0x00000895, 0x00000000);
2787 nv_icmd(priv, 0x00000896, 0x00000000);
2788 nv_icmd(priv, 0x00000897, 0x00000000);
2789 nv_icmd(priv, 0x00000898, 0x00000000);
2790 nv_icmd(priv, 0x00000899, 0x00000000);
2791 nv_icmd(priv, 0x0000089a, 0x00000000);
2792 nv_icmd(priv, 0x0000089b, 0x00000000);
2793 nv_icmd(priv, 0x0000089c, 0x00000000);
2794 nv_icmd(priv, 0x0000089d, 0x00000000);
2795 nv_icmd(priv, 0x0000089e, 0x00000000);
2796 nv_icmd(priv, 0x0000089f, 0x00000000);
2797 nv_icmd(priv, 0x000008e0, 0x00000000);
2798 nv_icmd(priv, 0x000008e1, 0x00000000);
2799 nv_icmd(priv, 0x000008e2, 0x00000000);
2800 nv_icmd(priv, 0x000008e3, 0x00000000);
2801 nv_icmd(priv, 0x000008e4, 0x00000000);
2802 nv_icmd(priv, 0x000008e5, 0x00000000);
2803 nv_icmd(priv, 0x000008e6, 0x00000000);
2804 nv_icmd(priv, 0x000008e7, 0x00000000);
2805 nv_icmd(priv, 0x000008e8, 0x00000000);
2806 nv_icmd(priv, 0x000008e9, 0x00000000);
2807 nv_icmd(priv, 0x000008ea, 0x00000000);
2808 nv_icmd(priv, 0x000008eb, 0x00000000);
2809 nv_icmd(priv, 0x000008ec, 0x00000000);
2810 nv_icmd(priv, 0x000008ed, 0x00000000);
2811 nv_icmd(priv, 0x000008ee, 0x00000000);
2812 nv_icmd(priv, 0x000008ef, 0x00000000);
2813 nv_icmd(priv, 0x000008a0, 0x00000000);
2814 nv_icmd(priv, 0x000008a1, 0x00000000);
2815 nv_icmd(priv, 0x000008a2, 0x00000000);
2816 nv_icmd(priv, 0x000008a3, 0x00000000);
2817 nv_icmd(priv, 0x000008a4, 0x00000000);
2818 nv_icmd(priv, 0x000008a5, 0x00000000);
2819 nv_icmd(priv, 0x000008a6, 0x00000000);
2820 nv_icmd(priv, 0x000008a7, 0x00000000);
2821 nv_icmd(priv, 0x000008a8, 0x00000000);
2822 nv_icmd(priv, 0x000008a9, 0x00000000);
2823 nv_icmd(priv, 0x000008aa, 0x00000000);
2824 nv_icmd(priv, 0x000008ab, 0x00000000);
2825 nv_icmd(priv, 0x000008ac, 0x00000000);
2826 nv_icmd(priv, 0x000008ad, 0x00000000);
2827 nv_icmd(priv, 0x000008ae, 0x00000000);
2828 nv_icmd(priv, 0x000008af, 0x00000000);
2829 nv_icmd(priv, 0x000008f0, 0x00000000);
2830 nv_icmd(priv, 0x000008f1, 0x00000000);
2831 nv_icmd(priv, 0x000008f2, 0x00000000);
2832 nv_icmd(priv, 0x000008f3, 0x00000000);
2833 nv_icmd(priv, 0x000008f4, 0x00000000);
2834 nv_icmd(priv, 0x000008f5, 0x00000000);
2835 nv_icmd(priv, 0x000008f6, 0x00000000);
2836 nv_icmd(priv, 0x000008f7, 0x00000000);
2837 nv_icmd(priv, 0x000008f8, 0x00000000);
2838 nv_icmd(priv, 0x000008f9, 0x00000000);
2839 nv_icmd(priv, 0x000008fa, 0x00000000);
2840 nv_icmd(priv, 0x000008fb, 0x00000000);
2841 nv_icmd(priv, 0x000008fc, 0x00000000);
2842 nv_icmd(priv, 0x000008fd, 0x00000000);
2843 nv_icmd(priv, 0x000008fe, 0x00000000);
2844 nv_icmd(priv, 0x000008ff, 0x00000000);
2845 nv_icmd(priv, 0x0000094c, 0x000000ff);
2846 nv_icmd(priv, 0x0000094d, 0xffffffff);
2847 nv_icmd(priv, 0x0000094e, 0x00000002);
2848 nv_icmd(priv, 0x000002ec, 0x00000001);
2849 nv_icmd(priv, 0x00000303, 0x00000001);
2850 nv_icmd(priv, 0x000002e6, 0x00000001);
2851 nv_icmd(priv, 0x00000466, 0x00000052);
2852 nv_icmd(priv, 0x00000301, 0x3f800000);
2853 nv_icmd(priv, 0x00000304, 0x30201000);
2854 nv_icmd(priv, 0x00000305, 0x70605040);
2855 nv_icmd(priv, 0x00000306, 0xb8a89888);
2856 nv_icmd(priv, 0x00000307, 0xf8e8d8c8);
2857 nv_icmd(priv, 0x0000030a, 0x00ffff00);
2858 nv_icmd(priv, 0x0000030b, 0x0000001a);
2859 nv_icmd(priv, 0x0000030c, 0x00000001);
2860 nv_icmd(priv, 0x00000318, 0x00000001);
2861 nv_icmd(priv, 0x00000340, 0x00000000);
2862 nv_icmd(priv, 0x00000375, 0x00000001);
2863 nv_icmd(priv, 0x00000351, 0x00000100);
2864 nv_icmd(priv, 0x0000037d, 0x00000006);
2865 nv_icmd(priv, 0x000003a0, 0x00000002);
2866 nv_icmd(priv, 0x000003aa, 0x00000001);
2867 nv_icmd(priv, 0x000003a9, 0x00000001);
2868 nv_icmd(priv, 0x00000380, 0x00000001);
2869 nv_icmd(priv, 0x00000360, 0x00000040);
2870 nv_icmd(priv, 0x00000366, 0x00000000);
2871 nv_icmd(priv, 0x00000367, 0x00000000);
2872 nv_icmd(priv, 0x00000368, 0x00001fff);
2873 nv_icmd(priv, 0x00000370, 0x00000000);
2874 nv_icmd(priv, 0x00000371, 0x00000000);
2875 nv_icmd(priv, 0x00000372, 0x003fffff);
2876 nv_icmd(priv, 0x0000037a, 0x00000012);
2877 nv_icmd(priv, 0x000005e0, 0x00000022);
2878 nv_icmd(priv, 0x000005e1, 0x00000022);
2879 nv_icmd(priv, 0x000005e2, 0x00000022);
2880 nv_icmd(priv, 0x000005e3, 0x00000022);
2881 nv_icmd(priv, 0x000005e4, 0x00000022);
2882 nv_icmd(priv, 0x00000619, 0x00000003);
2883 nv_icmd(priv, 0x00000811, 0x00000003);
2884 nv_icmd(priv, 0x00000812, 0x00000004);
2885 nv_icmd(priv, 0x00000813, 0x00000006);
2886 nv_icmd(priv, 0x00000814, 0x00000008);
2887 nv_icmd(priv, 0x00000815, 0x0000000b);
2888 nv_icmd(priv, 0x00000800, 0x00000001);
2889 nv_icmd(priv, 0x00000801, 0x00000001);
2890 nv_icmd(priv, 0x00000802, 0x00000001);
2891 nv_icmd(priv, 0x00000803, 0x00000001);
2892 nv_icmd(priv, 0x00000804, 0x00000001);
2893 nv_icmd(priv, 0x00000805, 0x00000001);
2894 nv_icmd(priv, 0x00000632, 0x00000001);
2895 nv_icmd(priv, 0x00000633, 0x00000002);
2896 nv_icmd(priv, 0x00000634, 0x00000003);
2897 nv_icmd(priv, 0x00000635, 0x00000004);
2898 nv_icmd(priv, 0x00000654, 0x3f800000);
2899 nv_icmd(priv, 0x00000657, 0x3f800000);
2900 nv_icmd(priv, 0x00000655, 0x3f800000);
2901 nv_icmd(priv, 0x00000656, 0x3f800000);
2902 nv_icmd(priv, 0x000006cd, 0x3f800000);
2903 nv_icmd(priv, 0x000007f5, 0x3f800000);
2904 nv_icmd(priv, 0x000007dc, 0x39291909);
2905 nv_icmd(priv, 0x000007dd, 0x79695949);
2906 nv_icmd(priv, 0x000007de, 0xb9a99989);
2907 nv_icmd(priv, 0x000007df, 0xf9e9d9c9);
2908 nv_icmd(priv, 0x000007e8, 0x00003210);
2909 nv_icmd(priv, 0x000007e9, 0x00007654);
2910 nv_icmd(priv, 0x000007ea, 0x00000098);
2911 nv_icmd(priv, 0x000007ec, 0x39291909);
2912 nv_icmd(priv, 0x000007ed, 0x79695949);
2913 nv_icmd(priv, 0x000007ee, 0xb9a99989);
2914 nv_icmd(priv, 0x000007ef, 0xf9e9d9c9);
2915 nv_icmd(priv, 0x000007f0, 0x00003210);
2916 nv_icmd(priv, 0x000007f1, 0x00007654);
2917 nv_icmd(priv, 0x000007f2, 0x00000098);
2918 nv_icmd(priv, 0x000005a5, 0x00000001);
2919 nv_icmd(priv, 0x00000980, 0x00000000);
2920 nv_icmd(priv, 0x00000981, 0x00000000);
2921 nv_icmd(priv, 0x00000982, 0x00000000);
2922 nv_icmd(priv, 0x00000983, 0x00000000);
2923 nv_icmd(priv, 0x00000984, 0x00000000);
2924 nv_icmd(priv, 0x00000985, 0x00000000);
2925 nv_icmd(priv, 0x00000986, 0x00000000);
2926 nv_icmd(priv, 0x00000987, 0x00000000);
2927 nv_icmd(priv, 0x00000988, 0x00000000);
2928 nv_icmd(priv, 0x00000989, 0x00000000);
2929 nv_icmd(priv, 0x0000098a, 0x00000000);
2930 nv_icmd(priv, 0x0000098b, 0x00000000);
2931 nv_icmd(priv, 0x0000098c, 0x00000000);
2932 nv_icmd(priv, 0x0000098d, 0x00000000);
2933 nv_icmd(priv, 0x0000098e, 0x00000000);
2934 nv_icmd(priv, 0x0000098f, 0x00000000);
2935 nv_icmd(priv, 0x00000990, 0x00000000);
2936 nv_icmd(priv, 0x00000991, 0x00000000);
2937 nv_icmd(priv, 0x00000992, 0x00000000);
2938 nv_icmd(priv, 0x00000993, 0x00000000);
2939 nv_icmd(priv, 0x00000994, 0x00000000);
2940 nv_icmd(priv, 0x00000995, 0x00000000);
2941 nv_icmd(priv, 0x00000996, 0x00000000);
2942 nv_icmd(priv, 0x00000997, 0x00000000);
2943 nv_icmd(priv, 0x00000998, 0x00000000);
2944 nv_icmd(priv, 0x00000999, 0x00000000);
2945 nv_icmd(priv, 0x0000099a, 0x00000000);
2946 nv_icmd(priv, 0x0000099b, 0x00000000);
2947 nv_icmd(priv, 0x0000099c, 0x00000000);
2948 nv_icmd(priv, 0x0000099d, 0x00000000);
2949 nv_icmd(priv, 0x0000099e, 0x00000000);
2950 nv_icmd(priv, 0x0000099f, 0x00000000);
2951 nv_icmd(priv, 0x000009a0, 0x00000000);
2952 nv_icmd(priv, 0x000009a1, 0x00000000);
2953 nv_icmd(priv, 0x000009a2, 0x00000000);
2954 nv_icmd(priv, 0x000009a3, 0x00000000);
2955 nv_icmd(priv, 0x000009a4, 0x00000000);
2956 nv_icmd(priv, 0x000009a5, 0x00000000);
2957 nv_icmd(priv, 0x000009a6, 0x00000000);
2958 nv_icmd(priv, 0x000009a7, 0x00000000);
2959 nv_icmd(priv, 0x000009a8, 0x00000000);
2960 nv_icmd(priv, 0x000009a9, 0x00000000);
2961 nv_icmd(priv, 0x000009aa, 0x00000000);
2962 nv_icmd(priv, 0x000009ab, 0x00000000);
2963 nv_icmd(priv, 0x000009ac, 0x00000000);
2964 nv_icmd(priv, 0x000009ad, 0x00000000);
2965 nv_icmd(priv, 0x000009ae, 0x00000000);
2966 nv_icmd(priv, 0x000009af, 0x00000000);
2967 nv_icmd(priv, 0x000009b0, 0x00000000);
2968 nv_icmd(priv, 0x000009b1, 0x00000000);
2969 nv_icmd(priv, 0x000009b2, 0x00000000);
2970 nv_icmd(priv, 0x000009b3, 0x00000000);
2971 nv_icmd(priv, 0x000009b4, 0x00000000);
2972 nv_icmd(priv, 0x000009b5, 0x00000000);
2973 nv_icmd(priv, 0x000009b6, 0x00000000);
2974 nv_icmd(priv, 0x000009b7, 0x00000000);
2975 nv_icmd(priv, 0x000009b8, 0x00000000);
2976 nv_icmd(priv, 0x000009b9, 0x00000000);
2977 nv_icmd(priv, 0x000009ba, 0x00000000);
2978 nv_icmd(priv, 0x000009bb, 0x00000000);
2979 nv_icmd(priv, 0x000009bc, 0x00000000);
2980 nv_icmd(priv, 0x000009bd, 0x00000000);
2981 nv_icmd(priv, 0x000009be, 0x00000000);
2982 nv_icmd(priv, 0x000009bf, 0x00000000);
2983 nv_icmd(priv, 0x000009c0, 0x00000000);
2984 nv_icmd(priv, 0x000009c1, 0x00000000);
2985 nv_icmd(priv, 0x000009c2, 0x00000000);
2986 nv_icmd(priv, 0x000009c3, 0x00000000);
2987 nv_icmd(priv, 0x000009c4, 0x00000000);
2988 nv_icmd(priv, 0x000009c5, 0x00000000);
2989 nv_icmd(priv, 0x000009c6, 0x00000000);
2990 nv_icmd(priv, 0x000009c7, 0x00000000);
2991 nv_icmd(priv, 0x000009c8, 0x00000000);
2992 nv_icmd(priv, 0x000009c9, 0x00000000);
2993 nv_icmd(priv, 0x000009ca, 0x00000000);
2994 nv_icmd(priv, 0x000009cb, 0x00000000);
2995 nv_icmd(priv, 0x000009cc, 0x00000000);
2996 nv_icmd(priv, 0x000009cd, 0x00000000);
2997 nv_icmd(priv, 0x000009ce, 0x00000000);
2998 nv_icmd(priv, 0x000009cf, 0x00000000);
2999 nv_icmd(priv, 0x000009d0, 0x00000000);
3000 nv_icmd(priv, 0x000009d1, 0x00000000);
3001 nv_icmd(priv, 0x000009d2, 0x00000000);
3002 nv_icmd(priv, 0x000009d3, 0x00000000);
3003 nv_icmd(priv, 0x000009d4, 0x00000000);
3004 nv_icmd(priv, 0x000009d5, 0x00000000);
3005 nv_icmd(priv, 0x000009d6, 0x00000000);
3006 nv_icmd(priv, 0x000009d7, 0x00000000);
3007 nv_icmd(priv, 0x000009d8, 0x00000000);
3008 nv_icmd(priv, 0x000009d9, 0x00000000);
3009 nv_icmd(priv, 0x000009da, 0x00000000);
3010 nv_icmd(priv, 0x000009db, 0x00000000);
3011 nv_icmd(priv, 0x000009dc, 0x00000000);
3012 nv_icmd(priv, 0x000009dd, 0x00000000);
3013 nv_icmd(priv, 0x000009de, 0x00000000);
3014 nv_icmd(priv, 0x000009df, 0x00000000);
3015 nv_icmd(priv, 0x000009e0, 0x00000000);
3016 nv_icmd(priv, 0x000009e1, 0x00000000);
3017 nv_icmd(priv, 0x000009e2, 0x00000000);
3018 nv_icmd(priv, 0x000009e3, 0x00000000);
3019 nv_icmd(priv, 0x000009e4, 0x00000000);
3020 nv_icmd(priv, 0x000009e5, 0x00000000);
3021 nv_icmd(priv, 0x000009e6, 0x00000000);
3022 nv_icmd(priv, 0x000009e7, 0x00000000);
3023 nv_icmd(priv, 0x000009e8, 0x00000000);
3024 nv_icmd(priv, 0x000009e9, 0x00000000);
3025 nv_icmd(priv, 0x000009ea, 0x00000000);
3026 nv_icmd(priv, 0x000009eb, 0x00000000);
3027 nv_icmd(priv, 0x000009ec, 0x00000000);
3028 nv_icmd(priv, 0x000009ed, 0x00000000);
3029 nv_icmd(priv, 0x000009ee, 0x00000000);
3030 nv_icmd(priv, 0x000009ef, 0x00000000);
3031 nv_icmd(priv, 0x000009f0, 0x00000000);
3032 nv_icmd(priv, 0x000009f1, 0x00000000);
3033 nv_icmd(priv, 0x000009f2, 0x00000000);
3034 nv_icmd(priv, 0x000009f3, 0x00000000);
3035 nv_icmd(priv, 0x000009f4, 0x00000000);
3036 nv_icmd(priv, 0x000009f5, 0x00000000);
3037 nv_icmd(priv, 0x000009f6, 0x00000000);
3038 nv_icmd(priv, 0x000009f7, 0x00000000);
3039 nv_icmd(priv, 0x000009f8, 0x00000000);
3040 nv_icmd(priv, 0x000009f9, 0x00000000);
3041 nv_icmd(priv, 0x000009fa, 0x00000000);
3042 nv_icmd(priv, 0x000009fb, 0x00000000);
3043 nv_icmd(priv, 0x000009fc, 0x00000000);
3044 nv_icmd(priv, 0x000009fd, 0x00000000);
3045 nv_icmd(priv, 0x000009fe, 0x00000000);
3046 nv_icmd(priv, 0x000009ff, 0x00000000);
3047 nv_icmd(priv, 0x00000468, 0x00000004);
3048 nv_icmd(priv, 0x0000046c, 0x00000001);
3049 nv_icmd(priv, 0x00000470, 0x00000000);
3050 nv_icmd(priv, 0x00000471, 0x00000000);
3051 nv_icmd(priv, 0x00000472, 0x00000000);
3052 nv_icmd(priv, 0x00000473, 0x00000000);
3053 nv_icmd(priv, 0x00000474, 0x00000000);
3054 nv_icmd(priv, 0x00000475, 0x00000000);
3055 nv_icmd(priv, 0x00000476, 0x00000000);
3056 nv_icmd(priv, 0x00000477, 0x00000000);
3057 nv_icmd(priv, 0x00000478, 0x00000000);
3058 nv_icmd(priv, 0x00000479, 0x00000000);
3059 nv_icmd(priv, 0x0000047a, 0x00000000);
3060 nv_icmd(priv, 0x0000047b, 0x00000000);
3061 nv_icmd(priv, 0x0000047c, 0x00000000);
3062 nv_icmd(priv, 0x0000047d, 0x00000000);
3063 nv_icmd(priv, 0x0000047e, 0x00000000);
3064 nv_icmd(priv, 0x0000047f, 0x00000000);
3065 nv_icmd(priv, 0x00000480, 0x00000000);
3066 nv_icmd(priv, 0x00000481, 0x00000000);
3067 nv_icmd(priv, 0x00000482, 0x00000000);
3068 nv_icmd(priv, 0x00000483, 0x00000000);
3069 nv_icmd(priv, 0x00000484, 0x00000000);
3070 nv_icmd(priv, 0x00000485, 0x00000000);
3071 nv_icmd(priv, 0x00000486, 0x00000000);
3072 nv_icmd(priv, 0x00000487, 0x00000000);
3073 nv_icmd(priv, 0x00000488, 0x00000000);
3074 nv_icmd(priv, 0x00000489, 0x00000000);
3075 nv_icmd(priv, 0x0000048a, 0x00000000);
3076 nv_icmd(priv, 0x0000048b, 0x00000000);
3077 nv_icmd(priv, 0x0000048c, 0x00000000);
3078 nv_icmd(priv, 0x0000048d, 0x00000000);
3079 nv_icmd(priv, 0x0000048e, 0x00000000);
3080 nv_icmd(priv, 0x0000048f, 0x00000000);
3081 nv_icmd(priv, 0x00000490, 0x00000000);
3082 nv_icmd(priv, 0x00000491, 0x00000000);
3083 nv_icmd(priv, 0x00000492, 0x00000000);
3084 nv_icmd(priv, 0x00000493, 0x00000000);
3085 nv_icmd(priv, 0x00000494, 0x00000000);
3086 nv_icmd(priv, 0x00000495, 0x00000000);
3087 nv_icmd(priv, 0x00000496, 0x00000000);
3088 nv_icmd(priv, 0x00000497, 0x00000000);
3089 nv_icmd(priv, 0x00000498, 0x00000000);
3090 nv_icmd(priv, 0x00000499, 0x00000000);
3091 nv_icmd(priv, 0x0000049a, 0x00000000);
3092 nv_icmd(priv, 0x0000049b, 0x00000000);
3093 nv_icmd(priv, 0x0000049c, 0x00000000);
3094 nv_icmd(priv, 0x0000049d, 0x00000000);
3095 nv_icmd(priv, 0x0000049e, 0x00000000);
3096 nv_icmd(priv, 0x0000049f, 0x00000000);
3097 nv_icmd(priv, 0x000004a0, 0x00000000);
3098 nv_icmd(priv, 0x000004a1, 0x00000000);
3099 nv_icmd(priv, 0x000004a2, 0x00000000);
3100 nv_icmd(priv, 0x000004a3, 0x00000000);
3101 nv_icmd(priv, 0x000004a4, 0x00000000);
3102 nv_icmd(priv, 0x000004a5, 0x00000000);
3103 nv_icmd(priv, 0x000004a6, 0x00000000);
3104 nv_icmd(priv, 0x000004a7, 0x00000000);
3105 nv_icmd(priv, 0x000004a8, 0x00000000);
3106 nv_icmd(priv, 0x000004a9, 0x00000000);
3107 nv_icmd(priv, 0x000004aa, 0x00000000);
3108 nv_icmd(priv, 0x000004ab, 0x00000000);
3109 nv_icmd(priv, 0x000004ac, 0x00000000);
3110 nv_icmd(priv, 0x000004ad, 0x00000000);
3111 nv_icmd(priv, 0x000004ae, 0x00000000);
3112 nv_icmd(priv, 0x000004af, 0x00000000);
3113 nv_icmd(priv, 0x000004b0, 0x00000000);
3114 nv_icmd(priv, 0x000004b1, 0x00000000);
3115 nv_icmd(priv, 0x000004b2, 0x00000000);
3116 nv_icmd(priv, 0x000004b3, 0x00000000);
3117 nv_icmd(priv, 0x000004b4, 0x00000000);
3118 nv_icmd(priv, 0x000004b5, 0x00000000);
3119 nv_icmd(priv, 0x000004b6, 0x00000000);
3120 nv_icmd(priv, 0x000004b7, 0x00000000);
3121 nv_icmd(priv, 0x000004b8, 0x00000000);
3122 nv_icmd(priv, 0x000004b9, 0x00000000);
3123 nv_icmd(priv, 0x000004ba, 0x00000000);
3124 nv_icmd(priv, 0x000004bb, 0x00000000);
3125 nv_icmd(priv, 0x000004bc, 0x00000000);
3126 nv_icmd(priv, 0x000004bd, 0x00000000);
3127 nv_icmd(priv, 0x000004be, 0x00000000);
3128 nv_icmd(priv, 0x000004bf, 0x00000000);
3129 nv_icmd(priv, 0x000004c0, 0x00000000);
3130 nv_icmd(priv, 0x000004c1, 0x00000000);
3131 nv_icmd(priv, 0x000004c2, 0x00000000);
3132 nv_icmd(priv, 0x000004c3, 0x00000000);
3133 nv_icmd(priv, 0x000004c4, 0x00000000);
3134 nv_icmd(priv, 0x000004c5, 0x00000000);
3135 nv_icmd(priv, 0x000004c6, 0x00000000);
3136 nv_icmd(priv, 0x000004c7, 0x00000000);
3137 nv_icmd(priv, 0x000004c8, 0x00000000);
3138 nv_icmd(priv, 0x000004c9, 0x00000000);
3139 nv_icmd(priv, 0x000004ca, 0x00000000);
3140 nv_icmd(priv, 0x000004cb, 0x00000000);
3141 nv_icmd(priv, 0x000004cc, 0x00000000);
3142 nv_icmd(priv, 0x000004cd, 0x00000000);
3143 nv_icmd(priv, 0x000004ce, 0x00000000);
3144 nv_icmd(priv, 0x000004cf, 0x00000000);
3145 nv_icmd(priv, 0x00000510, 0x3f800000);
3146 nv_icmd(priv, 0x00000511, 0x3f800000);
3147 nv_icmd(priv, 0x00000512, 0x3f800000);
3148 nv_icmd(priv, 0x00000513, 0x3f800000);
3149 nv_icmd(priv, 0x00000514, 0x3f800000);
3150 nv_icmd(priv, 0x00000515, 0x3f800000);
3151 nv_icmd(priv, 0x00000516, 0x3f800000);
3152 nv_icmd(priv, 0x00000517, 0x3f800000);
3153 nv_icmd(priv, 0x00000518, 0x3f800000);
3154 nv_icmd(priv, 0x00000519, 0x3f800000);
3155 nv_icmd(priv, 0x0000051a, 0x3f800000);
3156 nv_icmd(priv, 0x0000051b, 0x3f800000);
3157 nv_icmd(priv, 0x0000051c, 0x3f800000);
3158 nv_icmd(priv, 0x0000051d, 0x3f800000);
3159 nv_icmd(priv, 0x0000051e, 0x3f800000);
3160 nv_icmd(priv, 0x0000051f, 0x3f800000);
3161 nv_icmd(priv, 0x00000520, 0x000002b6);
3162 nv_icmd(priv, 0x00000529, 0x00000001);
3163 nv_icmd(priv, 0x00000530, 0xffff0000);
3164 nv_icmd(priv, 0x00000531, 0xffff0000);
3165 nv_icmd(priv, 0x00000532, 0xffff0000);
3166 nv_icmd(priv, 0x00000533, 0xffff0000);
3167 nv_icmd(priv, 0x00000534, 0xffff0000);
3168 nv_icmd(priv, 0x00000535, 0xffff0000);
3169 nv_icmd(priv, 0x00000536, 0xffff0000);
3170 nv_icmd(priv, 0x00000537, 0xffff0000);
3171 nv_icmd(priv, 0x00000538, 0xffff0000);
3172 nv_icmd(priv, 0x00000539, 0xffff0000);
3173 nv_icmd(priv, 0x0000053a, 0xffff0000);
3174 nv_icmd(priv, 0x0000053b, 0xffff0000);
3175 nv_icmd(priv, 0x0000053c, 0xffff0000);
3176 nv_icmd(priv, 0x0000053d, 0xffff0000);
3177 nv_icmd(priv, 0x0000053e, 0xffff0000);
3178 nv_icmd(priv, 0x0000053f, 0xffff0000);
3179 nv_icmd(priv, 0x00000585, 0x0000003f);
3180 nv_icmd(priv, 0x00000576, 0x00000003);
3181 switch (nv_device(priv)->chipset) {
3182 case 0xc1:
3183 case 0xc8:
3184 case 0xd9:
3185 case 0xd7:
3186 nv_icmd(priv, 0x0000057b, 0x00000059);
3187 break;
3188 case 0xc0:
3189 case 0xc3:
3190 case 0xc4:
3191 case 0xce:
3192 case 0xcf:
3193 break;
3194 default:
3195 BUG_ON(1);
3196 break;
3197 }
3198 nv_icmd(priv, 0x00000586, 0x00000040);
3199 nv_icmd(priv, 0x00000582, 0x00000080);
3200 nv_icmd(priv, 0x00000583, 0x00000080);
3201 nv_icmd(priv, 0x000005c2, 0x00000001);
3202 nv_icmd(priv, 0x00000638, 0x00000001);
3203 nv_icmd(priv, 0x00000639, 0x00000001);
3204 nv_icmd(priv, 0x0000063a, 0x00000002);
3205 nv_icmd(priv, 0x0000063b, 0x00000001);
3206 nv_icmd(priv, 0x0000063c, 0x00000001);
3207 nv_icmd(priv, 0x0000063d, 0x00000002);
3208 nv_icmd(priv, 0x0000063e, 0x00000001);
3209 nv_icmd(priv, 0x000008b8, 0x00000001);
3210 nv_icmd(priv, 0x000008b9, 0x00000001);
3211 nv_icmd(priv, 0x000008ba, 0x00000001);
3212 nv_icmd(priv, 0x000008bb, 0x00000001);
3213 nv_icmd(priv, 0x000008bc, 0x00000001);
3214 nv_icmd(priv, 0x000008bd, 0x00000001);
3215 nv_icmd(priv, 0x000008be, 0x00000001);
3216 nv_icmd(priv, 0x000008bf, 0x00000001);
3217 nv_icmd(priv, 0x00000900, 0x00000001);
3218 nv_icmd(priv, 0x00000901, 0x00000001);
3219 nv_icmd(priv, 0x00000902, 0x00000001);
3220 nv_icmd(priv, 0x00000903, 0x00000001);
3221 nv_icmd(priv, 0x00000904, 0x00000001);
3222 nv_icmd(priv, 0x00000905, 0x00000001);
3223 nv_icmd(priv, 0x00000906, 0x00000001);
3224 nv_icmd(priv, 0x00000907, 0x00000001);
3225 nv_icmd(priv, 0x00000908, 0x00000002);
3226 nv_icmd(priv, 0x00000909, 0x00000002);
3227 nv_icmd(priv, 0x0000090a, 0x00000002);
3228 nv_icmd(priv, 0x0000090b, 0x00000002);
3229 nv_icmd(priv, 0x0000090c, 0x00000002);
3230 nv_icmd(priv, 0x0000090d, 0x00000002);
3231 nv_icmd(priv, 0x0000090e, 0x00000002);
3232 nv_icmd(priv, 0x0000090f, 0x00000002);
3233 nv_icmd(priv, 0x00000910, 0x00000001);
3234 nv_icmd(priv, 0x00000911, 0x00000001);
3235 nv_icmd(priv, 0x00000912, 0x00000001);
3236 nv_icmd(priv, 0x00000913, 0x00000001);
3237 nv_icmd(priv, 0x00000914, 0x00000001);
3238 nv_icmd(priv, 0x00000915, 0x00000001);
3239 nv_icmd(priv, 0x00000916, 0x00000001);
3240 nv_icmd(priv, 0x00000917, 0x00000001);
3241 nv_icmd(priv, 0x00000918, 0x00000001);
3242 nv_icmd(priv, 0x00000919, 0x00000001);
3243 nv_icmd(priv, 0x0000091a, 0x00000001);
3244 nv_icmd(priv, 0x0000091b, 0x00000001);
3245 nv_icmd(priv, 0x0000091c, 0x00000001);
3246 nv_icmd(priv, 0x0000091d, 0x00000001);
3247 nv_icmd(priv, 0x0000091e, 0x00000001);
3248 nv_icmd(priv, 0x0000091f, 0x00000001);
3249 nv_icmd(priv, 0x00000920, 0x00000002);
3250 nv_icmd(priv, 0x00000921, 0x00000002);
3251 nv_icmd(priv, 0x00000922, 0x00000002);
3252 nv_icmd(priv, 0x00000923, 0x00000002);
3253 nv_icmd(priv, 0x00000924, 0x00000002);
3254 nv_icmd(priv, 0x00000925, 0x00000002);
3255 nv_icmd(priv, 0x00000926, 0x00000002);
3256 nv_icmd(priv, 0x00000927, 0x00000002);
3257 nv_icmd(priv, 0x00000928, 0x00000001);
3258 nv_icmd(priv, 0x00000929, 0x00000001);
3259 nv_icmd(priv, 0x0000092a, 0x00000001);
3260 nv_icmd(priv, 0x0000092b, 0x00000001);
3261 nv_icmd(priv, 0x0000092c, 0x00000001);
3262 nv_icmd(priv, 0x0000092d, 0x00000001);
3263 nv_icmd(priv, 0x0000092e, 0x00000001);
3264 nv_icmd(priv, 0x0000092f, 0x00000001);
3265 nv_icmd(priv, 0x00000648, 0x00000001);
3266 nv_icmd(priv, 0x00000649, 0x00000001);
3267 nv_icmd(priv, 0x0000064a, 0x00000001);
3268 nv_icmd(priv, 0x0000064b, 0x00000001);
3269 nv_icmd(priv, 0x0000064c, 0x00000001);
3270 nv_icmd(priv, 0x0000064d, 0x00000001);
3271 nv_icmd(priv, 0x0000064e, 0x00000001);
3272 nv_icmd(priv, 0x0000064f, 0x00000001);
3273 nv_icmd(priv, 0x00000650, 0x00000001);
3274 nv_icmd(priv, 0x00000658, 0x0000000f);
3275 nv_icmd(priv, 0x000007ff, 0x0000000a);
3276 nv_icmd(priv, 0x0000066a, 0x40000000);
3277 nv_icmd(priv, 0x0000066b, 0x10000000);
3278 nv_icmd(priv, 0x0000066c, 0xffff0000);
3279 nv_icmd(priv, 0x0000066d, 0xffff0000);
3280 nv_icmd(priv, 0x000007af, 0x00000008);
3281 nv_icmd(priv, 0x000007b0, 0x00000008);
3282 nv_icmd(priv, 0x000007f6, 0x00000001);
3283 nv_icmd(priv, 0x000006b2, 0x00000055);
3284 nv_icmd(priv, 0x000007ad, 0x00000003);
3285 nv_icmd(priv, 0x00000937, 0x00000001);
3286 nv_icmd(priv, 0x00000971, 0x00000008);
3287 nv_icmd(priv, 0x00000972, 0x00000040);
3288 nv_icmd(priv, 0x00000973, 0x0000012c);
3289 nv_icmd(priv, 0x0000097c, 0x00000040);
3290 nv_icmd(priv, 0x00000979, 0x00000003);
3291 nv_icmd(priv, 0x00000975, 0x00000020);
3292 nv_icmd(priv, 0x00000976, 0x00000001);
3293 nv_icmd(priv, 0x00000977, 0x00000020);
3294 nv_icmd(priv, 0x00000978, 0x00000001);
3295 nv_icmd(priv, 0x00000957, 0x00000003);
3296 nv_icmd(priv, 0x0000095e, 0x20164010);
3297 nv_icmd(priv, 0x0000095f, 0x00000020);
3298 switch (nv_device(priv)->chipset) {
3299 case 0xd9:
3300 case 0xd7:
3301 case 0xc8:
3302 nv_icmd(priv, 0x0000097d, 0x00000020);
3303 break;
3304 case 0xc0:
3305 case 0xc3:
3306 case 0xc4:
3307 case 0xc1:
3308 case 0xce:
3309 case 0xcf:
3310 break;
3311 default:
3312 BUG_ON(1);
3313 break;
3314 } 1169 }
3315 nv_icmd(priv, 0x00000683, 0x00000006);
3316 nv_icmd(priv, 0x00000685, 0x003fffff);
3317 nv_icmd(priv, 0x00000687, 0x00000c48);
3318 nv_icmd(priv, 0x000006a0, 0x00000005);
3319 nv_icmd(priv, 0x00000840, 0x00300008);
3320 nv_icmd(priv, 0x00000841, 0x04000080);
3321 nv_icmd(priv, 0x00000842, 0x00300008);
3322 nv_icmd(priv, 0x00000843, 0x04000080);
3323 nv_icmd(priv, 0x00000818, 0x00000000);
3324 nv_icmd(priv, 0x00000819, 0x00000000);
3325 nv_icmd(priv, 0x0000081a, 0x00000000);
3326 nv_icmd(priv, 0x0000081b, 0x00000000);
3327 nv_icmd(priv, 0x0000081c, 0x00000000);
3328 nv_icmd(priv, 0x0000081d, 0x00000000);
3329 nv_icmd(priv, 0x0000081e, 0x00000000);
3330 nv_icmd(priv, 0x0000081f, 0x00000000);
3331 nv_icmd(priv, 0x00000848, 0x00000000);
3332 nv_icmd(priv, 0x00000849, 0x00000000);
3333 nv_icmd(priv, 0x0000084a, 0x00000000);
3334 nv_icmd(priv, 0x0000084b, 0x00000000);
3335 nv_icmd(priv, 0x0000084c, 0x00000000);
3336 nv_icmd(priv, 0x0000084d, 0x00000000);
3337 nv_icmd(priv, 0x0000084e, 0x00000000);
3338 nv_icmd(priv, 0x0000084f, 0x00000000);
3339 nv_icmd(priv, 0x00000850, 0x00000000);
3340 nv_icmd(priv, 0x00000851, 0x00000000);
3341 nv_icmd(priv, 0x00000852, 0x00000000);
3342 nv_icmd(priv, 0x00000853, 0x00000000);
3343 nv_icmd(priv, 0x00000854, 0x00000000);
3344 nv_icmd(priv, 0x00000855, 0x00000000);
3345 nv_icmd(priv, 0x00000856, 0x00000000);
3346 nv_icmd(priv, 0x00000857, 0x00000000);
3347 nv_icmd(priv, 0x00000738, 0x00000000);
3348 nv_icmd(priv, 0x000006aa, 0x00000001);
3349 nv_icmd(priv, 0x000006ab, 0x00000002);
3350 nv_icmd(priv, 0x000006ac, 0x00000080);
3351 nv_icmd(priv, 0x000006ad, 0x00000100);
3352 nv_icmd(priv, 0x000006ae, 0x00000100);
3353 nv_icmd(priv, 0x000006b1, 0x00000011);
3354 nv_icmd(priv, 0x000006bb, 0x000000cf);
3355 nv_icmd(priv, 0x000006ce, 0x2a712488);
3356 nv_icmd(priv, 0x00000739, 0x4085c000);
3357 nv_icmd(priv, 0x0000073a, 0x00000080);
3358 nv_icmd(priv, 0x00000786, 0x80000100);
3359 nv_icmd(priv, 0x0000073c, 0x00010100);
3360 nv_icmd(priv, 0x0000073d, 0x02800000);
3361 nv_icmd(priv, 0x00000787, 0x000000cf);
3362 nv_icmd(priv, 0x0000078c, 0x00000008);
3363 nv_icmd(priv, 0x00000792, 0x00000001);
3364 nv_icmd(priv, 0x00000794, 0x00000001);
3365 nv_icmd(priv, 0x00000795, 0x00000001);
3366 nv_icmd(priv, 0x00000796, 0x00000001);
3367 nv_icmd(priv, 0x00000797, 0x000000cf);
3368 nv_icmd(priv, 0x00000836, 0x00000001);
3369 nv_icmd(priv, 0x0000079a, 0x00000002);
3370 nv_icmd(priv, 0x00000833, 0x04444480);
3371 nv_icmd(priv, 0x000007a1, 0x00000001);
3372 nv_icmd(priv, 0x000007a3, 0x00000001);
3373 nv_icmd(priv, 0x000007a4, 0x00000001);
3374 nv_icmd(priv, 0x000007a5, 0x00000001);
3375 nv_icmd(priv, 0x00000831, 0x00000004);
3376 nv_icmd(priv, 0x0000080c, 0x00000002);
3377 nv_icmd(priv, 0x0000080d, 0x00000100);
3378 nv_icmd(priv, 0x0000080e, 0x00000100);
3379 nv_icmd(priv, 0x0000080f, 0x00000001);
3380 nv_icmd(priv, 0x00000823, 0x00000002);
3381 nv_icmd(priv, 0x00000824, 0x00000100);
3382 nv_icmd(priv, 0x00000825, 0x00000100);
3383 nv_icmd(priv, 0x00000826, 0x00000001);
3384 nv_icmd(priv, 0x0000095d, 0x00000001);
3385 nv_icmd(priv, 0x0000082b, 0x00000004);
3386 nv_icmd(priv, 0x00000942, 0x00010001);
3387 nv_icmd(priv, 0x00000943, 0x00000001);
3388 nv_icmd(priv, 0x00000944, 0x00000022);
3389 nv_icmd(priv, 0x000007c5, 0x00010001);
3390 nv_icmd(priv, 0x00000834, 0x00000001);
3391 nv_icmd(priv, 0x000007c7, 0x00000001);
3392 nv_icmd(priv, 0x0000c1b0, 0x0000000f);
3393 nv_icmd(priv, 0x0000c1b1, 0x0000000f);
3394 nv_icmd(priv, 0x0000c1b2, 0x0000000f);
3395 nv_icmd(priv, 0x0000c1b3, 0x0000000f);
3396 nv_icmd(priv, 0x0000c1b4, 0x0000000f);
3397 nv_icmd(priv, 0x0000c1b5, 0x0000000f);
3398 nv_icmd(priv, 0x0000c1b6, 0x0000000f);
3399 nv_icmd(priv, 0x0000c1b7, 0x0000000f);
3400 nv_icmd(priv, 0x0000c1b8, 0x0fac6881);
3401 nv_icmd(priv, 0x0000c1b9, 0x00fac688);
3402 nv_icmd(priv, 0x0001e100, 0x00000001);
3403 nv_icmd(priv, 0x00001000, 0x00000002);
3404 nv_icmd(priv, 0x000006aa, 0x00000001);
3405 nv_icmd(priv, 0x000006ad, 0x00000100);
3406 nv_icmd(priv, 0x000006ae, 0x00000100);
3407 nv_icmd(priv, 0x000006b1, 0x00000011);
3408 nv_icmd(priv, 0x0000078c, 0x00000008);
3409 nv_icmd(priv, 0x00000792, 0x00000001);
3410 nv_icmd(priv, 0x00000794, 0x00000001);
3411 nv_icmd(priv, 0x00000795, 0x00000001);
3412 nv_icmd(priv, 0x00000796, 0x00000001);
3413 nv_icmd(priv, 0x00000797, 0x000000cf);
3414 nv_icmd(priv, 0x0000079a, 0x00000002);
3415 nv_icmd(priv, 0x00000833, 0x04444480);
3416 nv_icmd(priv, 0x000007a1, 0x00000001);
3417 nv_icmd(priv, 0x000007a3, 0x00000001);
3418 nv_icmd(priv, 0x000007a4, 0x00000001);
3419 nv_icmd(priv, 0x000007a5, 0x00000001);
3420 nv_icmd(priv, 0x00000831, 0x00000004);
3421 nv_icmd(priv, 0x0001e100, 0x00000001);
3422 nv_icmd(priv, 0x00001000, 0x00000014);
3423 nv_icmd(priv, 0x00000351, 0x00000100);
3424 nv_icmd(priv, 0x00000957, 0x00000003);
3425 nv_icmd(priv, 0x0000095d, 0x00000001);
3426 nv_icmd(priv, 0x0000082b, 0x00000004);
3427 nv_icmd(priv, 0x00000942, 0x00010001);
3428 nv_icmd(priv, 0x00000943, 0x00000001);
3429 nv_icmd(priv, 0x000007c5, 0x00010001);
3430 nv_icmd(priv, 0x00000834, 0x00000001);
3431 nv_icmd(priv, 0x000007c7, 0x00000001);
3432 nv_icmd(priv, 0x0001e100, 0x00000001);
3433 nv_icmd(priv, 0x00001000, 0x00000001);
3434 nv_icmd(priv, 0x0000080c, 0x00000002);
3435 nv_icmd(priv, 0x0000080d, 0x00000100);
3436 nv_icmd(priv, 0x0000080e, 0x00000100);
3437 nv_icmd(priv, 0x0000080f, 0x00000001);
3438 nv_icmd(priv, 0x00000823, 0x00000002);
3439 nv_icmd(priv, 0x00000824, 0x00000100);
3440 nv_icmd(priv, 0x00000825, 0x00000100);
3441 nv_icmd(priv, 0x00000826, 0x00000001);
3442 nv_icmd(priv, 0x0001e100, 0x00000001);
3443
3444
3445 nv_wr32(priv, 0x400208, 0x00000000);
3446 nv_wr32(priv, 0x404154, 0x00000400);
3447 1170
3448 nvc0_grctx_generate_9097(priv); 1171 priv->data = kmalloc(priv->size, GFP_KERNEL);
3449 if (fermi >= 0x9197) 1172 if (priv->data) {
3450 nvc0_grctx_generate_9197(priv); 1173 for (i = 0; i < priv->size; i += 4)
3451 if (fermi >= 0x9297) 1174 priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);
3452 nvc0_grctx_generate_9297(priv); 1175 ret = 0;
3453 nvc0_grctx_generate_902d(priv); 1176 } else {
3454 nvc0_grctx_generate_9039(priv); 1177 ret = -ENOMEM;
3455 nvc0_grctx_generate_90c0(priv);
3456
3457 switch (nv_device(priv)->chipset) {
3458 case 0xc0:
3459 case 0xc3:
3460 case 0xc4:
3461 case 0xc1:
3462 case 0xc8:
3463 case 0xce:
3464 case 0xcf:
3465 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
3466 break;
3467 case 0xd9:
3468 case 0xd7:
3469 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
3470 break;
3471 default:
3472 BUG_ON(1);
3473 break;
3474 } 1178 }
3475 1179
3476 nv_wr32(priv, 0x000260, r000260); 1180done:
3477 1181 nouveau_gpuobj_ref(NULL, &chan);
3478 return nvc0_grctx_fini(&info); 1182 return ret;
3479} 1183}
1184
1185struct nvc0_graph_init *
1186nvc0_grctx_init_hub[] = {
1187 nvc0_grctx_init_base,
1188 nvc0_grctx_init_unk40xx,
1189 nvc0_grctx_init_unk44xx,
1190 nvc0_grctx_init_unk46xx,
1191 nvc0_grctx_init_unk47xx,
1192 nvc0_grctx_init_unk58xx,
1193 nvc0_grctx_init_unk60xx,
1194 nvc0_grctx_init_unk64xx,
1195 nvc0_grctx_init_unk78xx,
1196 nvc0_grctx_init_unk80xx,
1197 nvc0_grctx_init_rop,
1198 NULL
1199};
1200
1201static struct nvc0_graph_init *
1202nvc0_grctx_init_gpc[] = {
1203 nvc0_grctx_init_gpc_0,
1204 nvc0_grctx_init_gpc_1,
1205 nvc0_grctx_init_tpc,
1206 NULL
1207};
1208
1209struct nvc0_graph_init
1210nvc0_grctx_init_mthd_magic[] = {
1211 { 0x3410, 1, 0x04, 0x00000000 },
1212 {}
1213};
1214
1215struct nvc0_graph_mthd
1216nvc0_grctx_init_mthd[] = {
1217 { 0x9097, nvc0_grctx_init_9097, },
1218 { 0x902d, nvc0_grctx_init_902d, },
1219 { 0x9039, nvc0_grctx_init_9039, },
1220 { 0x90c0, nvc0_grctx_init_90c0, },
1221 { 0x902d, nvc0_grctx_init_mthd_magic, },
1222 {}
1223};
1224
1225struct nouveau_oclass *
1226nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
1227 .base.handle = NV_ENGCTX(GR, 0xc0),
1228 .base.ofuncs = &(struct nouveau_ofuncs) {
1229 .ctor = nvc0_graph_context_ctor,
1230 .dtor = nvc0_graph_context_dtor,
1231 .init = _nouveau_graph_context_init,
1232 .fini = _nouveau_graph_context_fini,
1233 .rd32 = _nouveau_graph_context_rd32,
1234 .wr32 = _nouveau_graph_context_wr32,
1235 },
1236 .main = nvc0_grctx_generate_main,
1237 .mods = nvc0_grctx_generate_mods,
1238 .unkn = nvc0_grctx_generate_unkn,
1239 .hub = nvc0_grctx_init_hub,
1240 .gpc = nvc0_grctx_init_gpc,
1241 .icmd = nvc0_grctx_init_icmd,
1242 .mthd = nvc0_grctx_init_mthd,
1243}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
new file mode 100644
index 000000000000..e5be3ee7f172
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
@@ -0,0 +1,823 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27static struct nvc0_graph_init
28nvc1_grctx_init_icmd[] = {
29 { 0x001000, 1, 0x01, 0x00000004 },
30 { 0x0000a9, 1, 0x01, 0x0000ffff },
31 { 0x000038, 1, 0x01, 0x0fac6881 },
32 { 0x00003d, 1, 0x01, 0x00000001 },
33 { 0x0000e8, 8, 0x01, 0x00000400 },
34 { 0x000078, 8, 0x01, 0x00000300 },
35 { 0x000050, 1, 0x01, 0x00000011 },
36 { 0x000058, 8, 0x01, 0x00000008 },
37 { 0x000208, 8, 0x01, 0x00000001 },
38 { 0x000081, 1, 0x01, 0x00000001 },
39 { 0x000085, 1, 0x01, 0x00000004 },
40 { 0x000088, 1, 0x01, 0x00000400 },
41 { 0x000090, 1, 0x01, 0x00000300 },
42 { 0x000098, 1, 0x01, 0x00001001 },
43 { 0x0000e3, 1, 0x01, 0x00000001 },
44 { 0x0000da, 1, 0x01, 0x00000001 },
45 { 0x0000f8, 1, 0x01, 0x00000003 },
46 { 0x0000fa, 1, 0x01, 0x00000001 },
47 { 0x00009f, 4, 0x01, 0x0000ffff },
48 { 0x0000b1, 1, 0x01, 0x00000001 },
49 { 0x0000b2, 40, 0x01, 0x00000000 },
50 { 0x000210, 8, 0x01, 0x00000040 },
51 { 0x000218, 8, 0x01, 0x0000c080 },
52 { 0x0000ad, 1, 0x01, 0x0000013e },
53 { 0x0000e1, 1, 0x01, 0x00000010 },
54 { 0x000290, 16, 0x01, 0x00000000 },
55 { 0x0003b0, 16, 0x01, 0x00000000 },
56 { 0x0002a0, 16, 0x01, 0x00000000 },
57 { 0x000420, 16, 0x01, 0x00000000 },
58 { 0x0002b0, 16, 0x01, 0x00000000 },
59 { 0x000430, 16, 0x01, 0x00000000 },
60 { 0x0002c0, 16, 0x01, 0x00000000 },
61 { 0x0004d0, 16, 0x01, 0x00000000 },
62 { 0x000720, 16, 0x01, 0x00000000 },
63 { 0x0008c0, 16, 0x01, 0x00000000 },
64 { 0x000890, 16, 0x01, 0x00000000 },
65 { 0x0008e0, 16, 0x01, 0x00000000 },
66 { 0x0008a0, 16, 0x01, 0x00000000 },
67 { 0x0008f0, 16, 0x01, 0x00000000 },
68 { 0x00094c, 1, 0x01, 0x000000ff },
69 { 0x00094d, 1, 0x01, 0xffffffff },
70 { 0x00094e, 1, 0x01, 0x00000002 },
71 { 0x0002ec, 1, 0x01, 0x00000001 },
72 { 0x000303, 1, 0x01, 0x00000001 },
73 { 0x0002e6, 1, 0x01, 0x00000001 },
74 { 0x000466, 1, 0x01, 0x00000052 },
75 { 0x000301, 1, 0x01, 0x3f800000 },
76 { 0x000304, 1, 0x01, 0x30201000 },
77 { 0x000305, 1, 0x01, 0x70605040 },
78 { 0x000306, 1, 0x01, 0xb8a89888 },
79 { 0x000307, 1, 0x01, 0xf8e8d8c8 },
80 { 0x00030a, 1, 0x01, 0x00ffff00 },
81 { 0x00030b, 1, 0x01, 0x0000001a },
82 { 0x00030c, 1, 0x01, 0x00000001 },
83 { 0x000318, 1, 0x01, 0x00000001 },
84 { 0x000340, 1, 0x01, 0x00000000 },
85 { 0x000375, 1, 0x01, 0x00000001 },
86 { 0x000351, 1, 0x01, 0x00000100 },
87 { 0x00037d, 1, 0x01, 0x00000006 },
88 { 0x0003a0, 1, 0x01, 0x00000002 },
89 { 0x0003aa, 1, 0x01, 0x00000001 },
90 { 0x0003a9, 1, 0x01, 0x00000001 },
91 { 0x000380, 1, 0x01, 0x00000001 },
92 { 0x000360, 1, 0x01, 0x00000040 },
93 { 0x000366, 2, 0x01, 0x00000000 },
94 { 0x000368, 1, 0x01, 0x00001fff },
95 { 0x000370, 2, 0x01, 0x00000000 },
96 { 0x000372, 1, 0x01, 0x003fffff },
97 { 0x00037a, 1, 0x01, 0x00000012 },
98 { 0x0005e0, 5, 0x01, 0x00000022 },
99 { 0x000619, 1, 0x01, 0x00000003 },
100 { 0x000811, 1, 0x01, 0x00000003 },
101 { 0x000812, 1, 0x01, 0x00000004 },
102 { 0x000813, 1, 0x01, 0x00000006 },
103 { 0x000814, 1, 0x01, 0x00000008 },
104 { 0x000815, 1, 0x01, 0x0000000b },
105 { 0x000800, 6, 0x01, 0x00000001 },
106 { 0x000632, 1, 0x01, 0x00000001 },
107 { 0x000633, 1, 0x01, 0x00000002 },
108 { 0x000634, 1, 0x01, 0x00000003 },
109 { 0x000635, 1, 0x01, 0x00000004 },
110 { 0x000654, 1, 0x01, 0x3f800000 },
111 { 0x000657, 1, 0x01, 0x3f800000 },
112 { 0x000655, 2, 0x01, 0x3f800000 },
113 { 0x0006cd, 1, 0x01, 0x3f800000 },
114 { 0x0007f5, 1, 0x01, 0x3f800000 },
115 { 0x0007dc, 1, 0x01, 0x39291909 },
116 { 0x0007dd, 1, 0x01, 0x79695949 },
117 { 0x0007de, 1, 0x01, 0xb9a99989 },
118 { 0x0007df, 1, 0x01, 0xf9e9d9c9 },
119 { 0x0007e8, 1, 0x01, 0x00003210 },
120 { 0x0007e9, 1, 0x01, 0x00007654 },
121 { 0x0007ea, 1, 0x01, 0x00000098 },
122 { 0x0007ec, 1, 0x01, 0x39291909 },
123 { 0x0007ed, 1, 0x01, 0x79695949 },
124 { 0x0007ee, 1, 0x01, 0xb9a99989 },
125 { 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
126 { 0x0007f0, 1, 0x01, 0x00003210 },
127 { 0x0007f1, 1, 0x01, 0x00007654 },
128 { 0x0007f2, 1, 0x01, 0x00000098 },
129 { 0x0005a5, 1, 0x01, 0x00000001 },
130 { 0x000980, 128, 0x01, 0x00000000 },
131 { 0x000468, 1, 0x01, 0x00000004 },
132 { 0x00046c, 1, 0x01, 0x00000001 },
133 { 0x000470, 96, 0x01, 0x00000000 },
134 { 0x000510, 16, 0x01, 0x3f800000 },
135 { 0x000520, 1, 0x01, 0x000002b6 },
136 { 0x000529, 1, 0x01, 0x00000001 },
137 { 0x000530, 16, 0x01, 0xffff0000 },
138 { 0x000585, 1, 0x01, 0x0000003f },
139 { 0x000576, 1, 0x01, 0x00000003 },
140 { 0x00057b, 1, 0x01, 0x00000059 },
141 { 0x000586, 1, 0x01, 0x00000040 },
142 { 0x000582, 2, 0x01, 0x00000080 },
143 { 0x0005c2, 1, 0x01, 0x00000001 },
144 { 0x000638, 1, 0x01, 0x00000001 },
145 { 0x000639, 1, 0x01, 0x00000001 },
146 { 0x00063a, 1, 0x01, 0x00000002 },
147 { 0x00063b, 2, 0x01, 0x00000001 },
148 { 0x00063d, 1, 0x01, 0x00000002 },
149 { 0x00063e, 1, 0x01, 0x00000001 },
150 { 0x0008b8, 8, 0x01, 0x00000001 },
151 { 0x000900, 8, 0x01, 0x00000001 },
152 { 0x000908, 8, 0x01, 0x00000002 },
153 { 0x000910, 16, 0x01, 0x00000001 },
154 { 0x000920, 8, 0x01, 0x00000002 },
155 { 0x000928, 8, 0x01, 0x00000001 },
156 { 0x000648, 9, 0x01, 0x00000001 },
157 { 0x000658, 1, 0x01, 0x0000000f },
158 { 0x0007ff, 1, 0x01, 0x0000000a },
159 { 0x00066a, 1, 0x01, 0x40000000 },
160 { 0x00066b, 1, 0x01, 0x10000000 },
161 { 0x00066c, 2, 0x01, 0xffff0000 },
162 { 0x0007af, 2, 0x01, 0x00000008 },
163 { 0x0007f6, 1, 0x01, 0x00000001 },
164 { 0x0006b2, 1, 0x01, 0x00000055 },
165 { 0x0007ad, 1, 0x01, 0x00000003 },
166 { 0x000937, 1, 0x01, 0x00000001 },
167 { 0x000971, 1, 0x01, 0x00000008 },
168 { 0x000972, 1, 0x01, 0x00000040 },
169 { 0x000973, 1, 0x01, 0x0000012c },
170 { 0x00097c, 1, 0x01, 0x00000040 },
171 { 0x000979, 1, 0x01, 0x00000003 },
172 { 0x000975, 1, 0x01, 0x00000020 },
173 { 0x000976, 1, 0x01, 0x00000001 },
174 { 0x000977, 1, 0x01, 0x00000020 },
175 { 0x000978, 1, 0x01, 0x00000001 },
176 { 0x000957, 1, 0x01, 0x00000003 },
177 { 0x00095e, 1, 0x01, 0x20164010 },
178 { 0x00095f, 1, 0x01, 0x00000020 },
179 { 0x000683, 1, 0x01, 0x00000006 },
180 { 0x000685, 1, 0x01, 0x003fffff },
181 { 0x000687, 1, 0x01, 0x00000c48 },
182 { 0x0006a0, 1, 0x01, 0x00000005 },
183 { 0x000840, 1, 0x01, 0x00300008 },
184 { 0x000841, 1, 0x01, 0x04000080 },
185 { 0x000842, 1, 0x01, 0x00300008 },
186 { 0x000843, 1, 0x01, 0x04000080 },
187 { 0x000818, 8, 0x01, 0x00000000 },
188 { 0x000848, 16, 0x01, 0x00000000 },
189 { 0x000738, 1, 0x01, 0x00000000 },
190 { 0x0006aa, 1, 0x01, 0x00000001 },
191 { 0x0006ab, 1, 0x01, 0x00000002 },
192 { 0x0006ac, 1, 0x01, 0x00000080 },
193 { 0x0006ad, 2, 0x01, 0x00000100 },
194 { 0x0006b1, 1, 0x01, 0x00000011 },
195 { 0x0006bb, 1, 0x01, 0x000000cf },
196 { 0x0006ce, 1, 0x01, 0x2a712488 },
197 { 0x000739, 1, 0x01, 0x4085c000 },
198 { 0x00073a, 1, 0x01, 0x00000080 },
199 { 0x000786, 1, 0x01, 0x80000100 },
200 { 0x00073c, 1, 0x01, 0x00010100 },
201 { 0x00073d, 1, 0x01, 0x02800000 },
202 { 0x000787, 1, 0x01, 0x000000cf },
203 { 0x00078c, 1, 0x01, 0x00000008 },
204 { 0x000792, 1, 0x01, 0x00000001 },
205 { 0x000794, 1, 0x01, 0x00000001 },
206 { 0x000795, 2, 0x01, 0x00000001 },
207 { 0x000797, 1, 0x01, 0x000000cf },
208 { 0x000836, 1, 0x01, 0x00000001 },
209 { 0x00079a, 1, 0x01, 0x00000002 },
210 { 0x000833, 1, 0x01, 0x04444480 },
211 { 0x0007a1, 1, 0x01, 0x00000001 },
212 { 0x0007a3, 1, 0x01, 0x00000001 },
213 { 0x0007a4, 2, 0x01, 0x00000001 },
214 { 0x000831, 1, 0x01, 0x00000004 },
215 { 0x00080c, 1, 0x01, 0x00000002 },
216 { 0x00080d, 2, 0x01, 0x00000100 },
217 { 0x00080f, 1, 0x01, 0x00000001 },
218 { 0x000823, 1, 0x01, 0x00000002 },
219 { 0x000824, 2, 0x01, 0x00000100 },
220 { 0x000826, 1, 0x01, 0x00000001 },
221 { 0x00095d, 1, 0x01, 0x00000001 },
222 { 0x00082b, 1, 0x01, 0x00000004 },
223 { 0x000942, 1, 0x01, 0x00010001 },
224 { 0x000943, 1, 0x01, 0x00000001 },
225 { 0x000944, 1, 0x01, 0x00000022 },
226 { 0x0007c5, 1, 0x01, 0x00010001 },
227 { 0x000834, 1, 0x01, 0x00000001 },
228 { 0x0007c7, 1, 0x01, 0x00000001 },
229 { 0x00c1b0, 8, 0x01, 0x0000000f },
230 { 0x00c1b8, 1, 0x01, 0x0fac6881 },
231 { 0x00c1b9, 1, 0x01, 0x00fac688 },
232 { 0x01e100, 1, 0x01, 0x00000001 },
233 { 0x001000, 1, 0x01, 0x00000002 },
234 { 0x0006aa, 1, 0x01, 0x00000001 },
235 { 0x0006ad, 2, 0x01, 0x00000100 },
236 { 0x0006b1, 1, 0x01, 0x00000011 },
237 { 0x00078c, 1, 0x01, 0x00000008 },
238 { 0x000792, 1, 0x01, 0x00000001 },
239 { 0x000794, 1, 0x01, 0x00000001 },
240 { 0x000795, 2, 0x01, 0x00000001 },
241 { 0x000797, 1, 0x01, 0x000000cf },
242 { 0x00079a, 1, 0x01, 0x00000002 },
243 { 0x000833, 1, 0x01, 0x04444480 },
244 { 0x0007a1, 1, 0x01, 0x00000001 },
245 { 0x0007a3, 1, 0x01, 0x00000001 },
246 { 0x0007a4, 2, 0x01, 0x00000001 },
247 { 0x000831, 1, 0x01, 0x00000004 },
248 { 0x01e100, 1, 0x01, 0x00000001 },
249 { 0x001000, 1, 0x01, 0x00000014 },
250 { 0x000351, 1, 0x01, 0x00000100 },
251 { 0x000957, 1, 0x01, 0x00000003 },
252 { 0x00095d, 1, 0x01, 0x00000001 },
253 { 0x00082b, 1, 0x01, 0x00000004 },
254 { 0x000942, 1, 0x01, 0x00010001 },
255 { 0x000943, 1, 0x01, 0x00000001 },
256 { 0x0007c5, 1, 0x01, 0x00010001 },
257 { 0x000834, 1, 0x01, 0x00000001 },
258 { 0x0007c7, 1, 0x01, 0x00000001 },
259 { 0x01e100, 1, 0x01, 0x00000001 },
260 { 0x001000, 1, 0x01, 0x00000001 },
261 { 0x00080c, 1, 0x01, 0x00000002 },
262 { 0x00080d, 2, 0x01, 0x00000100 },
263 { 0x00080f, 1, 0x01, 0x00000001 },
264 { 0x000823, 1, 0x01, 0x00000002 },
265 { 0x000824, 2, 0x01, 0x00000100 },
266 { 0x000826, 1, 0x01, 0x00000001 },
267 { 0x01e100, 1, 0x01, 0x00000001 },
268 {}
269};
270
271struct nvc0_graph_init
272nvc1_grctx_init_9097[] = {
273 { 0x000800, 8, 0x40, 0x00000000 },
274 { 0x000804, 8, 0x40, 0x00000000 },
275 { 0x000808, 8, 0x40, 0x00000400 },
276 { 0x00080c, 8, 0x40, 0x00000300 },
277 { 0x000810, 1, 0x04, 0x000000cf },
278 { 0x000850, 7, 0x40, 0x00000000 },
279 { 0x000814, 8, 0x40, 0x00000040 },
280 { 0x000818, 8, 0x40, 0x00000001 },
281 { 0x00081c, 8, 0x40, 0x00000000 },
282 { 0x000820, 8, 0x40, 0x00000000 },
283 { 0x002700, 8, 0x20, 0x00000000 },
284 { 0x002704, 8, 0x20, 0x00000000 },
285 { 0x002708, 8, 0x20, 0x00000000 },
286 { 0x00270c, 8, 0x20, 0x00000000 },
287 { 0x002710, 8, 0x20, 0x00014000 },
288 { 0x002714, 8, 0x20, 0x00000040 },
289 { 0x001c00, 16, 0x10, 0x00000000 },
290 { 0x001c04, 16, 0x10, 0x00000000 },
291 { 0x001c08, 16, 0x10, 0x00000000 },
292 { 0x001c0c, 16, 0x10, 0x00000000 },
293 { 0x001d00, 16, 0x10, 0x00000000 },
294 { 0x001d04, 16, 0x10, 0x00000000 },
295 { 0x001d08, 16, 0x10, 0x00000000 },
296 { 0x001d0c, 16, 0x10, 0x00000000 },
297 { 0x001f00, 16, 0x08, 0x00000000 },
298 { 0x001f04, 16, 0x08, 0x00000000 },
299 { 0x001f80, 16, 0x08, 0x00000000 },
300 { 0x001f84, 16, 0x08, 0x00000000 },
301 { 0x002200, 5, 0x10, 0x00000022 },
302 { 0x002000, 1, 0x04, 0x00000000 },
303 { 0x002040, 1, 0x04, 0x00000011 },
304 { 0x002080, 1, 0x04, 0x00000020 },
305 { 0x0020c0, 1, 0x04, 0x00000030 },
306 { 0x002100, 1, 0x04, 0x00000040 },
307 { 0x002140, 1, 0x04, 0x00000051 },
308 { 0x00200c, 6, 0x40, 0x00000001 },
309 { 0x002010, 1, 0x04, 0x00000000 },
310 { 0x002050, 1, 0x04, 0x00000000 },
311 { 0x002090, 1, 0x04, 0x00000001 },
312 { 0x0020d0, 1, 0x04, 0x00000002 },
313 { 0x002110, 1, 0x04, 0x00000003 },
314 { 0x002150, 1, 0x04, 0x00000004 },
315 { 0x000380, 4, 0x20, 0x00000000 },
316 { 0x000384, 4, 0x20, 0x00000000 },
317 { 0x000388, 4, 0x20, 0x00000000 },
318 { 0x00038c, 4, 0x20, 0x00000000 },
319 { 0x000700, 4, 0x10, 0x00000000 },
320 { 0x000704, 4, 0x10, 0x00000000 },
321 { 0x000708, 4, 0x10, 0x00000000 },
322 { 0x002800, 128, 0x04, 0x00000000 },
323 { 0x000a00, 16, 0x20, 0x00000000 },
324 { 0x000a04, 16, 0x20, 0x00000000 },
325 { 0x000a08, 16, 0x20, 0x00000000 },
326 { 0x000a0c, 16, 0x20, 0x00000000 },
327 { 0x000a10, 16, 0x20, 0x00000000 },
328 { 0x000a14, 16, 0x20, 0x00000000 },
329 { 0x000c00, 16, 0x10, 0x00000000 },
330 { 0x000c04, 16, 0x10, 0x00000000 },
331 { 0x000c08, 16, 0x10, 0x00000000 },
332 { 0x000c0c, 16, 0x10, 0x3f800000 },
333 { 0x000d00, 8, 0x08, 0xffff0000 },
334 { 0x000d04, 8, 0x08, 0xffff0000 },
335 { 0x000e00, 16, 0x10, 0x00000000 },
336 { 0x000e04, 16, 0x10, 0xffff0000 },
337 { 0x000e08, 16, 0x10, 0xffff0000 },
338 { 0x000d40, 4, 0x08, 0x00000000 },
339 { 0x000d44, 4, 0x08, 0x00000000 },
340 { 0x001e00, 8, 0x20, 0x00000001 },
341 { 0x001e04, 8, 0x20, 0x00000001 },
342 { 0x001e08, 8, 0x20, 0x00000002 },
343 { 0x001e0c, 8, 0x20, 0x00000001 },
344 { 0x001e10, 8, 0x20, 0x00000001 },
345 { 0x001e14, 8, 0x20, 0x00000002 },
346 { 0x001e18, 8, 0x20, 0x00000001 },
347 { 0x00030c, 1, 0x04, 0x00000001 },
348 { 0x001944, 1, 0x04, 0x00000000 },
349 { 0x001514, 1, 0x04, 0x00000000 },
350 { 0x000d68, 1, 0x04, 0x0000ffff },
351 { 0x00121c, 1, 0x04, 0x0fac6881 },
352 { 0x000fac, 1, 0x04, 0x00000001 },
353 { 0x001538, 1, 0x04, 0x00000001 },
354 { 0x000fe0, 2, 0x04, 0x00000000 },
355 { 0x000fe8, 1, 0x04, 0x00000014 },
356 { 0x000fec, 1, 0x04, 0x00000040 },
357 { 0x000ff0, 1, 0x04, 0x00000000 },
358 { 0x00179c, 1, 0x04, 0x00000000 },
359 { 0x001228, 1, 0x04, 0x00000400 },
360 { 0x00122c, 1, 0x04, 0x00000300 },
361 { 0x001230, 1, 0x04, 0x00010001 },
362 { 0x0007f8, 1, 0x04, 0x00000000 },
363 { 0x0015b4, 1, 0x04, 0x00000001 },
364 { 0x0015cc, 1, 0x04, 0x00000000 },
365 { 0x001534, 1, 0x04, 0x00000000 },
366 { 0x000fb0, 1, 0x04, 0x00000000 },
367 { 0x0015d0, 1, 0x04, 0x00000000 },
368 { 0x00153c, 1, 0x04, 0x00000000 },
369 { 0x0016b4, 1, 0x04, 0x00000003 },
370 { 0x000fbc, 4, 0x04, 0x0000ffff },
371 { 0x000df8, 2, 0x04, 0x00000000 },
372 { 0x001948, 1, 0x04, 0x00000000 },
373 { 0x001970, 1, 0x04, 0x00000001 },
374 { 0x00161c, 1, 0x04, 0x000009f0 },
375 { 0x000dcc, 1, 0x04, 0x00000010 },
376 { 0x00163c, 1, 0x04, 0x00000000 },
377 { 0x0015e4, 1, 0x04, 0x00000000 },
378 { 0x001160, 32, 0x04, 0x25e00040 },
379 { 0x001880, 32, 0x04, 0x00000000 },
380 { 0x000f84, 2, 0x04, 0x00000000 },
381 { 0x0017c8, 2, 0x04, 0x00000000 },
382 { 0x0017d0, 1, 0x04, 0x000000ff },
383 { 0x0017d4, 1, 0x04, 0xffffffff },
384 { 0x0017d8, 1, 0x04, 0x00000002 },
385 { 0x0017dc, 1, 0x04, 0x00000000 },
386 { 0x0015f4, 2, 0x04, 0x00000000 },
387 { 0x001434, 2, 0x04, 0x00000000 },
388 { 0x000d74, 1, 0x04, 0x00000000 },
389 { 0x000dec, 1, 0x04, 0x00000001 },
390 { 0x0013a4, 1, 0x04, 0x00000000 },
391 { 0x001318, 1, 0x04, 0x00000001 },
392 { 0x001644, 1, 0x04, 0x00000000 },
393 { 0x000748, 1, 0x04, 0x00000000 },
394 { 0x000de8, 1, 0x04, 0x00000000 },
395 { 0x001648, 1, 0x04, 0x00000000 },
396 { 0x0012a4, 1, 0x04, 0x00000000 },
397 { 0x001120, 4, 0x04, 0x00000000 },
398 { 0x001118, 1, 0x04, 0x00000000 },
399 { 0x00164c, 1, 0x04, 0x00000000 },
400 { 0x001658, 1, 0x04, 0x00000000 },
401 { 0x001910, 1, 0x04, 0x00000290 },
402 { 0x001518, 1, 0x04, 0x00000000 },
403 { 0x00165c, 1, 0x04, 0x00000001 },
404 { 0x001520, 1, 0x04, 0x00000000 },
405 { 0x001604, 1, 0x04, 0x00000000 },
406 { 0x001570, 1, 0x04, 0x00000000 },
407 { 0x0013b0, 2, 0x04, 0x3f800000 },
408 { 0x00020c, 1, 0x04, 0x00000000 },
409 { 0x001670, 1, 0x04, 0x30201000 },
410 { 0x001674, 1, 0x04, 0x70605040 },
411 { 0x001678, 1, 0x04, 0xb8a89888 },
412 { 0x00167c, 1, 0x04, 0xf8e8d8c8 },
413 { 0x00166c, 1, 0x04, 0x00000000 },
414 { 0x001680, 1, 0x04, 0x00ffff00 },
415 { 0x0012d0, 1, 0x04, 0x00000003 },
416 { 0x0012d4, 1, 0x04, 0x00000002 },
417 { 0x001684, 2, 0x04, 0x00000000 },
418 { 0x000dac, 2, 0x04, 0x00001b02 },
419 { 0x000db4, 1, 0x04, 0x00000000 },
420 { 0x00168c, 1, 0x04, 0x00000000 },
421 { 0x0015bc, 1, 0x04, 0x00000000 },
422 { 0x00156c, 1, 0x04, 0x00000000 },
423 { 0x00187c, 1, 0x04, 0x00000000 },
424 { 0x001110, 1, 0x04, 0x00000001 },
425 { 0x000dc0, 3, 0x04, 0x00000000 },
426 { 0x001234, 1, 0x04, 0x00000000 },
427 { 0x001690, 1, 0x04, 0x00000000 },
428 { 0x0012ac, 1, 0x04, 0x00000001 },
429 { 0x0002c4, 1, 0x04, 0x00000000 },
430 { 0x000790, 5, 0x04, 0x00000000 },
431 { 0x00077c, 1, 0x04, 0x00000000 },
432 { 0x001000, 1, 0x04, 0x00000010 },
433 { 0x0010fc, 1, 0x04, 0x00000000 },
434 { 0x001290, 1, 0x04, 0x00000000 },
435 { 0x000218, 1, 0x04, 0x00000010 },
436 { 0x0012d8, 1, 0x04, 0x00000000 },
437 { 0x0012dc, 1, 0x04, 0x00000010 },
438 { 0x000d94, 1, 0x04, 0x00000001 },
439 { 0x00155c, 2, 0x04, 0x00000000 },
440 { 0x001564, 1, 0x04, 0x00001fff },
441 { 0x001574, 2, 0x04, 0x00000000 },
442 { 0x00157c, 1, 0x04, 0x003fffff },
443 { 0x001354, 1, 0x04, 0x00000000 },
444 { 0x001664, 1, 0x04, 0x00000000 },
445 { 0x001610, 1, 0x04, 0x00000012 },
446 { 0x001608, 2, 0x04, 0x00000000 },
447 { 0x00162c, 1, 0x04, 0x00000003 },
448 { 0x000210, 1, 0x04, 0x00000000 },
449 { 0x000320, 1, 0x04, 0x00000000 },
450 { 0x000324, 6, 0x04, 0x3f800000 },
451 { 0x000750, 1, 0x04, 0x00000000 },
452 { 0x000760, 1, 0x04, 0x39291909 },
453 { 0x000764, 1, 0x04, 0x79695949 },
454 { 0x000768, 1, 0x04, 0xb9a99989 },
455 { 0x00076c, 1, 0x04, 0xf9e9d9c9 },
456 { 0x000770, 1, 0x04, 0x30201000 },
457 { 0x000774, 1, 0x04, 0x70605040 },
458 { 0x000778, 1, 0x04, 0x00009080 },
459 { 0x000780, 1, 0x04, 0x39291909 },
460 { 0x000784, 1, 0x04, 0x79695949 },
461 { 0x000788, 1, 0x04, 0xb9a99989 },
462 { 0x00078c, 1, 0x04, 0xf9e9d9c9 },
463 { 0x0007d0, 1, 0x04, 0x30201000 },
464 { 0x0007d4, 1, 0x04, 0x70605040 },
465 { 0x0007d8, 1, 0x04, 0x00009080 },
466 { 0x00037c, 1, 0x04, 0x00000001 },
467 { 0x000740, 2, 0x04, 0x00000000 },
468 { 0x002600, 1, 0x04, 0x00000000 },
469 { 0x001918, 1, 0x04, 0x00000000 },
470 { 0x00191c, 1, 0x04, 0x00000900 },
471 { 0x001920, 1, 0x04, 0x00000405 },
472 { 0x001308, 1, 0x04, 0x00000001 },
473 { 0x001924, 1, 0x04, 0x00000000 },
474 { 0x0013ac, 1, 0x04, 0x00000000 },
475 { 0x00192c, 1, 0x04, 0x00000001 },
476 { 0x00193c, 1, 0x04, 0x00002c1c },
477 { 0x000d7c, 1, 0x04, 0x00000000 },
478 { 0x000f8c, 1, 0x04, 0x00000000 },
479 { 0x0002c0, 1, 0x04, 0x00000001 },
480 { 0x001510, 1, 0x04, 0x00000000 },
481 { 0x001940, 1, 0x04, 0x00000000 },
482 { 0x000ff4, 2, 0x04, 0x00000000 },
483 { 0x00194c, 2, 0x04, 0x00000000 },
484 { 0x001968, 1, 0x04, 0x00000000 },
485 { 0x001590, 1, 0x04, 0x0000003f },
486 { 0x0007e8, 4, 0x04, 0x00000000 },
487 { 0x00196c, 1, 0x04, 0x00000011 },
488 { 0x00197c, 1, 0x04, 0x00000000 },
489 { 0x000fcc, 2, 0x04, 0x00000000 },
490 { 0x0002d8, 1, 0x04, 0x00000040 },
491 { 0x001980, 1, 0x04, 0x00000080 },
492 { 0x001504, 1, 0x04, 0x00000080 },
493 { 0x001984, 1, 0x04, 0x00000000 },
494 { 0x000300, 1, 0x04, 0x00000001 },
495 { 0x0013a8, 1, 0x04, 0x00000000 },
496 { 0x0012ec, 1, 0x04, 0x00000000 },
497 { 0x001310, 1, 0x04, 0x00000000 },
498 { 0x001314, 1, 0x04, 0x00000001 },
499 { 0x001380, 1, 0x04, 0x00000000 },
500 { 0x001384, 4, 0x04, 0x00000001 },
501 { 0x001394, 1, 0x04, 0x00000000 },
502 { 0x00139c, 1, 0x04, 0x00000000 },
503 { 0x001398, 1, 0x04, 0x00000000 },
504 { 0x001594, 1, 0x04, 0x00000000 },
505 { 0x001598, 4, 0x04, 0x00000001 },
506 { 0x000f54, 3, 0x04, 0x00000000 },
507 { 0x0019bc, 1, 0x04, 0x00000000 },
508 { 0x000f9c, 2, 0x04, 0x00000000 },
509 { 0x0012cc, 1, 0x04, 0x00000000 },
510 { 0x0012e8, 1, 0x04, 0x00000000 },
511 { 0x00130c, 1, 0x04, 0x00000001 },
512 { 0x001360, 8, 0x04, 0x00000000 },
513 { 0x00133c, 2, 0x04, 0x00000001 },
514 { 0x001344, 1, 0x04, 0x00000002 },
515 { 0x001348, 2, 0x04, 0x00000001 },
516 { 0x001350, 1, 0x04, 0x00000002 },
517 { 0x001358, 1, 0x04, 0x00000001 },
518 { 0x0012e4, 1, 0x04, 0x00000000 },
519 { 0x00131c, 1, 0x04, 0x00000000 },
520 { 0x001320, 3, 0x04, 0x00000000 },
521 { 0x0019c0, 1, 0x04, 0x00000000 },
522 { 0x001140, 1, 0x04, 0x00000000 },
523 { 0x0019c4, 1, 0x04, 0x00000000 },
524 { 0x0019c8, 1, 0x04, 0x00001500 },
525 { 0x00135c, 1, 0x04, 0x00000000 },
526 { 0x000f90, 1, 0x04, 0x00000000 },
527 { 0x0019e0, 8, 0x04, 0x00000001 },
528 { 0x0019cc, 1, 0x04, 0x00000001 },
529 { 0x0015b8, 1, 0x04, 0x00000000 },
530 { 0x001a00, 1, 0x04, 0x00001111 },
531 { 0x001a04, 7, 0x04, 0x00000000 },
532 { 0x000d6c, 2, 0x04, 0xffff0000 },
533 { 0x0010f8, 1, 0x04, 0x00001010 },
534 { 0x000d80, 5, 0x04, 0x00000000 },
535 { 0x000da0, 1, 0x04, 0x00000000 },
536 { 0x001508, 1, 0x04, 0x80000000 },
537 { 0x00150c, 1, 0x04, 0x40000000 },
538 { 0x001668, 1, 0x04, 0x00000000 },
539 { 0x000318, 2, 0x04, 0x00000008 },
540 { 0x000d9c, 1, 0x04, 0x00000001 },
541 { 0x0007dc, 1, 0x04, 0x00000000 },
542 { 0x00074c, 1, 0x04, 0x00000055 },
543 { 0x001420, 1, 0x04, 0x00000003 },
544 { 0x0017bc, 2, 0x04, 0x00000000 },
545 { 0x0017c4, 1, 0x04, 0x00000001 },
546 { 0x001008, 1, 0x04, 0x00000008 },
547 { 0x00100c, 1, 0x04, 0x00000040 },
548 { 0x001010, 1, 0x04, 0x0000012c },
549 { 0x000d60, 1, 0x04, 0x00000040 },
550 { 0x00075c, 1, 0x04, 0x00000003 },
551 { 0x001018, 1, 0x04, 0x00000020 },
552 { 0x00101c, 1, 0x04, 0x00000001 },
553 { 0x001020, 1, 0x04, 0x00000020 },
554 { 0x001024, 1, 0x04, 0x00000001 },
555 { 0x001444, 3, 0x04, 0x00000000 },
556 { 0x000360, 1, 0x04, 0x20164010 },
557 { 0x000364, 1, 0x04, 0x00000020 },
558 { 0x000368, 1, 0x04, 0x00000000 },
559 { 0x000de4, 1, 0x04, 0x00000000 },
560 { 0x000204, 1, 0x04, 0x00000006 },
561 { 0x000208, 1, 0x04, 0x00000000 },
562 { 0x0002cc, 1, 0x04, 0x003fffff },
563 { 0x0002d0, 1, 0x04, 0x00000c48 },
564 { 0x001220, 1, 0x04, 0x00000005 },
565 { 0x000fdc, 1, 0x04, 0x00000000 },
566 { 0x000f98, 1, 0x04, 0x00300008 },
567 { 0x001284, 1, 0x04, 0x04000080 },
568 { 0x001450, 1, 0x04, 0x00300008 },
569 { 0x001454, 1, 0x04, 0x04000080 },
570 { 0x000214, 1, 0x04, 0x00000000 },
571 {}
572};
573
574static struct nvc0_graph_init
575nvc1_grctx_init_9197[] = {
576 { 0x003400, 128, 0x04, 0x00000000 },
577 { 0x0002e4, 1, 0x04, 0x0000b001 },
578 {}
579};
580
581static struct nvc0_graph_init
582nvc1_grctx_init_unk58xx[] = {
583 { 0x405800, 1, 0x04, 0x0f8000bf },
584 { 0x405830, 1, 0x04, 0x02180218 },
585 { 0x405834, 2, 0x04, 0x00000000 },
586 { 0x405854, 1, 0x04, 0x00000000 },
587 { 0x405870, 4, 0x04, 0x00000001 },
588 { 0x405a00, 2, 0x04, 0x00000000 },
589 { 0x405a18, 1, 0x04, 0x00000000 },
590};
591
592static struct nvc0_graph_init
593nvc1_grctx_init_rop[] = {
594 { 0x408800, 1, 0x04, 0x02802a3c },
595 { 0x408804, 1, 0x04, 0x00000040 },
596 { 0x408808, 1, 0x04, 0x1003e005 },
597 { 0x408900, 1, 0x04, 0x3080b801 },
598 { 0x408904, 1, 0x04, 0x62000001 },
599 { 0x408908, 1, 0x04, 0x00c80929 },
600 { 0x408980, 1, 0x04, 0x0000011d },
601};
602
603static struct nvc0_graph_init
604nvc1_grctx_init_gpc_0[] = {
605 { 0x418380, 1, 0x04, 0x00000016 },
606 { 0x418400, 1, 0x04, 0x38004e00 },
607 { 0x418404, 1, 0x04, 0x71e0ffff },
608 { 0x418408, 1, 0x04, 0x00000000 },
609 { 0x41840c, 1, 0x04, 0x00001008 },
610 { 0x418410, 1, 0x04, 0x0fff0fff },
611 { 0x418414, 1, 0x04, 0x00200fff },
612 { 0x418450, 6, 0x04, 0x00000000 },
613 { 0x418468, 1, 0x04, 0x00000001 },
614 { 0x41846c, 2, 0x04, 0x00000000 },
615 { 0x418600, 1, 0x04, 0x0000001f },
616 { 0x418684, 1, 0x04, 0x0000000f },
617 { 0x418700, 1, 0x04, 0x00000002 },
618 { 0x418704, 1, 0x04, 0x00000080 },
619 { 0x418708, 1, 0x04, 0x00000000 },
620 { 0x41870c, 1, 0x04, 0x07c80000 },
621 { 0x418710, 1, 0x04, 0x00000000 },
622 { 0x418800, 1, 0x04, 0x0006860a },
623 { 0x418808, 3, 0x04, 0x00000000 },
624 { 0x418828, 1, 0x04, 0x00008442 },
625 { 0x418830, 1, 0x04, 0x10000001 },
626 { 0x4188d8, 1, 0x04, 0x00000008 },
627 { 0x4188e0, 1, 0x04, 0x01000000 },
628 { 0x4188e8, 5, 0x04, 0x00000000 },
629 { 0x4188fc, 1, 0x04, 0x00100018 },
630 { 0x41891c, 1, 0x04, 0x00ff00ff },
631 { 0x418924, 1, 0x04, 0x00000000 },
632 { 0x418928, 1, 0x04, 0x00ffff00 },
633 { 0x41892c, 1, 0x04, 0x0000ff00 },
634 { 0x418a00, 3, 0x04, 0x00000000 },
635 { 0x418a0c, 1, 0x04, 0x00010000 },
636 { 0x418a10, 3, 0x04, 0x00000000 },
637 { 0x418a20, 3, 0x04, 0x00000000 },
638 { 0x418a2c, 1, 0x04, 0x00010000 },
639 { 0x418a30, 3, 0x04, 0x00000000 },
640 { 0x418a40, 3, 0x04, 0x00000000 },
641 { 0x418a4c, 1, 0x04, 0x00010000 },
642 { 0x418a50, 3, 0x04, 0x00000000 },
643 { 0x418a60, 3, 0x04, 0x00000000 },
644 { 0x418a6c, 1, 0x04, 0x00010000 },
645 { 0x418a70, 3, 0x04, 0x00000000 },
646 { 0x418a80, 3, 0x04, 0x00000000 },
647 { 0x418a8c, 1, 0x04, 0x00010000 },
648 { 0x418a90, 3, 0x04, 0x00000000 },
649 { 0x418aa0, 3, 0x04, 0x00000000 },
650 { 0x418aac, 1, 0x04, 0x00010000 },
651 { 0x418ab0, 3, 0x04, 0x00000000 },
652 { 0x418ac0, 3, 0x04, 0x00000000 },
653 { 0x418acc, 1, 0x04, 0x00010000 },
654 { 0x418ad0, 3, 0x04, 0x00000000 },
655 { 0x418ae0, 3, 0x04, 0x00000000 },
656 { 0x418aec, 1, 0x04, 0x00010000 },
657 { 0x418af0, 3, 0x04, 0x00000000 },
658 { 0x418b00, 1, 0x04, 0x00000000 },
659 { 0x418b08, 1, 0x04, 0x0a418820 },
660 { 0x418b0c, 1, 0x04, 0x062080e6 },
661 { 0x418b10, 1, 0x04, 0x020398a4 },
662 { 0x418b14, 1, 0x04, 0x0e629062 },
663 { 0x418b18, 1, 0x04, 0x0a418820 },
664 { 0x418b1c, 1, 0x04, 0x000000e6 },
665 { 0x418bb8, 1, 0x04, 0x00000103 },
666 { 0x418c08, 1, 0x04, 0x00000001 },
667 { 0x418c10, 8, 0x04, 0x00000000 },
668 { 0x418c6c, 1, 0x04, 0x00000001 },
669 { 0x418c80, 1, 0x04, 0x20200004 },
670 { 0x418c8c, 1, 0x04, 0x00000001 },
671 { 0x419000, 1, 0x04, 0x00000780 },
672 { 0x419004, 2, 0x04, 0x00000000 },
673 { 0x419014, 1, 0x04, 0x00000004 },
674};
675
676static struct nvc0_graph_init
677nvc1_grctx_init_tpc[] = {
678 { 0x419818, 1, 0x04, 0x00000000 },
679 { 0x41983c, 1, 0x04, 0x00038bc7 },
680 { 0x419848, 1, 0x04, 0x00000000 },
681 { 0x419864, 1, 0x04, 0x00000129 },
682 { 0x419888, 1, 0x04, 0x00000000 },
683 { 0x419a00, 1, 0x04, 0x000001f0 },
684 { 0x419a04, 1, 0x04, 0x00000001 },
685 { 0x419a08, 1, 0x04, 0x00000023 },
686 { 0x419a0c, 1, 0x04, 0x00020000 },
687 { 0x419a10, 1, 0x04, 0x00000000 },
688 { 0x419a14, 1, 0x04, 0x00000200 },
689 { 0x419a1c, 1, 0x04, 0x00000000 },
690 { 0x419a20, 1, 0x04, 0x00000800 },
691 { 0x419ac4, 1, 0x04, 0x0007f440 },
692 { 0x419b00, 1, 0x04, 0x0a418820 },
693 { 0x419b04, 1, 0x04, 0x062080e6 },
694 { 0x419b08, 1, 0x04, 0x020398a4 },
695 { 0x419b0c, 1, 0x04, 0x0e629062 },
696 { 0x419b10, 1, 0x04, 0x0a418820 },
697 { 0x419b14, 1, 0x04, 0x000000e6 },
698 { 0x419bd0, 1, 0x04, 0x00900103 },
699 { 0x419be0, 1, 0x04, 0x00400001 },
700 { 0x419be4, 1, 0x04, 0x00000000 },
701 { 0x419c00, 1, 0x04, 0x00000002 },
702 { 0x419c04, 1, 0x04, 0x00000006 },
703 { 0x419c08, 1, 0x04, 0x00000002 },
704 { 0x419c20, 1, 0x04, 0x00000000 },
705 { 0x419cb0, 1, 0x04, 0x00020048 },
706 { 0x419ce8, 1, 0x04, 0x00000000 },
707 { 0x419cf4, 1, 0x04, 0x00000183 },
708 { 0x419d20, 1, 0x04, 0x12180000 },
709 { 0x419d24, 1, 0x04, 0x00001fff },
710 { 0x419d44, 1, 0x04, 0x02180218 },
711 { 0x419e04, 3, 0x04, 0x00000000 },
712 { 0x419e10, 1, 0x04, 0x00000002 },
713 { 0x419e44, 1, 0x04, 0x001beff2 },
714 { 0x419e48, 1, 0x04, 0x00000000 },
715 { 0x419e4c, 1, 0x04, 0x0000000f },
716 { 0x419e50, 17, 0x04, 0x00000000 },
717 { 0x419e98, 1, 0x04, 0x00000000 },
718 { 0x419ee0, 1, 0x04, 0x00011110 },
719 { 0x419f30, 11, 0x04, 0x00000000 },
720};
721
722void
723nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
724{
725 int gpc, tpc;
726 u32 offset;
727
728 mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
729 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
730 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
731 mmio_list(0x408004, 0x00000000, 8, 0);
732 mmio_list(0x408008, 0x80000018, 0, 0);
733 mmio_list(0x40800c, 0x00000000, 8, 1);
734 mmio_list(0x408010, 0x80000000, 0, 0);
735 mmio_list(0x418810, 0x80000000, 12, 2);
736 mmio_list(0x419848, 0x10000000, 12, 2);
737 mmio_list(0x419004, 0x00000000, 8, 1);
738 mmio_list(0x419008, 0x00000000, 0, 0);
739 mmio_list(0x418808, 0x00000000, 8, 0);
740 mmio_list(0x41880c, 0x80000018, 0, 0);
741
742 mmio_list(0x405830, 0x02180218, 0, 0);
743 mmio_list(0x4064c4, 0x0086ffff, 0, 0);
744
745 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
746 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
747 u32 addr = TPC_UNIT(gpc, tpc, 0x0520);
748 mmio_list(addr, 0x12180000 | offset, 0, 0);
749 offset += 0x0324;
750 }
751 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
752 u32 addr = TPC_UNIT(gpc, tpc, 0x0544);
753 mmio_list(addr, 0x02180000 | offset, 0, 0);
754 offset += 0x0324;
755 }
756 }
757}
758
759void
760nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
761{
762 nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
763 nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
764 nv_mask(priv, 0x419814, 0x00000004, 0x00000004);
765 nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
766 nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
767 nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
768}
769
770static struct nvc0_graph_init *
771nvc1_grctx_init_hub[] = {
772 nvc0_grctx_init_base,
773 nvc0_grctx_init_unk40xx,
774 nvc0_grctx_init_unk44xx,
775 nvc0_grctx_init_unk46xx,
776 nvc0_grctx_init_unk47xx,
777 nvc1_grctx_init_unk58xx,
778 nvc0_grctx_init_unk60xx,
779 nvc0_grctx_init_unk64xx,
780 nvc0_grctx_init_unk78xx,
781 nvc0_grctx_init_unk80xx,
782 nvc1_grctx_init_rop,
783 NULL
784};
785
786struct nvc0_graph_init *
787nvc1_grctx_init_gpc[] = {
788 nvc1_grctx_init_gpc_0,
789 nvc0_grctx_init_gpc_1,
790 nvc1_grctx_init_tpc,
791 NULL
792};
793
794static struct nvc0_graph_mthd
795nvc1_grctx_init_mthd[] = {
796 { 0x9097, nvc1_grctx_init_9097, },
797 { 0x9197, nvc1_grctx_init_9197, },
798 { 0x902d, nvc0_grctx_init_902d, },
799 { 0x9039, nvc0_grctx_init_9039, },
800 { 0x90c0, nvc0_grctx_init_90c0, },
801 { 0x902d, nvc0_grctx_init_mthd_magic, },
802 {}
803};
804
805struct nouveau_oclass *
806nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
807 .base.handle = NV_ENGCTX(GR, 0xc1),
808 .base.ofuncs = &(struct nouveau_ofuncs) {
809 .ctor = nvc0_graph_context_ctor,
810 .dtor = nvc0_graph_context_dtor,
811 .init = _nouveau_graph_context_init,
812 .fini = _nouveau_graph_context_fini,
813 .rd32 = _nouveau_graph_context_rd32,
814 .wr32 = _nouveau_graph_context_wr32,
815 },
816 .main = nvc0_grctx_generate_main,
817 .mods = nvc1_grctx_generate_mods,
818 .unkn = nvc1_grctx_generate_unkn,
819 .hub = nvc1_grctx_init_hub,
820 .gpc = nvc1_grctx_init_gpc,
821 .icmd = nvc1_grctx_init_icmd,
822 .mthd = nvc1_grctx_init_mthd,
823}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c
new file mode 100644
index 000000000000..8f237b3bd8c6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27static struct nvc0_graph_init
28nvc3_grctx_init_tpc[] = {
29 { 0x419818, 1, 0x04, 0x00000000 },
30 { 0x41983c, 1, 0x04, 0x00038bc7 },
31 { 0x419848, 1, 0x04, 0x00000000 },
32 { 0x419864, 1, 0x04, 0x0000012a },
33 { 0x419888, 1, 0x04, 0x00000000 },
34 { 0x419a00, 1, 0x04, 0x000001f0 },
35 { 0x419a04, 1, 0x04, 0x00000001 },
36 { 0x419a08, 1, 0x04, 0x00000023 },
37 { 0x419a0c, 1, 0x04, 0x00020000 },
38 { 0x419a10, 1, 0x04, 0x00000000 },
39 { 0x419a14, 1, 0x04, 0x00000200 },
40 { 0x419a1c, 1, 0x04, 0x00000000 },
41 { 0x419a20, 1, 0x04, 0x00000800 },
42 { 0x419ac4, 1, 0x04, 0x0007f440 },
43 { 0x419b00, 1, 0x04, 0x0a418820 },
44 { 0x419b04, 1, 0x04, 0x062080e6 },
45 { 0x419b08, 1, 0x04, 0x020398a4 },
46 { 0x419b0c, 1, 0x04, 0x0e629062 },
47 { 0x419b10, 1, 0x04, 0x0a418820 },
48 { 0x419b14, 1, 0x04, 0x000000e6 },
49 { 0x419bd0, 1, 0x04, 0x00900103 },
50 { 0x419be0, 1, 0x04, 0x00000001 },
51 { 0x419be4, 1, 0x04, 0x00000000 },
52 { 0x419c00, 1, 0x04, 0x00000002 },
53 { 0x419c04, 1, 0x04, 0x00000006 },
54 { 0x419c08, 1, 0x04, 0x00000002 },
55 { 0x419c20, 1, 0x04, 0x00000000 },
56 { 0x419cb0, 1, 0x04, 0x00020048 },
57 { 0x419ce8, 1, 0x04, 0x00000000 },
58 { 0x419cf4, 1, 0x04, 0x00000183 },
59 { 0x419d20, 1, 0x04, 0x02180000 },
60 { 0x419d24, 1, 0x04, 0x00001fff },
61 { 0x419e04, 3, 0x04, 0x00000000 },
62 { 0x419e10, 1, 0x04, 0x00000002 },
63 { 0x419e44, 1, 0x04, 0x001beff2 },
64 { 0x419e48, 1, 0x04, 0x00000000 },
65 { 0x419e4c, 1, 0x04, 0x0000000f },
66 { 0x419e50, 17, 0x04, 0x00000000 },
67 { 0x419e98, 1, 0x04, 0x00000000 },
68 { 0x419ee0, 1, 0x04, 0x00011110 },
69 { 0x419f30, 11, 0x04, 0x00000000 },
70 {}
71};
72
73struct nvc0_graph_init *
74nvc3_grctx_init_gpc[] = {
75 nvc0_grctx_init_gpc_0,
76 nvc0_grctx_init_gpc_1,
77 nvc3_grctx_init_tpc,
78 NULL
79};
80
81struct nouveau_oclass *
82nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) {
83 .base.handle = NV_ENGCTX(GR, 0xc3),
84 .base.ofuncs = &(struct nouveau_ofuncs) {
85 .ctor = nvc0_graph_context_ctor,
86 .dtor = nvc0_graph_context_dtor,
87 .init = _nouveau_graph_context_init,
88 .fini = _nouveau_graph_context_fini,
89 .rd32 = _nouveau_graph_context_rd32,
90 .wr32 = _nouveau_graph_context_wr32,
91 },
92 .main = nvc0_grctx_generate_main,
93 .mods = nvc0_grctx_generate_mods,
94 .unkn = nvc0_grctx_generate_unkn,
95 .hub = nvc0_grctx_init_hub,
96 .gpc = nvc3_grctx_init_gpc,
97 .icmd = nvc0_grctx_init_icmd,
98 .mthd = nvc0_grctx_init_mthd,
99}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
new file mode 100644
index 000000000000..d0d4ce3c4892
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
@@ -0,0 +1,370 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27static struct nvc0_graph_init
28nvc8_grctx_init_icmd[] = {
29 { 0x001000, 1, 0x01, 0x00000004 },
30 { 0x0000a9, 1, 0x01, 0x0000ffff },
31 { 0x000038, 1, 0x01, 0x0fac6881 },
32 { 0x00003d, 1, 0x01, 0x00000001 },
33 { 0x0000e8, 8, 0x01, 0x00000400 },
34 { 0x000078, 8, 0x01, 0x00000300 },
35 { 0x000050, 1, 0x01, 0x00000011 },
36 { 0x000058, 8, 0x01, 0x00000008 },
37 { 0x000208, 8, 0x01, 0x00000001 },
38 { 0x000081, 1, 0x01, 0x00000001 },
39 { 0x000085, 1, 0x01, 0x00000004 },
40 { 0x000088, 1, 0x01, 0x00000400 },
41 { 0x000090, 1, 0x01, 0x00000300 },
42 { 0x000098, 1, 0x01, 0x00001001 },
43 { 0x0000e3, 1, 0x01, 0x00000001 },
44 { 0x0000da, 1, 0x01, 0x00000001 },
45 { 0x0000f8, 1, 0x01, 0x00000003 },
46 { 0x0000fa, 1, 0x01, 0x00000001 },
47 { 0x00009f, 4, 0x01, 0x0000ffff },
48 { 0x0000b1, 1, 0x01, 0x00000001 },
49 { 0x0000b2, 40, 0x01, 0x00000000 },
50 { 0x000210, 8, 0x01, 0x00000040 },
51 { 0x000218, 8, 0x01, 0x0000c080 },
52 { 0x0000ad, 1, 0x01, 0x0000013e },
53 { 0x0000e1, 1, 0x01, 0x00000010 },
54 { 0x000290, 16, 0x01, 0x00000000 },
55 { 0x0003b0, 16, 0x01, 0x00000000 },
56 { 0x0002a0, 16, 0x01, 0x00000000 },
57 { 0x000420, 16, 0x01, 0x00000000 },
58 { 0x0002b0, 16, 0x01, 0x00000000 },
59 { 0x000430, 16, 0x01, 0x00000000 },
60 { 0x0002c0, 16, 0x01, 0x00000000 },
61 { 0x0004d0, 16, 0x01, 0x00000000 },
62 { 0x000720, 16, 0x01, 0x00000000 },
63 { 0x0008c0, 16, 0x01, 0x00000000 },
64 { 0x000890, 16, 0x01, 0x00000000 },
65 { 0x0008e0, 16, 0x01, 0x00000000 },
66 { 0x0008a0, 16, 0x01, 0x00000000 },
67 { 0x0008f0, 16, 0x01, 0x00000000 },
68 { 0x00094c, 1, 0x01, 0x000000ff },
69 { 0x00094d, 1, 0x01, 0xffffffff },
70 { 0x00094e, 1, 0x01, 0x00000002 },
71 { 0x0002ec, 1, 0x01, 0x00000001 },
72 { 0x000303, 1, 0x01, 0x00000001 },
73 { 0x0002e6, 1, 0x01, 0x00000001 },
74 { 0x000466, 1, 0x01, 0x00000052 },
75 { 0x000301, 1, 0x01, 0x3f800000 },
76 { 0x000304, 1, 0x01, 0x30201000 },
77 { 0x000305, 1, 0x01, 0x70605040 },
78 { 0x000306, 1, 0x01, 0xb8a89888 },
79 { 0x000307, 1, 0x01, 0xf8e8d8c8 },
80 { 0x00030a, 1, 0x01, 0x00ffff00 },
81 { 0x00030b, 1, 0x01, 0x0000001a },
82 { 0x00030c, 1, 0x01, 0x00000001 },
83 { 0x000318, 1, 0x01, 0x00000001 },
84 { 0x000340, 1, 0x01, 0x00000000 },
85 { 0x000375, 1, 0x01, 0x00000001 },
86 { 0x000351, 1, 0x01, 0x00000100 },
87 { 0x00037d, 1, 0x01, 0x00000006 },
88 { 0x0003a0, 1, 0x01, 0x00000002 },
89 { 0x0003aa, 1, 0x01, 0x00000001 },
90 { 0x0003a9, 1, 0x01, 0x00000001 },
91 { 0x000380, 1, 0x01, 0x00000001 },
92 { 0x000360, 1, 0x01, 0x00000040 },
93 { 0x000366, 2, 0x01, 0x00000000 },
94 { 0x000368, 1, 0x01, 0x00001fff },
95 { 0x000370, 2, 0x01, 0x00000000 },
96 { 0x000372, 1, 0x01, 0x003fffff },
97 { 0x00037a, 1, 0x01, 0x00000012 },
98 { 0x0005e0, 5, 0x01, 0x00000022 },
99 { 0x000619, 1, 0x01, 0x00000003 },
100 { 0x000811, 1, 0x01, 0x00000003 },
101 { 0x000812, 1, 0x01, 0x00000004 },
102 { 0x000813, 1, 0x01, 0x00000006 },
103 { 0x000814, 1, 0x01, 0x00000008 },
104 { 0x000815, 1, 0x01, 0x0000000b },
105 { 0x000800, 6, 0x01, 0x00000001 },
106 { 0x000632, 1, 0x01, 0x00000001 },
107 { 0x000633, 1, 0x01, 0x00000002 },
108 { 0x000634, 1, 0x01, 0x00000003 },
109 { 0x000635, 1, 0x01, 0x00000004 },
110 { 0x000654, 1, 0x01, 0x3f800000 },
111 { 0x000657, 1, 0x01, 0x3f800000 },
112 { 0x000655, 2, 0x01, 0x3f800000 },
113 { 0x0006cd, 1, 0x01, 0x3f800000 },
114 { 0x0007f5, 1, 0x01, 0x3f800000 },
115 { 0x0007dc, 1, 0x01, 0x39291909 },
116 { 0x0007dd, 1, 0x01, 0x79695949 },
117 { 0x0007de, 1, 0x01, 0xb9a99989 },
118 { 0x0007df, 1, 0x01, 0xf9e9d9c9 },
119 { 0x0007e8, 1, 0x01, 0x00003210 },
120 { 0x0007e9, 1, 0x01, 0x00007654 },
121 { 0x0007ea, 1, 0x01, 0x00000098 },
122 { 0x0007ec, 1, 0x01, 0x39291909 },
123 { 0x0007ed, 1, 0x01, 0x79695949 },
124 { 0x0007ee, 1, 0x01, 0xb9a99989 },
125 { 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
126 { 0x0007f0, 1, 0x01, 0x00003210 },
127 { 0x0007f1, 1, 0x01, 0x00007654 },
128 { 0x0007f2, 1, 0x01, 0x00000098 },
129 { 0x0005a5, 1, 0x01, 0x00000001 },
130 { 0x000980, 128, 0x01, 0x00000000 },
131 { 0x000468, 1, 0x01, 0x00000004 },
132 { 0x00046c, 1, 0x01, 0x00000001 },
133 { 0x000470, 96, 0x01, 0x00000000 },
134 { 0x000510, 16, 0x01, 0x3f800000 },
135 { 0x000520, 1, 0x01, 0x000002b6 },
136 { 0x000529, 1, 0x01, 0x00000001 },
137 { 0x000530, 16, 0x01, 0xffff0000 },
138 { 0x000585, 1, 0x01, 0x0000003f },
139 { 0x000576, 1, 0x01, 0x00000003 },
140 { 0x00057b, 1, 0x01, 0x00000059 },
141 { 0x000586, 1, 0x01, 0x00000040 },
142 { 0x000582, 2, 0x01, 0x00000080 },
143 { 0x0005c2, 1, 0x01, 0x00000001 },
144 { 0x000638, 1, 0x01, 0x00000001 },
145 { 0x000639, 1, 0x01, 0x00000001 },
146 { 0x00063a, 1, 0x01, 0x00000002 },
147 { 0x00063b, 2, 0x01, 0x00000001 },
148 { 0x00063d, 1, 0x01, 0x00000002 },
149 { 0x00063e, 1, 0x01, 0x00000001 },
150 { 0x0008b8, 8, 0x01, 0x00000001 },
151 { 0x000900, 8, 0x01, 0x00000001 },
152 { 0x000908, 8, 0x01, 0x00000002 },
153 { 0x000910, 16, 0x01, 0x00000001 },
154 { 0x000920, 8, 0x01, 0x00000002 },
155 { 0x000928, 8, 0x01, 0x00000001 },
156 { 0x000648, 9, 0x01, 0x00000001 },
157 { 0x000658, 1, 0x01, 0x0000000f },
158 { 0x0007ff, 1, 0x01, 0x0000000a },
159 { 0x00066a, 1, 0x01, 0x40000000 },
160 { 0x00066b, 1, 0x01, 0x10000000 },
161 { 0x00066c, 2, 0x01, 0xffff0000 },
162 { 0x0007af, 2, 0x01, 0x00000008 },
163 { 0x0007f6, 1, 0x01, 0x00000001 },
164 { 0x0006b2, 1, 0x01, 0x00000055 },
165 { 0x0007ad, 1, 0x01, 0x00000003 },
166 { 0x000937, 1, 0x01, 0x00000001 },
167 { 0x000971, 1, 0x01, 0x00000008 },
168 { 0x000972, 1, 0x01, 0x00000040 },
169 { 0x000973, 1, 0x01, 0x0000012c },
170 { 0x00097c, 1, 0x01, 0x00000040 },
171 { 0x000979, 1, 0x01, 0x00000003 },
172 { 0x000975, 1, 0x01, 0x00000020 },
173 { 0x000976, 1, 0x01, 0x00000001 },
174 { 0x000977, 1, 0x01, 0x00000020 },
175 { 0x000978, 1, 0x01, 0x00000001 },
176 { 0x000957, 1, 0x01, 0x00000003 },
177 { 0x00095e, 1, 0x01, 0x20164010 },
178 { 0x00095f, 1, 0x01, 0x00000020 },
179 { 0x00097d, 1, 0x01, 0x00000020 },
180 { 0x000683, 1, 0x01, 0x00000006 },
181 { 0x000685, 1, 0x01, 0x003fffff },
182 { 0x000687, 1, 0x01, 0x00000c48 },
183 { 0x0006a0, 1, 0x01, 0x00000005 },
184 { 0x000840, 1, 0x01, 0x00300008 },
185 { 0x000841, 1, 0x01, 0x04000080 },
186 { 0x000842, 1, 0x01, 0x00300008 },
187 { 0x000843, 1, 0x01, 0x04000080 },
188 { 0x000818, 8, 0x01, 0x00000000 },
189 { 0x000848, 16, 0x01, 0x00000000 },
190 { 0x000738, 1, 0x01, 0x00000000 },
191 { 0x0006aa, 1, 0x01, 0x00000001 },
192 { 0x0006ab, 1, 0x01, 0x00000002 },
193 { 0x0006ac, 1, 0x01, 0x00000080 },
194 { 0x0006ad, 2, 0x01, 0x00000100 },
195 { 0x0006b1, 1, 0x01, 0x00000011 },
196 { 0x0006bb, 1, 0x01, 0x000000cf },
197 { 0x0006ce, 1, 0x01, 0x2a712488 },
198 { 0x000739, 1, 0x01, 0x4085c000 },
199 { 0x00073a, 1, 0x01, 0x00000080 },
200 { 0x000786, 1, 0x01, 0x80000100 },
201 { 0x00073c, 1, 0x01, 0x00010100 },
202 { 0x00073d, 1, 0x01, 0x02800000 },
203 { 0x000787, 1, 0x01, 0x000000cf },
204 { 0x00078c, 1, 0x01, 0x00000008 },
205 { 0x000792, 1, 0x01, 0x00000001 },
206 { 0x000794, 1, 0x01, 0x00000001 },
207 { 0x000795, 2, 0x01, 0x00000001 },
208 { 0x000797, 1, 0x01, 0x000000cf },
209 { 0x000836, 1, 0x01, 0x00000001 },
210 { 0x00079a, 1, 0x01, 0x00000002 },
211 { 0x000833, 1, 0x01, 0x04444480 },
212 { 0x0007a1, 1, 0x01, 0x00000001 },
213 { 0x0007a3, 1, 0x01, 0x00000001 },
214 { 0x0007a4, 2, 0x01, 0x00000001 },
215 { 0x000831, 1, 0x01, 0x00000004 },
216 { 0x00080c, 1, 0x01, 0x00000002 },
217 { 0x00080d, 2, 0x01, 0x00000100 },
218 { 0x00080f, 1, 0x01, 0x00000001 },
219 { 0x000823, 1, 0x01, 0x00000002 },
220 { 0x000824, 2, 0x01, 0x00000100 },
221 { 0x000826, 1, 0x01, 0x00000001 },
222 { 0x00095d, 1, 0x01, 0x00000001 },
223 { 0x00082b, 1, 0x01, 0x00000004 },
224 { 0x000942, 1, 0x01, 0x00010001 },
225 { 0x000943, 1, 0x01, 0x00000001 },
226 { 0x000944, 1, 0x01, 0x00000022 },
227 { 0x0007c5, 1, 0x01, 0x00010001 },
228 { 0x000834, 1, 0x01, 0x00000001 },
229 { 0x0007c7, 1, 0x01, 0x00000001 },
230 { 0x00c1b0, 8, 0x01, 0x0000000f },
231 { 0x00c1b8, 1, 0x01, 0x0fac6881 },
232 { 0x00c1b9, 1, 0x01, 0x00fac688 },
233 { 0x01e100, 1, 0x01, 0x00000001 },
234 { 0x001000, 1, 0x01, 0x00000002 },
235 { 0x0006aa, 1, 0x01, 0x00000001 },
236 { 0x0006ad, 2, 0x01, 0x00000100 },
237 { 0x0006b1, 1, 0x01, 0x00000011 },
238 { 0x00078c, 1, 0x01, 0x00000008 },
239 { 0x000792, 1, 0x01, 0x00000001 },
240 { 0x000794, 1, 0x01, 0x00000001 },
241 { 0x000795, 2, 0x01, 0x00000001 },
242 { 0x000797, 1, 0x01, 0x000000cf },
243 { 0x00079a, 1, 0x01, 0x00000002 },
244 { 0x000833, 1, 0x01, 0x04444480 },
245 { 0x0007a1, 1, 0x01, 0x00000001 },
246 { 0x0007a3, 1, 0x01, 0x00000001 },
247 { 0x0007a4, 2, 0x01, 0x00000001 },
248 { 0x000831, 1, 0x01, 0x00000004 },
249 { 0x01e100, 1, 0x01, 0x00000001 },
250 { 0x001000, 1, 0x01, 0x00000014 },
251 { 0x000351, 1, 0x01, 0x00000100 },
252 { 0x000957, 1, 0x01, 0x00000003 },
253 { 0x00095d, 1, 0x01, 0x00000001 },
254 { 0x00082b, 1, 0x01, 0x00000004 },
255 { 0x000942, 1, 0x01, 0x00010001 },
256 { 0x000943, 1, 0x01, 0x00000001 },
257 { 0x0007c5, 1, 0x01, 0x00010001 },
258 { 0x000834, 1, 0x01, 0x00000001 },
259 { 0x0007c7, 1, 0x01, 0x00000001 },
260 { 0x01e100, 1, 0x01, 0x00000001 },
261 { 0x001000, 1, 0x01, 0x00000001 },
262 { 0x00080c, 1, 0x01, 0x00000002 },
263 { 0x00080d, 2, 0x01, 0x00000100 },
264 { 0x00080f, 1, 0x01, 0x00000001 },
265 { 0x000823, 1, 0x01, 0x00000002 },
266 { 0x000824, 2, 0x01, 0x00000100 },
267 { 0x000826, 1, 0x01, 0x00000001 },
268 { 0x01e100, 1, 0x01, 0x00000001 },
269 {}
270};
271
272static struct nvc0_graph_init
273nvc8_grctx_init_tpc[] = {
274 { 0x419818, 1, 0x04, 0x00000000 },
275 { 0x41983c, 1, 0x04, 0x00038bc7 },
276 { 0x419848, 1, 0x04, 0x00000000 },
277 { 0x419864, 1, 0x04, 0x0000012a },
278 { 0x419888, 1, 0x04, 0x00000000 },
279 { 0x419a00, 1, 0x04, 0x000001f0 },
280 { 0x419a04, 1, 0x04, 0x00000001 },
281 { 0x419a08, 1, 0x04, 0x00000023 },
282 { 0x419a0c, 1, 0x04, 0x00020000 },
283 { 0x419a10, 1, 0x04, 0x00000000 },
284 { 0x419a14, 1, 0x04, 0x00000200 },
285 { 0x419a1c, 1, 0x04, 0x00000000 },
286 { 0x419a20, 1, 0x04, 0x00000800 },
287 { 0x419b00, 1, 0x04, 0x0a418820 },
288 { 0x419b04, 1, 0x04, 0x062080e6 },
289 { 0x419b08, 1, 0x04, 0x020398a4 },
290 { 0x419b0c, 1, 0x04, 0x0e629062 },
291 { 0x419b10, 1, 0x04, 0x0a418820 },
292 { 0x419b14, 1, 0x04, 0x000000e6 },
293 { 0x419bd0, 1, 0x04, 0x00900103 },
294 { 0x419be0, 1, 0x04, 0x00000001 },
295 { 0x419be4, 1, 0x04, 0x00000000 },
296 { 0x419c00, 1, 0x04, 0x00000002 },
297 { 0x419c04, 1, 0x04, 0x00000006 },
298 { 0x419c08, 1, 0x04, 0x00000002 },
299 { 0x419c20, 1, 0x04, 0x00000000 },
300 { 0x419cb0, 1, 0x04, 0x00060048 },
301 { 0x419ce8, 1, 0x04, 0x00000000 },
302 { 0x419cf4, 1, 0x04, 0x00000183 },
303 { 0x419d20, 1, 0x04, 0x02180000 },
304 { 0x419d24, 1, 0x04, 0x00001fff },
305 { 0x419e04, 3, 0x04, 0x00000000 },
306 { 0x419e10, 1, 0x04, 0x00000002 },
307 { 0x419e44, 1, 0x04, 0x001beff2 },
308 { 0x419e48, 1, 0x04, 0x00000000 },
309 { 0x419e4c, 1, 0x04, 0x0000000f },
310 { 0x419e50, 17, 0x04, 0x00000000 },
311 { 0x419e98, 1, 0x04, 0x00000000 },
312 { 0x419f50, 2, 0x04, 0x00000000 },
313 {}
314};
315
316struct nvc0_graph_init
317nvc8_grctx_init_9197[] = {
318 { 0x0002e4, 1, 0x04, 0x0000b001 },
319 {}
320};
321
322struct nvc0_graph_init
323nvc8_grctx_init_9297[] = {
324 { 0x003400, 128, 0x04, 0x00000000 },
325 { 0x00036c, 2, 0x04, 0x00000000 },
326 { 0x0007a4, 2, 0x04, 0x00000000 },
327 { 0x000374, 1, 0x04, 0x00000000 },
328 { 0x000378, 1, 0x04, 0x00000020 },
329 {}
330};
331
332static struct nvc0_graph_mthd
333nvc8_grctx_init_mthd[] = {
334 { 0x9097, nvc1_grctx_init_9097, },
335 { 0x9197, nvc8_grctx_init_9197, },
336 { 0x9297, nvc8_grctx_init_9297, },
337 { 0x902d, nvc0_grctx_init_902d, },
338 { 0x9039, nvc0_grctx_init_9039, },
339 { 0x90c0, nvc0_grctx_init_90c0, },
340 { 0x902d, nvc0_grctx_init_mthd_magic, },
341 {}
342};
343
344static struct nvc0_graph_init *
345nvc8_grctx_init_gpc[] = {
346 nvc0_grctx_init_gpc_0,
347 nvc0_grctx_init_gpc_1,
348 nvc8_grctx_init_tpc,
349 NULL
350};
351
352struct nouveau_oclass *
353nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
354 .base.handle = NV_ENGCTX(GR, 0xc8),
355 .base.ofuncs = &(struct nouveau_ofuncs) {
356 .ctor = nvc0_graph_context_ctor,
357 .dtor = nvc0_graph_context_dtor,
358 .init = _nouveau_graph_context_init,
359 .fini = _nouveau_graph_context_fini,
360 .rd32 = _nouveau_graph_context_rd32,
361 .wr32 = _nouveau_graph_context_wr32,
362 },
363 .main = nvc0_grctx_generate_main,
364 .mods = nvc0_grctx_generate_mods,
365 .unkn = nvc0_grctx_generate_unkn,
366 .hub = nvc0_grctx_init_hub,
367 .gpc = nvc8_grctx_init_gpc,
368 .icmd = nvc8_grctx_init_icmd,
369 .mthd = nvc8_grctx_init_mthd,
370}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
new file mode 100644
index 000000000000..438e78410808
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
@@ -0,0 +1,290 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27struct nvc0_graph_init
28nvd7_grctx_init_unk40xx[] = {
29 { 0x404004, 10, 0x04, 0x00000000 },
30 { 0x404044, 1, 0x04, 0x00000000 },
31 { 0x404094, 1, 0x04, 0x00000000 },
32 { 0x404098, 12, 0x04, 0x00000000 },
33 { 0x4040c8, 1, 0x04, 0xf0000087 },
34 { 0x4040d0, 6, 0x04, 0x00000000 },
35 { 0x4040e8, 1, 0x04, 0x00001000 },
36 { 0x4040f8, 1, 0x04, 0x00000000 },
37 { 0x404130, 1, 0x04, 0x00000000 },
38 { 0x404134, 1, 0x04, 0x00000000 },
39 { 0x404138, 1, 0x04, 0x20000040 },
40 { 0x404150, 1, 0x04, 0x0000002e },
41 { 0x404154, 1, 0x04, 0x00000400 },
42 { 0x404158, 1, 0x04, 0x00000200 },
43 { 0x404164, 1, 0x04, 0x00000055 },
44 { 0x404168, 1, 0x04, 0x00000000 },
45 { 0x404178, 2, 0x04, 0x00000000 },
46 { 0x404200, 8, 0x04, 0x00000000 },
47 {}
48};
49
50static struct nvc0_graph_init
51nvd7_grctx_init_unk58xx[] = {
52 { 0x405800, 1, 0x04, 0x0f8000bf },
53 { 0x405830, 1, 0x04, 0x02180324 },
54 { 0x405834, 1, 0x04, 0x08000000 },
55 { 0x405838, 1, 0x04, 0x00000000 },
56 { 0x405854, 1, 0x04, 0x00000000 },
57 { 0x405870, 4, 0x04, 0x00000001 },
58 { 0x405a00, 2, 0x04, 0x00000000 },
59 { 0x405a18, 1, 0x04, 0x00000000 },
60 {}
61};
62
63static struct nvc0_graph_init
64nvd7_grctx_init_unk64xx[] = {
65 { 0x4064a8, 1, 0x04, 0x00000000 },
66 { 0x4064ac, 1, 0x04, 0x00003fff },
67 { 0x4064b4, 3, 0x04, 0x00000000 },
68 { 0x4064c0, 1, 0x04, 0x801a0078 },
69 { 0x4064c4, 1, 0x04, 0x00c9ffff },
70 { 0x4064d0, 8, 0x04, 0x00000000 },
71 {}
72};
73
74static struct nvc0_graph_init
75nvd7_grctx_init_gpc_0[] = {
76 { 0x418380, 1, 0x04, 0x00000016 },
77 { 0x418400, 1, 0x04, 0x38004e00 },
78 { 0x418404, 1, 0x04, 0x71e0ffff },
79 { 0x41840c, 1, 0x04, 0x00001008 },
80 { 0x418410, 1, 0x04, 0x0fff0fff },
81 { 0x418414, 1, 0x04, 0x02200fff },
82 { 0x418450, 6, 0x04, 0x00000000 },
83 { 0x418468, 1, 0x04, 0x00000001 },
84 { 0x41846c, 2, 0x04, 0x00000000 },
85 { 0x418600, 1, 0x04, 0x0000001f },
86 { 0x418684, 1, 0x04, 0x0000000f },
87 { 0x418700, 1, 0x04, 0x00000002 },
88 { 0x418704, 1, 0x04, 0x00000080 },
89 { 0x418708, 3, 0x04, 0x00000000 },
90 { 0x418800, 1, 0x04, 0x7006860a },
91 { 0x418808, 3, 0x04, 0x00000000 },
92 { 0x418828, 1, 0x04, 0x00008442 },
93 { 0x418830, 1, 0x04, 0x10000001 },
94 { 0x4188d8, 1, 0x04, 0x00000008 },
95 { 0x4188e0, 1, 0x04, 0x01000000 },
96 { 0x4188e8, 5, 0x04, 0x00000000 },
97 { 0x4188fc, 1, 0x04, 0x20100018 },
98 { 0x41891c, 1, 0x04, 0x00ff00ff },
99 { 0x418924, 1, 0x04, 0x00000000 },
100 { 0x418928, 1, 0x04, 0x00ffff00 },
101 { 0x41892c, 1, 0x04, 0x0000ff00 },
102 { 0x418b00, 1, 0x04, 0x00000006 },
103 { 0x418b08, 1, 0x04, 0x0a418820 },
104 { 0x418b0c, 1, 0x04, 0x062080e6 },
105 { 0x418b10, 1, 0x04, 0x020398a4 },
106 { 0x418b14, 1, 0x04, 0x0e629062 },
107 { 0x418b18, 1, 0x04, 0x0a418820 },
108 { 0x418b1c, 1, 0x04, 0x000000e6 },
109 { 0x418bb8, 1, 0x04, 0x00000103 },
110 { 0x418c08, 1, 0x04, 0x00000001 },
111 { 0x418c10, 8, 0x04, 0x00000000 },
112 { 0x418c6c, 1, 0x04, 0x00000001 },
113 { 0x418c80, 1, 0x04, 0x20200004 },
114 { 0x418c8c, 1, 0x04, 0x00000001 },
115 { 0x419000, 1, 0x04, 0x00000780 },
116 { 0x419004, 2, 0x04, 0x00000000 },
117 { 0x419014, 1, 0x04, 0x00000004 },
118 {}
119};
120
121static struct nvc0_graph_init
122nvd7_grctx_init_tpc[] = {
123 { 0x419848, 1, 0x04, 0x00000000 },
124 { 0x419864, 1, 0x04, 0x00000129 },
125 { 0x419888, 1, 0x04, 0x00000000 },
126 { 0x419a00, 1, 0x04, 0x000001f0 },
127 { 0x419a04, 1, 0x04, 0x00000001 },
128 { 0x419a08, 1, 0x04, 0x00000023 },
129 { 0x419a0c, 1, 0x04, 0x00020000 },
130 { 0x419a10, 1, 0x04, 0x00000000 },
131 { 0x419a14, 1, 0x04, 0x00000200 },
132 { 0x419a1c, 1, 0x04, 0x00008000 },
133 { 0x419a20, 1, 0x04, 0x00000800 },
134 { 0x419ac4, 1, 0x04, 0x0017f440 },
135 { 0x419c00, 1, 0x04, 0x0000000a },
136 { 0x419c04, 1, 0x04, 0x00000006 },
137 { 0x419c08, 1, 0x04, 0x00000002 },
138 { 0x419c20, 1, 0x04, 0x00000000 },
139 { 0x419c24, 1, 0x04, 0x00084210 },
140 { 0x419c28, 1, 0x04, 0x3efbefbe },
141 { 0x419cb0, 1, 0x04, 0x00020048 },
142 { 0x419ce8, 1, 0x04, 0x00000000 },
143 { 0x419cf4, 1, 0x04, 0x00000183 },
144 { 0x419e04, 3, 0x04, 0x00000000 },
145 { 0x419e10, 1, 0x04, 0x00000002 },
146 { 0x419e44, 1, 0x04, 0x001beff2 },
147 { 0x419e48, 1, 0x04, 0x00000000 },
148 { 0x419e4c, 1, 0x04, 0x0000000f },
149 { 0x419e50, 17, 0x04, 0x00000000 },
150 { 0x419e98, 1, 0x04, 0x00000000 },
151 { 0x419ee0, 1, 0x04, 0x00010110 },
152 { 0x419f30, 11, 0x04, 0x00000000 },
153 {}
154};
155
156static struct nvc0_graph_init
157nvd7_grctx_init_unk[] = {
158 { 0x41be24, 1, 0x04, 0x00000002 },
159 { 0x41bec0, 1, 0x04, 0x12180000 },
160 { 0x41bec4, 1, 0x04, 0x00003fff },
161 { 0x41bee4, 1, 0x04, 0x03240218 },
162 { 0x41bf00, 1, 0x04, 0x0a418820 },
163 { 0x41bf04, 1, 0x04, 0x062080e6 },
164 { 0x41bf08, 1, 0x04, 0x020398a4 },
165 { 0x41bf0c, 1, 0x04, 0x0e629062 },
166 { 0x41bf10, 1, 0x04, 0x0a418820 },
167 { 0x41bf14, 1, 0x04, 0x000000e6 },
168 { 0x41bfd0, 1, 0x04, 0x00900103 },
169 { 0x41bfe0, 1, 0x04, 0x00400001 },
170 { 0x41bfe4, 1, 0x04, 0x00000000 },
171 {}
172};
173
174static void
175nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
176{
177 u32 magic[GPC_MAX][2];
178 u32 offset;
179 int gpc;
180
181 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
182 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
183 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
184 mmio_list(0x40800c, 0x00000000, 8, 1);
185 mmio_list(0x408010, 0x80000000, 0, 0);
186 mmio_list(0x419004, 0x00000000, 8, 1);
187 mmio_list(0x419008, 0x00000000, 0, 0);
188 mmio_list(0x408004, 0x00000000, 8, 0);
189 mmio_list(0x408008, 0x80000018, 0, 0);
190 mmio_list(0x418808, 0x00000000, 8, 0);
191 mmio_list(0x41880c, 0x80000018, 0, 0);
192 mmio_list(0x418810, 0x80000000, 12, 2);
193 mmio_list(0x419848, 0x10000000, 12, 2);
194
195 mmio_list(0x405830, 0x02180324, 0, 0);
196 mmio_list(0x4064c4, 0x00c9ffff, 0, 0);
197
198 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
199 u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
200 u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
201 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
202 magic[gpc][1] = 0x00000000 | (magic1 << 16);
203 offset += 0x0324 * priv->tpc_nr[gpc];
204 }
205
206 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
207 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
208 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
209 offset += 0x07ff * priv->tpc_nr[gpc];
210 }
211 mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
212}
213
214void
215nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
216{
217 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
218 int i;
219
220 nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
221
222 for (i = 0; oclass->hub[i]; i++)
223 nvc0_graph_mmio(priv, oclass->hub[i]);
224 for (i = 0; oclass->gpc[i]; i++)
225 nvc0_graph_mmio(priv, oclass->gpc[i]);
226
227 nv_wr32(priv, 0x404154, 0x00000000);
228
229 oclass->mods(priv, info);
230 oclass->unkn(priv);
231
232 nvc0_grctx_generate_tpcid(priv);
233 nvc0_grctx_generate_r406028(priv);
234 nvc0_grctx_generate_r4060a8(priv);
235 nve4_grctx_generate_r418bb8(priv);
236 nvc0_grctx_generate_r406800(priv);
237
238 for (i = 0; i < 8; i++)
239 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
240
241 nvc0_graph_icmd(priv, oclass->icmd);
242 nv_wr32(priv, 0x404154, 0x00000400);
243 nvc0_graph_mthd(priv, oclass->mthd);
244 nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
245}
246
247
248static struct nvc0_graph_init *
249nvd7_grctx_init_hub[] = {
250 nvc0_grctx_init_base,
251 nvd7_grctx_init_unk40xx,
252 nvc0_grctx_init_unk44xx,
253 nvc0_grctx_init_unk46xx,
254 nvc0_grctx_init_unk47xx,
255 nvd7_grctx_init_unk58xx,
256 nvc0_grctx_init_unk60xx,
257 nvd7_grctx_init_unk64xx,
258 nvc0_grctx_init_unk78xx,
259 nvc0_grctx_init_unk80xx,
260 nvd9_grctx_init_rop,
261};
262
263struct nvc0_graph_init *
264nvd7_grctx_init_gpc[] = {
265 nvd7_grctx_init_gpc_0,
266 nvc0_grctx_init_gpc_1,
267 nvd7_grctx_init_tpc,
268 nvd7_grctx_init_unk,
269 NULL
270};
271
272struct nouveau_oclass *
273nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
274 .base.handle = NV_ENGCTX(GR, 0xd7),
275 .base.ofuncs = &(struct nouveau_ofuncs) {
276 .ctor = nvc0_graph_context_ctor,
277 .dtor = nvc0_graph_context_dtor,
278 .init = _nouveau_graph_context_init,
279 .fini = _nouveau_graph_context_fini,
280 .rd32 = _nouveau_graph_context_rd32,
281 .wr32 = _nouveau_graph_context_wr32,
282 },
283 .main = nvd7_grctx_generate_main,
284 .mods = nvd7_grctx_generate_mods,
285 .unkn = nve4_grctx_generate_unkn,
286 .hub = nvd7_grctx_init_hub,
287 .gpc = nvd7_grctx_init_gpc,
288 .icmd = nvd9_grctx_init_icmd,
289 .mthd = nvd9_grctx_init_mthd,
290}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
new file mode 100644
index 000000000000..818a4751df46
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
@@ -0,0 +1,515 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27struct nvc0_graph_init
28nvd9_grctx_init_90c0[] = {
29 { 0x002700, 4, 0x40, 0x00000000 },
30 { 0x002720, 4, 0x40, 0x00000000 },
31 { 0x002704, 4, 0x40, 0x00000000 },
32 { 0x002724, 4, 0x40, 0x00000000 },
33 { 0x002708, 4, 0x40, 0x00000000 },
34 { 0x002728, 4, 0x40, 0x00000000 },
35 { 0x00270c, 8, 0x20, 0x00000000 },
36 { 0x002710, 4, 0x40, 0x00014000 },
37 { 0x002730, 4, 0x40, 0x00014000 },
38 { 0x002714, 4, 0x40, 0x00000040 },
39 { 0x002734, 4, 0x40, 0x00000040 },
40 { 0x00030c, 1, 0x04, 0x00000001 },
41 { 0x001944, 1, 0x04, 0x00000000 },
42 { 0x000758, 1, 0x04, 0x00000100 },
43 { 0x0002c4, 1, 0x04, 0x00000000 },
44 { 0x000790, 5, 0x04, 0x00000000 },
45 { 0x00077c, 1, 0x04, 0x00000000 },
46 { 0x000204, 3, 0x04, 0x00000000 },
47 { 0x000214, 1, 0x04, 0x00000000 },
48 { 0x00024c, 1, 0x04, 0x00000000 },
49 { 0x000d94, 1, 0x04, 0x00000001 },
50 { 0x001608, 2, 0x04, 0x00000000 },
51 { 0x001664, 1, 0x04, 0x00000000 },
52 {}
53};
54
55struct nvc0_graph_init
56nvd9_grctx_init_icmd[] = {
57 { 0x001000, 1, 0x01, 0x00000004 },
58 { 0x0000a9, 1, 0x01, 0x0000ffff },
59 { 0x000038, 1, 0x01, 0x0fac6881 },
60 { 0x00003d, 1, 0x01, 0x00000001 },
61 { 0x0000e8, 8, 0x01, 0x00000400 },
62 { 0x000078, 8, 0x01, 0x00000300 },
63 { 0x000050, 1, 0x01, 0x00000011 },
64 { 0x000058, 8, 0x01, 0x00000008 },
65 { 0x000208, 8, 0x01, 0x00000001 },
66 { 0x000081, 1, 0x01, 0x00000001 },
67 { 0x000085, 1, 0x01, 0x00000004 },
68 { 0x000088, 1, 0x01, 0x00000400 },
69 { 0x000090, 1, 0x01, 0x00000300 },
70 { 0x000098, 1, 0x01, 0x00001001 },
71 { 0x0000e3, 1, 0x01, 0x00000001 },
72 { 0x0000da, 1, 0x01, 0x00000001 },
73 { 0x0000f8, 1, 0x01, 0x00000003 },
74 { 0x0000fa, 1, 0x01, 0x00000001 },
75 { 0x00009f, 4, 0x01, 0x0000ffff },
76 { 0x0000b1, 1, 0x01, 0x00000001 },
77 { 0x0000b2, 40, 0x01, 0x00000000 },
78 { 0x000210, 8, 0x01, 0x00000040 },
79 { 0x000400, 24, 0x01, 0x00000040 },
80 { 0x000218, 8, 0x01, 0x0000c080 },
81 { 0x000440, 24, 0x01, 0x0000c080 },
82 { 0x0000ad, 1, 0x01, 0x0000013e },
83 { 0x0000e1, 1, 0x01, 0x00000010 },
84 { 0x000290, 16, 0x01, 0x00000000 },
85 { 0x0003b0, 16, 0x01, 0x00000000 },
86 { 0x0002a0, 16, 0x01, 0x00000000 },
87 { 0x000420, 16, 0x01, 0x00000000 },
88 { 0x0002b0, 16, 0x01, 0x00000000 },
89 { 0x000430, 16, 0x01, 0x00000000 },
90 { 0x0002c0, 16, 0x01, 0x00000000 },
91 { 0x0004d0, 16, 0x01, 0x00000000 },
92 { 0x000720, 16, 0x01, 0x00000000 },
93 { 0x0008c0, 16, 0x01, 0x00000000 },
94 { 0x000890, 16, 0x01, 0x00000000 },
95 { 0x0008e0, 16, 0x01, 0x00000000 },
96 { 0x0008a0, 16, 0x01, 0x00000000 },
97 { 0x0008f0, 16, 0x01, 0x00000000 },
98 { 0x00094c, 1, 0x01, 0x000000ff },
99 { 0x00094d, 1, 0x01, 0xffffffff },
100 { 0x00094e, 1, 0x01, 0x00000002 },
101 { 0x0002ec, 1, 0x01, 0x00000001 },
102 { 0x000303, 1, 0x01, 0x00000001 },
103 { 0x0002e6, 1, 0x01, 0x00000001 },
104 { 0x000466, 1, 0x01, 0x00000052 },
105 { 0x000301, 1, 0x01, 0x3f800000 },
106 { 0x000304, 1, 0x01, 0x30201000 },
107 { 0x000305, 1, 0x01, 0x70605040 },
108 { 0x000306, 1, 0x01, 0xb8a89888 },
109 { 0x000307, 1, 0x01, 0xf8e8d8c8 },
110 { 0x00030a, 1, 0x01, 0x00ffff00 },
111 { 0x00030b, 1, 0x01, 0x0000001a },
112 { 0x00030c, 1, 0x01, 0x00000001 },
113 { 0x000318, 1, 0x01, 0x00000001 },
114 { 0x000340, 1, 0x01, 0x00000000 },
115 { 0x000375, 1, 0x01, 0x00000001 },
116 { 0x000351, 1, 0x01, 0x00000100 },
117 { 0x00037d, 1, 0x01, 0x00000006 },
118 { 0x0003a0, 1, 0x01, 0x00000002 },
119 { 0x0003aa, 1, 0x01, 0x00000001 },
120 { 0x0003a9, 1, 0x01, 0x00000001 },
121 { 0x000380, 1, 0x01, 0x00000001 },
122 { 0x000360, 1, 0x01, 0x00000040 },
123 { 0x000366, 2, 0x01, 0x00000000 },
124 { 0x000368, 1, 0x01, 0x00001fff },
125 { 0x000370, 2, 0x01, 0x00000000 },
126 { 0x000372, 1, 0x01, 0x003fffff },
127 { 0x00037a, 1, 0x01, 0x00000012 },
128 { 0x0005e0, 5, 0x01, 0x00000022 },
129 { 0x000619, 1, 0x01, 0x00000003 },
130 { 0x000811, 1, 0x01, 0x00000003 },
131 { 0x000812, 1, 0x01, 0x00000004 },
132 { 0x000813, 1, 0x01, 0x00000006 },
133 { 0x000814, 1, 0x01, 0x00000008 },
134 { 0x000815, 1, 0x01, 0x0000000b },
135 { 0x000800, 6, 0x01, 0x00000001 },
136 { 0x000632, 1, 0x01, 0x00000001 },
137 { 0x000633, 1, 0x01, 0x00000002 },
138 { 0x000634, 1, 0x01, 0x00000003 },
139 { 0x000635, 1, 0x01, 0x00000004 },
140 { 0x000654, 1, 0x01, 0x3f800000 },
141 { 0x000657, 1, 0x01, 0x3f800000 },
142 { 0x000655, 2, 0x01, 0x3f800000 },
143 { 0x0006cd, 1, 0x01, 0x3f800000 },
144 { 0x0007f5, 1, 0x01, 0x3f800000 },
145 { 0x0007dc, 1, 0x01, 0x39291909 },
146 { 0x0007dd, 1, 0x01, 0x79695949 },
147 { 0x0007de, 1, 0x01, 0xb9a99989 },
148 { 0x0007df, 1, 0x01, 0xf9e9d9c9 },
149 { 0x0007e8, 1, 0x01, 0x00003210 },
150 { 0x0007e9, 1, 0x01, 0x00007654 },
151 { 0x0007ea, 1, 0x01, 0x00000098 },
152 { 0x0007ec, 1, 0x01, 0x39291909 },
153 { 0x0007ed, 1, 0x01, 0x79695949 },
154 { 0x0007ee, 1, 0x01, 0xb9a99989 },
155 { 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
156 { 0x0007f0, 1, 0x01, 0x00003210 },
157 { 0x0007f1, 1, 0x01, 0x00007654 },
158 { 0x0007f2, 1, 0x01, 0x00000098 },
159 { 0x0005a5, 1, 0x01, 0x00000001 },
160 { 0x000980, 128, 0x01, 0x00000000 },
161 { 0x000468, 1, 0x01, 0x00000004 },
162 { 0x00046c, 1, 0x01, 0x00000001 },
163 { 0x000470, 96, 0x01, 0x00000000 },
164 { 0x000510, 16, 0x01, 0x3f800000 },
165 { 0x000520, 1, 0x01, 0x000002b6 },
166 { 0x000529, 1, 0x01, 0x00000001 },
167 { 0x000530, 16, 0x01, 0xffff0000 },
168 { 0x000585, 1, 0x01, 0x0000003f },
169 { 0x000576, 1, 0x01, 0x00000003 },
170 { 0x00057b, 1, 0x01, 0x00000059 },
171 { 0x000586, 1, 0x01, 0x00000040 },
172 { 0x000582, 2, 0x01, 0x00000080 },
173 { 0x0005c2, 1, 0x01, 0x00000001 },
174 { 0x000638, 1, 0x01, 0x00000001 },
175 { 0x000639, 1, 0x01, 0x00000001 },
176 { 0x00063a, 1, 0x01, 0x00000002 },
177 { 0x00063b, 2, 0x01, 0x00000001 },
178 { 0x00063d, 1, 0x01, 0x00000002 },
179 { 0x00063e, 1, 0x01, 0x00000001 },
180 { 0x0008b8, 8, 0x01, 0x00000001 },
181 { 0x000900, 8, 0x01, 0x00000001 },
182 { 0x000908, 8, 0x01, 0x00000002 },
183 { 0x000910, 16, 0x01, 0x00000001 },
184 { 0x000920, 8, 0x01, 0x00000002 },
185 { 0x000928, 8, 0x01, 0x00000001 },
186 { 0x000648, 9, 0x01, 0x00000001 },
187 { 0x000658, 1, 0x01, 0x0000000f },
188 { 0x0007ff, 1, 0x01, 0x0000000a },
189 { 0x00066a, 1, 0x01, 0x40000000 },
190 { 0x00066b, 1, 0x01, 0x10000000 },
191 { 0x00066c, 2, 0x01, 0xffff0000 },
192 { 0x0007af, 2, 0x01, 0x00000008 },
193 { 0x0007f6, 1, 0x01, 0x00000001 },
194 { 0x0006b2, 1, 0x01, 0x00000055 },
195 { 0x0007ad, 1, 0x01, 0x00000003 },
196 { 0x000937, 1, 0x01, 0x00000001 },
197 { 0x000971, 1, 0x01, 0x00000008 },
198 { 0x000972, 1, 0x01, 0x00000040 },
199 { 0x000973, 1, 0x01, 0x0000012c },
200 { 0x00097c, 1, 0x01, 0x00000040 },
201 { 0x000979, 1, 0x01, 0x00000003 },
202 { 0x000975, 1, 0x01, 0x00000020 },
203 { 0x000976, 1, 0x01, 0x00000001 },
204 { 0x000977, 1, 0x01, 0x00000020 },
205 { 0x000978, 1, 0x01, 0x00000001 },
206 { 0x000957, 1, 0x01, 0x00000003 },
207 { 0x00095e, 1, 0x01, 0x20164010 },
208 { 0x00095f, 1, 0x01, 0x00000020 },
209 { 0x00097d, 1, 0x01, 0x00000020 },
210 { 0x000683, 1, 0x01, 0x00000006 },
211 { 0x000685, 1, 0x01, 0x003fffff },
212 { 0x000687, 1, 0x01, 0x00000c48 },
213 { 0x0006a0, 1, 0x01, 0x00000005 },
214 { 0x000840, 1, 0x01, 0x00300008 },
215 { 0x000841, 1, 0x01, 0x04000080 },
216 { 0x000842, 1, 0x01, 0x00300008 },
217 { 0x000843, 1, 0x01, 0x04000080 },
218 { 0x000818, 8, 0x01, 0x00000000 },
219 { 0x000848, 16, 0x01, 0x00000000 },
220 { 0x000738, 1, 0x01, 0x00000000 },
221 { 0x0006aa, 1, 0x01, 0x00000001 },
222 { 0x0006ab, 1, 0x01, 0x00000002 },
223 { 0x0006ac, 1, 0x01, 0x00000080 },
224 { 0x0006ad, 2, 0x01, 0x00000100 },
225 { 0x0006b1, 1, 0x01, 0x00000011 },
226 { 0x0006bb, 1, 0x01, 0x000000cf },
227 { 0x0006ce, 1, 0x01, 0x2a712488 },
228 { 0x000739, 1, 0x01, 0x4085c000 },
229 { 0x00073a, 1, 0x01, 0x00000080 },
230 { 0x000786, 1, 0x01, 0x80000100 },
231 { 0x00073c, 1, 0x01, 0x00010100 },
232 { 0x00073d, 1, 0x01, 0x02800000 },
233 { 0x000787, 1, 0x01, 0x000000cf },
234 { 0x00078c, 1, 0x01, 0x00000008 },
235 { 0x000792, 1, 0x01, 0x00000001 },
236 { 0x000794, 1, 0x01, 0x00000001 },
237 { 0x000795, 2, 0x01, 0x00000001 },
238 { 0x000797, 1, 0x01, 0x000000cf },
239 { 0x000836, 1, 0x01, 0x00000001 },
240 { 0x00079a, 1, 0x01, 0x00000002 },
241 { 0x000833, 1, 0x01, 0x04444480 },
242 { 0x0007a1, 1, 0x01, 0x00000001 },
243 { 0x0007a3, 1, 0x01, 0x00000001 },
244 { 0x0007a4, 2, 0x01, 0x00000001 },
245 { 0x000831, 1, 0x01, 0x00000004 },
246 { 0x00080c, 1, 0x01, 0x00000002 },
247 { 0x00080d, 2, 0x01, 0x00000100 },
248 { 0x00080f, 1, 0x01, 0x00000001 },
249 { 0x000823, 1, 0x01, 0x00000002 },
250 { 0x000824, 2, 0x01, 0x00000100 },
251 { 0x000826, 1, 0x01, 0x00000001 },
252 { 0x00095d, 1, 0x01, 0x00000001 },
253 { 0x00082b, 1, 0x01, 0x00000004 },
254 { 0x000942, 1, 0x01, 0x00010001 },
255 { 0x000943, 1, 0x01, 0x00000001 },
256 { 0x000944, 1, 0x01, 0x00000022 },
257 { 0x0007c5, 1, 0x01, 0x00010001 },
258 { 0x000834, 1, 0x01, 0x00000001 },
259 { 0x0007c7, 1, 0x01, 0x00000001 },
260 { 0x00c1b0, 8, 0x01, 0x0000000f },
261 { 0x00c1b8, 1, 0x01, 0x0fac6881 },
262 { 0x00c1b9, 1, 0x01, 0x00fac688 },
263 { 0x01e100, 1, 0x01, 0x00000001 },
264 { 0x001000, 1, 0x01, 0x00000002 },
265 { 0x0006aa, 1, 0x01, 0x00000001 },
266 { 0x0006ad, 2, 0x01, 0x00000100 },
267 { 0x0006b1, 1, 0x01, 0x00000011 },
268 { 0x00078c, 1, 0x01, 0x00000008 },
269 { 0x000792, 1, 0x01, 0x00000001 },
270 { 0x000794, 1, 0x01, 0x00000001 },
271 { 0x000795, 2, 0x01, 0x00000001 },
272 { 0x000797, 1, 0x01, 0x000000cf },
273 { 0x00079a, 1, 0x01, 0x00000002 },
274 { 0x000833, 1, 0x01, 0x04444480 },
275 { 0x0007a1, 1, 0x01, 0x00000001 },
276 { 0x0007a3, 1, 0x01, 0x00000001 },
277 { 0x0007a4, 2, 0x01, 0x00000001 },
278 { 0x000831, 1, 0x01, 0x00000004 },
279 { 0x01e100, 1, 0x01, 0x00000001 },
280 { 0x001000, 1, 0x01, 0x00000014 },
281 { 0x000351, 1, 0x01, 0x00000100 },
282 { 0x000957, 1, 0x01, 0x00000003 },
283 { 0x00095d, 1, 0x01, 0x00000001 },
284 { 0x00082b, 1, 0x01, 0x00000004 },
285 { 0x000942, 1, 0x01, 0x00010001 },
286 { 0x000943, 1, 0x01, 0x00000001 },
287 { 0x0007c5, 1, 0x01, 0x00010001 },
288 { 0x000834, 1, 0x01, 0x00000001 },
289 { 0x0007c7, 1, 0x01, 0x00000001 },
290 { 0x01e100, 1, 0x01, 0x00000001 },
291 { 0x001000, 1, 0x01, 0x00000001 },
292 { 0x00080c, 1, 0x01, 0x00000002 },
293 { 0x00080d, 2, 0x01, 0x00000100 },
294 { 0x00080f, 1, 0x01, 0x00000001 },
295 { 0x000823, 1, 0x01, 0x00000002 },
296 { 0x000824, 2, 0x01, 0x00000100 },
297 { 0x000826, 1, 0x01, 0x00000001 },
298 { 0x01e100, 1, 0x01, 0x00000001 },
299 {}
300};
301
302struct nvc0_graph_init
303nvd9_grctx_init_unk40xx[] = {
304 { 0x404004, 11, 0x04, 0x00000000 },
305 { 0x404044, 1, 0x04, 0x00000000 },
306 { 0x404094, 1, 0x04, 0x00000000 },
307 { 0x404098, 12, 0x04, 0x00000000 },
308 { 0x4040c8, 1, 0x04, 0xf0000087 },
309 { 0x4040d0, 6, 0x04, 0x00000000 },
310 { 0x4040e8, 1, 0x04, 0x00001000 },
311 { 0x4040f8, 1, 0x04, 0x00000000 },
312 { 0x404130, 1, 0x04, 0x00000000 },
313 { 0x404134, 1, 0x04, 0x00000000 },
314 { 0x404138, 1, 0x04, 0x20000040 },
315 { 0x404150, 1, 0x04, 0x0000002e },
316 { 0x404154, 1, 0x04, 0x00000400 },
317 { 0x404158, 1, 0x04, 0x00000200 },
318 { 0x404164, 1, 0x04, 0x00000055 },
319 { 0x404168, 1, 0x04, 0x00000000 },
320 { 0x404178, 2, 0x04, 0x00000000 },
321 { 0x404200, 8, 0x04, 0x00000000 },
322 {}
323};
324
325static struct nvc0_graph_init
326nvd9_grctx_init_unk58xx[] = {
327 { 0x405800, 1, 0x04, 0x0f8000bf },
328 { 0x405830, 1, 0x04, 0x02180218 },
329 { 0x405834, 1, 0x04, 0x08000000 },
330 { 0x405838, 1, 0x04, 0x00000000 },
331 { 0x405854, 1, 0x04, 0x00000000 },
332 { 0x405870, 4, 0x04, 0x00000001 },
333 { 0x405a00, 2, 0x04, 0x00000000 },
334 { 0x405a18, 1, 0x04, 0x00000000 },
335 {}
336};
337
338static struct nvc0_graph_init
339nvd9_grctx_init_unk64xx[] = {
340 { 0x4064a8, 1, 0x04, 0x00000000 },
341 { 0x4064ac, 1, 0x04, 0x00003fff },
342 { 0x4064b4, 3, 0x04, 0x00000000 },
343 { 0x4064c0, 1, 0x04, 0x80140078 },
344 { 0x4064c4, 1, 0x04, 0x0086ffff },
345 {}
346};
347
348struct nvc0_graph_init
349nvd9_grctx_init_rop[] = {
350 { 0x408800, 1, 0x04, 0x02802a3c },
351 { 0x408804, 1, 0x04, 0x00000040 },
352 { 0x408808, 1, 0x04, 0x1043e005 },
353 { 0x408900, 1, 0x04, 0x3080b801 },
354 { 0x408904, 1, 0x04, 0x1043e005 },
355 { 0x408908, 1, 0x04, 0x00c8102f },
356 { 0x408980, 1, 0x04, 0x0000011d },
357 {}
358};
359
360static struct nvc0_graph_init
361nvd9_grctx_init_gpc_0[] = {
362 { 0x418380, 1, 0x04, 0x00000016 },
363 { 0x418400, 1, 0x04, 0x38004e00 },
364 { 0x418404, 1, 0x04, 0x71e0ffff },
365 { 0x41840c, 1, 0x04, 0x00001008 },
366 { 0x418410, 1, 0x04, 0x0fff0fff },
367 { 0x418414, 1, 0x04, 0x02200fff },
368 { 0x418450, 6, 0x04, 0x00000000 },
369 { 0x418468, 1, 0x04, 0x00000001 },
370 { 0x41846c, 2, 0x04, 0x00000000 },
371 { 0x418600, 1, 0x04, 0x0000001f },
372 { 0x418684, 1, 0x04, 0x0000000f },
373 { 0x418700, 1, 0x04, 0x00000002 },
374 { 0x418704, 1, 0x04, 0x00000080 },
375 { 0x418708, 3, 0x04, 0x00000000 },
376 { 0x418800, 1, 0x04, 0x7006860a },
377 { 0x418808, 3, 0x04, 0x00000000 },
378 { 0x418828, 1, 0x04, 0x00008442 },
379 { 0x418830, 1, 0x04, 0x10000001 },
380 { 0x4188d8, 1, 0x04, 0x00000008 },
381 { 0x4188e0, 1, 0x04, 0x01000000 },
382 { 0x4188e8, 5, 0x04, 0x00000000 },
383 { 0x4188fc, 1, 0x04, 0x20100008 },
384 { 0x41891c, 1, 0x04, 0x00ff00ff },
385 { 0x418924, 1, 0x04, 0x00000000 },
386 { 0x418928, 1, 0x04, 0x00ffff00 },
387 { 0x41892c, 1, 0x04, 0x0000ff00 },
388 { 0x418b00, 1, 0x04, 0x00000006 },
389 { 0x418b08, 1, 0x04, 0x0a418820 },
390 { 0x418b0c, 1, 0x04, 0x062080e6 },
391 { 0x418b10, 1, 0x04, 0x020398a4 },
392 { 0x418b14, 1, 0x04, 0x0e629062 },
393 { 0x418b18, 1, 0x04, 0x0a418820 },
394 { 0x418b1c, 1, 0x04, 0x000000e6 },
395 { 0x418bb8, 1, 0x04, 0x00000103 },
396 { 0x418c08, 1, 0x04, 0x00000001 },
397 { 0x418c10, 8, 0x04, 0x00000000 },
398 { 0x418c6c, 1, 0x04, 0x00000001 },
399 { 0x418c80, 1, 0x04, 0x20200004 },
400 { 0x418c8c, 1, 0x04, 0x00000001 },
401 { 0x419000, 1, 0x04, 0x00000780 },
402 { 0x419004, 2, 0x04, 0x00000000 },
403 { 0x419014, 1, 0x04, 0x00000004 },
404 {}
405};
406
407static struct nvc0_graph_init
408nvd9_grctx_init_tpc[] = {
409 { 0x419818, 1, 0x04, 0x00000000 },
410 { 0x41983c, 1, 0x04, 0x00038bc7 },
411 { 0x419848, 1, 0x04, 0x00000000 },
412 { 0x419864, 1, 0x04, 0x00000129 },
413 { 0x419888, 1, 0x04, 0x00000000 },
414 { 0x419a00, 1, 0x04, 0x000001f0 },
415 { 0x419a04, 1, 0x04, 0x00000001 },
416 { 0x419a08, 1, 0x04, 0x00000023 },
417 { 0x419a0c, 1, 0x04, 0x00020000 },
418 { 0x419a10, 1, 0x04, 0x00000000 },
419 { 0x419a14, 1, 0x04, 0x00000200 },
420 { 0x419a1c, 1, 0x04, 0x00000000 },
421 { 0x419a20, 1, 0x04, 0x00000800 },
422 { 0x419ac4, 1, 0x04, 0x0017f440 },
423 { 0x419b00, 1, 0x04, 0x0a418820 },
424 { 0x419b04, 1, 0x04, 0x062080e6 },
425 { 0x419b08, 1, 0x04, 0x020398a4 },
426 { 0x419b0c, 1, 0x04, 0x0e629062 },
427 { 0x419b10, 1, 0x04, 0x0a418820 },
428 { 0x419b14, 1, 0x04, 0x000000e6 },
429 { 0x419bd0, 1, 0x04, 0x00900103 },
430 { 0x419be0, 1, 0x04, 0x00400001 },
431 { 0x419be4, 1, 0x04, 0x00000000 },
432 { 0x419c00, 1, 0x04, 0x0000000a },
433 { 0x419c04, 1, 0x04, 0x00000006 },
434 { 0x419c08, 1, 0x04, 0x00000002 },
435 { 0x419c20, 1, 0x04, 0x00000000 },
436 { 0x419c24, 1, 0x04, 0x00084210 },
437 { 0x419c28, 1, 0x04, 0x3cf3cf3c },
438 { 0x419cb0, 1, 0x04, 0x00020048 },
439 { 0x419ce8, 1, 0x04, 0x00000000 },
440 { 0x419cf4, 1, 0x04, 0x00000183 },
441 { 0x419d20, 1, 0x04, 0x12180000 },
442 { 0x419d24, 1, 0x04, 0x00001fff },
443 { 0x419d44, 1, 0x04, 0x02180218 },
444 { 0x419e04, 3, 0x04, 0x00000000 },
445 { 0x419e10, 1, 0x04, 0x00000002 },
446 { 0x419e44, 1, 0x04, 0x001beff2 },
447 { 0x419e48, 1, 0x04, 0x00000000 },
448 { 0x419e4c, 1, 0x04, 0x0000000f },
449 { 0x419e50, 17, 0x04, 0x00000000 },
450 { 0x419e98, 1, 0x04, 0x00000000 },
451 { 0x419ee0, 1, 0x04, 0x00010110 },
452 { 0x419f30, 11, 0x04, 0x00000000 },
453 {}
454};
455
456static struct nvc0_graph_init *
457nvd9_grctx_init_hub[] = {
458 nvc0_grctx_init_base,
459 nvd9_grctx_init_unk40xx,
460 nvc0_grctx_init_unk44xx,
461 nvc0_grctx_init_unk46xx,
462 nvc0_grctx_init_unk47xx,
463 nvd9_grctx_init_unk58xx,
464 nvc0_grctx_init_unk60xx,
465 nvd9_grctx_init_unk64xx,
466 nvc0_grctx_init_unk78xx,
467 nvc0_grctx_init_unk80xx,
468 nvd9_grctx_init_rop,
469};
470
471struct nvc0_graph_init *
472nvd9_grctx_init_gpc[] = {
473 nvd9_grctx_init_gpc_0,
474 nvc0_grctx_init_gpc_1,
475 nvd9_grctx_init_tpc,
476 NULL
477};
478
479struct nvc0_graph_init
480nvd9_grctx_init_mthd_magic[] = {
481 { 0x3410, 1, 0x04, 0x80002006 },
482 {}
483};
484
485struct nvc0_graph_mthd
486nvd9_grctx_init_mthd[] = {
487 { 0x9097, nvc1_grctx_init_9097, },
488 { 0x9197, nvc8_grctx_init_9197, },
489 { 0x9297, nvc8_grctx_init_9297, },
490 { 0x902d, nvc0_grctx_init_902d, },
491 { 0x9039, nvc0_grctx_init_9039, },
492 { 0x90c0, nvd9_grctx_init_90c0, },
493 { 0x902d, nvd9_grctx_init_mthd_magic, },
494 {}
495};
496
497struct nouveau_oclass *
498nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
499 .base.handle = NV_ENGCTX(GR, 0xd9),
500 .base.ofuncs = &(struct nouveau_ofuncs) {
501 .ctor = nvc0_graph_context_ctor,
502 .dtor = nvc0_graph_context_dtor,
503 .init = _nouveau_graph_context_init,
504 .fini = _nouveau_graph_context_fini,
505 .rd32 = _nouveau_graph_context_rd32,
506 .wr32 = _nouveau_graph_context_wr32,
507 },
508 .main = nvc0_grctx_generate_main,
509 .mods = nvc1_grctx_generate_mods,
510 .unkn = nvc1_grctx_generate_unkn,
511 .hub = nvd9_grctx_init_hub,
512 .gpc = nvd9_grctx_init_gpc,
513 .icmd = nvd9_grctx_init_icmd,
514 .mthd = nvd9_grctx_init_mthd,
515}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
deleted file mode 100644
index 848570b4c519..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
+++ /dev/null
@@ -1,2924 +0,0 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nvc0.h"
26
27static void
28nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
29{
30 nv_wr32(priv, 0x400208, 0x80000000);
31 nv_icmd(priv, 0x001000, 0x00000004);
32 nv_icmd(priv, 0x000039, 0x00000000);
33 nv_icmd(priv, 0x00003a, 0x00000000);
34 nv_icmd(priv, 0x00003b, 0x00000000);
35 nv_icmd(priv, 0x0000a9, 0x0000ffff);
36 nv_icmd(priv, 0x000038, 0x0fac6881);
37 nv_icmd(priv, 0x00003d, 0x00000001);
38 nv_icmd(priv, 0x0000e8, 0x00000400);
39 nv_icmd(priv, 0x0000e9, 0x00000400);
40 nv_icmd(priv, 0x0000ea, 0x00000400);
41 nv_icmd(priv, 0x0000eb, 0x00000400);
42 nv_icmd(priv, 0x0000ec, 0x00000400);
43 nv_icmd(priv, 0x0000ed, 0x00000400);
44 nv_icmd(priv, 0x0000ee, 0x00000400);
45 nv_icmd(priv, 0x0000ef, 0x00000400);
46 nv_icmd(priv, 0x000078, 0x00000300);
47 nv_icmd(priv, 0x000079, 0x00000300);
48 nv_icmd(priv, 0x00007a, 0x00000300);
49 nv_icmd(priv, 0x00007b, 0x00000300);
50 nv_icmd(priv, 0x00007c, 0x00000300);
51 nv_icmd(priv, 0x00007d, 0x00000300);
52 nv_icmd(priv, 0x00007e, 0x00000300);
53 nv_icmd(priv, 0x00007f, 0x00000300);
54 nv_icmd(priv, 0x000050, 0x00000011);
55 nv_icmd(priv, 0x000058, 0x00000008);
56 nv_icmd(priv, 0x000059, 0x00000008);
57 nv_icmd(priv, 0x00005a, 0x00000008);
58 nv_icmd(priv, 0x00005b, 0x00000008);
59 nv_icmd(priv, 0x00005c, 0x00000008);
60 nv_icmd(priv, 0x00005d, 0x00000008);
61 nv_icmd(priv, 0x00005e, 0x00000008);
62 nv_icmd(priv, 0x00005f, 0x00000008);
63 nv_icmd(priv, 0x000208, 0x00000001);
64 nv_icmd(priv, 0x000209, 0x00000001);
65 nv_icmd(priv, 0x00020a, 0x00000001);
66 nv_icmd(priv, 0x00020b, 0x00000001);
67 nv_icmd(priv, 0x00020c, 0x00000001);
68 nv_icmd(priv, 0x00020d, 0x00000001);
69 nv_icmd(priv, 0x00020e, 0x00000001);
70 nv_icmd(priv, 0x00020f, 0x00000001);
71 nv_icmd(priv, 0x000081, 0x00000001);
72 nv_icmd(priv, 0x000085, 0x00000004);
73 nv_icmd(priv, 0x000088, 0x00000400);
74 nv_icmd(priv, 0x000090, 0x00000300);
75 nv_icmd(priv, 0x000098, 0x00001001);
76 nv_icmd(priv, 0x0000e3, 0x00000001);
77 nv_icmd(priv, 0x0000da, 0x00000001);
78 nv_icmd(priv, 0x0000f8, 0x00000003);
79 nv_icmd(priv, 0x0000fa, 0x00000001);
80 nv_icmd(priv, 0x00009f, 0x0000ffff);
81 nv_icmd(priv, 0x0000a0, 0x0000ffff);
82 nv_icmd(priv, 0x0000a1, 0x0000ffff);
83 nv_icmd(priv, 0x0000a2, 0x0000ffff);
84 nv_icmd(priv, 0x0000b1, 0x00000001);
85 nv_icmd(priv, 0x0000ad, 0x0000013e);
86 nv_icmd(priv, 0x0000e1, 0x00000010);
87 nv_icmd(priv, 0x000290, 0x00000000);
88 nv_icmd(priv, 0x000291, 0x00000000);
89 nv_icmd(priv, 0x000292, 0x00000000);
90 nv_icmd(priv, 0x000293, 0x00000000);
91 nv_icmd(priv, 0x000294, 0x00000000);
92 nv_icmd(priv, 0x000295, 0x00000000);
93 nv_icmd(priv, 0x000296, 0x00000000);
94 nv_icmd(priv, 0x000297, 0x00000000);
95 nv_icmd(priv, 0x000298, 0x00000000);
96 nv_icmd(priv, 0x000299, 0x00000000);
97 nv_icmd(priv, 0x00029a, 0x00000000);
98 nv_icmd(priv, 0x00029b, 0x00000000);
99 nv_icmd(priv, 0x00029c, 0x00000000);
100 nv_icmd(priv, 0x00029d, 0x00000000);
101 nv_icmd(priv, 0x00029e, 0x00000000);
102 nv_icmd(priv, 0x00029f, 0x00000000);
103 nv_icmd(priv, 0x0003b0, 0x00000000);
104 nv_icmd(priv, 0x0003b1, 0x00000000);
105 nv_icmd(priv, 0x0003b2, 0x00000000);
106 nv_icmd(priv, 0x0003b3, 0x00000000);
107 nv_icmd(priv, 0x0003b4, 0x00000000);
108 nv_icmd(priv, 0x0003b5, 0x00000000);
109 nv_icmd(priv, 0x0003b6, 0x00000000);
110 nv_icmd(priv, 0x0003b7, 0x00000000);
111 nv_icmd(priv, 0x0003b8, 0x00000000);
112 nv_icmd(priv, 0x0003b9, 0x00000000);
113 nv_icmd(priv, 0x0003ba, 0x00000000);
114 nv_icmd(priv, 0x0003bb, 0x00000000);
115 nv_icmd(priv, 0x0003bc, 0x00000000);
116 nv_icmd(priv, 0x0003bd, 0x00000000);
117 nv_icmd(priv, 0x0003be, 0x00000000);
118 nv_icmd(priv, 0x0003bf, 0x00000000);
119 nv_icmd(priv, 0x0002a0, 0x00000000);
120 nv_icmd(priv, 0x0002a1, 0x00000000);
121 nv_icmd(priv, 0x0002a2, 0x00000000);
122 nv_icmd(priv, 0x0002a3, 0x00000000);
123 nv_icmd(priv, 0x0002a4, 0x00000000);
124 nv_icmd(priv, 0x0002a5, 0x00000000);
125 nv_icmd(priv, 0x0002a6, 0x00000000);
126 nv_icmd(priv, 0x0002a7, 0x00000000);
127 nv_icmd(priv, 0x0002a8, 0x00000000);
128 nv_icmd(priv, 0x0002a9, 0x00000000);
129 nv_icmd(priv, 0x0002aa, 0x00000000);
130 nv_icmd(priv, 0x0002ab, 0x00000000);
131 nv_icmd(priv, 0x0002ac, 0x00000000);
132 nv_icmd(priv, 0x0002ad, 0x00000000);
133 nv_icmd(priv, 0x0002ae, 0x00000000);
134 nv_icmd(priv, 0x0002af, 0x00000000);
135 nv_icmd(priv, 0x000420, 0x00000000);
136 nv_icmd(priv, 0x000421, 0x00000000);
137 nv_icmd(priv, 0x000422, 0x00000000);
138 nv_icmd(priv, 0x000423, 0x00000000);
139 nv_icmd(priv, 0x000424, 0x00000000);
140 nv_icmd(priv, 0x000425, 0x00000000);
141 nv_icmd(priv, 0x000426, 0x00000000);
142 nv_icmd(priv, 0x000427, 0x00000000);
143 nv_icmd(priv, 0x000428, 0x00000000);
144 nv_icmd(priv, 0x000429, 0x00000000);
145 nv_icmd(priv, 0x00042a, 0x00000000);
146 nv_icmd(priv, 0x00042b, 0x00000000);
147 nv_icmd(priv, 0x00042c, 0x00000000);
148 nv_icmd(priv, 0x00042d, 0x00000000);
149 nv_icmd(priv, 0x00042e, 0x00000000);
150 nv_icmd(priv, 0x00042f, 0x00000000);
151 nv_icmd(priv, 0x0002b0, 0x00000000);
152 nv_icmd(priv, 0x0002b1, 0x00000000);
153 nv_icmd(priv, 0x0002b2, 0x00000000);
154 nv_icmd(priv, 0x0002b3, 0x00000000);
155 nv_icmd(priv, 0x0002b4, 0x00000000);
156 nv_icmd(priv, 0x0002b5, 0x00000000);
157 nv_icmd(priv, 0x0002b6, 0x00000000);
158 nv_icmd(priv, 0x0002b7, 0x00000000);
159 nv_icmd(priv, 0x0002b8, 0x00000000);
160 nv_icmd(priv, 0x0002b9, 0x00000000);
161 nv_icmd(priv, 0x0002ba, 0x00000000);
162 nv_icmd(priv, 0x0002bb, 0x00000000);
163 nv_icmd(priv, 0x0002bc, 0x00000000);
164 nv_icmd(priv, 0x0002bd, 0x00000000);
165 nv_icmd(priv, 0x0002be, 0x00000000);
166 nv_icmd(priv, 0x0002bf, 0x00000000);
167 nv_icmd(priv, 0x000430, 0x00000000);
168 nv_icmd(priv, 0x000431, 0x00000000);
169 nv_icmd(priv, 0x000432, 0x00000000);
170 nv_icmd(priv, 0x000433, 0x00000000);
171 nv_icmd(priv, 0x000434, 0x00000000);
172 nv_icmd(priv, 0x000435, 0x00000000);
173 nv_icmd(priv, 0x000436, 0x00000000);
174 nv_icmd(priv, 0x000437, 0x00000000);
175 nv_icmd(priv, 0x000438, 0x00000000);
176 nv_icmd(priv, 0x000439, 0x00000000);
177 nv_icmd(priv, 0x00043a, 0x00000000);
178 nv_icmd(priv, 0x00043b, 0x00000000);
179 nv_icmd(priv, 0x00043c, 0x00000000);
180 nv_icmd(priv, 0x00043d, 0x00000000);
181 nv_icmd(priv, 0x00043e, 0x00000000);
182 nv_icmd(priv, 0x00043f, 0x00000000);
183 nv_icmd(priv, 0x0002c0, 0x00000000);
184 nv_icmd(priv, 0x0002c1, 0x00000000);
185 nv_icmd(priv, 0x0002c2, 0x00000000);
186 nv_icmd(priv, 0x0002c3, 0x00000000);
187 nv_icmd(priv, 0x0002c4, 0x00000000);
188 nv_icmd(priv, 0x0002c5, 0x00000000);
189 nv_icmd(priv, 0x0002c6, 0x00000000);
190 nv_icmd(priv, 0x0002c7, 0x00000000);
191 nv_icmd(priv, 0x0002c8, 0x00000000);
192 nv_icmd(priv, 0x0002c9, 0x00000000);
193 nv_icmd(priv, 0x0002ca, 0x00000000);
194 nv_icmd(priv, 0x0002cb, 0x00000000);
195 nv_icmd(priv, 0x0002cc, 0x00000000);
196 nv_icmd(priv, 0x0002cd, 0x00000000);
197 nv_icmd(priv, 0x0002ce, 0x00000000);
198 nv_icmd(priv, 0x0002cf, 0x00000000);
199 nv_icmd(priv, 0x0004d0, 0x00000000);
200 nv_icmd(priv, 0x0004d1, 0x00000000);
201 nv_icmd(priv, 0x0004d2, 0x00000000);
202 nv_icmd(priv, 0x0004d3, 0x00000000);
203 nv_icmd(priv, 0x0004d4, 0x00000000);
204 nv_icmd(priv, 0x0004d5, 0x00000000);
205 nv_icmd(priv, 0x0004d6, 0x00000000);
206 nv_icmd(priv, 0x0004d7, 0x00000000);
207 nv_icmd(priv, 0x0004d8, 0x00000000);
208 nv_icmd(priv, 0x0004d9, 0x00000000);
209 nv_icmd(priv, 0x0004da, 0x00000000);
210 nv_icmd(priv, 0x0004db, 0x00000000);
211 nv_icmd(priv, 0x0004dc, 0x00000000);
212 nv_icmd(priv, 0x0004dd, 0x00000000);
213 nv_icmd(priv, 0x0004de, 0x00000000);
214 nv_icmd(priv, 0x0004df, 0x00000000);
215 nv_icmd(priv, 0x000720, 0x00000000);
216 nv_icmd(priv, 0x000721, 0x00000000);
217 nv_icmd(priv, 0x000722, 0x00000000);
218 nv_icmd(priv, 0x000723, 0x00000000);
219 nv_icmd(priv, 0x000724, 0x00000000);
220 nv_icmd(priv, 0x000725, 0x00000000);
221 nv_icmd(priv, 0x000726, 0x00000000);
222 nv_icmd(priv, 0x000727, 0x00000000);
223 nv_icmd(priv, 0x000728, 0x00000000);
224 nv_icmd(priv, 0x000729, 0x00000000);
225 nv_icmd(priv, 0x00072a, 0x00000000);
226 nv_icmd(priv, 0x00072b, 0x00000000);
227 nv_icmd(priv, 0x00072c, 0x00000000);
228 nv_icmd(priv, 0x00072d, 0x00000000);
229 nv_icmd(priv, 0x00072e, 0x00000000);
230 nv_icmd(priv, 0x00072f, 0x00000000);
231 nv_icmd(priv, 0x0008c0, 0x00000000);
232 nv_icmd(priv, 0x0008c1, 0x00000000);
233 nv_icmd(priv, 0x0008c2, 0x00000000);
234 nv_icmd(priv, 0x0008c3, 0x00000000);
235 nv_icmd(priv, 0x0008c4, 0x00000000);
236 nv_icmd(priv, 0x0008c5, 0x00000000);
237 nv_icmd(priv, 0x0008c6, 0x00000000);
238 nv_icmd(priv, 0x0008c7, 0x00000000);
239 nv_icmd(priv, 0x0008c8, 0x00000000);
240 nv_icmd(priv, 0x0008c9, 0x00000000);
241 nv_icmd(priv, 0x0008ca, 0x00000000);
242 nv_icmd(priv, 0x0008cb, 0x00000000);
243 nv_icmd(priv, 0x0008cc, 0x00000000);
244 nv_icmd(priv, 0x0008cd, 0x00000000);
245 nv_icmd(priv, 0x0008ce, 0x00000000);
246 nv_icmd(priv, 0x0008cf, 0x00000000);
247 nv_icmd(priv, 0x000890, 0x00000000);
248 nv_icmd(priv, 0x000891, 0x00000000);
249 nv_icmd(priv, 0x000892, 0x00000000);
250 nv_icmd(priv, 0x000893, 0x00000000);
251 nv_icmd(priv, 0x000894, 0x00000000);
252 nv_icmd(priv, 0x000895, 0x00000000);
253 nv_icmd(priv, 0x000896, 0x00000000);
254 nv_icmd(priv, 0x000897, 0x00000000);
255 nv_icmd(priv, 0x000898, 0x00000000);
256 nv_icmd(priv, 0x000899, 0x00000000);
257 nv_icmd(priv, 0x00089a, 0x00000000);
258 nv_icmd(priv, 0x00089b, 0x00000000);
259 nv_icmd(priv, 0x00089c, 0x00000000);
260 nv_icmd(priv, 0x00089d, 0x00000000);
261 nv_icmd(priv, 0x00089e, 0x00000000);
262 nv_icmd(priv, 0x00089f, 0x00000000);
263 nv_icmd(priv, 0x0008e0, 0x00000000);
264 nv_icmd(priv, 0x0008e1, 0x00000000);
265 nv_icmd(priv, 0x0008e2, 0x00000000);
266 nv_icmd(priv, 0x0008e3, 0x00000000);
267 nv_icmd(priv, 0x0008e4, 0x00000000);
268 nv_icmd(priv, 0x0008e5, 0x00000000);
269 nv_icmd(priv, 0x0008e6, 0x00000000);
270 nv_icmd(priv, 0x0008e7, 0x00000000);
271 nv_icmd(priv, 0x0008e8, 0x00000000);
272 nv_icmd(priv, 0x0008e9, 0x00000000);
273 nv_icmd(priv, 0x0008ea, 0x00000000);
274 nv_icmd(priv, 0x0008eb, 0x00000000);
275 nv_icmd(priv, 0x0008ec, 0x00000000);
276 nv_icmd(priv, 0x0008ed, 0x00000000);
277 nv_icmd(priv, 0x0008ee, 0x00000000);
278 nv_icmd(priv, 0x0008ef, 0x00000000);
279 nv_icmd(priv, 0x0008a0, 0x00000000);
280 nv_icmd(priv, 0x0008a1, 0x00000000);
281 nv_icmd(priv, 0x0008a2, 0x00000000);
282 nv_icmd(priv, 0x0008a3, 0x00000000);
283 nv_icmd(priv, 0x0008a4, 0x00000000);
284 nv_icmd(priv, 0x0008a5, 0x00000000);
285 nv_icmd(priv, 0x0008a6, 0x00000000);
286 nv_icmd(priv, 0x0008a7, 0x00000000);
287 nv_icmd(priv, 0x0008a8, 0x00000000);
288 nv_icmd(priv, 0x0008a9, 0x00000000);
289 nv_icmd(priv, 0x0008aa, 0x00000000);
290 nv_icmd(priv, 0x0008ab, 0x00000000);
291 nv_icmd(priv, 0x0008ac, 0x00000000);
292 nv_icmd(priv, 0x0008ad, 0x00000000);
293 nv_icmd(priv, 0x0008ae, 0x00000000);
294 nv_icmd(priv, 0x0008af, 0x00000000);
295 nv_icmd(priv, 0x0008f0, 0x00000000);
296 nv_icmd(priv, 0x0008f1, 0x00000000);
297 nv_icmd(priv, 0x0008f2, 0x00000000);
298 nv_icmd(priv, 0x0008f3, 0x00000000);
299 nv_icmd(priv, 0x0008f4, 0x00000000);
300 nv_icmd(priv, 0x0008f5, 0x00000000);
301 nv_icmd(priv, 0x0008f6, 0x00000000);
302 nv_icmd(priv, 0x0008f7, 0x00000000);
303 nv_icmd(priv, 0x0008f8, 0x00000000);
304 nv_icmd(priv, 0x0008f9, 0x00000000);
305 nv_icmd(priv, 0x0008fa, 0x00000000);
306 nv_icmd(priv, 0x0008fb, 0x00000000);
307 nv_icmd(priv, 0x0008fc, 0x00000000);
308 nv_icmd(priv, 0x0008fd, 0x00000000);
309 nv_icmd(priv, 0x0008fe, 0x00000000);
310 nv_icmd(priv, 0x0008ff, 0x00000000);
311 nv_icmd(priv, 0x00094c, 0x000000ff);
312 nv_icmd(priv, 0x00094d, 0xffffffff);
313 nv_icmd(priv, 0x00094e, 0x00000002);
314 nv_icmd(priv, 0x0002ec, 0x00000001);
315 nv_icmd(priv, 0x000303, 0x00000001);
316 nv_icmd(priv, 0x0002e6, 0x00000001);
317 nv_icmd(priv, 0x000466, 0x00000052);
318 nv_icmd(priv, 0x000301, 0x3f800000);
319 nv_icmd(priv, 0x000304, 0x30201000);
320 nv_icmd(priv, 0x000305, 0x70605040);
321 nv_icmd(priv, 0x000306, 0xb8a89888);
322 nv_icmd(priv, 0x000307, 0xf8e8d8c8);
323 nv_icmd(priv, 0x00030a, 0x00ffff00);
324 nv_icmd(priv, 0x00030b, 0x0000001a);
325 nv_icmd(priv, 0x00030c, 0x00000001);
326 nv_icmd(priv, 0x000318, 0x00000001);
327 nv_icmd(priv, 0x000340, 0x00000000);
328 nv_icmd(priv, 0x000375, 0x00000001);
329 nv_icmd(priv, 0x00037d, 0x00000006);
330 nv_icmd(priv, 0x0003a0, 0x00000002);
331 nv_icmd(priv, 0x0003aa, 0x00000001);
332 nv_icmd(priv, 0x0003a9, 0x00000001);
333 nv_icmd(priv, 0x000380, 0x00000001);
334 nv_icmd(priv, 0x000383, 0x00000011);
335 nv_icmd(priv, 0x000360, 0x00000040);
336 nv_icmd(priv, 0x000366, 0x00000000);
337 nv_icmd(priv, 0x000367, 0x00000000);
338 nv_icmd(priv, 0x000368, 0x00000fff);
339 nv_icmd(priv, 0x000370, 0x00000000);
340 nv_icmd(priv, 0x000371, 0x00000000);
341 nv_icmd(priv, 0x000372, 0x000fffff);
342 nv_icmd(priv, 0x00037a, 0x00000012);
343 nv_icmd(priv, 0x000619, 0x00000003);
344 nv_icmd(priv, 0x000811, 0x00000003);
345 nv_icmd(priv, 0x000812, 0x00000004);
346 nv_icmd(priv, 0x000813, 0x00000006);
347 nv_icmd(priv, 0x000814, 0x00000008);
348 nv_icmd(priv, 0x000815, 0x0000000b);
349 nv_icmd(priv, 0x000800, 0x00000001);
350 nv_icmd(priv, 0x000801, 0x00000001);
351 nv_icmd(priv, 0x000802, 0x00000001);
352 nv_icmd(priv, 0x000803, 0x00000001);
353 nv_icmd(priv, 0x000804, 0x00000001);
354 nv_icmd(priv, 0x000805, 0x00000001);
355 nv_icmd(priv, 0x000632, 0x00000001);
356 nv_icmd(priv, 0x000633, 0x00000002);
357 nv_icmd(priv, 0x000634, 0x00000003);
358 nv_icmd(priv, 0x000635, 0x00000004);
359 nv_icmd(priv, 0x000654, 0x3f800000);
360 nv_icmd(priv, 0x000657, 0x3f800000);
361 nv_icmd(priv, 0x000655, 0x3f800000);
362 nv_icmd(priv, 0x000656, 0x3f800000);
363 nv_icmd(priv, 0x0006cd, 0x3f800000);
364 nv_icmd(priv, 0x0007f5, 0x3f800000);
365 nv_icmd(priv, 0x0007dc, 0x39291909);
366 nv_icmd(priv, 0x0007dd, 0x79695949);
367 nv_icmd(priv, 0x0007de, 0xb9a99989);
368 nv_icmd(priv, 0x0007df, 0xf9e9d9c9);
369 nv_icmd(priv, 0x0007e8, 0x00003210);
370 nv_icmd(priv, 0x0007e9, 0x00007654);
371 nv_icmd(priv, 0x0007ea, 0x00000098);
372 nv_icmd(priv, 0x0007ec, 0x39291909);
373 nv_icmd(priv, 0x0007ed, 0x79695949);
374 nv_icmd(priv, 0x0007ee, 0xb9a99989);
375 nv_icmd(priv, 0x0007ef, 0xf9e9d9c9);
376 nv_icmd(priv, 0x0007f0, 0x00003210);
377 nv_icmd(priv, 0x0007f1, 0x00007654);
378 nv_icmd(priv, 0x0007f2, 0x00000098);
379 nv_icmd(priv, 0x0005a5, 0x00000001);
380 nv_icmd(priv, 0x000980, 0x00000000);
381 nv_icmd(priv, 0x000981, 0x00000000);
382 nv_icmd(priv, 0x000982, 0x00000000);
383 nv_icmd(priv, 0x000983, 0x00000000);
384 nv_icmd(priv, 0x000984, 0x00000000);
385 nv_icmd(priv, 0x000985, 0x00000000);
386 nv_icmd(priv, 0x000986, 0x00000000);
387 nv_icmd(priv, 0x000987, 0x00000000);
388 nv_icmd(priv, 0x000988, 0x00000000);
389 nv_icmd(priv, 0x000989, 0x00000000);
390 nv_icmd(priv, 0x00098a, 0x00000000);
391 nv_icmd(priv, 0x00098b, 0x00000000);
392 nv_icmd(priv, 0x00098c, 0x00000000);
393 nv_icmd(priv, 0x00098d, 0x00000000);
394 nv_icmd(priv, 0x00098e, 0x00000000);
395 nv_icmd(priv, 0x00098f, 0x00000000);
396 nv_icmd(priv, 0x000990, 0x00000000);
397 nv_icmd(priv, 0x000991, 0x00000000);
398 nv_icmd(priv, 0x000992, 0x00000000);
399 nv_icmd(priv, 0x000993, 0x00000000);
400 nv_icmd(priv, 0x000994, 0x00000000);
401 nv_icmd(priv, 0x000995, 0x00000000);
402 nv_icmd(priv, 0x000996, 0x00000000);
403 nv_icmd(priv, 0x000997, 0x00000000);
404 nv_icmd(priv, 0x000998, 0x00000000);
405 nv_icmd(priv, 0x000999, 0x00000000);
406 nv_icmd(priv, 0x00099a, 0x00000000);
407 nv_icmd(priv, 0x00099b, 0x00000000);
408 nv_icmd(priv, 0x00099c, 0x00000000);
409 nv_icmd(priv, 0x00099d, 0x00000000);
410 nv_icmd(priv, 0x00099e, 0x00000000);
411 nv_icmd(priv, 0x00099f, 0x00000000);
412 nv_icmd(priv, 0x0009a0, 0x00000000);
413 nv_icmd(priv, 0x0009a1, 0x00000000);
414 nv_icmd(priv, 0x0009a2, 0x00000000);
415 nv_icmd(priv, 0x0009a3, 0x00000000);
416 nv_icmd(priv, 0x0009a4, 0x00000000);
417 nv_icmd(priv, 0x0009a5, 0x00000000);
418 nv_icmd(priv, 0x0009a6, 0x00000000);
419 nv_icmd(priv, 0x0009a7, 0x00000000);
420 nv_icmd(priv, 0x0009a8, 0x00000000);
421 nv_icmd(priv, 0x0009a9, 0x00000000);
422 nv_icmd(priv, 0x0009aa, 0x00000000);
423 nv_icmd(priv, 0x0009ab, 0x00000000);
424 nv_icmd(priv, 0x0009ac, 0x00000000);
425 nv_icmd(priv, 0x0009ad, 0x00000000);
426 nv_icmd(priv, 0x0009ae, 0x00000000);
427 nv_icmd(priv, 0x0009af, 0x00000000);
428 nv_icmd(priv, 0x0009b0, 0x00000000);
429 nv_icmd(priv, 0x0009b1, 0x00000000);
430 nv_icmd(priv, 0x0009b2, 0x00000000);
431 nv_icmd(priv, 0x0009b3, 0x00000000);
432 nv_icmd(priv, 0x0009b4, 0x00000000);
433 nv_icmd(priv, 0x0009b5, 0x00000000);
434 nv_icmd(priv, 0x0009b6, 0x00000000);
435 nv_icmd(priv, 0x0009b7, 0x00000000);
436 nv_icmd(priv, 0x0009b8, 0x00000000);
437 nv_icmd(priv, 0x0009b9, 0x00000000);
438 nv_icmd(priv, 0x0009ba, 0x00000000);
439 nv_icmd(priv, 0x0009bb, 0x00000000);
440 nv_icmd(priv, 0x0009bc, 0x00000000);
441 nv_icmd(priv, 0x0009bd, 0x00000000);
442 nv_icmd(priv, 0x0009be, 0x00000000);
443 nv_icmd(priv, 0x0009bf, 0x00000000);
444 nv_icmd(priv, 0x0009c0, 0x00000000);
445 nv_icmd(priv, 0x0009c1, 0x00000000);
446 nv_icmd(priv, 0x0009c2, 0x00000000);
447 nv_icmd(priv, 0x0009c3, 0x00000000);
448 nv_icmd(priv, 0x0009c4, 0x00000000);
449 nv_icmd(priv, 0x0009c5, 0x00000000);
450 nv_icmd(priv, 0x0009c6, 0x00000000);
451 nv_icmd(priv, 0x0009c7, 0x00000000);
452 nv_icmd(priv, 0x0009c8, 0x00000000);
453 nv_icmd(priv, 0x0009c9, 0x00000000);
454 nv_icmd(priv, 0x0009ca, 0x00000000);
455 nv_icmd(priv, 0x0009cb, 0x00000000);
456 nv_icmd(priv, 0x0009cc, 0x00000000);
457 nv_icmd(priv, 0x0009cd, 0x00000000);
458 nv_icmd(priv, 0x0009ce, 0x00000000);
459 nv_icmd(priv, 0x0009cf, 0x00000000);
460 nv_icmd(priv, 0x0009d0, 0x00000000);
461 nv_icmd(priv, 0x0009d1, 0x00000000);
462 nv_icmd(priv, 0x0009d2, 0x00000000);
463 nv_icmd(priv, 0x0009d3, 0x00000000);
464 nv_icmd(priv, 0x0009d4, 0x00000000);
465 nv_icmd(priv, 0x0009d5, 0x00000000);
466 nv_icmd(priv, 0x0009d6, 0x00000000);
467 nv_icmd(priv, 0x0009d7, 0x00000000);
468 nv_icmd(priv, 0x0009d8, 0x00000000);
469 nv_icmd(priv, 0x0009d9, 0x00000000);
470 nv_icmd(priv, 0x0009da, 0x00000000);
471 nv_icmd(priv, 0x0009db, 0x00000000);
472 nv_icmd(priv, 0x0009dc, 0x00000000);
473 nv_icmd(priv, 0x0009dd, 0x00000000);
474 nv_icmd(priv, 0x0009de, 0x00000000);
475 nv_icmd(priv, 0x0009df, 0x00000000);
476 nv_icmd(priv, 0x0009e0, 0x00000000);
477 nv_icmd(priv, 0x0009e1, 0x00000000);
478 nv_icmd(priv, 0x0009e2, 0x00000000);
479 nv_icmd(priv, 0x0009e3, 0x00000000);
480 nv_icmd(priv, 0x0009e4, 0x00000000);
481 nv_icmd(priv, 0x0009e5, 0x00000000);
482 nv_icmd(priv, 0x0009e6, 0x00000000);
483 nv_icmd(priv, 0x0009e7, 0x00000000);
484 nv_icmd(priv, 0x0009e8, 0x00000000);
485 nv_icmd(priv, 0x0009e9, 0x00000000);
486 nv_icmd(priv, 0x0009ea, 0x00000000);
487 nv_icmd(priv, 0x0009eb, 0x00000000);
488 nv_icmd(priv, 0x0009ec, 0x00000000);
489 nv_icmd(priv, 0x0009ed, 0x00000000);
490 nv_icmd(priv, 0x0009ee, 0x00000000);
491 nv_icmd(priv, 0x0009ef, 0x00000000);
492 nv_icmd(priv, 0x0009f0, 0x00000000);
493 nv_icmd(priv, 0x0009f1, 0x00000000);
494 nv_icmd(priv, 0x0009f2, 0x00000000);
495 nv_icmd(priv, 0x0009f3, 0x00000000);
496 nv_icmd(priv, 0x0009f4, 0x00000000);
497 nv_icmd(priv, 0x0009f5, 0x00000000);
498 nv_icmd(priv, 0x0009f6, 0x00000000);
499 nv_icmd(priv, 0x0009f7, 0x00000000);
500 nv_icmd(priv, 0x0009f8, 0x00000000);
501 nv_icmd(priv, 0x0009f9, 0x00000000);
502 nv_icmd(priv, 0x0009fa, 0x00000000);
503 nv_icmd(priv, 0x0009fb, 0x00000000);
504 nv_icmd(priv, 0x0009fc, 0x00000000);
505 nv_icmd(priv, 0x0009fd, 0x00000000);
506 nv_icmd(priv, 0x0009fe, 0x00000000);
507 nv_icmd(priv, 0x0009ff, 0x00000000);
508 nv_icmd(priv, 0x000468, 0x00000004);
509 nv_icmd(priv, 0x00046c, 0x00000001);
510 nv_icmd(priv, 0x000470, 0x00000000);
511 nv_icmd(priv, 0x000471, 0x00000000);
512 nv_icmd(priv, 0x000472, 0x00000000);
513 nv_icmd(priv, 0x000473, 0x00000000);
514 nv_icmd(priv, 0x000474, 0x00000000);
515 nv_icmd(priv, 0x000475, 0x00000000);
516 nv_icmd(priv, 0x000476, 0x00000000);
517 nv_icmd(priv, 0x000477, 0x00000000);
518 nv_icmd(priv, 0x000478, 0x00000000);
519 nv_icmd(priv, 0x000479, 0x00000000);
520 nv_icmd(priv, 0x00047a, 0x00000000);
521 nv_icmd(priv, 0x00047b, 0x00000000);
522 nv_icmd(priv, 0x00047c, 0x00000000);
523 nv_icmd(priv, 0x00047d, 0x00000000);
524 nv_icmd(priv, 0x00047e, 0x00000000);
525 nv_icmd(priv, 0x00047f, 0x00000000);
526 nv_icmd(priv, 0x000480, 0x00000000);
527 nv_icmd(priv, 0x000481, 0x00000000);
528 nv_icmd(priv, 0x000482, 0x00000000);
529 nv_icmd(priv, 0x000483, 0x00000000);
530 nv_icmd(priv, 0x000484, 0x00000000);
531 nv_icmd(priv, 0x000485, 0x00000000);
532 nv_icmd(priv, 0x000486, 0x00000000);
533 nv_icmd(priv, 0x000487, 0x00000000);
534 nv_icmd(priv, 0x000488, 0x00000000);
535 nv_icmd(priv, 0x000489, 0x00000000);
536 nv_icmd(priv, 0x00048a, 0x00000000);
537 nv_icmd(priv, 0x00048b, 0x00000000);
538 nv_icmd(priv, 0x00048c, 0x00000000);
539 nv_icmd(priv, 0x00048d, 0x00000000);
540 nv_icmd(priv, 0x00048e, 0x00000000);
541 nv_icmd(priv, 0x00048f, 0x00000000);
542 nv_icmd(priv, 0x000490, 0x00000000);
543 nv_icmd(priv, 0x000491, 0x00000000);
544 nv_icmd(priv, 0x000492, 0x00000000);
545 nv_icmd(priv, 0x000493, 0x00000000);
546 nv_icmd(priv, 0x000494, 0x00000000);
547 nv_icmd(priv, 0x000495, 0x00000000);
548 nv_icmd(priv, 0x000496, 0x00000000);
549 nv_icmd(priv, 0x000497, 0x00000000);
550 nv_icmd(priv, 0x000498, 0x00000000);
551 nv_icmd(priv, 0x000499, 0x00000000);
552 nv_icmd(priv, 0x00049a, 0x00000000);
553 nv_icmd(priv, 0x00049b, 0x00000000);
554 nv_icmd(priv, 0x00049c, 0x00000000);
555 nv_icmd(priv, 0x00049d, 0x00000000);
556 nv_icmd(priv, 0x00049e, 0x00000000);
557 nv_icmd(priv, 0x00049f, 0x00000000);
558 nv_icmd(priv, 0x0004a0, 0x00000000);
559 nv_icmd(priv, 0x0004a1, 0x00000000);
560 nv_icmd(priv, 0x0004a2, 0x00000000);
561 nv_icmd(priv, 0x0004a3, 0x00000000);
562 nv_icmd(priv, 0x0004a4, 0x00000000);
563 nv_icmd(priv, 0x0004a5, 0x00000000);
564 nv_icmd(priv, 0x0004a6, 0x00000000);
565 nv_icmd(priv, 0x0004a7, 0x00000000);
566 nv_icmd(priv, 0x0004a8, 0x00000000);
567 nv_icmd(priv, 0x0004a9, 0x00000000);
568 nv_icmd(priv, 0x0004aa, 0x00000000);
569 nv_icmd(priv, 0x0004ab, 0x00000000);
570 nv_icmd(priv, 0x0004ac, 0x00000000);
571 nv_icmd(priv, 0x0004ad, 0x00000000);
572 nv_icmd(priv, 0x0004ae, 0x00000000);
573 nv_icmd(priv, 0x0004af, 0x00000000);
574 nv_icmd(priv, 0x0004b0, 0x00000000);
575 nv_icmd(priv, 0x0004b1, 0x00000000);
576 nv_icmd(priv, 0x0004b2, 0x00000000);
577 nv_icmd(priv, 0x0004b3, 0x00000000);
578 nv_icmd(priv, 0x0004b4, 0x00000000);
579 nv_icmd(priv, 0x0004b5, 0x00000000);
580 nv_icmd(priv, 0x0004b6, 0x00000000);
581 nv_icmd(priv, 0x0004b7, 0x00000000);
582 nv_icmd(priv, 0x0004b8, 0x00000000);
583 nv_icmd(priv, 0x0004b9, 0x00000000);
584 nv_icmd(priv, 0x0004ba, 0x00000000);
585 nv_icmd(priv, 0x0004bb, 0x00000000);
586 nv_icmd(priv, 0x0004bc, 0x00000000);
587 nv_icmd(priv, 0x0004bd, 0x00000000);
588 nv_icmd(priv, 0x0004be, 0x00000000);
589 nv_icmd(priv, 0x0004bf, 0x00000000);
590 nv_icmd(priv, 0x0004c0, 0x00000000);
591 nv_icmd(priv, 0x0004c1, 0x00000000);
592 nv_icmd(priv, 0x0004c2, 0x00000000);
593 nv_icmd(priv, 0x0004c3, 0x00000000);
594 nv_icmd(priv, 0x0004c4, 0x00000000);
595 nv_icmd(priv, 0x0004c5, 0x00000000);
596 nv_icmd(priv, 0x0004c6, 0x00000000);
597 nv_icmd(priv, 0x0004c7, 0x00000000);
598 nv_icmd(priv, 0x0004c8, 0x00000000);
599 nv_icmd(priv, 0x0004c9, 0x00000000);
600 nv_icmd(priv, 0x0004ca, 0x00000000);
601 nv_icmd(priv, 0x0004cb, 0x00000000);
602 nv_icmd(priv, 0x0004cc, 0x00000000);
603 nv_icmd(priv, 0x0004cd, 0x00000000);
604 nv_icmd(priv, 0x0004ce, 0x00000000);
605 nv_icmd(priv, 0x0004cf, 0x00000000);
606 nv_icmd(priv, 0x000510, 0x3f800000);
607 nv_icmd(priv, 0x000511, 0x3f800000);
608 nv_icmd(priv, 0x000512, 0x3f800000);
609 nv_icmd(priv, 0x000513, 0x3f800000);
610 nv_icmd(priv, 0x000514, 0x3f800000);
611 nv_icmd(priv, 0x000515, 0x3f800000);
612 nv_icmd(priv, 0x000516, 0x3f800000);
613 nv_icmd(priv, 0x000517, 0x3f800000);
614 nv_icmd(priv, 0x000518, 0x3f800000);
615 nv_icmd(priv, 0x000519, 0x3f800000);
616 nv_icmd(priv, 0x00051a, 0x3f800000);
617 nv_icmd(priv, 0x00051b, 0x3f800000);
618 nv_icmd(priv, 0x00051c, 0x3f800000);
619 nv_icmd(priv, 0x00051d, 0x3f800000);
620 nv_icmd(priv, 0x00051e, 0x3f800000);
621 nv_icmd(priv, 0x00051f, 0x3f800000);
622 nv_icmd(priv, 0x000520, 0x000002b6);
623 nv_icmd(priv, 0x000529, 0x00000001);
624 nv_icmd(priv, 0x000530, 0xffff0000);
625 nv_icmd(priv, 0x000531, 0xffff0000);
626 nv_icmd(priv, 0x000532, 0xffff0000);
627 nv_icmd(priv, 0x000533, 0xffff0000);
628 nv_icmd(priv, 0x000534, 0xffff0000);
629 nv_icmd(priv, 0x000535, 0xffff0000);
630 nv_icmd(priv, 0x000536, 0xffff0000);
631 nv_icmd(priv, 0x000537, 0xffff0000);
632 nv_icmd(priv, 0x000538, 0xffff0000);
633 nv_icmd(priv, 0x000539, 0xffff0000);
634 nv_icmd(priv, 0x00053a, 0xffff0000);
635 nv_icmd(priv, 0x00053b, 0xffff0000);
636 nv_icmd(priv, 0x00053c, 0xffff0000);
637 nv_icmd(priv, 0x00053d, 0xffff0000);
638 nv_icmd(priv, 0x00053e, 0xffff0000);
639 nv_icmd(priv, 0x00053f, 0xffff0000);
640 nv_icmd(priv, 0x000585, 0x0000003f);
641 nv_icmd(priv, 0x000576, 0x00000003);
642 nv_icmd(priv, 0x00057b, 0x00000059);
643 nv_icmd(priv, 0x000586, 0x00000040);
644 nv_icmd(priv, 0x000582, 0x00000080);
645 nv_icmd(priv, 0x000583, 0x00000080);
646 nv_icmd(priv, 0x0005c2, 0x00000001);
647 nv_icmd(priv, 0x000638, 0x00000001);
648 nv_icmd(priv, 0x000639, 0x00000001);
649 nv_icmd(priv, 0x00063a, 0x00000002);
650 nv_icmd(priv, 0x00063b, 0x00000001);
651 nv_icmd(priv, 0x00063c, 0x00000001);
652 nv_icmd(priv, 0x00063d, 0x00000002);
653 nv_icmd(priv, 0x00063e, 0x00000001);
654 nv_icmd(priv, 0x0008b8, 0x00000001);
655 nv_icmd(priv, 0x0008b9, 0x00000001);
656 nv_icmd(priv, 0x0008ba, 0x00000001);
657 nv_icmd(priv, 0x0008bb, 0x00000001);
658 nv_icmd(priv, 0x0008bc, 0x00000001);
659 nv_icmd(priv, 0x0008bd, 0x00000001);
660 nv_icmd(priv, 0x0008be, 0x00000001);
661 nv_icmd(priv, 0x0008bf, 0x00000001);
662 nv_icmd(priv, 0x000900, 0x00000001);
663 nv_icmd(priv, 0x000901, 0x00000001);
664 nv_icmd(priv, 0x000902, 0x00000001);
665 nv_icmd(priv, 0x000903, 0x00000001);
666 nv_icmd(priv, 0x000904, 0x00000001);
667 nv_icmd(priv, 0x000905, 0x00000001);
668 nv_icmd(priv, 0x000906, 0x00000001);
669 nv_icmd(priv, 0x000907, 0x00000001);
670 nv_icmd(priv, 0x000908, 0x00000002);
671 nv_icmd(priv, 0x000909, 0x00000002);
672 nv_icmd(priv, 0x00090a, 0x00000002);
673 nv_icmd(priv, 0x00090b, 0x00000002);
674 nv_icmd(priv, 0x00090c, 0x00000002);
675 nv_icmd(priv, 0x00090d, 0x00000002);
676 nv_icmd(priv, 0x00090e, 0x00000002);
677 nv_icmd(priv, 0x00090f, 0x00000002);
678 nv_icmd(priv, 0x000910, 0x00000001);
679 nv_icmd(priv, 0x000911, 0x00000001);
680 nv_icmd(priv, 0x000912, 0x00000001);
681 nv_icmd(priv, 0x000913, 0x00000001);
682 nv_icmd(priv, 0x000914, 0x00000001);
683 nv_icmd(priv, 0x000915, 0x00000001);
684 nv_icmd(priv, 0x000916, 0x00000001);
685 nv_icmd(priv, 0x000917, 0x00000001);
686 nv_icmd(priv, 0x000918, 0x00000001);
687 nv_icmd(priv, 0x000919, 0x00000001);
688 nv_icmd(priv, 0x00091a, 0x00000001);
689 nv_icmd(priv, 0x00091b, 0x00000001);
690 nv_icmd(priv, 0x00091c, 0x00000001);
691 nv_icmd(priv, 0x00091d, 0x00000001);
692 nv_icmd(priv, 0x00091e, 0x00000001);
693 nv_icmd(priv, 0x00091f, 0x00000001);
694 nv_icmd(priv, 0x000920, 0x00000002);
695 nv_icmd(priv, 0x000921, 0x00000002);
696 nv_icmd(priv, 0x000922, 0x00000002);
697 nv_icmd(priv, 0x000923, 0x00000002);
698 nv_icmd(priv, 0x000924, 0x00000002);
699 nv_icmd(priv, 0x000925, 0x00000002);
700 nv_icmd(priv, 0x000926, 0x00000002);
701 nv_icmd(priv, 0x000927, 0x00000002);
702 nv_icmd(priv, 0x000928, 0x00000001);
703 nv_icmd(priv, 0x000929, 0x00000001);
704 nv_icmd(priv, 0x00092a, 0x00000001);
705 nv_icmd(priv, 0x00092b, 0x00000001);
706 nv_icmd(priv, 0x00092c, 0x00000001);
707 nv_icmd(priv, 0x00092d, 0x00000001);
708 nv_icmd(priv, 0x00092e, 0x00000001);
709 nv_icmd(priv, 0x00092f, 0x00000001);
710 nv_icmd(priv, 0x000648, 0x00000001);
711 nv_icmd(priv, 0x000649, 0x00000001);
712 nv_icmd(priv, 0x00064a, 0x00000001);
713 nv_icmd(priv, 0x00064b, 0x00000001);
714 nv_icmd(priv, 0x00064c, 0x00000001);
715 nv_icmd(priv, 0x00064d, 0x00000001);
716 nv_icmd(priv, 0x00064e, 0x00000001);
717 nv_icmd(priv, 0x00064f, 0x00000001);
718 nv_icmd(priv, 0x000650, 0x00000001);
719 nv_icmd(priv, 0x000658, 0x0000000f);
720 nv_icmd(priv, 0x0007ff, 0x0000000a);
721 nv_icmd(priv, 0x00066a, 0x40000000);
722 nv_icmd(priv, 0x00066b, 0x10000000);
723 nv_icmd(priv, 0x00066c, 0xffff0000);
724 nv_icmd(priv, 0x00066d, 0xffff0000);
725 nv_icmd(priv, 0x0007af, 0x00000008);
726 nv_icmd(priv, 0x0007b0, 0x00000008);
727 nv_icmd(priv, 0x0007f6, 0x00000001);
728 nv_icmd(priv, 0x0006b2, 0x00000055);
729 nv_icmd(priv, 0x0007ad, 0x00000003);
730 nv_icmd(priv, 0x000937, 0x00000001);
731 nv_icmd(priv, 0x000971, 0x00000008);
732 nv_icmd(priv, 0x000972, 0x00000040);
733 nv_icmd(priv, 0x000973, 0x0000012c);
734 nv_icmd(priv, 0x00097c, 0x00000040);
735 nv_icmd(priv, 0x000979, 0x00000003);
736 nv_icmd(priv, 0x000975, 0x00000020);
737 nv_icmd(priv, 0x000976, 0x00000001);
738 nv_icmd(priv, 0x000977, 0x00000020);
739 nv_icmd(priv, 0x000978, 0x00000001);
740 nv_icmd(priv, 0x000957, 0x00000003);
741 nv_icmd(priv, 0x00095e, 0x20164010);
742 nv_icmd(priv, 0x00095f, 0x00000020);
743 nv_icmd(priv, 0x00097d, 0x00000020);
744 nv_icmd(priv, 0x000683, 0x00000006);
745 nv_icmd(priv, 0x000685, 0x003fffff);
746 nv_icmd(priv, 0x000687, 0x003fffff);
747 nv_icmd(priv, 0x0006a0, 0x00000005);
748 nv_icmd(priv, 0x000840, 0x00400008);
749 nv_icmd(priv, 0x000841, 0x08000080);
750 nv_icmd(priv, 0x000842, 0x00400008);
751 nv_icmd(priv, 0x000843, 0x08000080);
752 nv_icmd(priv, 0x0006aa, 0x00000001);
753 nv_icmd(priv, 0x0006ab, 0x00000002);
754 nv_icmd(priv, 0x0006ac, 0x00000080);
755 nv_icmd(priv, 0x0006ad, 0x00000100);
756 nv_icmd(priv, 0x0006ae, 0x00000100);
757 nv_icmd(priv, 0x0006b1, 0x00000011);
758 nv_icmd(priv, 0x0006bb, 0x000000cf);
759 nv_icmd(priv, 0x0006ce, 0x2a712488);
760 nv_icmd(priv, 0x000739, 0x4085c000);
761 nv_icmd(priv, 0x00073a, 0x00000080);
762 nv_icmd(priv, 0x000786, 0x80000100);
763 nv_icmd(priv, 0x00073c, 0x00010100);
764 nv_icmd(priv, 0x00073d, 0x02800000);
765 nv_icmd(priv, 0x000787, 0x000000cf);
766 nv_icmd(priv, 0x00078c, 0x00000008);
767 nv_icmd(priv, 0x000792, 0x00000001);
768 nv_icmd(priv, 0x000794, 0x00000001);
769 nv_icmd(priv, 0x000795, 0x00000001);
770 nv_icmd(priv, 0x000796, 0x00000001);
771 nv_icmd(priv, 0x000797, 0x000000cf);
772 nv_icmd(priv, 0x000836, 0x00000001);
773 nv_icmd(priv, 0x00079a, 0x00000002);
774 nv_icmd(priv, 0x000833, 0x04444480);
775 nv_icmd(priv, 0x0007a1, 0x00000001);
776 nv_icmd(priv, 0x0007a3, 0x00000001);
777 nv_icmd(priv, 0x0007a4, 0x00000001);
778 nv_icmd(priv, 0x0007a5, 0x00000001);
779 nv_icmd(priv, 0x000831, 0x00000004);
780 nv_icmd(priv, 0x000b07, 0x00000002);
781 nv_icmd(priv, 0x000b08, 0x00000100);
782 nv_icmd(priv, 0x000b09, 0x00000100);
783 nv_icmd(priv, 0x000b0a, 0x00000001);
784 nv_icmd(priv, 0x000a04, 0x000000ff);
785 nv_icmd(priv, 0x000a0b, 0x00000040);
786 nv_icmd(priv, 0x00097f, 0x00000100);
787 nv_icmd(priv, 0x000a02, 0x00000001);
788 nv_icmd(priv, 0x000809, 0x00000007);
789 nv_icmd(priv, 0x00c221, 0x00000040);
790 nv_icmd(priv, 0x00c1b0, 0x0000000f);
791 nv_icmd(priv, 0x00c1b1, 0x0000000f);
792 nv_icmd(priv, 0x00c1b2, 0x0000000f);
793 nv_icmd(priv, 0x00c1b3, 0x0000000f);
794 nv_icmd(priv, 0x00c1b4, 0x0000000f);
795 nv_icmd(priv, 0x00c1b5, 0x0000000f);
796 nv_icmd(priv, 0x00c1b6, 0x0000000f);
797 nv_icmd(priv, 0x00c1b7, 0x0000000f);
798 nv_icmd(priv, 0x00c1b8, 0x0fac6881);
799 nv_icmd(priv, 0x00c1b9, 0x00fac688);
800 nv_icmd(priv, 0x00c401, 0x00000001);
801 nv_icmd(priv, 0x00c402, 0x00010001);
802 nv_icmd(priv, 0x00c403, 0x00000001);
803 nv_icmd(priv, 0x00c404, 0x00000001);
804 nv_icmd(priv, 0x00c40e, 0x00000020);
805 nv_icmd(priv, 0x00c500, 0x00000003);
806 nv_icmd(priv, 0x01e100, 0x00000001);
807 nv_icmd(priv, 0x001000, 0x00000002);
808 nv_icmd(priv, 0x0006aa, 0x00000001);
809 nv_icmd(priv, 0x0006ad, 0x00000100);
810 nv_icmd(priv, 0x0006ae, 0x00000100);
811 nv_icmd(priv, 0x0006b1, 0x00000011);
812 nv_icmd(priv, 0x00078c, 0x00000008);
813 nv_icmd(priv, 0x000792, 0x00000001);
814 nv_icmd(priv, 0x000794, 0x00000001);
815 nv_icmd(priv, 0x000795, 0x00000001);
816 nv_icmd(priv, 0x000796, 0x00000001);
817 nv_icmd(priv, 0x000797, 0x000000cf);
818 nv_icmd(priv, 0x00079a, 0x00000002);
819 nv_icmd(priv, 0x000833, 0x04444480);
820 nv_icmd(priv, 0x0007a1, 0x00000001);
821 nv_icmd(priv, 0x0007a3, 0x00000001);
822 nv_icmd(priv, 0x0007a4, 0x00000001);
823 nv_icmd(priv, 0x0007a5, 0x00000001);
824 nv_icmd(priv, 0x000831, 0x00000004);
825 nv_icmd(priv, 0x01e100, 0x00000001);
826 nv_icmd(priv, 0x001000, 0x00000008);
827 nv_icmd(priv, 0x000039, 0x00000000);
828 nv_icmd(priv, 0x00003a, 0x00000000);
829 nv_icmd(priv, 0x00003b, 0x00000000);
830 nv_icmd(priv, 0x000380, 0x00000001);
831 nv_icmd(priv, 0x000366, 0x00000000);
832 nv_icmd(priv, 0x000367, 0x00000000);
833 nv_icmd(priv, 0x000368, 0x00000fff);
834 nv_icmd(priv, 0x000370, 0x00000000);
835 nv_icmd(priv, 0x000371, 0x00000000);
836 nv_icmd(priv, 0x000372, 0x000fffff);
837 nv_icmd(priv, 0x000813, 0x00000006);
838 nv_icmd(priv, 0x000814, 0x00000008);
839 nv_icmd(priv, 0x000957, 0x00000003);
840 nv_icmd(priv, 0x000b07, 0x00000002);
841 nv_icmd(priv, 0x000b08, 0x00000100);
842 nv_icmd(priv, 0x000b09, 0x00000100);
843 nv_icmd(priv, 0x000b0a, 0x00000001);
844 nv_icmd(priv, 0x000a04, 0x000000ff);
845 nv_icmd(priv, 0x00097f, 0x00000100);
846 nv_icmd(priv, 0x000a02, 0x00000001);
847 nv_icmd(priv, 0x000809, 0x00000007);
848 nv_icmd(priv, 0x00c221, 0x00000040);
849 nv_icmd(priv, 0x00c401, 0x00000001);
850 nv_icmd(priv, 0x00c402, 0x00010001);
851 nv_icmd(priv, 0x00c403, 0x00000001);
852 nv_icmd(priv, 0x00c404, 0x00000001);
853 nv_icmd(priv, 0x00c40e, 0x00000020);
854 nv_icmd(priv, 0x00c500, 0x00000003);
855 nv_icmd(priv, 0x01e100, 0x00000001);
856 nv_icmd(priv, 0x001000, 0x00000001);
857 nv_icmd(priv, 0x000b07, 0x00000002);
858 nv_icmd(priv, 0x000b08, 0x00000100);
859 nv_icmd(priv, 0x000b09, 0x00000100);
860 nv_icmd(priv, 0x000b0a, 0x00000001);
861 nv_icmd(priv, 0x01e100, 0x00000001);
862 nv_wr32(priv, 0x400208, 0x00000000);
863}
864
865static void
866nve0_grctx_generate_a097(struct nvc0_graph_priv *priv)
867{
868 nv_mthd(priv, 0xa097, 0x0800, 0x00000000);
869 nv_mthd(priv, 0xa097, 0x0840, 0x00000000);
870 nv_mthd(priv, 0xa097, 0x0880, 0x00000000);
871 nv_mthd(priv, 0xa097, 0x08c0, 0x00000000);
872 nv_mthd(priv, 0xa097, 0x0900, 0x00000000);
873 nv_mthd(priv, 0xa097, 0x0940, 0x00000000);
874 nv_mthd(priv, 0xa097, 0x0980, 0x00000000);
875 nv_mthd(priv, 0xa097, 0x09c0, 0x00000000);
876 nv_mthd(priv, 0xa097, 0x0804, 0x00000000);
877 nv_mthd(priv, 0xa097, 0x0844, 0x00000000);
878 nv_mthd(priv, 0xa097, 0x0884, 0x00000000);
879 nv_mthd(priv, 0xa097, 0x08c4, 0x00000000);
880 nv_mthd(priv, 0xa097, 0x0904, 0x00000000);
881 nv_mthd(priv, 0xa097, 0x0944, 0x00000000);
882 nv_mthd(priv, 0xa097, 0x0984, 0x00000000);
883 nv_mthd(priv, 0xa097, 0x09c4, 0x00000000);
884 nv_mthd(priv, 0xa097, 0x0808, 0x00000400);
885 nv_mthd(priv, 0xa097, 0x0848, 0x00000400);
886 nv_mthd(priv, 0xa097, 0x0888, 0x00000400);
887 nv_mthd(priv, 0xa097, 0x08c8, 0x00000400);
888 nv_mthd(priv, 0xa097, 0x0908, 0x00000400);
889 nv_mthd(priv, 0xa097, 0x0948, 0x00000400);
890 nv_mthd(priv, 0xa097, 0x0988, 0x00000400);
891 nv_mthd(priv, 0xa097, 0x09c8, 0x00000400);
892 nv_mthd(priv, 0xa097, 0x080c, 0x00000300);
893 nv_mthd(priv, 0xa097, 0x084c, 0x00000300);
894 nv_mthd(priv, 0xa097, 0x088c, 0x00000300);
895 nv_mthd(priv, 0xa097, 0x08cc, 0x00000300);
896 nv_mthd(priv, 0xa097, 0x090c, 0x00000300);
897 nv_mthd(priv, 0xa097, 0x094c, 0x00000300);
898 nv_mthd(priv, 0xa097, 0x098c, 0x00000300);
899 nv_mthd(priv, 0xa097, 0x09cc, 0x00000300);
900 nv_mthd(priv, 0xa097, 0x0810, 0x000000cf);
901 nv_mthd(priv, 0xa097, 0x0850, 0x00000000);
902 nv_mthd(priv, 0xa097, 0x0890, 0x00000000);
903 nv_mthd(priv, 0xa097, 0x08d0, 0x00000000);
904 nv_mthd(priv, 0xa097, 0x0910, 0x00000000);
905 nv_mthd(priv, 0xa097, 0x0950, 0x00000000);
906 nv_mthd(priv, 0xa097, 0x0990, 0x00000000);
907 nv_mthd(priv, 0xa097, 0x09d0, 0x00000000);
908 nv_mthd(priv, 0xa097, 0x0814, 0x00000040);
909 nv_mthd(priv, 0xa097, 0x0854, 0x00000040);
910 nv_mthd(priv, 0xa097, 0x0894, 0x00000040);
911 nv_mthd(priv, 0xa097, 0x08d4, 0x00000040);
912 nv_mthd(priv, 0xa097, 0x0914, 0x00000040);
913 nv_mthd(priv, 0xa097, 0x0954, 0x00000040);
914 nv_mthd(priv, 0xa097, 0x0994, 0x00000040);
915 nv_mthd(priv, 0xa097, 0x09d4, 0x00000040);
916 nv_mthd(priv, 0xa097, 0x0818, 0x00000001);
917 nv_mthd(priv, 0xa097, 0x0858, 0x00000001);
918 nv_mthd(priv, 0xa097, 0x0898, 0x00000001);
919 nv_mthd(priv, 0xa097, 0x08d8, 0x00000001);
920 nv_mthd(priv, 0xa097, 0x0918, 0x00000001);
921 nv_mthd(priv, 0xa097, 0x0958, 0x00000001);
922 nv_mthd(priv, 0xa097, 0x0998, 0x00000001);
923 nv_mthd(priv, 0xa097, 0x09d8, 0x00000001);
924 nv_mthd(priv, 0xa097, 0x081c, 0x00000000);
925 nv_mthd(priv, 0xa097, 0x085c, 0x00000000);
926 nv_mthd(priv, 0xa097, 0x089c, 0x00000000);
927 nv_mthd(priv, 0xa097, 0x08dc, 0x00000000);
928 nv_mthd(priv, 0xa097, 0x091c, 0x00000000);
929 nv_mthd(priv, 0xa097, 0x095c, 0x00000000);
930 nv_mthd(priv, 0xa097, 0x099c, 0x00000000);
931 nv_mthd(priv, 0xa097, 0x09dc, 0x00000000);
932 nv_mthd(priv, 0xa097, 0x0820, 0x00000000);
933 nv_mthd(priv, 0xa097, 0x0860, 0x00000000);
934 nv_mthd(priv, 0xa097, 0x08a0, 0x00000000);
935 nv_mthd(priv, 0xa097, 0x08e0, 0x00000000);
936 nv_mthd(priv, 0xa097, 0x0920, 0x00000000);
937 nv_mthd(priv, 0xa097, 0x0960, 0x00000000);
938 nv_mthd(priv, 0xa097, 0x09a0, 0x00000000);
939 nv_mthd(priv, 0xa097, 0x09e0, 0x00000000);
940 nv_mthd(priv, 0xa097, 0x1c00, 0x00000000);
941 nv_mthd(priv, 0xa097, 0x1c10, 0x00000000);
942 nv_mthd(priv, 0xa097, 0x1c20, 0x00000000);
943 nv_mthd(priv, 0xa097, 0x1c30, 0x00000000);
944 nv_mthd(priv, 0xa097, 0x1c40, 0x00000000);
945 nv_mthd(priv, 0xa097, 0x1c50, 0x00000000);
946 nv_mthd(priv, 0xa097, 0x1c60, 0x00000000);
947 nv_mthd(priv, 0xa097, 0x1c70, 0x00000000);
948 nv_mthd(priv, 0xa097, 0x1c80, 0x00000000);
949 nv_mthd(priv, 0xa097, 0x1c90, 0x00000000);
950 nv_mthd(priv, 0xa097, 0x1ca0, 0x00000000);
951 nv_mthd(priv, 0xa097, 0x1cb0, 0x00000000);
952 nv_mthd(priv, 0xa097, 0x1cc0, 0x00000000);
953 nv_mthd(priv, 0xa097, 0x1cd0, 0x00000000);
954 nv_mthd(priv, 0xa097, 0x1ce0, 0x00000000);
955 nv_mthd(priv, 0xa097, 0x1cf0, 0x00000000);
956 nv_mthd(priv, 0xa097, 0x1c04, 0x00000000);
957 nv_mthd(priv, 0xa097, 0x1c14, 0x00000000);
958 nv_mthd(priv, 0xa097, 0x1c24, 0x00000000);
959 nv_mthd(priv, 0xa097, 0x1c34, 0x00000000);
960 nv_mthd(priv, 0xa097, 0x1c44, 0x00000000);
961 nv_mthd(priv, 0xa097, 0x1c54, 0x00000000);
962 nv_mthd(priv, 0xa097, 0x1c64, 0x00000000);
963 nv_mthd(priv, 0xa097, 0x1c74, 0x00000000);
964 nv_mthd(priv, 0xa097, 0x1c84, 0x00000000);
965 nv_mthd(priv, 0xa097, 0x1c94, 0x00000000);
966 nv_mthd(priv, 0xa097, 0x1ca4, 0x00000000);
967 nv_mthd(priv, 0xa097, 0x1cb4, 0x00000000);
968 nv_mthd(priv, 0xa097, 0x1cc4, 0x00000000);
969 nv_mthd(priv, 0xa097, 0x1cd4, 0x00000000);
970 nv_mthd(priv, 0xa097, 0x1ce4, 0x00000000);
971 nv_mthd(priv, 0xa097, 0x1cf4, 0x00000000);
972 nv_mthd(priv, 0xa097, 0x1c08, 0x00000000);
973 nv_mthd(priv, 0xa097, 0x1c18, 0x00000000);
974 nv_mthd(priv, 0xa097, 0x1c28, 0x00000000);
975 nv_mthd(priv, 0xa097, 0x1c38, 0x00000000);
976 nv_mthd(priv, 0xa097, 0x1c48, 0x00000000);
977 nv_mthd(priv, 0xa097, 0x1c58, 0x00000000);
978 nv_mthd(priv, 0xa097, 0x1c68, 0x00000000);
979 nv_mthd(priv, 0xa097, 0x1c78, 0x00000000);
980 nv_mthd(priv, 0xa097, 0x1c88, 0x00000000);
981 nv_mthd(priv, 0xa097, 0x1c98, 0x00000000);
982 nv_mthd(priv, 0xa097, 0x1ca8, 0x00000000);
983 nv_mthd(priv, 0xa097, 0x1cb8, 0x00000000);
984 nv_mthd(priv, 0xa097, 0x1cc8, 0x00000000);
985 nv_mthd(priv, 0xa097, 0x1cd8, 0x00000000);
986 nv_mthd(priv, 0xa097, 0x1ce8, 0x00000000);
987 nv_mthd(priv, 0xa097, 0x1cf8, 0x00000000);
988 nv_mthd(priv, 0xa097, 0x1c0c, 0x00000000);
989 nv_mthd(priv, 0xa097, 0x1c1c, 0x00000000);
990 nv_mthd(priv, 0xa097, 0x1c2c, 0x00000000);
991 nv_mthd(priv, 0xa097, 0x1c3c, 0x00000000);
992 nv_mthd(priv, 0xa097, 0x1c4c, 0x00000000);
993 nv_mthd(priv, 0xa097, 0x1c5c, 0x00000000);
994 nv_mthd(priv, 0xa097, 0x1c6c, 0x00000000);
995 nv_mthd(priv, 0xa097, 0x1c7c, 0x00000000);
996 nv_mthd(priv, 0xa097, 0x1c8c, 0x00000000);
997 nv_mthd(priv, 0xa097, 0x1c9c, 0x00000000);
998 nv_mthd(priv, 0xa097, 0x1cac, 0x00000000);
999 nv_mthd(priv, 0xa097, 0x1cbc, 0x00000000);
1000 nv_mthd(priv, 0xa097, 0x1ccc, 0x00000000);
1001 nv_mthd(priv, 0xa097, 0x1cdc, 0x00000000);
1002 nv_mthd(priv, 0xa097, 0x1cec, 0x00000000);
1003 nv_mthd(priv, 0xa097, 0x1cfc, 0x00000000);
1004 nv_mthd(priv, 0xa097, 0x1d00, 0x00000000);
1005 nv_mthd(priv, 0xa097, 0x1d10, 0x00000000);
1006 nv_mthd(priv, 0xa097, 0x1d20, 0x00000000);
1007 nv_mthd(priv, 0xa097, 0x1d30, 0x00000000);
1008 nv_mthd(priv, 0xa097, 0x1d40, 0x00000000);
1009 nv_mthd(priv, 0xa097, 0x1d50, 0x00000000);
1010 nv_mthd(priv, 0xa097, 0x1d60, 0x00000000);
1011 nv_mthd(priv, 0xa097, 0x1d70, 0x00000000);
1012 nv_mthd(priv, 0xa097, 0x1d80, 0x00000000);
1013 nv_mthd(priv, 0xa097, 0x1d90, 0x00000000);
1014 nv_mthd(priv, 0xa097, 0x1da0, 0x00000000);
1015 nv_mthd(priv, 0xa097, 0x1db0, 0x00000000);
1016 nv_mthd(priv, 0xa097, 0x1dc0, 0x00000000);
1017 nv_mthd(priv, 0xa097, 0x1dd0, 0x00000000);
1018 nv_mthd(priv, 0xa097, 0x1de0, 0x00000000);
1019 nv_mthd(priv, 0xa097, 0x1df0, 0x00000000);
1020 nv_mthd(priv, 0xa097, 0x1d04, 0x00000000);
1021 nv_mthd(priv, 0xa097, 0x1d14, 0x00000000);
1022 nv_mthd(priv, 0xa097, 0x1d24, 0x00000000);
1023 nv_mthd(priv, 0xa097, 0x1d34, 0x00000000);
1024 nv_mthd(priv, 0xa097, 0x1d44, 0x00000000);
1025 nv_mthd(priv, 0xa097, 0x1d54, 0x00000000);
1026 nv_mthd(priv, 0xa097, 0x1d64, 0x00000000);
1027 nv_mthd(priv, 0xa097, 0x1d74, 0x00000000);
1028 nv_mthd(priv, 0xa097, 0x1d84, 0x00000000);
1029 nv_mthd(priv, 0xa097, 0x1d94, 0x00000000);
1030 nv_mthd(priv, 0xa097, 0x1da4, 0x00000000);
1031 nv_mthd(priv, 0xa097, 0x1db4, 0x00000000);
1032 nv_mthd(priv, 0xa097, 0x1dc4, 0x00000000);
1033 nv_mthd(priv, 0xa097, 0x1dd4, 0x00000000);
1034 nv_mthd(priv, 0xa097, 0x1de4, 0x00000000);
1035 nv_mthd(priv, 0xa097, 0x1df4, 0x00000000);
1036 nv_mthd(priv, 0xa097, 0x1d08, 0x00000000);
1037 nv_mthd(priv, 0xa097, 0x1d18, 0x00000000);
1038 nv_mthd(priv, 0xa097, 0x1d28, 0x00000000);
1039 nv_mthd(priv, 0xa097, 0x1d38, 0x00000000);
1040 nv_mthd(priv, 0xa097, 0x1d48, 0x00000000);
1041 nv_mthd(priv, 0xa097, 0x1d58, 0x00000000);
1042 nv_mthd(priv, 0xa097, 0x1d68, 0x00000000);
1043 nv_mthd(priv, 0xa097, 0x1d78, 0x00000000);
1044 nv_mthd(priv, 0xa097, 0x1d88, 0x00000000);
1045 nv_mthd(priv, 0xa097, 0x1d98, 0x00000000);
1046 nv_mthd(priv, 0xa097, 0x1da8, 0x00000000);
1047 nv_mthd(priv, 0xa097, 0x1db8, 0x00000000);
1048 nv_mthd(priv, 0xa097, 0x1dc8, 0x00000000);
1049 nv_mthd(priv, 0xa097, 0x1dd8, 0x00000000);
1050 nv_mthd(priv, 0xa097, 0x1de8, 0x00000000);
1051 nv_mthd(priv, 0xa097, 0x1df8, 0x00000000);
1052 nv_mthd(priv, 0xa097, 0x1d0c, 0x00000000);
1053 nv_mthd(priv, 0xa097, 0x1d1c, 0x00000000);
1054 nv_mthd(priv, 0xa097, 0x1d2c, 0x00000000);
1055 nv_mthd(priv, 0xa097, 0x1d3c, 0x00000000);
1056 nv_mthd(priv, 0xa097, 0x1d4c, 0x00000000);
1057 nv_mthd(priv, 0xa097, 0x1d5c, 0x00000000);
1058 nv_mthd(priv, 0xa097, 0x1d6c, 0x00000000);
1059 nv_mthd(priv, 0xa097, 0x1d7c, 0x00000000);
1060 nv_mthd(priv, 0xa097, 0x1d8c, 0x00000000);
1061 nv_mthd(priv, 0xa097, 0x1d9c, 0x00000000);
1062 nv_mthd(priv, 0xa097, 0x1dac, 0x00000000);
1063 nv_mthd(priv, 0xa097, 0x1dbc, 0x00000000);
1064 nv_mthd(priv, 0xa097, 0x1dcc, 0x00000000);
1065 nv_mthd(priv, 0xa097, 0x1ddc, 0x00000000);
1066 nv_mthd(priv, 0xa097, 0x1dec, 0x00000000);
1067 nv_mthd(priv, 0xa097, 0x1dfc, 0x00000000);
1068 nv_mthd(priv, 0xa097, 0x1f00, 0x00000000);
1069 nv_mthd(priv, 0xa097, 0x1f08, 0x00000000);
1070 nv_mthd(priv, 0xa097, 0x1f10, 0x00000000);
1071 nv_mthd(priv, 0xa097, 0x1f18, 0x00000000);
1072 nv_mthd(priv, 0xa097, 0x1f20, 0x00000000);
1073 nv_mthd(priv, 0xa097, 0x1f28, 0x00000000);
1074 nv_mthd(priv, 0xa097, 0x1f30, 0x00000000);
1075 nv_mthd(priv, 0xa097, 0x1f38, 0x00000000);
1076 nv_mthd(priv, 0xa097, 0x1f40, 0x00000000);
1077 nv_mthd(priv, 0xa097, 0x1f48, 0x00000000);
1078 nv_mthd(priv, 0xa097, 0x1f50, 0x00000000);
1079 nv_mthd(priv, 0xa097, 0x1f58, 0x00000000);
1080 nv_mthd(priv, 0xa097, 0x1f60, 0x00000000);
1081 nv_mthd(priv, 0xa097, 0x1f68, 0x00000000);
1082 nv_mthd(priv, 0xa097, 0x1f70, 0x00000000);
1083 nv_mthd(priv, 0xa097, 0x1f78, 0x00000000);
1084 nv_mthd(priv, 0xa097, 0x1f04, 0x00000000);
1085 nv_mthd(priv, 0xa097, 0x1f0c, 0x00000000);
1086 nv_mthd(priv, 0xa097, 0x1f14, 0x00000000);
1087 nv_mthd(priv, 0xa097, 0x1f1c, 0x00000000);
1088 nv_mthd(priv, 0xa097, 0x1f24, 0x00000000);
1089 nv_mthd(priv, 0xa097, 0x1f2c, 0x00000000);
1090 nv_mthd(priv, 0xa097, 0x1f34, 0x00000000);
1091 nv_mthd(priv, 0xa097, 0x1f3c, 0x00000000);
1092 nv_mthd(priv, 0xa097, 0x1f44, 0x00000000);
1093 nv_mthd(priv, 0xa097, 0x1f4c, 0x00000000);
1094 nv_mthd(priv, 0xa097, 0x1f54, 0x00000000);
1095 nv_mthd(priv, 0xa097, 0x1f5c, 0x00000000);
1096 nv_mthd(priv, 0xa097, 0x1f64, 0x00000000);
1097 nv_mthd(priv, 0xa097, 0x1f6c, 0x00000000);
1098 nv_mthd(priv, 0xa097, 0x1f74, 0x00000000);
1099 nv_mthd(priv, 0xa097, 0x1f7c, 0x00000000);
1100 nv_mthd(priv, 0xa097, 0x1f80, 0x00000000);
1101 nv_mthd(priv, 0xa097, 0x1f88, 0x00000000);
1102 nv_mthd(priv, 0xa097, 0x1f90, 0x00000000);
1103 nv_mthd(priv, 0xa097, 0x1f98, 0x00000000);
1104 nv_mthd(priv, 0xa097, 0x1fa0, 0x00000000);
1105 nv_mthd(priv, 0xa097, 0x1fa8, 0x00000000);
1106 nv_mthd(priv, 0xa097, 0x1fb0, 0x00000000);
1107 nv_mthd(priv, 0xa097, 0x1fb8, 0x00000000);
1108 nv_mthd(priv, 0xa097, 0x1fc0, 0x00000000);
1109 nv_mthd(priv, 0xa097, 0x1fc8, 0x00000000);
1110 nv_mthd(priv, 0xa097, 0x1fd0, 0x00000000);
1111 nv_mthd(priv, 0xa097, 0x1fd8, 0x00000000);
1112 nv_mthd(priv, 0xa097, 0x1fe0, 0x00000000);
1113 nv_mthd(priv, 0xa097, 0x1fe8, 0x00000000);
1114 nv_mthd(priv, 0xa097, 0x1ff0, 0x00000000);
1115 nv_mthd(priv, 0xa097, 0x1ff8, 0x00000000);
1116 nv_mthd(priv, 0xa097, 0x1f84, 0x00000000);
1117 nv_mthd(priv, 0xa097, 0x1f8c, 0x00000000);
1118 nv_mthd(priv, 0xa097, 0x1f94, 0x00000000);
1119 nv_mthd(priv, 0xa097, 0x1f9c, 0x00000000);
1120 nv_mthd(priv, 0xa097, 0x1fa4, 0x00000000);
1121 nv_mthd(priv, 0xa097, 0x1fac, 0x00000000);
1122 nv_mthd(priv, 0xa097, 0x1fb4, 0x00000000);
1123 nv_mthd(priv, 0xa097, 0x1fbc, 0x00000000);
1124 nv_mthd(priv, 0xa097, 0x1fc4, 0x00000000);
1125 nv_mthd(priv, 0xa097, 0x1fcc, 0x00000000);
1126 nv_mthd(priv, 0xa097, 0x1fd4, 0x00000000);
1127 nv_mthd(priv, 0xa097, 0x1fdc, 0x00000000);
1128 nv_mthd(priv, 0xa097, 0x1fe4, 0x00000000);
1129 nv_mthd(priv, 0xa097, 0x1fec, 0x00000000);
1130 nv_mthd(priv, 0xa097, 0x1ff4, 0x00000000);
1131 nv_mthd(priv, 0xa097, 0x1ffc, 0x00000000);
1132 nv_mthd(priv, 0xa097, 0x2000, 0x00000000);
1133 nv_mthd(priv, 0xa097, 0x2040, 0x00000011);
1134 nv_mthd(priv, 0xa097, 0x2080, 0x00000020);
1135 nv_mthd(priv, 0xa097, 0x20c0, 0x00000030);
1136 nv_mthd(priv, 0xa097, 0x2100, 0x00000040);
1137 nv_mthd(priv, 0xa097, 0x2140, 0x00000051);
1138 nv_mthd(priv, 0xa097, 0x200c, 0x00000001);
1139 nv_mthd(priv, 0xa097, 0x204c, 0x00000001);
1140 nv_mthd(priv, 0xa097, 0x208c, 0x00000001);
1141 nv_mthd(priv, 0xa097, 0x20cc, 0x00000001);
1142 nv_mthd(priv, 0xa097, 0x210c, 0x00000001);
1143 nv_mthd(priv, 0xa097, 0x214c, 0x00000001);
1144 nv_mthd(priv, 0xa097, 0x2010, 0x00000000);
1145 nv_mthd(priv, 0xa097, 0x2050, 0x00000000);
1146 nv_mthd(priv, 0xa097, 0x2090, 0x00000001);
1147 nv_mthd(priv, 0xa097, 0x20d0, 0x00000002);
1148 nv_mthd(priv, 0xa097, 0x2110, 0x00000003);
1149 nv_mthd(priv, 0xa097, 0x2150, 0x00000004);
1150 nv_mthd(priv, 0xa097, 0x0380, 0x00000000);
1151 nv_mthd(priv, 0xa097, 0x03a0, 0x00000000);
1152 nv_mthd(priv, 0xa097, 0x03c0, 0x00000000);
1153 nv_mthd(priv, 0xa097, 0x03e0, 0x00000000);
1154 nv_mthd(priv, 0xa097, 0x0384, 0x00000000);
1155 nv_mthd(priv, 0xa097, 0x03a4, 0x00000000);
1156 nv_mthd(priv, 0xa097, 0x03c4, 0x00000000);
1157 nv_mthd(priv, 0xa097, 0x03e4, 0x00000000);
1158 nv_mthd(priv, 0xa097, 0x0388, 0x00000000);
1159 nv_mthd(priv, 0xa097, 0x03a8, 0x00000000);
1160 nv_mthd(priv, 0xa097, 0x03c8, 0x00000000);
1161 nv_mthd(priv, 0xa097, 0x03e8, 0x00000000);
1162 nv_mthd(priv, 0xa097, 0x038c, 0x00000000);
1163 nv_mthd(priv, 0xa097, 0x03ac, 0x00000000);
1164 nv_mthd(priv, 0xa097, 0x03cc, 0x00000000);
1165 nv_mthd(priv, 0xa097, 0x03ec, 0x00000000);
1166 nv_mthd(priv, 0xa097, 0x0700, 0x00000000);
1167 nv_mthd(priv, 0xa097, 0x0710, 0x00000000);
1168 nv_mthd(priv, 0xa097, 0x0720, 0x00000000);
1169 nv_mthd(priv, 0xa097, 0x0730, 0x00000000);
1170 nv_mthd(priv, 0xa097, 0x0704, 0x00000000);
1171 nv_mthd(priv, 0xa097, 0x0714, 0x00000000);
1172 nv_mthd(priv, 0xa097, 0x0724, 0x00000000);
1173 nv_mthd(priv, 0xa097, 0x0734, 0x00000000);
1174 nv_mthd(priv, 0xa097, 0x0708, 0x00000000);
1175 nv_mthd(priv, 0xa097, 0x0718, 0x00000000);
1176 nv_mthd(priv, 0xa097, 0x0728, 0x00000000);
1177 nv_mthd(priv, 0xa097, 0x0738, 0x00000000);
1178 nv_mthd(priv, 0xa097, 0x2800, 0x00000000);
1179 nv_mthd(priv, 0xa097, 0x2804, 0x00000000);
1180 nv_mthd(priv, 0xa097, 0x2808, 0x00000000);
1181 nv_mthd(priv, 0xa097, 0x280c, 0x00000000);
1182 nv_mthd(priv, 0xa097, 0x2810, 0x00000000);
1183 nv_mthd(priv, 0xa097, 0x2814, 0x00000000);
1184 nv_mthd(priv, 0xa097, 0x2818, 0x00000000);
1185 nv_mthd(priv, 0xa097, 0x281c, 0x00000000);
1186 nv_mthd(priv, 0xa097, 0x2820, 0x00000000);
1187 nv_mthd(priv, 0xa097, 0x2824, 0x00000000);
1188 nv_mthd(priv, 0xa097, 0x2828, 0x00000000);
1189 nv_mthd(priv, 0xa097, 0x282c, 0x00000000);
1190 nv_mthd(priv, 0xa097, 0x2830, 0x00000000);
1191 nv_mthd(priv, 0xa097, 0x2834, 0x00000000);
1192 nv_mthd(priv, 0xa097, 0x2838, 0x00000000);
1193 nv_mthd(priv, 0xa097, 0x283c, 0x00000000);
1194 nv_mthd(priv, 0xa097, 0x2840, 0x00000000);
1195 nv_mthd(priv, 0xa097, 0x2844, 0x00000000);
1196 nv_mthd(priv, 0xa097, 0x2848, 0x00000000);
1197 nv_mthd(priv, 0xa097, 0x284c, 0x00000000);
1198 nv_mthd(priv, 0xa097, 0x2850, 0x00000000);
1199 nv_mthd(priv, 0xa097, 0x2854, 0x00000000);
1200 nv_mthd(priv, 0xa097, 0x2858, 0x00000000);
1201 nv_mthd(priv, 0xa097, 0x285c, 0x00000000);
1202 nv_mthd(priv, 0xa097, 0x2860, 0x00000000);
1203 nv_mthd(priv, 0xa097, 0x2864, 0x00000000);
1204 nv_mthd(priv, 0xa097, 0x2868, 0x00000000);
1205 nv_mthd(priv, 0xa097, 0x286c, 0x00000000);
1206 nv_mthd(priv, 0xa097, 0x2870, 0x00000000);
1207 nv_mthd(priv, 0xa097, 0x2874, 0x00000000);
1208 nv_mthd(priv, 0xa097, 0x2878, 0x00000000);
1209 nv_mthd(priv, 0xa097, 0x287c, 0x00000000);
1210 nv_mthd(priv, 0xa097, 0x2880, 0x00000000);
1211 nv_mthd(priv, 0xa097, 0x2884, 0x00000000);
1212 nv_mthd(priv, 0xa097, 0x2888, 0x00000000);
1213 nv_mthd(priv, 0xa097, 0x288c, 0x00000000);
1214 nv_mthd(priv, 0xa097, 0x2890, 0x00000000);
1215 nv_mthd(priv, 0xa097, 0x2894, 0x00000000);
1216 nv_mthd(priv, 0xa097, 0x2898, 0x00000000);
1217 nv_mthd(priv, 0xa097, 0x289c, 0x00000000);
1218 nv_mthd(priv, 0xa097, 0x28a0, 0x00000000);
1219 nv_mthd(priv, 0xa097, 0x28a4, 0x00000000);
1220 nv_mthd(priv, 0xa097, 0x28a8, 0x00000000);
1221 nv_mthd(priv, 0xa097, 0x28ac, 0x00000000);
1222 nv_mthd(priv, 0xa097, 0x28b0, 0x00000000);
1223 nv_mthd(priv, 0xa097, 0x28b4, 0x00000000);
1224 nv_mthd(priv, 0xa097, 0x28b8, 0x00000000);
1225 nv_mthd(priv, 0xa097, 0x28bc, 0x00000000);
1226 nv_mthd(priv, 0xa097, 0x28c0, 0x00000000);
1227 nv_mthd(priv, 0xa097, 0x28c4, 0x00000000);
1228 nv_mthd(priv, 0xa097, 0x28c8, 0x00000000);
1229 nv_mthd(priv, 0xa097, 0x28cc, 0x00000000);
1230 nv_mthd(priv, 0xa097, 0x28d0, 0x00000000);
1231 nv_mthd(priv, 0xa097, 0x28d4, 0x00000000);
1232 nv_mthd(priv, 0xa097, 0x28d8, 0x00000000);
1233 nv_mthd(priv, 0xa097, 0x28dc, 0x00000000);
1234 nv_mthd(priv, 0xa097, 0x28e0, 0x00000000);
1235 nv_mthd(priv, 0xa097, 0x28e4, 0x00000000);
1236 nv_mthd(priv, 0xa097, 0x28e8, 0x00000000);
1237 nv_mthd(priv, 0xa097, 0x28ec, 0x00000000);
1238 nv_mthd(priv, 0xa097, 0x28f0, 0x00000000);
1239 nv_mthd(priv, 0xa097, 0x28f4, 0x00000000);
1240 nv_mthd(priv, 0xa097, 0x28f8, 0x00000000);
1241 nv_mthd(priv, 0xa097, 0x28fc, 0x00000000);
1242 nv_mthd(priv, 0xa097, 0x2900, 0x00000000);
1243 nv_mthd(priv, 0xa097, 0x2904, 0x00000000);
1244 nv_mthd(priv, 0xa097, 0x2908, 0x00000000);
1245 nv_mthd(priv, 0xa097, 0x290c, 0x00000000);
1246 nv_mthd(priv, 0xa097, 0x2910, 0x00000000);
1247 nv_mthd(priv, 0xa097, 0x2914, 0x00000000);
1248 nv_mthd(priv, 0xa097, 0x2918, 0x00000000);
1249 nv_mthd(priv, 0xa097, 0x291c, 0x00000000);
1250 nv_mthd(priv, 0xa097, 0x2920, 0x00000000);
1251 nv_mthd(priv, 0xa097, 0x2924, 0x00000000);
1252 nv_mthd(priv, 0xa097, 0x2928, 0x00000000);
1253 nv_mthd(priv, 0xa097, 0x292c, 0x00000000);
1254 nv_mthd(priv, 0xa097, 0x2930, 0x00000000);
1255 nv_mthd(priv, 0xa097, 0x2934, 0x00000000);
1256 nv_mthd(priv, 0xa097, 0x2938, 0x00000000);
1257 nv_mthd(priv, 0xa097, 0x293c, 0x00000000);
1258 nv_mthd(priv, 0xa097, 0x2940, 0x00000000);
1259 nv_mthd(priv, 0xa097, 0x2944, 0x00000000);
1260 nv_mthd(priv, 0xa097, 0x2948, 0x00000000);
1261 nv_mthd(priv, 0xa097, 0x294c, 0x00000000);
1262 nv_mthd(priv, 0xa097, 0x2950, 0x00000000);
1263 nv_mthd(priv, 0xa097, 0x2954, 0x00000000);
1264 nv_mthd(priv, 0xa097, 0x2958, 0x00000000);
1265 nv_mthd(priv, 0xa097, 0x295c, 0x00000000);
1266 nv_mthd(priv, 0xa097, 0x2960, 0x00000000);
1267 nv_mthd(priv, 0xa097, 0x2964, 0x00000000);
1268 nv_mthd(priv, 0xa097, 0x2968, 0x00000000);
1269 nv_mthd(priv, 0xa097, 0x296c, 0x00000000);
1270 nv_mthd(priv, 0xa097, 0x2970, 0x00000000);
1271 nv_mthd(priv, 0xa097, 0x2974, 0x00000000);
1272 nv_mthd(priv, 0xa097, 0x2978, 0x00000000);
1273 nv_mthd(priv, 0xa097, 0x297c, 0x00000000);
1274 nv_mthd(priv, 0xa097, 0x2980, 0x00000000);
1275 nv_mthd(priv, 0xa097, 0x2984, 0x00000000);
1276 nv_mthd(priv, 0xa097, 0x2988, 0x00000000);
1277 nv_mthd(priv, 0xa097, 0x298c, 0x00000000);
1278 nv_mthd(priv, 0xa097, 0x2990, 0x00000000);
1279 nv_mthd(priv, 0xa097, 0x2994, 0x00000000);
1280 nv_mthd(priv, 0xa097, 0x2998, 0x00000000);
1281 nv_mthd(priv, 0xa097, 0x299c, 0x00000000);
1282 nv_mthd(priv, 0xa097, 0x29a0, 0x00000000);
1283 nv_mthd(priv, 0xa097, 0x29a4, 0x00000000);
1284 nv_mthd(priv, 0xa097, 0x29a8, 0x00000000);
1285 nv_mthd(priv, 0xa097, 0x29ac, 0x00000000);
1286 nv_mthd(priv, 0xa097, 0x29b0, 0x00000000);
1287 nv_mthd(priv, 0xa097, 0x29b4, 0x00000000);
1288 nv_mthd(priv, 0xa097, 0x29b8, 0x00000000);
1289 nv_mthd(priv, 0xa097, 0x29bc, 0x00000000);
1290 nv_mthd(priv, 0xa097, 0x29c0, 0x00000000);
1291 nv_mthd(priv, 0xa097, 0x29c4, 0x00000000);
1292 nv_mthd(priv, 0xa097, 0x29c8, 0x00000000);
1293 nv_mthd(priv, 0xa097, 0x29cc, 0x00000000);
1294 nv_mthd(priv, 0xa097, 0x29d0, 0x00000000);
1295 nv_mthd(priv, 0xa097, 0x29d4, 0x00000000);
1296 nv_mthd(priv, 0xa097, 0x29d8, 0x00000000);
1297 nv_mthd(priv, 0xa097, 0x29dc, 0x00000000);
1298 nv_mthd(priv, 0xa097, 0x29e0, 0x00000000);
1299 nv_mthd(priv, 0xa097, 0x29e4, 0x00000000);
1300 nv_mthd(priv, 0xa097, 0x29e8, 0x00000000);
1301 nv_mthd(priv, 0xa097, 0x29ec, 0x00000000);
1302 nv_mthd(priv, 0xa097, 0x29f0, 0x00000000);
1303 nv_mthd(priv, 0xa097, 0x29f4, 0x00000000);
1304 nv_mthd(priv, 0xa097, 0x29f8, 0x00000000);
1305 nv_mthd(priv, 0xa097, 0x29fc, 0x00000000);
1306 nv_mthd(priv, 0xa097, 0x0a00, 0x00000000);
1307 nv_mthd(priv, 0xa097, 0x0a20, 0x00000000);
1308 nv_mthd(priv, 0xa097, 0x0a40, 0x00000000);
1309 nv_mthd(priv, 0xa097, 0x0a60, 0x00000000);
1310 nv_mthd(priv, 0xa097, 0x0a80, 0x00000000);
1311 nv_mthd(priv, 0xa097, 0x0aa0, 0x00000000);
1312 nv_mthd(priv, 0xa097, 0x0ac0, 0x00000000);
1313 nv_mthd(priv, 0xa097, 0x0ae0, 0x00000000);
1314 nv_mthd(priv, 0xa097, 0x0b00, 0x00000000);
1315 nv_mthd(priv, 0xa097, 0x0b20, 0x00000000);
1316 nv_mthd(priv, 0xa097, 0x0b40, 0x00000000);
1317 nv_mthd(priv, 0xa097, 0x0b60, 0x00000000);
1318 nv_mthd(priv, 0xa097, 0x0b80, 0x00000000);
1319 nv_mthd(priv, 0xa097, 0x0ba0, 0x00000000);
1320 nv_mthd(priv, 0xa097, 0x0bc0, 0x00000000);
1321 nv_mthd(priv, 0xa097, 0x0be0, 0x00000000);
1322 nv_mthd(priv, 0xa097, 0x0a04, 0x00000000);
1323 nv_mthd(priv, 0xa097, 0x0a24, 0x00000000);
1324 nv_mthd(priv, 0xa097, 0x0a44, 0x00000000);
1325 nv_mthd(priv, 0xa097, 0x0a64, 0x00000000);
1326 nv_mthd(priv, 0xa097, 0x0a84, 0x00000000);
1327 nv_mthd(priv, 0xa097, 0x0aa4, 0x00000000);
1328 nv_mthd(priv, 0xa097, 0x0ac4, 0x00000000);
1329 nv_mthd(priv, 0xa097, 0x0ae4, 0x00000000);
1330 nv_mthd(priv, 0xa097, 0x0b04, 0x00000000);
1331 nv_mthd(priv, 0xa097, 0x0b24, 0x00000000);
1332 nv_mthd(priv, 0xa097, 0x0b44, 0x00000000);
1333 nv_mthd(priv, 0xa097, 0x0b64, 0x00000000);
1334 nv_mthd(priv, 0xa097, 0x0b84, 0x00000000);
1335 nv_mthd(priv, 0xa097, 0x0ba4, 0x00000000);
1336 nv_mthd(priv, 0xa097, 0x0bc4, 0x00000000);
1337 nv_mthd(priv, 0xa097, 0x0be4, 0x00000000);
1338 nv_mthd(priv, 0xa097, 0x0a08, 0x00000000);
1339 nv_mthd(priv, 0xa097, 0x0a28, 0x00000000);
1340 nv_mthd(priv, 0xa097, 0x0a48, 0x00000000);
1341 nv_mthd(priv, 0xa097, 0x0a68, 0x00000000);
1342 nv_mthd(priv, 0xa097, 0x0a88, 0x00000000);
1343 nv_mthd(priv, 0xa097, 0x0aa8, 0x00000000);
1344 nv_mthd(priv, 0xa097, 0x0ac8, 0x00000000);
1345 nv_mthd(priv, 0xa097, 0x0ae8, 0x00000000);
1346 nv_mthd(priv, 0xa097, 0x0b08, 0x00000000);
1347 nv_mthd(priv, 0xa097, 0x0b28, 0x00000000);
1348 nv_mthd(priv, 0xa097, 0x0b48, 0x00000000);
1349 nv_mthd(priv, 0xa097, 0x0b68, 0x00000000);
1350 nv_mthd(priv, 0xa097, 0x0b88, 0x00000000);
1351 nv_mthd(priv, 0xa097, 0x0ba8, 0x00000000);
1352 nv_mthd(priv, 0xa097, 0x0bc8, 0x00000000);
1353 nv_mthd(priv, 0xa097, 0x0be8, 0x00000000);
1354 nv_mthd(priv, 0xa097, 0x0a0c, 0x00000000);
1355 nv_mthd(priv, 0xa097, 0x0a2c, 0x00000000);
1356 nv_mthd(priv, 0xa097, 0x0a4c, 0x00000000);
1357 nv_mthd(priv, 0xa097, 0x0a6c, 0x00000000);
1358 nv_mthd(priv, 0xa097, 0x0a8c, 0x00000000);
1359 nv_mthd(priv, 0xa097, 0x0aac, 0x00000000);
1360 nv_mthd(priv, 0xa097, 0x0acc, 0x00000000);
1361 nv_mthd(priv, 0xa097, 0x0aec, 0x00000000);
1362 nv_mthd(priv, 0xa097, 0x0b0c, 0x00000000);
1363 nv_mthd(priv, 0xa097, 0x0b2c, 0x00000000);
1364 nv_mthd(priv, 0xa097, 0x0b4c, 0x00000000);
1365 nv_mthd(priv, 0xa097, 0x0b6c, 0x00000000);
1366 nv_mthd(priv, 0xa097, 0x0b8c, 0x00000000);
1367 nv_mthd(priv, 0xa097, 0x0bac, 0x00000000);
1368 nv_mthd(priv, 0xa097, 0x0bcc, 0x00000000);
1369 nv_mthd(priv, 0xa097, 0x0bec, 0x00000000);
1370 nv_mthd(priv, 0xa097, 0x0a10, 0x00000000);
1371 nv_mthd(priv, 0xa097, 0x0a30, 0x00000000);
1372 nv_mthd(priv, 0xa097, 0x0a50, 0x00000000);
1373 nv_mthd(priv, 0xa097, 0x0a70, 0x00000000);
1374 nv_mthd(priv, 0xa097, 0x0a90, 0x00000000);
1375 nv_mthd(priv, 0xa097, 0x0ab0, 0x00000000);
1376 nv_mthd(priv, 0xa097, 0x0ad0, 0x00000000);
1377 nv_mthd(priv, 0xa097, 0x0af0, 0x00000000);
1378 nv_mthd(priv, 0xa097, 0x0b10, 0x00000000);
1379 nv_mthd(priv, 0xa097, 0x0b30, 0x00000000);
1380 nv_mthd(priv, 0xa097, 0x0b50, 0x00000000);
1381 nv_mthd(priv, 0xa097, 0x0b70, 0x00000000);
1382 nv_mthd(priv, 0xa097, 0x0b90, 0x00000000);
1383 nv_mthd(priv, 0xa097, 0x0bb0, 0x00000000);
1384 nv_mthd(priv, 0xa097, 0x0bd0, 0x00000000);
1385 nv_mthd(priv, 0xa097, 0x0bf0, 0x00000000);
1386 nv_mthd(priv, 0xa097, 0x0a14, 0x00000000);
1387 nv_mthd(priv, 0xa097, 0x0a34, 0x00000000);
1388 nv_mthd(priv, 0xa097, 0x0a54, 0x00000000);
1389 nv_mthd(priv, 0xa097, 0x0a74, 0x00000000);
1390 nv_mthd(priv, 0xa097, 0x0a94, 0x00000000);
1391 nv_mthd(priv, 0xa097, 0x0ab4, 0x00000000);
1392 nv_mthd(priv, 0xa097, 0x0ad4, 0x00000000);
1393 nv_mthd(priv, 0xa097, 0x0af4, 0x00000000);
1394 nv_mthd(priv, 0xa097, 0x0b14, 0x00000000);
1395 nv_mthd(priv, 0xa097, 0x0b34, 0x00000000);
1396 nv_mthd(priv, 0xa097, 0x0b54, 0x00000000);
1397 nv_mthd(priv, 0xa097, 0x0b74, 0x00000000);
1398 nv_mthd(priv, 0xa097, 0x0b94, 0x00000000);
1399 nv_mthd(priv, 0xa097, 0x0bb4, 0x00000000);
1400 nv_mthd(priv, 0xa097, 0x0bd4, 0x00000000);
1401 nv_mthd(priv, 0xa097, 0x0bf4, 0x00000000);
1402 nv_mthd(priv, 0xa097, 0x0c00, 0x00000000);
1403 nv_mthd(priv, 0xa097, 0x0c10, 0x00000000);
1404 nv_mthd(priv, 0xa097, 0x0c20, 0x00000000);
1405 nv_mthd(priv, 0xa097, 0x0c30, 0x00000000);
1406 nv_mthd(priv, 0xa097, 0x0c40, 0x00000000);
1407 nv_mthd(priv, 0xa097, 0x0c50, 0x00000000);
1408 nv_mthd(priv, 0xa097, 0x0c60, 0x00000000);
1409 nv_mthd(priv, 0xa097, 0x0c70, 0x00000000);
1410 nv_mthd(priv, 0xa097, 0x0c80, 0x00000000);
1411 nv_mthd(priv, 0xa097, 0x0c90, 0x00000000);
1412 nv_mthd(priv, 0xa097, 0x0ca0, 0x00000000);
1413 nv_mthd(priv, 0xa097, 0x0cb0, 0x00000000);
1414 nv_mthd(priv, 0xa097, 0x0cc0, 0x00000000);
1415 nv_mthd(priv, 0xa097, 0x0cd0, 0x00000000);
1416 nv_mthd(priv, 0xa097, 0x0ce0, 0x00000000);
1417 nv_mthd(priv, 0xa097, 0x0cf0, 0x00000000);
1418 nv_mthd(priv, 0xa097, 0x0c04, 0x00000000);
1419 nv_mthd(priv, 0xa097, 0x0c14, 0x00000000);
1420 nv_mthd(priv, 0xa097, 0x0c24, 0x00000000);
1421 nv_mthd(priv, 0xa097, 0x0c34, 0x00000000);
1422 nv_mthd(priv, 0xa097, 0x0c44, 0x00000000);
1423 nv_mthd(priv, 0xa097, 0x0c54, 0x00000000);
1424 nv_mthd(priv, 0xa097, 0x0c64, 0x00000000);
1425 nv_mthd(priv, 0xa097, 0x0c74, 0x00000000);
1426 nv_mthd(priv, 0xa097, 0x0c84, 0x00000000);
1427 nv_mthd(priv, 0xa097, 0x0c94, 0x00000000);
1428 nv_mthd(priv, 0xa097, 0x0ca4, 0x00000000);
1429 nv_mthd(priv, 0xa097, 0x0cb4, 0x00000000);
1430 nv_mthd(priv, 0xa097, 0x0cc4, 0x00000000);
1431 nv_mthd(priv, 0xa097, 0x0cd4, 0x00000000);
1432 nv_mthd(priv, 0xa097, 0x0ce4, 0x00000000);
1433 nv_mthd(priv, 0xa097, 0x0cf4, 0x00000000);
1434 nv_mthd(priv, 0xa097, 0x0c08, 0x00000000);
1435 nv_mthd(priv, 0xa097, 0x0c18, 0x00000000);
1436 nv_mthd(priv, 0xa097, 0x0c28, 0x00000000);
1437 nv_mthd(priv, 0xa097, 0x0c38, 0x00000000);
1438 nv_mthd(priv, 0xa097, 0x0c48, 0x00000000);
1439 nv_mthd(priv, 0xa097, 0x0c58, 0x00000000);
1440 nv_mthd(priv, 0xa097, 0x0c68, 0x00000000);
1441 nv_mthd(priv, 0xa097, 0x0c78, 0x00000000);
1442 nv_mthd(priv, 0xa097, 0x0c88, 0x00000000);
1443 nv_mthd(priv, 0xa097, 0x0c98, 0x00000000);
1444 nv_mthd(priv, 0xa097, 0x0ca8, 0x00000000);
1445 nv_mthd(priv, 0xa097, 0x0cb8, 0x00000000);
1446 nv_mthd(priv, 0xa097, 0x0cc8, 0x00000000);
1447 nv_mthd(priv, 0xa097, 0x0cd8, 0x00000000);
1448 nv_mthd(priv, 0xa097, 0x0ce8, 0x00000000);
1449 nv_mthd(priv, 0xa097, 0x0cf8, 0x00000000);
1450 nv_mthd(priv, 0xa097, 0x0c0c, 0x3f800000);
1451 nv_mthd(priv, 0xa097, 0x0c1c, 0x3f800000);
1452 nv_mthd(priv, 0xa097, 0x0c2c, 0x3f800000);
1453 nv_mthd(priv, 0xa097, 0x0c3c, 0x3f800000);
1454 nv_mthd(priv, 0xa097, 0x0c4c, 0x3f800000);
1455 nv_mthd(priv, 0xa097, 0x0c5c, 0x3f800000);
1456 nv_mthd(priv, 0xa097, 0x0c6c, 0x3f800000);
1457 nv_mthd(priv, 0xa097, 0x0c7c, 0x3f800000);
1458 nv_mthd(priv, 0xa097, 0x0c8c, 0x3f800000);
1459 nv_mthd(priv, 0xa097, 0x0c9c, 0x3f800000);
1460 nv_mthd(priv, 0xa097, 0x0cac, 0x3f800000);
1461 nv_mthd(priv, 0xa097, 0x0cbc, 0x3f800000);
1462 nv_mthd(priv, 0xa097, 0x0ccc, 0x3f800000);
1463 nv_mthd(priv, 0xa097, 0x0cdc, 0x3f800000);
1464 nv_mthd(priv, 0xa097, 0x0cec, 0x3f800000);
1465 nv_mthd(priv, 0xa097, 0x0cfc, 0x3f800000);
1466 nv_mthd(priv, 0xa097, 0x0d00, 0xffff0000);
1467 nv_mthd(priv, 0xa097, 0x0d08, 0xffff0000);
1468 nv_mthd(priv, 0xa097, 0x0d10, 0xffff0000);
1469 nv_mthd(priv, 0xa097, 0x0d18, 0xffff0000);
1470 nv_mthd(priv, 0xa097, 0x0d20, 0xffff0000);
1471 nv_mthd(priv, 0xa097, 0x0d28, 0xffff0000);
1472 nv_mthd(priv, 0xa097, 0x0d30, 0xffff0000);
1473 nv_mthd(priv, 0xa097, 0x0d38, 0xffff0000);
1474 nv_mthd(priv, 0xa097, 0x0d04, 0xffff0000);
1475 nv_mthd(priv, 0xa097, 0x0d0c, 0xffff0000);
1476 nv_mthd(priv, 0xa097, 0x0d14, 0xffff0000);
1477 nv_mthd(priv, 0xa097, 0x0d1c, 0xffff0000);
1478 nv_mthd(priv, 0xa097, 0x0d24, 0xffff0000);
1479 nv_mthd(priv, 0xa097, 0x0d2c, 0xffff0000);
1480 nv_mthd(priv, 0xa097, 0x0d34, 0xffff0000);
1481 nv_mthd(priv, 0xa097, 0x0d3c, 0xffff0000);
1482 nv_mthd(priv, 0xa097, 0x0e00, 0x00000000);
1483 nv_mthd(priv, 0xa097, 0x0e10, 0x00000000);
1484 nv_mthd(priv, 0xa097, 0x0e20, 0x00000000);
1485 nv_mthd(priv, 0xa097, 0x0e30, 0x00000000);
1486 nv_mthd(priv, 0xa097, 0x0e40, 0x00000000);
1487 nv_mthd(priv, 0xa097, 0x0e50, 0x00000000);
1488 nv_mthd(priv, 0xa097, 0x0e60, 0x00000000);
1489 nv_mthd(priv, 0xa097, 0x0e70, 0x00000000);
1490 nv_mthd(priv, 0xa097, 0x0e80, 0x00000000);
1491 nv_mthd(priv, 0xa097, 0x0e90, 0x00000000);
1492 nv_mthd(priv, 0xa097, 0x0ea0, 0x00000000);
1493 nv_mthd(priv, 0xa097, 0x0eb0, 0x00000000);
1494 nv_mthd(priv, 0xa097, 0x0ec0, 0x00000000);
1495 nv_mthd(priv, 0xa097, 0x0ed0, 0x00000000);
1496 nv_mthd(priv, 0xa097, 0x0ee0, 0x00000000);
1497 nv_mthd(priv, 0xa097, 0x0ef0, 0x00000000);
1498 nv_mthd(priv, 0xa097, 0x0e04, 0xffff0000);
1499 nv_mthd(priv, 0xa097, 0x0e14, 0xffff0000);
1500 nv_mthd(priv, 0xa097, 0x0e24, 0xffff0000);
1501 nv_mthd(priv, 0xa097, 0x0e34, 0xffff0000);
1502 nv_mthd(priv, 0xa097, 0x0e44, 0xffff0000);
1503 nv_mthd(priv, 0xa097, 0x0e54, 0xffff0000);
1504 nv_mthd(priv, 0xa097, 0x0e64, 0xffff0000);
1505 nv_mthd(priv, 0xa097, 0x0e74, 0xffff0000);
1506 nv_mthd(priv, 0xa097, 0x0e84, 0xffff0000);
1507 nv_mthd(priv, 0xa097, 0x0e94, 0xffff0000);
1508 nv_mthd(priv, 0xa097, 0x0ea4, 0xffff0000);
1509 nv_mthd(priv, 0xa097, 0x0eb4, 0xffff0000);
1510 nv_mthd(priv, 0xa097, 0x0ec4, 0xffff0000);
1511 nv_mthd(priv, 0xa097, 0x0ed4, 0xffff0000);
1512 nv_mthd(priv, 0xa097, 0x0ee4, 0xffff0000);
1513 nv_mthd(priv, 0xa097, 0x0ef4, 0xffff0000);
1514 nv_mthd(priv, 0xa097, 0x0e08, 0xffff0000);
1515 nv_mthd(priv, 0xa097, 0x0e18, 0xffff0000);
1516 nv_mthd(priv, 0xa097, 0x0e28, 0xffff0000);
1517 nv_mthd(priv, 0xa097, 0x0e38, 0xffff0000);
1518 nv_mthd(priv, 0xa097, 0x0e48, 0xffff0000);
1519 nv_mthd(priv, 0xa097, 0x0e58, 0xffff0000);
1520 nv_mthd(priv, 0xa097, 0x0e68, 0xffff0000);
1521 nv_mthd(priv, 0xa097, 0x0e78, 0xffff0000);
1522 nv_mthd(priv, 0xa097, 0x0e88, 0xffff0000);
1523 nv_mthd(priv, 0xa097, 0x0e98, 0xffff0000);
1524 nv_mthd(priv, 0xa097, 0x0ea8, 0xffff0000);
1525 nv_mthd(priv, 0xa097, 0x0eb8, 0xffff0000);
1526 nv_mthd(priv, 0xa097, 0x0ec8, 0xffff0000);
1527 nv_mthd(priv, 0xa097, 0x0ed8, 0xffff0000);
1528 nv_mthd(priv, 0xa097, 0x0ee8, 0xffff0000);
1529 nv_mthd(priv, 0xa097, 0x0ef8, 0xffff0000);
1530 nv_mthd(priv, 0xa097, 0x0d40, 0x00000000);
1531 nv_mthd(priv, 0xa097, 0x0d48, 0x00000000);
1532 nv_mthd(priv, 0xa097, 0x0d50, 0x00000000);
1533 nv_mthd(priv, 0xa097, 0x0d58, 0x00000000);
1534 nv_mthd(priv, 0xa097, 0x0d44, 0x00000000);
1535 nv_mthd(priv, 0xa097, 0x0d4c, 0x00000000);
1536 nv_mthd(priv, 0xa097, 0x0d54, 0x00000000);
1537 nv_mthd(priv, 0xa097, 0x0d5c, 0x00000000);
1538 nv_mthd(priv, 0xa097, 0x1e00, 0x00000001);
1539 nv_mthd(priv, 0xa097, 0x1e20, 0x00000001);
1540 nv_mthd(priv, 0xa097, 0x1e40, 0x00000001);
1541 nv_mthd(priv, 0xa097, 0x1e60, 0x00000001);
1542 nv_mthd(priv, 0xa097, 0x1e80, 0x00000001);
1543 nv_mthd(priv, 0xa097, 0x1ea0, 0x00000001);
1544 nv_mthd(priv, 0xa097, 0x1ec0, 0x00000001);
1545 nv_mthd(priv, 0xa097, 0x1ee0, 0x00000001);
1546 nv_mthd(priv, 0xa097, 0x1e04, 0x00000001);
1547 nv_mthd(priv, 0xa097, 0x1e24, 0x00000001);
1548 nv_mthd(priv, 0xa097, 0x1e44, 0x00000001);
1549 nv_mthd(priv, 0xa097, 0x1e64, 0x00000001);
1550 nv_mthd(priv, 0xa097, 0x1e84, 0x00000001);
1551 nv_mthd(priv, 0xa097, 0x1ea4, 0x00000001);
1552 nv_mthd(priv, 0xa097, 0x1ec4, 0x00000001);
1553 nv_mthd(priv, 0xa097, 0x1ee4, 0x00000001);
1554 nv_mthd(priv, 0xa097, 0x1e08, 0x00000002);
1555 nv_mthd(priv, 0xa097, 0x1e28, 0x00000002);
1556 nv_mthd(priv, 0xa097, 0x1e48, 0x00000002);
1557 nv_mthd(priv, 0xa097, 0x1e68, 0x00000002);
1558 nv_mthd(priv, 0xa097, 0x1e88, 0x00000002);
1559 nv_mthd(priv, 0xa097, 0x1ea8, 0x00000002);
1560 nv_mthd(priv, 0xa097, 0x1ec8, 0x00000002);
1561 nv_mthd(priv, 0xa097, 0x1ee8, 0x00000002);
1562 nv_mthd(priv, 0xa097, 0x1e0c, 0x00000001);
1563 nv_mthd(priv, 0xa097, 0x1e2c, 0x00000001);
1564 nv_mthd(priv, 0xa097, 0x1e4c, 0x00000001);
1565 nv_mthd(priv, 0xa097, 0x1e6c, 0x00000001);
1566 nv_mthd(priv, 0xa097, 0x1e8c, 0x00000001);
1567 nv_mthd(priv, 0xa097, 0x1eac, 0x00000001);
1568 nv_mthd(priv, 0xa097, 0x1ecc, 0x00000001);
1569 nv_mthd(priv, 0xa097, 0x1eec, 0x00000001);
1570 nv_mthd(priv, 0xa097, 0x1e10, 0x00000001);
1571 nv_mthd(priv, 0xa097, 0x1e30, 0x00000001);
1572 nv_mthd(priv, 0xa097, 0x1e50, 0x00000001);
1573 nv_mthd(priv, 0xa097, 0x1e70, 0x00000001);
1574 nv_mthd(priv, 0xa097, 0x1e90, 0x00000001);
1575 nv_mthd(priv, 0xa097, 0x1eb0, 0x00000001);
1576 nv_mthd(priv, 0xa097, 0x1ed0, 0x00000001);
1577 nv_mthd(priv, 0xa097, 0x1ef0, 0x00000001);
1578 nv_mthd(priv, 0xa097, 0x1e14, 0x00000002);
1579 nv_mthd(priv, 0xa097, 0x1e34, 0x00000002);
1580 nv_mthd(priv, 0xa097, 0x1e54, 0x00000002);
1581 nv_mthd(priv, 0xa097, 0x1e74, 0x00000002);
1582 nv_mthd(priv, 0xa097, 0x1e94, 0x00000002);
1583 nv_mthd(priv, 0xa097, 0x1eb4, 0x00000002);
1584 nv_mthd(priv, 0xa097, 0x1ed4, 0x00000002);
1585 nv_mthd(priv, 0xa097, 0x1ef4, 0x00000002);
1586 nv_mthd(priv, 0xa097, 0x1e18, 0x00000001);
1587 nv_mthd(priv, 0xa097, 0x1e38, 0x00000001);
1588 nv_mthd(priv, 0xa097, 0x1e58, 0x00000001);
1589 nv_mthd(priv, 0xa097, 0x1e78, 0x00000001);
1590 nv_mthd(priv, 0xa097, 0x1e98, 0x00000001);
1591 nv_mthd(priv, 0xa097, 0x1eb8, 0x00000001);
1592 nv_mthd(priv, 0xa097, 0x1ed8, 0x00000001);
1593 nv_mthd(priv, 0xa097, 0x1ef8, 0x00000001);
1594 nv_mthd(priv, 0xa097, 0x3400, 0x00000000);
1595 nv_mthd(priv, 0xa097, 0x3404, 0x00000000);
1596 nv_mthd(priv, 0xa097, 0x3408, 0x00000000);
1597 nv_mthd(priv, 0xa097, 0x340c, 0x00000000);
1598 nv_mthd(priv, 0xa097, 0x3410, 0x00000000);
1599 nv_mthd(priv, 0xa097, 0x3414, 0x00000000);
1600 nv_mthd(priv, 0xa097, 0x3418, 0x00000000);
1601 nv_mthd(priv, 0xa097, 0x341c, 0x00000000);
1602 nv_mthd(priv, 0xa097, 0x3420, 0x00000000);
1603 nv_mthd(priv, 0xa097, 0x3424, 0x00000000);
1604 nv_mthd(priv, 0xa097, 0x3428, 0x00000000);
1605 nv_mthd(priv, 0xa097, 0x342c, 0x00000000);
1606 nv_mthd(priv, 0xa097, 0x3430, 0x00000000);
1607 nv_mthd(priv, 0xa097, 0x3434, 0x00000000);
1608 nv_mthd(priv, 0xa097, 0x3438, 0x00000000);
1609 nv_mthd(priv, 0xa097, 0x343c, 0x00000000);
1610 nv_mthd(priv, 0xa097, 0x3440, 0x00000000);
1611 nv_mthd(priv, 0xa097, 0x3444, 0x00000000);
1612 nv_mthd(priv, 0xa097, 0x3448, 0x00000000);
1613 nv_mthd(priv, 0xa097, 0x344c, 0x00000000);
1614 nv_mthd(priv, 0xa097, 0x3450, 0x00000000);
1615 nv_mthd(priv, 0xa097, 0x3454, 0x00000000);
1616 nv_mthd(priv, 0xa097, 0x3458, 0x00000000);
1617 nv_mthd(priv, 0xa097, 0x345c, 0x00000000);
1618 nv_mthd(priv, 0xa097, 0x3460, 0x00000000);
1619 nv_mthd(priv, 0xa097, 0x3464, 0x00000000);
1620 nv_mthd(priv, 0xa097, 0x3468, 0x00000000);
1621 nv_mthd(priv, 0xa097, 0x346c, 0x00000000);
1622 nv_mthd(priv, 0xa097, 0x3470, 0x00000000);
1623 nv_mthd(priv, 0xa097, 0x3474, 0x00000000);
1624 nv_mthd(priv, 0xa097, 0x3478, 0x00000000);
1625 nv_mthd(priv, 0xa097, 0x347c, 0x00000000);
1626 nv_mthd(priv, 0xa097, 0x3480, 0x00000000);
1627 nv_mthd(priv, 0xa097, 0x3484, 0x00000000);
1628 nv_mthd(priv, 0xa097, 0x3488, 0x00000000);
1629 nv_mthd(priv, 0xa097, 0x348c, 0x00000000);
1630 nv_mthd(priv, 0xa097, 0x3490, 0x00000000);
1631 nv_mthd(priv, 0xa097, 0x3494, 0x00000000);
1632 nv_mthd(priv, 0xa097, 0x3498, 0x00000000);
1633 nv_mthd(priv, 0xa097, 0x349c, 0x00000000);
1634 nv_mthd(priv, 0xa097, 0x34a0, 0x00000000);
1635 nv_mthd(priv, 0xa097, 0x34a4, 0x00000000);
1636 nv_mthd(priv, 0xa097, 0x34a8, 0x00000000);
1637 nv_mthd(priv, 0xa097, 0x34ac, 0x00000000);
1638 nv_mthd(priv, 0xa097, 0x34b0, 0x00000000);
1639 nv_mthd(priv, 0xa097, 0x34b4, 0x00000000);
1640 nv_mthd(priv, 0xa097, 0x34b8, 0x00000000);
1641 nv_mthd(priv, 0xa097, 0x34bc, 0x00000000);
1642 nv_mthd(priv, 0xa097, 0x34c0, 0x00000000);
1643 nv_mthd(priv, 0xa097, 0x34c4, 0x00000000);
1644 nv_mthd(priv, 0xa097, 0x34c8, 0x00000000);
1645 nv_mthd(priv, 0xa097, 0x34cc, 0x00000000);
1646 nv_mthd(priv, 0xa097, 0x34d0, 0x00000000);
1647 nv_mthd(priv, 0xa097, 0x34d4, 0x00000000);
1648 nv_mthd(priv, 0xa097, 0x34d8, 0x00000000);
1649 nv_mthd(priv, 0xa097, 0x34dc, 0x00000000);
1650 nv_mthd(priv, 0xa097, 0x34e0, 0x00000000);
1651 nv_mthd(priv, 0xa097, 0x34e4, 0x00000000);
1652 nv_mthd(priv, 0xa097, 0x34e8, 0x00000000);
1653 nv_mthd(priv, 0xa097, 0x34ec, 0x00000000);
1654 nv_mthd(priv, 0xa097, 0x34f0, 0x00000000);
1655 nv_mthd(priv, 0xa097, 0x34f4, 0x00000000);
1656 nv_mthd(priv, 0xa097, 0x34f8, 0x00000000);
1657 nv_mthd(priv, 0xa097, 0x34fc, 0x00000000);
1658 nv_mthd(priv, 0xa097, 0x3500, 0x00000000);
1659 nv_mthd(priv, 0xa097, 0x3504, 0x00000000);
1660 nv_mthd(priv, 0xa097, 0x3508, 0x00000000);
1661 nv_mthd(priv, 0xa097, 0x350c, 0x00000000);
1662 nv_mthd(priv, 0xa097, 0x3510, 0x00000000);
1663 nv_mthd(priv, 0xa097, 0x3514, 0x00000000);
1664 nv_mthd(priv, 0xa097, 0x3518, 0x00000000);
1665 nv_mthd(priv, 0xa097, 0x351c, 0x00000000);
1666 nv_mthd(priv, 0xa097, 0x3520, 0x00000000);
1667 nv_mthd(priv, 0xa097, 0x3524, 0x00000000);
1668 nv_mthd(priv, 0xa097, 0x3528, 0x00000000);
1669 nv_mthd(priv, 0xa097, 0x352c, 0x00000000);
1670 nv_mthd(priv, 0xa097, 0x3530, 0x00000000);
1671 nv_mthd(priv, 0xa097, 0x3534, 0x00000000);
1672 nv_mthd(priv, 0xa097, 0x3538, 0x00000000);
1673 nv_mthd(priv, 0xa097, 0x353c, 0x00000000);
1674 nv_mthd(priv, 0xa097, 0x3540, 0x00000000);
1675 nv_mthd(priv, 0xa097, 0x3544, 0x00000000);
1676 nv_mthd(priv, 0xa097, 0x3548, 0x00000000);
1677 nv_mthd(priv, 0xa097, 0x354c, 0x00000000);
1678 nv_mthd(priv, 0xa097, 0x3550, 0x00000000);
1679 nv_mthd(priv, 0xa097, 0x3554, 0x00000000);
1680 nv_mthd(priv, 0xa097, 0x3558, 0x00000000);
1681 nv_mthd(priv, 0xa097, 0x355c, 0x00000000);
1682 nv_mthd(priv, 0xa097, 0x3560, 0x00000000);
1683 nv_mthd(priv, 0xa097, 0x3564, 0x00000000);
1684 nv_mthd(priv, 0xa097, 0x3568, 0x00000000);
1685 nv_mthd(priv, 0xa097, 0x356c, 0x00000000);
1686 nv_mthd(priv, 0xa097, 0x3570, 0x00000000);
1687 nv_mthd(priv, 0xa097, 0x3574, 0x00000000);
1688 nv_mthd(priv, 0xa097, 0x3578, 0x00000000);
1689 nv_mthd(priv, 0xa097, 0x357c, 0x00000000);
1690 nv_mthd(priv, 0xa097, 0x3580, 0x00000000);
1691 nv_mthd(priv, 0xa097, 0x3584, 0x00000000);
1692 nv_mthd(priv, 0xa097, 0x3588, 0x00000000);
1693 nv_mthd(priv, 0xa097, 0x358c, 0x00000000);
1694 nv_mthd(priv, 0xa097, 0x3590, 0x00000000);
1695 nv_mthd(priv, 0xa097, 0x3594, 0x00000000);
1696 nv_mthd(priv, 0xa097, 0x3598, 0x00000000);
1697 nv_mthd(priv, 0xa097, 0x359c, 0x00000000);
1698 nv_mthd(priv, 0xa097, 0x35a0, 0x00000000);
1699 nv_mthd(priv, 0xa097, 0x35a4, 0x00000000);
1700 nv_mthd(priv, 0xa097, 0x35a8, 0x00000000);
1701 nv_mthd(priv, 0xa097, 0x35ac, 0x00000000);
1702 nv_mthd(priv, 0xa097, 0x35b0, 0x00000000);
1703 nv_mthd(priv, 0xa097, 0x35b4, 0x00000000);
1704 nv_mthd(priv, 0xa097, 0x35b8, 0x00000000);
1705 nv_mthd(priv, 0xa097, 0x35bc, 0x00000000);
1706 nv_mthd(priv, 0xa097, 0x35c0, 0x00000000);
1707 nv_mthd(priv, 0xa097, 0x35c4, 0x00000000);
1708 nv_mthd(priv, 0xa097, 0x35c8, 0x00000000);
1709 nv_mthd(priv, 0xa097, 0x35cc, 0x00000000);
1710 nv_mthd(priv, 0xa097, 0x35d0, 0x00000000);
1711 nv_mthd(priv, 0xa097, 0x35d4, 0x00000000);
1712 nv_mthd(priv, 0xa097, 0x35d8, 0x00000000);
1713 nv_mthd(priv, 0xa097, 0x35dc, 0x00000000);
1714 nv_mthd(priv, 0xa097, 0x35e0, 0x00000000);
1715 nv_mthd(priv, 0xa097, 0x35e4, 0x00000000);
1716 nv_mthd(priv, 0xa097, 0x35e8, 0x00000000);
1717 nv_mthd(priv, 0xa097, 0x35ec, 0x00000000);
1718 nv_mthd(priv, 0xa097, 0x35f0, 0x00000000);
1719 nv_mthd(priv, 0xa097, 0x35f4, 0x00000000);
1720 nv_mthd(priv, 0xa097, 0x35f8, 0x00000000);
1721 nv_mthd(priv, 0xa097, 0x35fc, 0x00000000);
1722 nv_mthd(priv, 0xa097, 0x030c, 0x00000001);
1723 nv_mthd(priv, 0xa097, 0x1944, 0x00000000);
1724 nv_mthd(priv, 0xa097, 0x1514, 0x00000000);
1725 nv_mthd(priv, 0xa097, 0x0d68, 0x0000ffff);
1726 nv_mthd(priv, 0xa097, 0x121c, 0x0fac6881);
1727 nv_mthd(priv, 0xa097, 0x0fac, 0x00000001);
1728 nv_mthd(priv, 0xa097, 0x1538, 0x00000001);
1729 nv_mthd(priv, 0xa097, 0x0fe0, 0x00000000);
1730 nv_mthd(priv, 0xa097, 0x0fe4, 0x00000000);
1731 nv_mthd(priv, 0xa097, 0x0fe8, 0x00000014);
1732 nv_mthd(priv, 0xa097, 0x0fec, 0x00000040);
1733 nv_mthd(priv, 0xa097, 0x0ff0, 0x00000000);
1734 nv_mthd(priv, 0xa097, 0x179c, 0x00000000);
1735 nv_mthd(priv, 0xa097, 0x1228, 0x00000400);
1736 nv_mthd(priv, 0xa097, 0x122c, 0x00000300);
1737 nv_mthd(priv, 0xa097, 0x1230, 0x00010001);
1738 nv_mthd(priv, 0xa097, 0x07f8, 0x00000000);
1739 nv_mthd(priv, 0xa097, 0x15b4, 0x00000001);
1740 nv_mthd(priv, 0xa097, 0x15cc, 0x00000000);
1741 nv_mthd(priv, 0xa097, 0x1534, 0x00000000);
1742 nv_mthd(priv, 0xa097, 0x0fb0, 0x00000000);
1743 nv_mthd(priv, 0xa097, 0x15d0, 0x00000000);
1744 nv_mthd(priv, 0xa097, 0x153c, 0x00000000);
1745 nv_mthd(priv, 0xa097, 0x16b4, 0x00000003);
1746 nv_mthd(priv, 0xa097, 0x0fbc, 0x0000ffff);
1747 nv_mthd(priv, 0xa097, 0x0fc0, 0x0000ffff);
1748 nv_mthd(priv, 0xa097, 0x0fc4, 0x0000ffff);
1749 nv_mthd(priv, 0xa097, 0x0fc8, 0x0000ffff);
1750 nv_mthd(priv, 0xa097, 0x0df8, 0x00000000);
1751 nv_mthd(priv, 0xa097, 0x0dfc, 0x00000000);
1752 nv_mthd(priv, 0xa097, 0x1948, 0x00000000);
1753 nv_mthd(priv, 0xa097, 0x1970, 0x00000001);
1754 nv_mthd(priv, 0xa097, 0x161c, 0x000009f0);
1755 nv_mthd(priv, 0xa097, 0x0dcc, 0x00000010);
1756 nv_mthd(priv, 0xa097, 0x163c, 0x00000000);
1757 nv_mthd(priv, 0xa097, 0x15e4, 0x00000000);
1758 nv_mthd(priv, 0xa097, 0x1160, 0x25e00040);
1759 nv_mthd(priv, 0xa097, 0x1164, 0x25e00040);
1760 nv_mthd(priv, 0xa097, 0x1168, 0x25e00040);
1761 nv_mthd(priv, 0xa097, 0x116c, 0x25e00040);
1762 nv_mthd(priv, 0xa097, 0x1170, 0x25e00040);
1763 nv_mthd(priv, 0xa097, 0x1174, 0x25e00040);
1764 nv_mthd(priv, 0xa097, 0x1178, 0x25e00040);
1765 nv_mthd(priv, 0xa097, 0x117c, 0x25e00040);
1766 nv_mthd(priv, 0xa097, 0x1180, 0x25e00040);
1767 nv_mthd(priv, 0xa097, 0x1184, 0x25e00040);
1768 nv_mthd(priv, 0xa097, 0x1188, 0x25e00040);
1769 nv_mthd(priv, 0xa097, 0x118c, 0x25e00040);
1770 nv_mthd(priv, 0xa097, 0x1190, 0x25e00040);
1771 nv_mthd(priv, 0xa097, 0x1194, 0x25e00040);
1772 nv_mthd(priv, 0xa097, 0x1198, 0x25e00040);
1773 nv_mthd(priv, 0xa097, 0x119c, 0x25e00040);
1774 nv_mthd(priv, 0xa097, 0x11a0, 0x25e00040);
1775 nv_mthd(priv, 0xa097, 0x11a4, 0x25e00040);
1776 nv_mthd(priv, 0xa097, 0x11a8, 0x25e00040);
1777 nv_mthd(priv, 0xa097, 0x11ac, 0x25e00040);
1778 nv_mthd(priv, 0xa097, 0x11b0, 0x25e00040);
1779 nv_mthd(priv, 0xa097, 0x11b4, 0x25e00040);
1780 nv_mthd(priv, 0xa097, 0x11b8, 0x25e00040);
1781 nv_mthd(priv, 0xa097, 0x11bc, 0x25e00040);
1782 nv_mthd(priv, 0xa097, 0x11c0, 0x25e00040);
1783 nv_mthd(priv, 0xa097, 0x11c4, 0x25e00040);
1784 nv_mthd(priv, 0xa097, 0x11c8, 0x25e00040);
1785 nv_mthd(priv, 0xa097, 0x11cc, 0x25e00040);
1786 nv_mthd(priv, 0xa097, 0x11d0, 0x25e00040);
1787 nv_mthd(priv, 0xa097, 0x11d4, 0x25e00040);
1788 nv_mthd(priv, 0xa097, 0x11d8, 0x25e00040);
1789 nv_mthd(priv, 0xa097, 0x11dc, 0x25e00040);
1790 nv_mthd(priv, 0xa097, 0x1880, 0x00000000);
1791 nv_mthd(priv, 0xa097, 0x1884, 0x00000000);
1792 nv_mthd(priv, 0xa097, 0x1888, 0x00000000);
1793 nv_mthd(priv, 0xa097, 0x188c, 0x00000000);
1794 nv_mthd(priv, 0xa097, 0x1890, 0x00000000);
1795 nv_mthd(priv, 0xa097, 0x1894, 0x00000000);
1796 nv_mthd(priv, 0xa097, 0x1898, 0x00000000);
1797 nv_mthd(priv, 0xa097, 0x189c, 0x00000000);
1798 nv_mthd(priv, 0xa097, 0x18a0, 0x00000000);
1799 nv_mthd(priv, 0xa097, 0x18a4, 0x00000000);
1800 nv_mthd(priv, 0xa097, 0x18a8, 0x00000000);
1801 nv_mthd(priv, 0xa097, 0x18ac, 0x00000000);
1802 nv_mthd(priv, 0xa097, 0x18b0, 0x00000000);
1803 nv_mthd(priv, 0xa097, 0x18b4, 0x00000000);
1804 nv_mthd(priv, 0xa097, 0x18b8, 0x00000000);
1805 nv_mthd(priv, 0xa097, 0x18bc, 0x00000000);
1806 nv_mthd(priv, 0xa097, 0x18c0, 0x00000000);
1807 nv_mthd(priv, 0xa097, 0x18c4, 0x00000000);
1808 nv_mthd(priv, 0xa097, 0x18c8, 0x00000000);
1809 nv_mthd(priv, 0xa097, 0x18cc, 0x00000000);
1810 nv_mthd(priv, 0xa097, 0x18d0, 0x00000000);
1811 nv_mthd(priv, 0xa097, 0x18d4, 0x00000000);
1812 nv_mthd(priv, 0xa097, 0x18d8, 0x00000000);
1813 nv_mthd(priv, 0xa097, 0x18dc, 0x00000000);
1814 nv_mthd(priv, 0xa097, 0x18e0, 0x00000000);
1815 nv_mthd(priv, 0xa097, 0x18e4, 0x00000000);
1816 nv_mthd(priv, 0xa097, 0x18e8, 0x00000000);
1817 nv_mthd(priv, 0xa097, 0x18ec, 0x00000000);
1818 nv_mthd(priv, 0xa097, 0x18f0, 0x00000000);
1819 nv_mthd(priv, 0xa097, 0x18f4, 0x00000000);
1820 nv_mthd(priv, 0xa097, 0x18f8, 0x00000000);
1821 nv_mthd(priv, 0xa097, 0x18fc, 0x00000000);
1822 nv_mthd(priv, 0xa097, 0x0f84, 0x00000000);
1823 nv_mthd(priv, 0xa097, 0x0f88, 0x00000000);
1824 nv_mthd(priv, 0xa097, 0x17c8, 0x00000000);
1825 nv_mthd(priv, 0xa097, 0x17cc, 0x00000000);
1826 nv_mthd(priv, 0xa097, 0x17d0, 0x000000ff);
1827 nv_mthd(priv, 0xa097, 0x17d4, 0xffffffff);
1828 nv_mthd(priv, 0xa097, 0x17d8, 0x00000002);
1829 nv_mthd(priv, 0xa097, 0x17dc, 0x00000000);
1830 nv_mthd(priv, 0xa097, 0x15f4, 0x00000000);
1831 nv_mthd(priv, 0xa097, 0x15f8, 0x00000000);
1832 nv_mthd(priv, 0xa097, 0x1434, 0x00000000);
1833 nv_mthd(priv, 0xa097, 0x1438, 0x00000000);
1834 nv_mthd(priv, 0xa097, 0x0d74, 0x00000000);
1835 nv_mthd(priv, 0xa097, 0x0dec, 0x00000001);
1836 nv_mthd(priv, 0xa097, 0x13a4, 0x00000000);
1837 nv_mthd(priv, 0xa097, 0x1318, 0x00000001);
1838 nv_mthd(priv, 0xa097, 0x1644, 0x00000000);
1839 nv_mthd(priv, 0xa097, 0x0748, 0x00000000);
1840 nv_mthd(priv, 0xa097, 0x0de8, 0x00000000);
1841 nv_mthd(priv, 0xa097, 0x1648, 0x00000000);
1842 nv_mthd(priv, 0xa097, 0x12a4, 0x00000000);
1843 nv_mthd(priv, 0xa097, 0x1120, 0x00000000);
1844 nv_mthd(priv, 0xa097, 0x1124, 0x00000000);
1845 nv_mthd(priv, 0xa097, 0x1128, 0x00000000);
1846 nv_mthd(priv, 0xa097, 0x112c, 0x00000000);
1847 nv_mthd(priv, 0xa097, 0x1118, 0x00000000);
1848 nv_mthd(priv, 0xa097, 0x164c, 0x00000000);
1849 nv_mthd(priv, 0xa097, 0x1658, 0x00000000);
1850 nv_mthd(priv, 0xa097, 0x1910, 0x00000290);
1851 nv_mthd(priv, 0xa097, 0x1518, 0x00000000);
1852 nv_mthd(priv, 0xa097, 0x165c, 0x00000001);
1853 nv_mthd(priv, 0xa097, 0x1520, 0x00000000);
1854 nv_mthd(priv, 0xa097, 0x1604, 0x00000000);
1855 nv_mthd(priv, 0xa097, 0x1570, 0x00000000);
1856 nv_mthd(priv, 0xa097, 0x13b0, 0x3f800000);
1857 nv_mthd(priv, 0xa097, 0x13b4, 0x3f800000);
1858 nv_mthd(priv, 0xa097, 0x020c, 0x00000000);
1859 nv_mthd(priv, 0xa097, 0x1670, 0x30201000);
1860 nv_mthd(priv, 0xa097, 0x1674, 0x70605040);
1861 nv_mthd(priv, 0xa097, 0x1678, 0xb8a89888);
1862 nv_mthd(priv, 0xa097, 0x167c, 0xf8e8d8c8);
1863 nv_mthd(priv, 0xa097, 0x166c, 0x00000000);
1864 nv_mthd(priv, 0xa097, 0x1680, 0x00ffff00);
1865 nv_mthd(priv, 0xa097, 0x12d0, 0x00000003);
1866 nv_mthd(priv, 0xa097, 0x12d4, 0x00000002);
1867 nv_mthd(priv, 0xa097, 0x1684, 0x00000000);
1868 nv_mthd(priv, 0xa097, 0x1688, 0x00000000);
1869 nv_mthd(priv, 0xa097, 0x0dac, 0x00001b02);
1870 nv_mthd(priv, 0xa097, 0x0db0, 0x00001b02);
1871 nv_mthd(priv, 0xa097, 0x0db4, 0x00000000);
1872 nv_mthd(priv, 0xa097, 0x168c, 0x00000000);
1873 nv_mthd(priv, 0xa097, 0x15bc, 0x00000000);
1874 nv_mthd(priv, 0xa097, 0x156c, 0x00000000);
1875 nv_mthd(priv, 0xa097, 0x187c, 0x00000000);
1876 nv_mthd(priv, 0xa097, 0x1110, 0x00000001);
1877 nv_mthd(priv, 0xa097, 0x0dc0, 0x00000000);
1878 nv_mthd(priv, 0xa097, 0x0dc4, 0x00000000);
1879 nv_mthd(priv, 0xa097, 0x0dc8, 0x00000000);
1880 nv_mthd(priv, 0xa097, 0x1234, 0x00000000);
1881 nv_mthd(priv, 0xa097, 0x1690, 0x00000000);
1882 nv_mthd(priv, 0xa097, 0x12ac, 0x00000001);
1883 nv_mthd(priv, 0xa097, 0x0790, 0x00000000);
1884 nv_mthd(priv, 0xa097, 0x0794, 0x00000000);
1885 nv_mthd(priv, 0xa097, 0x0798, 0x00000000);
1886 nv_mthd(priv, 0xa097, 0x079c, 0x00000000);
1887 nv_mthd(priv, 0xa097, 0x07a0, 0x00000000);
1888 nv_mthd(priv, 0xa097, 0x077c, 0x00000000);
1889 nv_mthd(priv, 0xa097, 0x1000, 0x00000010);
1890 nv_mthd(priv, 0xa097, 0x10fc, 0x00000000);
1891 nv_mthd(priv, 0xa097, 0x1290, 0x00000000);
1892 nv_mthd(priv, 0xa097, 0x0218, 0x00000010);
1893 nv_mthd(priv, 0xa097, 0x12d8, 0x00000000);
1894 nv_mthd(priv, 0xa097, 0x12dc, 0x00000010);
1895 nv_mthd(priv, 0xa097, 0x0d94, 0x00000001);
1896 nv_mthd(priv, 0xa097, 0x155c, 0x00000000);
1897 nv_mthd(priv, 0xa097, 0x1560, 0x00000000);
1898 nv_mthd(priv, 0xa097, 0x1564, 0x00000fff);
1899 nv_mthd(priv, 0xa097, 0x1574, 0x00000000);
1900 nv_mthd(priv, 0xa097, 0x1578, 0x00000000);
1901 nv_mthd(priv, 0xa097, 0x157c, 0x000fffff);
1902 nv_mthd(priv, 0xa097, 0x1354, 0x00000000);
1903 nv_mthd(priv, 0xa097, 0x1610, 0x00000012);
1904 nv_mthd(priv, 0xa097, 0x1608, 0x00000000);
1905 nv_mthd(priv, 0xa097, 0x160c, 0x00000000);
1906 nv_mthd(priv, 0xa097, 0x260c, 0x00000000);
1907 nv_mthd(priv, 0xa097, 0x07ac, 0x00000000);
1908 nv_mthd(priv, 0xa097, 0x162c, 0x00000003);
1909 nv_mthd(priv, 0xa097, 0x0210, 0x00000000);
1910 nv_mthd(priv, 0xa097, 0x0320, 0x00000000);
1911 nv_mthd(priv, 0xa097, 0x0324, 0x3f800000);
1912 nv_mthd(priv, 0xa097, 0x0328, 0x3f800000);
1913 nv_mthd(priv, 0xa097, 0x032c, 0x3f800000);
1914 nv_mthd(priv, 0xa097, 0x0330, 0x3f800000);
1915 nv_mthd(priv, 0xa097, 0x0334, 0x3f800000);
1916 nv_mthd(priv, 0xa097, 0x0338, 0x3f800000);
1917 nv_mthd(priv, 0xa097, 0x0750, 0x00000000);
1918 nv_mthd(priv, 0xa097, 0x0760, 0x39291909);
1919 nv_mthd(priv, 0xa097, 0x0764, 0x79695949);
1920 nv_mthd(priv, 0xa097, 0x0768, 0xb9a99989);
1921 nv_mthd(priv, 0xa097, 0x076c, 0xf9e9d9c9);
1922 nv_mthd(priv, 0xa097, 0x0770, 0x30201000);
1923 nv_mthd(priv, 0xa097, 0x0774, 0x70605040);
1924 nv_mthd(priv, 0xa097, 0x0778, 0x00009080);
1925 nv_mthd(priv, 0xa097, 0x0780, 0x39291909);
1926 nv_mthd(priv, 0xa097, 0x0784, 0x79695949);
1927 nv_mthd(priv, 0xa097, 0x0788, 0xb9a99989);
1928 nv_mthd(priv, 0xa097, 0x078c, 0xf9e9d9c9);
1929 nv_mthd(priv, 0xa097, 0x07d0, 0x30201000);
1930 nv_mthd(priv, 0xa097, 0x07d4, 0x70605040);
1931 nv_mthd(priv, 0xa097, 0x07d8, 0x00009080);
1932 nv_mthd(priv, 0xa097, 0x037c, 0x00000001);
1933 nv_mthd(priv, 0xa097, 0x0740, 0x00000000);
1934 nv_mthd(priv, 0xa097, 0x0744, 0x00000000);
1935 nv_mthd(priv, 0xa097, 0x2600, 0x00000000);
1936 nv_mthd(priv, 0xa097, 0x1918, 0x00000000);
1937 nv_mthd(priv, 0xa097, 0x191c, 0x00000900);
1938 nv_mthd(priv, 0xa097, 0x1920, 0x00000405);
1939 nv_mthd(priv, 0xa097, 0x1308, 0x00000001);
1940 nv_mthd(priv, 0xa097, 0x1924, 0x00000000);
1941 nv_mthd(priv, 0xa097, 0x13ac, 0x00000000);
1942 nv_mthd(priv, 0xa097, 0x192c, 0x00000001);
1943 nv_mthd(priv, 0xa097, 0x193c, 0x00002c1c);
1944 nv_mthd(priv, 0xa097, 0x0d7c, 0x00000000);
1945 nv_mthd(priv, 0xa097, 0x0f8c, 0x00000000);
1946 nv_mthd(priv, 0xa097, 0x02c0, 0x00000001);
1947 nv_mthd(priv, 0xa097, 0x1510, 0x00000000);
1948 nv_mthd(priv, 0xa097, 0x1940, 0x00000000);
1949 nv_mthd(priv, 0xa097, 0x0ff4, 0x00000000);
1950 nv_mthd(priv, 0xa097, 0x0ff8, 0x00000000);
1951 nv_mthd(priv, 0xa097, 0x194c, 0x00000000);
1952 nv_mthd(priv, 0xa097, 0x1950, 0x00000000);
1953 nv_mthd(priv, 0xa097, 0x1968, 0x00000000);
1954 nv_mthd(priv, 0xa097, 0x1590, 0x0000003f);
1955 nv_mthd(priv, 0xa097, 0x07e8, 0x00000000);
1956 nv_mthd(priv, 0xa097, 0x07ec, 0x00000000);
1957 nv_mthd(priv, 0xa097, 0x07f0, 0x00000000);
1958 nv_mthd(priv, 0xa097, 0x07f4, 0x00000000);
1959 nv_mthd(priv, 0xa097, 0x196c, 0x00000011);
1960 nv_mthd(priv, 0xa097, 0x02e4, 0x0000b001);
1961 nv_mthd(priv, 0xa097, 0x036c, 0x00000000);
1962 nv_mthd(priv, 0xa097, 0x0370, 0x00000000);
1963 nv_mthd(priv, 0xa097, 0x197c, 0x00000000);
1964 nv_mthd(priv, 0xa097, 0x0fcc, 0x00000000);
1965 nv_mthd(priv, 0xa097, 0x0fd0, 0x00000000);
1966 nv_mthd(priv, 0xa097, 0x02d8, 0x00000040);
1967 nv_mthd(priv, 0xa097, 0x1980, 0x00000080);
1968 nv_mthd(priv, 0xa097, 0x1504, 0x00000080);
1969 nv_mthd(priv, 0xa097, 0x1984, 0x00000000);
1970 nv_mthd(priv, 0xa097, 0x0300, 0x00000001);
1971 nv_mthd(priv, 0xa097, 0x13a8, 0x00000000);
1972 nv_mthd(priv, 0xa097, 0x12ec, 0x00000000);
1973 nv_mthd(priv, 0xa097, 0x1310, 0x00000000);
1974 nv_mthd(priv, 0xa097, 0x1314, 0x00000001);
1975 nv_mthd(priv, 0xa097, 0x1380, 0x00000000);
1976 nv_mthd(priv, 0xa097, 0x1384, 0x00000001);
1977 nv_mthd(priv, 0xa097, 0x1388, 0x00000001);
1978 nv_mthd(priv, 0xa097, 0x138c, 0x00000001);
1979 nv_mthd(priv, 0xa097, 0x1390, 0x00000001);
1980 nv_mthd(priv, 0xa097, 0x1394, 0x00000000);
1981 nv_mthd(priv, 0xa097, 0x139c, 0x00000000);
1982 nv_mthd(priv, 0xa097, 0x1398, 0x00000000);
1983 nv_mthd(priv, 0xa097, 0x1594, 0x00000000);
1984 nv_mthd(priv, 0xa097, 0x1598, 0x00000001);
1985 nv_mthd(priv, 0xa097, 0x159c, 0x00000001);
1986 nv_mthd(priv, 0xa097, 0x15a0, 0x00000001);
1987 nv_mthd(priv, 0xa097, 0x15a4, 0x00000001);
1988 nv_mthd(priv, 0xa097, 0x0f54, 0x00000000);
1989 nv_mthd(priv, 0xa097, 0x0f58, 0x00000000);
1990 nv_mthd(priv, 0xa097, 0x0f5c, 0x00000000);
1991 nv_mthd(priv, 0xa097, 0x19bc, 0x00000000);
1992 nv_mthd(priv, 0xa097, 0x0f9c, 0x00000000);
1993 nv_mthd(priv, 0xa097, 0x0fa0, 0x00000000);
1994 nv_mthd(priv, 0xa097, 0x12cc, 0x00000000);
1995 nv_mthd(priv, 0xa097, 0x12e8, 0x00000000);
1996 nv_mthd(priv, 0xa097, 0x130c, 0x00000001);
1997 nv_mthd(priv, 0xa097, 0x1360, 0x00000000);
1998 nv_mthd(priv, 0xa097, 0x1364, 0x00000000);
1999 nv_mthd(priv, 0xa097, 0x1368, 0x00000000);
2000 nv_mthd(priv, 0xa097, 0x136c, 0x00000000);
2001 nv_mthd(priv, 0xa097, 0x1370, 0x00000000);
2002 nv_mthd(priv, 0xa097, 0x1374, 0x00000000);
2003 nv_mthd(priv, 0xa097, 0x1378, 0x00000000);
2004 nv_mthd(priv, 0xa097, 0x137c, 0x00000000);
2005 nv_mthd(priv, 0xa097, 0x133c, 0x00000001);
2006 nv_mthd(priv, 0xa097, 0x1340, 0x00000001);
2007 nv_mthd(priv, 0xa097, 0x1344, 0x00000002);
2008 nv_mthd(priv, 0xa097, 0x1348, 0x00000001);
2009 nv_mthd(priv, 0xa097, 0x134c, 0x00000001);
2010 nv_mthd(priv, 0xa097, 0x1350, 0x00000002);
2011 nv_mthd(priv, 0xa097, 0x1358, 0x00000001);
2012 nv_mthd(priv, 0xa097, 0x12e4, 0x00000000);
2013 nv_mthd(priv, 0xa097, 0x131c, 0x00000000);
2014 nv_mthd(priv, 0xa097, 0x1320, 0x00000000);
2015 nv_mthd(priv, 0xa097, 0x1324, 0x00000000);
2016 nv_mthd(priv, 0xa097, 0x1328, 0x00000000);
2017 nv_mthd(priv, 0xa097, 0x19c0, 0x00000000);
2018 nv_mthd(priv, 0xa097, 0x1140, 0x00000000);
2019 nv_mthd(priv, 0xa097, 0x19c4, 0x00000000);
2020 nv_mthd(priv, 0xa097, 0x19c8, 0x00001500);
2021 nv_mthd(priv, 0xa097, 0x135c, 0x00000000);
2022 nv_mthd(priv, 0xa097, 0x0f90, 0x00000000);
2023 nv_mthd(priv, 0xa097, 0x19e0, 0x00000001);
2024 nv_mthd(priv, 0xa097, 0x19e4, 0x00000001);
2025 nv_mthd(priv, 0xa097, 0x19e8, 0x00000001);
2026 nv_mthd(priv, 0xa097, 0x19ec, 0x00000001);
2027 nv_mthd(priv, 0xa097, 0x19f0, 0x00000001);
2028 nv_mthd(priv, 0xa097, 0x19f4, 0x00000001);
2029 nv_mthd(priv, 0xa097, 0x19f8, 0x00000001);
2030 nv_mthd(priv, 0xa097, 0x19fc, 0x00000001);
2031 nv_mthd(priv, 0xa097, 0x19cc, 0x00000001);
2032 nv_mthd(priv, 0xa097, 0x15b8, 0x00000000);
2033 nv_mthd(priv, 0xa097, 0x1a00, 0x00001111);
2034 nv_mthd(priv, 0xa097, 0x1a04, 0x00000000);
2035 nv_mthd(priv, 0xa097, 0x1a08, 0x00000000);
2036 nv_mthd(priv, 0xa097, 0x1a0c, 0x00000000);
2037 nv_mthd(priv, 0xa097, 0x1a10, 0x00000000);
2038 nv_mthd(priv, 0xa097, 0x1a14, 0x00000000);
2039 nv_mthd(priv, 0xa097, 0x1a18, 0x00000000);
2040 nv_mthd(priv, 0xa097, 0x1a1c, 0x00000000);
2041 nv_mthd(priv, 0xa097, 0x0d6c, 0xffff0000);
2042 nv_mthd(priv, 0xa097, 0x0d70, 0xffff0000);
2043 nv_mthd(priv, 0xa097, 0x10f8, 0x00001010);
2044 nv_mthd(priv, 0xa097, 0x0d80, 0x00000000);
2045 nv_mthd(priv, 0xa097, 0x0d84, 0x00000000);
2046 nv_mthd(priv, 0xa097, 0x0d88, 0x00000000);
2047 nv_mthd(priv, 0xa097, 0x0d8c, 0x00000000);
2048 nv_mthd(priv, 0xa097, 0x0d90, 0x00000000);
2049 nv_mthd(priv, 0xa097, 0x0da0, 0x00000000);
2050 nv_mthd(priv, 0xa097, 0x07a4, 0x00000000);
2051 nv_mthd(priv, 0xa097, 0x07a8, 0x00000000);
2052 nv_mthd(priv, 0xa097, 0x1508, 0x80000000);
2053 nv_mthd(priv, 0xa097, 0x150c, 0x40000000);
2054 nv_mthd(priv, 0xa097, 0x1668, 0x00000000);
2055 nv_mthd(priv, 0xa097, 0x0318, 0x00000008);
2056 nv_mthd(priv, 0xa097, 0x031c, 0x00000008);
2057 nv_mthd(priv, 0xa097, 0x0d9c, 0x00000001);
2058 nv_mthd(priv, 0xa097, 0x0374, 0x00000000);
2059 nv_mthd(priv, 0xa097, 0x0378, 0x00000020);
2060 nv_mthd(priv, 0xa097, 0x07dc, 0x00000000);
2061 nv_mthd(priv, 0xa097, 0x074c, 0x00000055);
2062 nv_mthd(priv, 0xa097, 0x1420, 0x00000003);
2063 nv_mthd(priv, 0xa097, 0x17bc, 0x00000000);
2064 nv_mthd(priv, 0xa097, 0x17c0, 0x00000000);
2065 nv_mthd(priv, 0xa097, 0x17c4, 0x00000001);
2066 nv_mthd(priv, 0xa097, 0x1008, 0x00000008);
2067 nv_mthd(priv, 0xa097, 0x100c, 0x00000040);
2068 nv_mthd(priv, 0xa097, 0x1010, 0x0000012c);
2069 nv_mthd(priv, 0xa097, 0x0d60, 0x00000040);
2070 nv_mthd(priv, 0xa097, 0x075c, 0x00000003);
2071 nv_mthd(priv, 0xa097, 0x1018, 0x00000020);
2072 nv_mthd(priv, 0xa097, 0x101c, 0x00000001);
2073 nv_mthd(priv, 0xa097, 0x1020, 0x00000020);
2074 nv_mthd(priv, 0xa097, 0x1024, 0x00000001);
2075 nv_mthd(priv, 0xa097, 0x1444, 0x00000000);
2076 nv_mthd(priv, 0xa097, 0x1448, 0x00000000);
2077 nv_mthd(priv, 0xa097, 0x144c, 0x00000000);
2078 nv_mthd(priv, 0xa097, 0x0360, 0x20164010);
2079 nv_mthd(priv, 0xa097, 0x0364, 0x00000020);
2080 nv_mthd(priv, 0xa097, 0x0368, 0x00000000);
2081 nv_mthd(priv, 0xa097, 0x0de4, 0x00000000);
2082 nv_mthd(priv, 0xa097, 0x0204, 0x00000006);
2083 nv_mthd(priv, 0xa097, 0x0208, 0x00000000);
2084 nv_mthd(priv, 0xa097, 0x02cc, 0x003fffff);
2085 nv_mthd(priv, 0xa097, 0x02d0, 0x003fffff);
2086 nv_mthd(priv, 0xa097, 0x1220, 0x00000005);
2087 nv_mthd(priv, 0xa097, 0x0fdc, 0x00000000);
2088 nv_mthd(priv, 0xa097, 0x0f98, 0x00400008);
2089 nv_mthd(priv, 0xa097, 0x1284, 0x08000080);
2090 nv_mthd(priv, 0xa097, 0x1450, 0x00400008);
2091 nv_mthd(priv, 0xa097, 0x1454, 0x08000080);
2092 nv_mthd(priv, 0xa097, 0x0214, 0x00000000);
2093}
2094
2095static void
2096nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
2097{
2098 nv_mthd(priv, 0x902d, 0x0200, 0x000000cf);
2099 nv_mthd(priv, 0x902d, 0x0204, 0x00000001);
2100 nv_mthd(priv, 0x902d, 0x0208, 0x00000020);
2101 nv_mthd(priv, 0x902d, 0x020c, 0x00000001);
2102 nv_mthd(priv, 0x902d, 0x0210, 0x00000000);
2103 nv_mthd(priv, 0x902d, 0x0214, 0x00000080);
2104 nv_mthd(priv, 0x902d, 0x0218, 0x00000100);
2105 nv_mthd(priv, 0x902d, 0x021c, 0x00000100);
2106 nv_mthd(priv, 0x902d, 0x0220, 0x00000000);
2107 nv_mthd(priv, 0x902d, 0x0224, 0x00000000);
2108 nv_mthd(priv, 0x902d, 0x0230, 0x000000cf);
2109 nv_mthd(priv, 0x902d, 0x0234, 0x00000001);
2110 nv_mthd(priv, 0x902d, 0x0238, 0x00000020);
2111 nv_mthd(priv, 0x902d, 0x023c, 0x00000001);
2112 nv_mthd(priv, 0x902d, 0x0244, 0x00000080);
2113 nv_mthd(priv, 0x902d, 0x0248, 0x00000100);
2114 nv_mthd(priv, 0x902d, 0x024c, 0x00000100);
2115 switch (nv_device(priv)->chipset) {
2116 case 0xe6:
2117 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
2118 break;
2119 case 0xe4:
2120 case 0xe7:
2121 default:
2122 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
2123 break;
2124 }
2125}
2126
2127static void
2128nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
2129{
2130 switch (nv_device(priv)->chipset) {
2131 case 0xf0:
2132 nv_wr32(priv, 0x404004, 0x00000000);
2133 nv_wr32(priv, 0x404008, 0x00000000);
2134 nv_wr32(priv, 0x40400c, 0x00000000);
2135 break;
2136 default:
2137 break;
2138 }
2139 nv_wr32(priv, 0x404010, 0x0);
2140 nv_wr32(priv, 0x404014, 0x0);
2141 nv_wr32(priv, 0x404018, 0x0);
2142 nv_wr32(priv, 0x40401c, 0x0);
2143 nv_wr32(priv, 0x404020, 0x0);
2144 nv_wr32(priv, 0x404024, 0xe000);
2145 nv_wr32(priv, 0x404028, 0x0);
2146 switch (nv_device(priv)->chipset) {
2147 case 0xf0:
2148 nv_wr32(priv, 0x40402c, 0x00000000);
2149 nv_wr32(priv, 0x404030, 0x00000000);
2150 nv_wr32(priv, 0x404034, 0x00000000);
2151 nv_wr32(priv, 0x404038, 0x00000000);
2152 nv_wr32(priv, 0x40403c, 0x00000000);
2153 nv_wr32(priv, 0x404040, 0x00000000);
2154 nv_wr32(priv, 0x404044, 0x00000000);
2155 break;
2156 default:
2157 break;
2158 }
2159 nv_wr32(priv, 0x4040a8, 0x0);
2160 nv_wr32(priv, 0x4040ac, 0x0);
2161 nv_wr32(priv, 0x4040b0, 0x0);
2162 nv_wr32(priv, 0x4040b4, 0x0);
2163 nv_wr32(priv, 0x4040b8, 0x0);
2164 nv_wr32(priv, 0x4040bc, 0x0);
2165 nv_wr32(priv, 0x4040c0, 0x0);
2166 nv_wr32(priv, 0x4040c4, 0x0);
2167 nv_wr32(priv, 0x4040c8, 0xf800008f);
2168 nv_wr32(priv, 0x4040d0, 0x0);
2169 nv_wr32(priv, 0x4040d4, 0x0);
2170 nv_wr32(priv, 0x4040d8, 0x0);
2171 nv_wr32(priv, 0x4040dc, 0x0);
2172 nv_wr32(priv, 0x4040e0, 0x0);
2173 nv_wr32(priv, 0x4040e4, 0x0);
2174 nv_wr32(priv, 0x4040e8, 0x1000);
2175 nv_wr32(priv, 0x4040f8, 0x0);
2176 switch (nv_device(priv)->chipset) {
2177 case 0xf0:
2178 nv_wr32(priv, 0x404100, 0x00000000);
2179 nv_wr32(priv, 0x404104, 0x00000000);
2180 nv_wr32(priv, 0x404108, 0x00000000);
2181 nv_wr32(priv, 0x40410c, 0x00000000);
2182 nv_wr32(priv, 0x404110, 0x00000000);
2183 nv_wr32(priv, 0x404114, 0x00000000);
2184 nv_wr32(priv, 0x404118, 0x00000000);
2185 nv_wr32(priv, 0x40411c, 0x00000000);
2186 nv_wr32(priv, 0x404120, 0x00000000);
2187 nv_wr32(priv, 0x404124, 0x00000000);
2188 break;
2189 default:
2190 break;
2191 }
2192 nv_wr32(priv, 0x404130, 0x0);
2193 nv_wr32(priv, 0x404134, 0x0);
2194 nv_wr32(priv, 0x404138, 0x20000040);
2195 nv_wr32(priv, 0x404150, 0x2e);
2196 nv_wr32(priv, 0x404154, 0x400);
2197 nv_wr32(priv, 0x404158, 0x200);
2198 nv_wr32(priv, 0x404164, 0x55);
2199 switch (nv_device(priv)->chipset) {
2200 case 0xf0:
2201 nv_wr32(priv, 0x40417c, 0x00000000);
2202 nv_wr32(priv, 0x404180, 0x00000000);
2203 break;
2204 default:
2205 break;
2206 }
2207 nv_wr32(priv, 0x4041a0, 0x0);
2208 nv_wr32(priv, 0x4041a4, 0x0);
2209 nv_wr32(priv, 0x4041a8, 0x0);
2210 nv_wr32(priv, 0x4041ac, 0x0);
2211 switch (nv_device(priv)->chipset) {
2212 case 0xf0:
2213 nv_wr32(priv, 0x404200, 0xa197);
2214 nv_wr32(priv, 0x404204, 0xa1c0);
2215 nv_wr32(priv, 0x404208, 0xa140);
2216 nv_wr32(priv, 0x40420c, 0x902d);
2217 break;
2218 default:
2219 nv_wr32(priv, 0x404200, 0x0);
2220 nv_wr32(priv, 0x404204, 0x0);
2221 nv_wr32(priv, 0x404208, 0x0);
2222 nv_wr32(priv, 0x40420c, 0x0);
2223 break;
2224 }
2225}
2226
2227static void
2228nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv)
2229{
2230 nv_wr32(priv, 0x404404, 0x0);
2231 nv_wr32(priv, 0x404408, 0x0);
2232 nv_wr32(priv, 0x40440c, 0x0);
2233 nv_wr32(priv, 0x404410, 0x0);
2234 nv_wr32(priv, 0x404414, 0x0);
2235 nv_wr32(priv, 0x404418, 0x0);
2236 nv_wr32(priv, 0x40441c, 0x0);
2237 nv_wr32(priv, 0x404420, 0x0);
2238 nv_wr32(priv, 0x404424, 0x0);
2239 nv_wr32(priv, 0x404428, 0x0);
2240 nv_wr32(priv, 0x40442c, 0x0);
2241 nv_wr32(priv, 0x404430, 0x0);
2242 switch (nv_device(priv)->chipset) {
2243 case 0xf0:
2244 break;
2245 default:
2246 nv_wr32(priv, 0x404434, 0x0);
2247 break;
2248 }
2249 nv_wr32(priv, 0x404438, 0x0);
2250 nv_wr32(priv, 0x404460, 0x0);
2251 nv_wr32(priv, 0x404464, 0x0);
2252 nv_wr32(priv, 0x404468, 0xffffff);
2253 nv_wr32(priv, 0x40446c, 0x0);
2254 nv_wr32(priv, 0x404480, 0x1);
2255 nv_wr32(priv, 0x404498, 0x1);
2256}
2257
2258static void
2259nve0_graph_generate_unk46xx(struct nvc0_graph_priv *priv)
2260{
2261 nv_wr32(priv, 0x404604, 0x14);
2262 nv_wr32(priv, 0x404608, 0x0);
2263 nv_wr32(priv, 0x40460c, 0x3fff);
2264 nv_wr32(priv, 0x404610, 0x100);
2265 nv_wr32(priv, 0x404618, 0x0);
2266 nv_wr32(priv, 0x40461c, 0x0);
2267 nv_wr32(priv, 0x404620, 0x0);
2268 nv_wr32(priv, 0x404624, 0x0);
2269 nv_wr32(priv, 0x40462c, 0x0);
2270 nv_wr32(priv, 0x404630, 0x0);
2271 nv_wr32(priv, 0x404640, 0x0);
2272 nv_wr32(priv, 0x404654, 0x0);
2273 nv_wr32(priv, 0x404660, 0x0);
2274 nv_wr32(priv, 0x404678, 0x0);
2275 nv_wr32(priv, 0x40467c, 0x2);
2276 nv_wr32(priv, 0x404680, 0x0);
2277 nv_wr32(priv, 0x404684, 0x0);
2278 nv_wr32(priv, 0x404688, 0x0);
2279 nv_wr32(priv, 0x40468c, 0x0);
2280 nv_wr32(priv, 0x404690, 0x0);
2281 nv_wr32(priv, 0x404694, 0x0);
2282 nv_wr32(priv, 0x404698, 0x0);
2283 nv_wr32(priv, 0x40469c, 0x0);
2284 nv_wr32(priv, 0x4046a0, 0x7f0080);
2285 nv_wr32(priv, 0x4046a4, 0x0);
2286 nv_wr32(priv, 0x4046a8, 0x0);
2287 nv_wr32(priv, 0x4046ac, 0x0);
2288 nv_wr32(priv, 0x4046b0, 0x0);
2289 nv_wr32(priv, 0x4046b4, 0x0);
2290 nv_wr32(priv, 0x4046b8, 0x0);
2291 nv_wr32(priv, 0x4046bc, 0x0);
2292 nv_wr32(priv, 0x4046c0, 0x0);
2293 nv_wr32(priv, 0x4046c8, 0x0);
2294 nv_wr32(priv, 0x4046cc, 0x0);
2295 nv_wr32(priv, 0x4046d0, 0x0);
2296}
2297
2298static void
2299nve0_graph_generate_unk47xx(struct nvc0_graph_priv *priv)
2300{
2301 nv_wr32(priv, 0x404700, 0x0);
2302 nv_wr32(priv, 0x404704, 0x0);
2303 nv_wr32(priv, 0x404708, 0x0);
2304 nv_wr32(priv, 0x404718, 0x0);
2305 nv_wr32(priv, 0x40471c, 0x0);
2306 nv_wr32(priv, 0x404720, 0x0);
2307 nv_wr32(priv, 0x404724, 0x0);
2308 nv_wr32(priv, 0x404728, 0x0);
2309 nv_wr32(priv, 0x40472c, 0x0);
2310 nv_wr32(priv, 0x404730, 0x0);
2311 nv_wr32(priv, 0x404734, 0x100);
2312 nv_wr32(priv, 0x404738, 0x0);
2313 nv_wr32(priv, 0x40473c, 0x0);
2314 nv_wr32(priv, 0x404744, 0x0);
2315 nv_wr32(priv, 0x404748, 0x0);
2316 nv_wr32(priv, 0x404754, 0x0);
2317}
2318
2319static void
2320nve0_graph_generate_unk58xx(struct nvc0_graph_priv *priv)
2321{
2322 nv_wr32(priv, 0x405800, 0xf8000bf);
2323 nv_wr32(priv, 0x405830, 0x2180648);
2324 nv_wr32(priv, 0x405834, 0x8000000);
2325 nv_wr32(priv, 0x405838, 0x0);
2326 nv_wr32(priv, 0x405854, 0x0);
2327 nv_wr32(priv, 0x405870, 0x1);
2328 nv_wr32(priv, 0x405874, 0x1);
2329 nv_wr32(priv, 0x405878, 0x1);
2330 nv_wr32(priv, 0x40587c, 0x1);
2331 nv_wr32(priv, 0x405a00, 0x0);
2332 nv_wr32(priv, 0x405a04, 0x0);
2333 nv_wr32(priv, 0x405a18, 0x0);
2334}
2335
2336static void
2337nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv)
2338{
2339 nv_wr32(priv, 0x405b00, 0x0);
2340 nv_wr32(priv, 0x405b10, 0x1000);
2341 switch (nv_device(priv)->chipset) {
2342 case 0xf0:
2343 nv_wr32(priv, 0x405b20, 0x04000000);
2344 break;
2345 default:
2346 break;
2347 }
2348}
2349
2350static void
2351nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv)
2352{
2353 switch (nv_device(priv)->chipset) {
2354 case 0xf0:
2355 nv_wr32(priv, 0x406020, 0x34103c1);
2356 break;
2357 default:
2358 nv_wr32(priv, 0x406020, 0x4103c1);
2359 break;
2360 }
2361 nv_wr32(priv, 0x406028, 0x1);
2362 nv_wr32(priv, 0x40602c, 0x1);
2363 nv_wr32(priv, 0x406030, 0x1);
2364 nv_wr32(priv, 0x406034, 0x1);
2365}
2366
2367static void
2368nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
2369{
2370 nv_wr32(priv, 0x4064a8, 0x0);
2371 nv_wr32(priv, 0x4064ac, 0x3fff);
2372 switch (nv_device(priv)->chipset) {
2373 case 0xf0:
2374 nv_wr32(priv, 0x4064b0, 0x0);
2375 break;
2376 default:
2377 break;
2378 }
2379 nv_wr32(priv, 0x4064b4, 0x0);
2380 nv_wr32(priv, 0x4064b8, 0x0);
2381 switch (nv_device(priv)->chipset) {
2382 case 0xf0:
2383 nv_wr32(priv, 0x4064c0, 0x802000f0);
2384 nv_wr32(priv, 0x4064c4, 0x192ffff);
2385 nv_wr32(priv, 0x4064c8, 0x18007c0);
2386 break;
2387 default:
2388 nv_wr32(priv, 0x4064c0, 0x801a00f0);
2389 nv_wr32(priv, 0x4064c4, 0x192ffff);
2390 nv_wr32(priv, 0x4064c8, 0x1800600);
2391 break;
2392 }
2393 nv_wr32(priv, 0x4064cc, 0x0);
2394 nv_wr32(priv, 0x4064d0, 0x0);
2395 nv_wr32(priv, 0x4064d4, 0x0);
2396 nv_wr32(priv, 0x4064d8, 0x0);
2397 nv_wr32(priv, 0x4064dc, 0x0);
2398 nv_wr32(priv, 0x4064e0, 0x0);
2399 nv_wr32(priv, 0x4064e4, 0x0);
2400 nv_wr32(priv, 0x4064e8, 0x0);
2401 nv_wr32(priv, 0x4064ec, 0x0);
2402 nv_wr32(priv, 0x4064fc, 0x22a);
2403}
2404
2405static void
2406nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv)
2407{
2408 switch (nv_device(priv)->chipset) {
2409 case 0xf0:
2410 break;
2411 default:
2412 nv_wr32(priv, 0x407040, 0x0);
2413 break;
2414 }
2415}
2416
2417static void
2418nve0_graph_generate_unk78xx(struct nvc0_graph_priv *priv)
2419{
2420 nv_wr32(priv, 0x407804, 0x23);
2421 nv_wr32(priv, 0x40780c, 0xa418820);
2422 nv_wr32(priv, 0x407810, 0x62080e6);
2423 nv_wr32(priv, 0x407814, 0x20398a4);
2424 nv_wr32(priv, 0x407818, 0xe629062);
2425 nv_wr32(priv, 0x40781c, 0xa418820);
2426 nv_wr32(priv, 0x407820, 0xe6);
2427 nv_wr32(priv, 0x4078bc, 0x103);
2428}
2429
2430static void
2431nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv)
2432{
2433 nv_wr32(priv, 0x408000, 0x0);
2434 nv_wr32(priv, 0x408004, 0x0);
2435 nv_wr32(priv, 0x408008, 0x30);
2436 nv_wr32(priv, 0x40800c, 0x0);
2437 nv_wr32(priv, 0x408010, 0x0);
2438 nv_wr32(priv, 0x408014, 0x69);
2439 nv_wr32(priv, 0x408018, 0xe100e100);
2440 nv_wr32(priv, 0x408064, 0x0);
2441}
2442
2443static void
2444nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)
2445{
2446 switch (nv_device(priv)->chipset) {
2447 case 0xf0:
2448 nv_wr32(priv, 0x408800, 0x12802a3c);
2449 break;
2450 default:
2451 nv_wr32(priv, 0x408800, 0x2802a3c);
2452 break;
2453 }
2454 nv_wr32(priv, 0x408804, 0x40);
2455 switch (nv_device(priv)->chipset) {
2456 case 0xf0:
2457 nv_wr32(priv, 0x408808, 0x1003e005);
2458 break;
2459 default:
2460 nv_wr32(priv, 0x408808, 0x1043e005);
2461 break;
2462 }
2463 nv_wr32(priv, 0x408840, 0xb);
2464 nv_wr32(priv, 0x408900, 0x3080b801);
2465 nv_wr32(priv, 0x408904, 0x62000001);
2466 nv_wr32(priv, 0x408908, 0xc8102f);
2467 nv_wr32(priv, 0x408980, 0x11d);
2468}
2469
2470static void
2471nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
2472{
2473 int i;
2474
2475 nv_wr32(priv, 0x418380, 0x16);
2476 nv_wr32(priv, 0x418400, 0x38004e00);
2477 nv_wr32(priv, 0x418404, 0x71e0ffff);
2478 nv_wr32(priv, 0x41840c, 0x1008);
2479 nv_wr32(priv, 0x418410, 0xfff0fff);
2480 nv_wr32(priv, 0x418414, 0x2200fff);
2481 nv_wr32(priv, 0x418450, 0x0);
2482 nv_wr32(priv, 0x418454, 0x0);
2483 nv_wr32(priv, 0x418458, 0x0);
2484 nv_wr32(priv, 0x41845c, 0x0);
2485 nv_wr32(priv, 0x418460, 0x0);
2486 nv_wr32(priv, 0x418464, 0x0);
2487 nv_wr32(priv, 0x418468, 0x1);
2488 nv_wr32(priv, 0x41846c, 0x0);
2489 nv_wr32(priv, 0x418470, 0x0);
2490 nv_wr32(priv, 0x418600, 0x1f);
2491 nv_wr32(priv, 0x418684, 0xf);
2492 nv_wr32(priv, 0x418700, 0x2);
2493 nv_wr32(priv, 0x418704, 0x80);
2494 nv_wr32(priv, 0x418708, 0x0);
2495 nv_wr32(priv, 0x41870c, 0x0);
2496 nv_wr32(priv, 0x418710, 0x0);
2497 nv_wr32(priv, 0x418800, 0x7006860a);
2498 nv_wr32(priv, 0x418808, 0x0);
2499 switch (nv_device(priv)->chipset) {
2500 case 0xf0:
2501 nv_wr32(priv, 0x41880c, 0x30);
2502 break;
2503 default:
2504 nv_wr32(priv, 0x41880c, 0x0);
2505 break;
2506 }
2507 nv_wr32(priv, 0x418810, 0x0);
2508 nv_wr32(priv, 0x418828, 0x44);
2509 nv_wr32(priv, 0x418830, 0x10000001);
2510 nv_wr32(priv, 0x4188d8, 0x8);
2511 nv_wr32(priv, 0x4188e0, 0x1000000);
2512 nv_wr32(priv, 0x4188e8, 0x0);
2513 nv_wr32(priv, 0x4188ec, 0x0);
2514 nv_wr32(priv, 0x4188f0, 0x0);
2515 nv_wr32(priv, 0x4188f4, 0x0);
2516 nv_wr32(priv, 0x4188f8, 0x0);
2517 nv_wr32(priv, 0x4188fc, 0x20100018);
2518 nv_wr32(priv, 0x41891c, 0xff00ff);
2519 nv_wr32(priv, 0x418924, 0x0);
2520 nv_wr32(priv, 0x418928, 0xffff00);
2521 nv_wr32(priv, 0x41892c, 0xff00);
2522 for (i = 0; i < 8; i++) {
2523 nv_wr32(priv, 0x418a00 + (i * 0x20), 0x0);
2524 nv_wr32(priv, 0x418a04 + (i * 0x20), 0x0);
2525 nv_wr32(priv, 0x418a08 + (i * 0x20), 0x0);
2526 nv_wr32(priv, 0x418a0c + (i * 0x20), 0x10000);
2527 nv_wr32(priv, 0x418a10 + (i * 0x20), 0x0);
2528 nv_wr32(priv, 0x418a14 + (i * 0x20), 0x0);
2529 nv_wr32(priv, 0x418a18 + (i * 0x20), 0x0);
2530 }
2531 nv_wr32(priv, 0x418b00, 0x6);
2532 nv_wr32(priv, 0x418b08, 0xa418820);
2533 nv_wr32(priv, 0x418b0c, 0x62080e6);
2534 nv_wr32(priv, 0x418b10, 0x20398a4);
2535 nv_wr32(priv, 0x418b14, 0xe629062);
2536 nv_wr32(priv, 0x418b18, 0xa418820);
2537 nv_wr32(priv, 0x418b1c, 0xe6);
2538 nv_wr32(priv, 0x418bb8, 0x103);
2539 nv_wr32(priv, 0x418c08, 0x1);
2540 nv_wr32(priv, 0x418c10, 0x0);
2541 nv_wr32(priv, 0x418c14, 0x0);
2542 nv_wr32(priv, 0x418c18, 0x0);
2543 nv_wr32(priv, 0x418c1c, 0x0);
2544 nv_wr32(priv, 0x418c20, 0x0);
2545 nv_wr32(priv, 0x418c24, 0x0);
2546 nv_wr32(priv, 0x418c28, 0x0);
2547 nv_wr32(priv, 0x418c2c, 0x0);
2548 nv_wr32(priv, 0x418c40, 0xffffffff);
2549 nv_wr32(priv, 0x418c6c, 0x1);
2550 nv_wr32(priv, 0x418c80, 0x20200004);
2551 nv_wr32(priv, 0x418c8c, 0x1);
2552 switch (nv_device(priv)->chipset) {
2553 case 0xf0:
2554 nv_wr32(priv, 0x418d24, 0x0);
2555 break;
2556 default:
2557 break;
2558 }
2559 nv_wr32(priv, 0x419000, 0x780);
2560 nv_wr32(priv, 0x419004, 0x0);
2561 nv_wr32(priv, 0x419008, 0x0);
2562 nv_wr32(priv, 0x419014, 0x4);
2563}
2564
2565static void
2566nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
2567{
2568 nv_wr32(priv, 0x419848, 0x0);
2569 nv_wr32(priv, 0x419864, 0x129);
2570 nv_wr32(priv, 0x419888, 0x0);
2571 nv_wr32(priv, 0x419a00, 0xf0);
2572 nv_wr32(priv, 0x419a04, 0x1);
2573 nv_wr32(priv, 0x419a08, 0x21);
2574 nv_wr32(priv, 0x419a0c, 0x20000);
2575 nv_wr32(priv, 0x419a10, 0x0);
2576 nv_wr32(priv, 0x419a14, 0x200);
2577 nv_wr32(priv, 0x419a1c, 0xc000);
2578 switch (nv_device(priv)->chipset) {
2579 case 0xf0:
2580 nv_wr32(priv, 0x419a20, 0x20800);
2581 break;
2582 default:
2583 nv_wr32(priv, 0x419a20, 0x800);
2584 break;
2585 }
2586 nv_wr32(priv, 0x419a30, 0x1);
2587 nv_wr32(priv, 0x419ac4, 0x37f440);
2588 switch (nv_device(priv)->chipset) {
2589 case 0xf0:
2590 nv_wr32(priv, 0x419c00, 0x1a);
2591 break;
2592 default:
2593 nv_wr32(priv, 0x419c00, 0xa);
2594 break;
2595 }
2596 nv_wr32(priv, 0x419c04, 0x80000006);
2597 nv_wr32(priv, 0x419c08, 0x2);
2598 nv_wr32(priv, 0x419c20, 0x0);
2599 nv_wr32(priv, 0x419c24, 0x84210);
2600 nv_wr32(priv, 0x419c28, 0x3efbefbe);
2601 nv_wr32(priv, 0x419ce8, 0x0);
2602 switch (nv_device(priv)->chipset) {
2603 case 0xf0:
2604 nv_wr32(priv, 0x419cf4, 0x203);
2605 nv_wr32(priv, 0x419e04, 0x0);
2606 nv_wr32(priv, 0x419e08, 0x1d);
2607 nv_wr32(priv, 0x419e0c, 0x0);
2608 nv_wr32(priv, 0x419e10, 0x1c02);
2609
2610 break;
2611 default:
2612 nv_wr32(priv, 0x419cf4, 0x3203);
2613 nv_wr32(priv, 0x419e04, 0x0);
2614 nv_wr32(priv, 0x419e08, 0x0);
2615 nv_wr32(priv, 0x419e0c, 0x0);
2616 nv_wr32(priv, 0x419e10, 0x402);
2617 break;
2618 }
2619 nv_wr32(priv, 0x419e44, 0x13eff2);
2620 nv_wr32(priv, 0x419e48, 0x0);
2621 nv_wr32(priv, 0x419e4c, 0x7f);
2622 nv_wr32(priv, 0x419e50, 0x0);
2623 nv_wr32(priv, 0x419e54, 0x0);
2624 switch (nv_device(priv)->chipset) {
2625 case 0xf0:
2626 nv_wr32(priv, 0x419e58, 0x1);
2627 break;
2628 default:
2629 nv_wr32(priv, 0x419e58, 0x0);
2630 break;
2631 }
2632 nv_wr32(priv, 0x419e5c, 0x0);
2633 nv_wr32(priv, 0x419e60, 0x0);
2634 nv_wr32(priv, 0x419e64, 0x0);
2635 switch (nv_device(priv)->chipset) {
2636 case 0xf0:
2637 nv_wr32(priv, 0x419e68, 0x2);
2638 break;
2639 default:
2640 nv_wr32(priv, 0x419e68, 0x0);
2641 break;
2642 }
2643 nv_wr32(priv, 0x419e6c, 0x0);
2644 nv_wr32(priv, 0x419e70, 0x0);
2645 nv_wr32(priv, 0x419e74, 0x0);
2646 nv_wr32(priv, 0x419e78, 0x0);
2647 nv_wr32(priv, 0x419e7c, 0x0);
2648 nv_wr32(priv, 0x419e80, 0x0);
2649 nv_wr32(priv, 0x419e84, 0x0);
2650 nv_wr32(priv, 0x419e88, 0x0);
2651 nv_wr32(priv, 0x419e8c, 0x0);
2652 nv_wr32(priv, 0x419e90, 0x0);
2653 nv_wr32(priv, 0x419e94, 0x0);
2654 nv_wr32(priv, 0x419e98, 0x0);
2655 switch (nv_device(priv)->chipset) {
2656 case 0xe4:
2657 case 0xe7:
2658 case 0xe6:
2659 nv_wr32(priv, 0x419eac, 0x1f8f);
2660 nv_wr32(priv, 0x419eb0, 0xd3f);
2661 break;
2662 case 0xf0:
2663 nv_wr32(priv, 0x419eac, 0x1fcf);
2664 nv_wr32(priv, 0x419eb0, 0xdb00da0);
2665 nv_wr32(priv, 0x419eb8, 0x0);
2666 break;
2667 }
2668 nv_wr32(priv, 0x419ec8, 0x1304f);
2669 nv_wr32(priv, 0x419f30, 0x0);
2670 nv_wr32(priv, 0x419f34, 0x0);
2671 nv_wr32(priv, 0x419f38, 0x0);
2672 nv_wr32(priv, 0x419f3c, 0x0);
2673 switch (nv_device(priv)->chipset) {
2674 case 0xf0:
2675 nv_wr32(priv, 0x419f40, 0x18);
2676 break;
2677 default:
2678 nv_wr32(priv, 0x419f40, 0x0);
2679 break;
2680 }
2681 nv_wr32(priv, 0x419f44, 0x0);
2682 nv_wr32(priv, 0x419f48, 0x0);
2683 nv_wr32(priv, 0x419f4c, 0x0);
2684 nv_wr32(priv, 0x419f58, 0x0);
2685 switch (nv_device(priv)->chipset) {
2686 case 0xe4:
2687 case 0xe7:
2688 case 0xe6:
2689 nv_wr32(priv, 0x419f70, 0x0);
2690 nv_wr32(priv, 0x419f78, 0xb);
2691 nv_wr32(priv, 0x419f7c, 0x27a);
2692 break;
2693 case 0xf0:
2694 nv_wr32(priv, 0x419f70, 0x7300);
2695 nv_wr32(priv, 0x419f78, 0xeb);
2696 nv_wr32(priv, 0x419f7c, 0x404);
2697 break;
2698 }
2699}
2700
2701static void
2702nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv)
2703{
2704 nv_wr32(priv, 0x41be24, 0x6);
2705 switch (nv_device(priv)->chipset) {
2706 case 0xf0:
2707 nv_wr32(priv, 0x41bec0, 0x10000000);
2708 break;
2709 default:
2710 nv_wr32(priv, 0x41bec0, 0x12180000);
2711 break;
2712 }
2713 nv_wr32(priv, 0x41bec4, 0x37f7f);
2714 switch (nv_device(priv)->chipset) {
2715 case 0xf0:
2716 nv_wr32(priv, 0x41bee4, 0x0);
2717 break;
2718 default:
2719 nv_wr32(priv, 0x41bee4, 0x6480430);
2720 break;
2721 }
2722 nv_wr32(priv, 0x41bf00, 0xa418820);
2723 nv_wr32(priv, 0x41bf04, 0x62080e6);
2724 nv_wr32(priv, 0x41bf08, 0x20398a4);
2725 nv_wr32(priv, 0x41bf0c, 0xe629062);
2726 nv_wr32(priv, 0x41bf10, 0xa418820);
2727 nv_wr32(priv, 0x41bf14, 0xe6);
2728 nv_wr32(priv, 0x41bfd0, 0x900103);
2729 nv_wr32(priv, 0x41bfe0, 0x400001);
2730 nv_wr32(priv, 0x41bfe4, 0x0);
2731}
2732
2733int
2734nve0_grctx_generate(struct nvc0_graph_priv *priv)
2735{
2736 struct nvc0_grctx info;
2737 int ret, i, gpc, tpc, id;
2738 u32 data[6] = {}, data2[2] = {}, tmp;
2739 u32 tpc_set = 0, tpc_mask = 0;
2740 u32 magic[GPC_MAX][2], offset;
2741 u8 tpcnr[GPC_MAX], a, b;
2742 u8 shift, ntpcv;
2743
2744 ret = nvc0_grctx_init(priv, &info);
2745 if (ret)
2746 return ret;
2747
2748 nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
2749 nv_wr32(priv, 0x400204, 0x00000000);
2750 nv_wr32(priv, 0x400208, 0x00000000);
2751
2752 nve0_graph_generate_unk40xx(priv);
2753 nve0_graph_generate_unk44xx(priv);
2754 nve0_graph_generate_unk46xx(priv);
2755 nve0_graph_generate_unk47xx(priv);
2756 nve0_graph_generate_unk58xx(priv);
2757 nve0_graph_generate_unk5bxx(priv);
2758 nve0_graph_generate_unk60xx(priv);
2759 nve0_graph_generate_unk64xx(priv);
2760 nve0_graph_generate_unk70xx(priv);
2761 nve0_graph_generate_unk78xx(priv);
2762 nve0_graph_generate_unk80xx(priv);
2763 nve0_graph_generate_unk88xx(priv);
2764 nve0_graph_generate_gpc(priv);
2765 nve0_graph_generate_tpc(priv);
2766 nve0_graph_generate_tpcunk(priv);
2767
2768 nv_wr32(priv, 0x404154, 0x0);
2769
2770 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
2771 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
2772 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
2773 mmio_list(0x40800c, 0x00000000, 8, 1);
2774 mmio_list(0x408010, 0x80000000, 0, 0);
2775 mmio_list(0x419004, 0x00000000, 8, 1);
2776 mmio_list(0x419008, 0x00000000, 0, 0);
2777 mmio_list(0x4064cc, 0x80000000, 0, 0);
2778 mmio_list(0x408004, 0x00000000, 8, 0);
2779 mmio_list(0x408008, 0x80000030, 0, 0);
2780 mmio_list(0x418808, 0x00000000, 8, 0);
2781 mmio_list(0x41880c, 0x80000030, 0, 0);
2782 mmio_list(0x4064c8, 0x01800600, 0, 0);
2783 mmio_list(0x418810, 0x80000000, 12, 2);
2784 mmio_list(0x419848, 0x10000000, 12, 2);
2785 mmio_list(0x405830, 0x02180648, 0, 0);
2786 mmio_list(0x4064c4, 0x0192ffff, 0, 0);
2787 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
2788 u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
2789 u16 magic1 = 0x0648 * priv->tpc_nr[gpc];
2790 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
2791 magic[gpc][1] = 0x00000000 | (magic1 << 16);
2792 offset += 0x0324 * priv->tpc_nr[gpc];
2793 }
2794 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
2795 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
2796 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
2797 offset += 0x07ff * priv->tpc_nr[gpc];
2798 }
2799 mmio_list(0x17e91c, 0x06060609, 0, 0);
2800 mmio_list(0x17e920, 0x00090a05, 0, 0);
2801
2802 nv_wr32(priv, 0x418c6c, 0x1);
2803 nv_wr32(priv, 0x41980c, 0x10);
2804 nv_wr32(priv, 0x41be08, 0x4);
2805 nv_wr32(priv, 0x4064c0, 0x801a00f0);
2806 nv_wr32(priv, 0x405800, 0xf8000bf);
2807 nv_wr32(priv, 0x419c00, 0xa);
2808
2809 for (tpc = 0, id = 0; tpc < 4; tpc++) {
2810 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
2811 if (tpc < priv->tpc_nr[gpc]) {
2812 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0698), id);
2813 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x04e8), id);
2814 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
2815 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0088), id++);
2816 }
2817
2818 nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
2819 nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
2820 }
2821 }
2822
2823 tmp = 0;
2824 for (i = 0; i < priv->gpc_nr; i++)
2825 tmp |= priv->tpc_nr[i] << (i * 4);
2826 nv_wr32(priv, 0x406028, tmp);
2827 nv_wr32(priv, 0x405870, tmp);
2828
2829 nv_wr32(priv, 0x40602c, 0x0);
2830 nv_wr32(priv, 0x405874, 0x0);
2831 nv_wr32(priv, 0x406030, 0x0);
2832 nv_wr32(priv, 0x405878, 0x0);
2833 nv_wr32(priv, 0x406034, 0x0);
2834 nv_wr32(priv, 0x40587c, 0x0);
2835
2836 /* calculate first set of magics */
2837 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
2838
2839 gpc = -1;
2840 for (tpc = 0; tpc < priv->tpc_total; tpc++) {
2841 do {
2842 gpc = (gpc + 1) % priv->gpc_nr;
2843 } while (!tpcnr[gpc]);
2844 tpcnr[gpc]--;
2845
2846 data[tpc / 6] |= gpc << ((tpc % 6) * 5);
2847 }
2848
2849 for (; tpc < 32; tpc++)
2850 data[tpc / 6] |= 7 << ((tpc % 6) * 5);
2851
2852 /* and the second... */
2853 shift = 0;
2854 ntpcv = priv->tpc_total;
2855 while (!(ntpcv & (1 << 4))) {
2856 ntpcv <<= 1;
2857 shift++;
2858 }
2859
2860 data2[0] = ntpcv << 16;
2861 data2[0] |= shift << 21;
2862 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
2863 data2[0] |= priv->tpc_total << 8;
2864 data2[0] |= priv->magic_not_rop_nr;
2865 for (i = 1; i < 7; i++)
2866 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
2867
2868 /* and write it all the various parts of PGRAPH */
2869 nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | priv->magic_not_rop_nr);
2870 for (i = 0; i < 6; i++)
2871 nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
2872
2873 nv_wr32(priv, 0x41bfd0, data2[0]);
2874 nv_wr32(priv, 0x41bfe4, data2[1]);
2875 for (i = 0; i < 6; i++)
2876 nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
2877
2878 nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | priv->magic_not_rop_nr);
2879 for (i = 0; i < 6; i++)
2880 nv_wr32(priv, 0x40780c + (i * 4), data[i]);
2881
2882
2883 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
2884 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
2885 tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
2886
2887 for (i = 0, gpc = -1, b = -1; i < 32; i++) {
2888 a = (i * (priv->tpc_total - 1)) / 32;
2889 if (a != b) {
2890 b = a;
2891 do {
2892 gpc = (gpc + 1) % priv->gpc_nr;
2893 } while (!tpcnr[gpc]);
2894 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
2895
2896 tpc_set |= 1 << ((gpc * 8) + tpc);
2897 }
2898
2899 nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set);
2900 nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask);
2901 }
2902
2903 for (i = 0; i < 8; i++)
2904 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
2905
2906 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
2907 if (priv->gpc_nr == 1) {
2908 nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
2909 nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
2910 } else {
2911 nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
2912 nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
2913 }
2914 nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
2915
2916 nve0_grctx_generate_icmd(priv);
2917 nve0_grctx_generate_a097(priv);
2918 nve0_grctx_generate_902d(priv);
2919
2920 nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
2921 nv_wr32(priv, 0x418800, 0x7026860a); //XXX
2922 nv_wr32(priv, 0x41be10, 0x00bb8bc7); //XXX
2923 return nvc0_grctx_fini(&info);
2924}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
new file mode 100644
index 000000000000..e2de73ee5eee
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -0,0 +1,1018 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27struct nvc0_graph_init
28nve4_grctx_init_icmd[] = {
29 { 0x001000, 1, 0x01, 0x00000004 },
30 { 0x000039, 3, 0x01, 0x00000000 },
31 { 0x0000a9, 1, 0x01, 0x0000ffff },
32 { 0x000038, 1, 0x01, 0x0fac6881 },
33 { 0x00003d, 1, 0x01, 0x00000001 },
34 { 0x0000e8, 8, 0x01, 0x00000400 },
35 { 0x000078, 8, 0x01, 0x00000300 },
36 { 0x000050, 1, 0x01, 0x00000011 },
37 { 0x000058, 8, 0x01, 0x00000008 },
38 { 0x000208, 8, 0x01, 0x00000001 },
39 { 0x000081, 1, 0x01, 0x00000001 },
40 { 0x000085, 1, 0x01, 0x00000004 },
41 { 0x000088, 1, 0x01, 0x00000400 },
42 { 0x000090, 1, 0x01, 0x00000300 },
43 { 0x000098, 1, 0x01, 0x00001001 },
44 { 0x0000e3, 1, 0x01, 0x00000001 },
45 { 0x0000da, 1, 0x01, 0x00000001 },
46 { 0x0000f8, 1, 0x01, 0x00000003 },
47 { 0x0000fa, 1, 0x01, 0x00000001 },
48 { 0x00009f, 4, 0x01, 0x0000ffff },
49 { 0x0000b1, 1, 0x01, 0x00000001 },
50 { 0x0000ad, 1, 0x01, 0x0000013e },
51 { 0x0000e1, 1, 0x01, 0x00000010 },
52 { 0x000290, 16, 0x01, 0x00000000 },
53 { 0x0003b0, 16, 0x01, 0x00000000 },
54 { 0x0002a0, 16, 0x01, 0x00000000 },
55 { 0x000420, 16, 0x01, 0x00000000 },
56 { 0x0002b0, 16, 0x01, 0x00000000 },
57 { 0x000430, 16, 0x01, 0x00000000 },
58 { 0x0002c0, 16, 0x01, 0x00000000 },
59 { 0x0004d0, 16, 0x01, 0x00000000 },
60 { 0x000720, 16, 0x01, 0x00000000 },
61 { 0x0008c0, 16, 0x01, 0x00000000 },
62 { 0x000890, 16, 0x01, 0x00000000 },
63 { 0x0008e0, 16, 0x01, 0x00000000 },
64 { 0x0008a0, 16, 0x01, 0x00000000 },
65 { 0x0008f0, 16, 0x01, 0x00000000 },
66 { 0x00094c, 1, 0x01, 0x000000ff },
67 { 0x00094d, 1, 0x01, 0xffffffff },
68 { 0x00094e, 1, 0x01, 0x00000002 },
69 { 0x0002ec, 1, 0x01, 0x00000001 },
70 { 0x000303, 1, 0x01, 0x00000001 },
71 { 0x0002e6, 1, 0x01, 0x00000001 },
72 { 0x000466, 1, 0x01, 0x00000052 },
73 { 0x000301, 1, 0x01, 0x3f800000 },
74 { 0x000304, 1, 0x01, 0x30201000 },
75 { 0x000305, 1, 0x01, 0x70605040 },
76 { 0x000306, 1, 0x01, 0xb8a89888 },
77 { 0x000307, 1, 0x01, 0xf8e8d8c8 },
78 { 0x00030a, 1, 0x01, 0x00ffff00 },
79 { 0x00030b, 1, 0x01, 0x0000001a },
80 { 0x00030c, 1, 0x01, 0x00000001 },
81 { 0x000318, 1, 0x01, 0x00000001 },
82 { 0x000340, 1, 0x01, 0x00000000 },
83 { 0x000375, 1, 0x01, 0x00000001 },
84 { 0x00037d, 1, 0x01, 0x00000006 },
85 { 0x0003a0, 1, 0x01, 0x00000002 },
86 { 0x0003aa, 1, 0x01, 0x00000001 },
87 { 0x0003a9, 1, 0x01, 0x00000001 },
88 { 0x000380, 1, 0x01, 0x00000001 },
89 { 0x000383, 1, 0x01, 0x00000011 },
90 { 0x000360, 1, 0x01, 0x00000040 },
91 { 0x000366, 2, 0x01, 0x00000000 },
92 { 0x000368, 1, 0x01, 0x00000fff },
93 { 0x000370, 2, 0x01, 0x00000000 },
94 { 0x000372, 1, 0x01, 0x000fffff },
95 { 0x00037a, 1, 0x01, 0x00000012 },
96 { 0x000619, 1, 0x01, 0x00000003 },
97 { 0x000811, 1, 0x01, 0x00000003 },
98 { 0x000812, 1, 0x01, 0x00000004 },
99 { 0x000813, 1, 0x01, 0x00000006 },
100 { 0x000814, 1, 0x01, 0x00000008 },
101 { 0x000815, 1, 0x01, 0x0000000b },
102 { 0x000800, 6, 0x01, 0x00000001 },
103 { 0x000632, 1, 0x01, 0x00000001 },
104 { 0x000633, 1, 0x01, 0x00000002 },
105 { 0x000634, 1, 0x01, 0x00000003 },
106 { 0x000635, 1, 0x01, 0x00000004 },
107 { 0x000654, 1, 0x01, 0x3f800000 },
108 { 0x000657, 1, 0x01, 0x3f800000 },
109 { 0x000655, 2, 0x01, 0x3f800000 },
110 { 0x0006cd, 1, 0x01, 0x3f800000 },
111 { 0x0007f5, 1, 0x01, 0x3f800000 },
112 { 0x0007dc, 1, 0x01, 0x39291909 },
113 { 0x0007dd, 1, 0x01, 0x79695949 },
114 { 0x0007de, 1, 0x01, 0xb9a99989 },
115 { 0x0007df, 1, 0x01, 0xf9e9d9c9 },
116 { 0x0007e8, 1, 0x01, 0x00003210 },
117 { 0x0007e9, 1, 0x01, 0x00007654 },
118 { 0x0007ea, 1, 0x01, 0x00000098 },
119 { 0x0007ec, 1, 0x01, 0x39291909 },
120 { 0x0007ed, 1, 0x01, 0x79695949 },
121 { 0x0007ee, 1, 0x01, 0xb9a99989 },
122 { 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
123 { 0x0007f0, 1, 0x01, 0x00003210 },
124 { 0x0007f1, 1, 0x01, 0x00007654 },
125 { 0x0007f2, 1, 0x01, 0x00000098 },
126 { 0x0005a5, 1, 0x01, 0x00000001 },
127 { 0x000980, 128, 0x01, 0x00000000 },
128 { 0x000468, 1, 0x01, 0x00000004 },
129 { 0x00046c, 1, 0x01, 0x00000001 },
130 { 0x000470, 96, 0x01, 0x00000000 },
131 { 0x000510, 16, 0x01, 0x3f800000 },
132 { 0x000520, 1, 0x01, 0x000002b6 },
133 { 0x000529, 1, 0x01, 0x00000001 },
134 { 0x000530, 16, 0x01, 0xffff0000 },
135 { 0x000585, 1, 0x01, 0x0000003f },
136 { 0x000576, 1, 0x01, 0x00000003 },
137 { 0x00057b, 1, 0x01, 0x00000059 },
138 { 0x000586, 1, 0x01, 0x00000040 },
139 { 0x000582, 2, 0x01, 0x00000080 },
140 { 0x0005c2, 1, 0x01, 0x00000001 },
141 { 0x000638, 1, 0x01, 0x00000001 },
142 { 0x000639, 1, 0x01, 0x00000001 },
143 { 0x00063a, 1, 0x01, 0x00000002 },
144 { 0x00063b, 2, 0x01, 0x00000001 },
145 { 0x00063d, 1, 0x01, 0x00000002 },
146 { 0x00063e, 1, 0x01, 0x00000001 },
147 { 0x0008b8, 8, 0x01, 0x00000001 },
148 { 0x000900, 8, 0x01, 0x00000001 },
149 { 0x000908, 8, 0x01, 0x00000002 },
150 { 0x000910, 16, 0x01, 0x00000001 },
151 { 0x000920, 8, 0x01, 0x00000002 },
152 { 0x000928, 8, 0x01, 0x00000001 },
153 { 0x000648, 9, 0x01, 0x00000001 },
154 { 0x000658, 1, 0x01, 0x0000000f },
155 { 0x0007ff, 1, 0x01, 0x0000000a },
156 { 0x00066a, 1, 0x01, 0x40000000 },
157 { 0x00066b, 1, 0x01, 0x10000000 },
158 { 0x00066c, 2, 0x01, 0xffff0000 },
159 { 0x0007af, 2, 0x01, 0x00000008 },
160 { 0x0007f6, 1, 0x01, 0x00000001 },
161 { 0x0006b2, 1, 0x01, 0x00000055 },
162 { 0x0007ad, 1, 0x01, 0x00000003 },
163 { 0x000937, 1, 0x01, 0x00000001 },
164 { 0x000971, 1, 0x01, 0x00000008 },
165 { 0x000972, 1, 0x01, 0x00000040 },
166 { 0x000973, 1, 0x01, 0x0000012c },
167 { 0x00097c, 1, 0x01, 0x00000040 },
168 { 0x000979, 1, 0x01, 0x00000003 },
169 { 0x000975, 1, 0x01, 0x00000020 },
170 { 0x000976, 1, 0x01, 0x00000001 },
171 { 0x000977, 1, 0x01, 0x00000020 },
172 { 0x000978, 1, 0x01, 0x00000001 },
173 { 0x000957, 1, 0x01, 0x00000003 },
174 { 0x00095e, 1, 0x01, 0x20164010 },
175 { 0x00095f, 1, 0x01, 0x00000020 },
176 { 0x00097d, 1, 0x01, 0x00000020 },
177 { 0x000683, 1, 0x01, 0x00000006 },
178 { 0x000685, 1, 0x01, 0x003fffff },
179 { 0x000687, 1, 0x01, 0x003fffff },
180 { 0x0006a0, 1, 0x01, 0x00000005 },
181 { 0x000840, 1, 0x01, 0x00400008 },
182 { 0x000841, 1, 0x01, 0x08000080 },
183 { 0x000842, 1, 0x01, 0x00400008 },
184 { 0x000843, 1, 0x01, 0x08000080 },
185 { 0x0006aa, 1, 0x01, 0x00000001 },
186 { 0x0006ab, 1, 0x01, 0x00000002 },
187 { 0x0006ac, 1, 0x01, 0x00000080 },
188 { 0x0006ad, 2, 0x01, 0x00000100 },
189 { 0x0006b1, 1, 0x01, 0x00000011 },
190 { 0x0006bb, 1, 0x01, 0x000000cf },
191 { 0x0006ce, 1, 0x01, 0x2a712488 },
192 { 0x000739, 1, 0x01, 0x4085c000 },
193 { 0x00073a, 1, 0x01, 0x00000080 },
194 { 0x000786, 1, 0x01, 0x80000100 },
195 { 0x00073c, 1, 0x01, 0x00010100 },
196 { 0x00073d, 1, 0x01, 0x02800000 },
197 { 0x000787, 1, 0x01, 0x000000cf },
198 { 0x00078c, 1, 0x01, 0x00000008 },
199 { 0x000792, 1, 0x01, 0x00000001 },
200 { 0x000794, 1, 0x01, 0x00000001 },
201 { 0x000795, 2, 0x01, 0x00000001 },
202 { 0x000797, 1, 0x01, 0x000000cf },
203 { 0x000836, 1, 0x01, 0x00000001 },
204 { 0x00079a, 1, 0x01, 0x00000002 },
205 { 0x000833, 1, 0x01, 0x04444480 },
206 { 0x0007a1, 1, 0x01, 0x00000001 },
207 { 0x0007a3, 1, 0x01, 0x00000001 },
208 { 0x0007a4, 2, 0x01, 0x00000001 },
209 { 0x000831, 1, 0x01, 0x00000004 },
210 { 0x000b07, 1, 0x01, 0x00000002 },
211 { 0x000b08, 2, 0x01, 0x00000100 },
212 { 0x000b0a, 1, 0x01, 0x00000001 },
213 { 0x000a04, 1, 0x01, 0x000000ff },
214 { 0x000a0b, 1, 0x01, 0x00000040 },
215 { 0x00097f, 1, 0x01, 0x00000100 },
216 { 0x000a02, 1, 0x01, 0x00000001 },
217 { 0x000809, 1, 0x01, 0x00000007 },
218 { 0x00c221, 1, 0x01, 0x00000040 },
219 { 0x00c1b0, 8, 0x01, 0x0000000f },
220 { 0x00c1b8, 1, 0x01, 0x0fac6881 },
221 { 0x00c1b9, 1, 0x01, 0x00fac688 },
222 { 0x00c401, 1, 0x01, 0x00000001 },
223 { 0x00c402, 1, 0x01, 0x00010001 },
224 { 0x00c403, 2, 0x01, 0x00000001 },
225 { 0x00c40e, 1, 0x01, 0x00000020 },
226 { 0x00c500, 1, 0x01, 0x00000003 },
227 { 0x01e100, 1, 0x01, 0x00000001 },
228 { 0x001000, 1, 0x01, 0x00000002 },
229 { 0x0006aa, 1, 0x01, 0x00000001 },
230 { 0x0006ad, 2, 0x01, 0x00000100 },
231 { 0x0006b1, 1, 0x01, 0x00000011 },
232 { 0x00078c, 1, 0x01, 0x00000008 },
233 { 0x000792, 1, 0x01, 0x00000001 },
234 { 0x000794, 1, 0x01, 0x00000001 },
235 { 0x000795, 2, 0x01, 0x00000001 },
236 { 0x000797, 1, 0x01, 0x000000cf },
237 { 0x00079a, 1, 0x01, 0x00000002 },
238 { 0x000833, 1, 0x01, 0x04444480 },
239 { 0x0007a1, 1, 0x01, 0x00000001 },
240 { 0x0007a3, 1, 0x01, 0x00000001 },
241 { 0x0007a4, 2, 0x01, 0x00000001 },
242 { 0x000831, 1, 0x01, 0x00000004 },
243 { 0x01e100, 1, 0x01, 0x00000001 },
244 { 0x001000, 1, 0x01, 0x00000008 },
245 { 0x000039, 3, 0x01, 0x00000000 },
246 { 0x000380, 1, 0x01, 0x00000001 },
247 { 0x000366, 2, 0x01, 0x00000000 },
248 { 0x000368, 1, 0x01, 0x00000fff },
249 { 0x000370, 2, 0x01, 0x00000000 },
250 { 0x000372, 1, 0x01, 0x000fffff },
251 { 0x000813, 1, 0x01, 0x00000006 },
252 { 0x000814, 1, 0x01, 0x00000008 },
253 { 0x000957, 1, 0x01, 0x00000003 },
254 { 0x000b07, 1, 0x01, 0x00000002 },
255 { 0x000b08, 2, 0x01, 0x00000100 },
256 { 0x000b0a, 1, 0x01, 0x00000001 },
257 { 0x000a04, 1, 0x01, 0x000000ff },
258 { 0x00097f, 1, 0x01, 0x00000100 },
259 { 0x000a02, 1, 0x01, 0x00000001 },
260 { 0x000809, 1, 0x01, 0x00000007 },
261 { 0x00c221, 1, 0x01, 0x00000040 },
262 { 0x00c401, 1, 0x01, 0x00000001 },
263 { 0x00c402, 1, 0x01, 0x00010001 },
264 { 0x00c403, 2, 0x01, 0x00000001 },
265 { 0x00c40e, 1, 0x01, 0x00000020 },
266 { 0x00c500, 1, 0x01, 0x00000003 },
267 { 0x01e100, 1, 0x01, 0x00000001 },
268 { 0x001000, 1, 0x01, 0x00000001 },
269 { 0x000b07, 1, 0x01, 0x00000002 },
270 { 0x000b08, 2, 0x01, 0x00000100 },
271 { 0x000b0a, 1, 0x01, 0x00000001 },
272 { 0x01e100, 1, 0x01, 0x00000001 },
273 {}
274};
275
276struct nvc0_graph_init
277nve4_grctx_init_a097[] = {
278 { 0x000800, 8, 0x40, 0x00000000 },
279 { 0x000804, 8, 0x40, 0x00000000 },
280 { 0x000808, 8, 0x40, 0x00000400 },
281 { 0x00080c, 8, 0x40, 0x00000300 },
282 { 0x000810, 1, 0x04, 0x000000cf },
283 { 0x000850, 7, 0x40, 0x00000000 },
284 { 0x000814, 8, 0x40, 0x00000040 },
285 { 0x000818, 8, 0x40, 0x00000001 },
286 { 0x00081c, 8, 0x40, 0x00000000 },
287 { 0x000820, 8, 0x40, 0x00000000 },
288 { 0x001c00, 16, 0x10, 0x00000000 },
289 { 0x001c04, 16, 0x10, 0x00000000 },
290 { 0x001c08, 16, 0x10, 0x00000000 },
291 { 0x001c0c, 16, 0x10, 0x00000000 },
292 { 0x001d00, 16, 0x10, 0x00000000 },
293 { 0x001d04, 16, 0x10, 0x00000000 },
294 { 0x001d08, 16, 0x10, 0x00000000 },
295 { 0x001d0c, 16, 0x10, 0x00000000 },
296 { 0x001f00, 16, 0x08, 0x00000000 },
297 { 0x001f04, 16, 0x08, 0x00000000 },
298 { 0x001f80, 16, 0x08, 0x00000000 },
299 { 0x001f84, 16, 0x08, 0x00000000 },
300 { 0x002000, 1, 0x04, 0x00000000 },
301 { 0x002040, 1, 0x04, 0x00000011 },
302 { 0x002080, 1, 0x04, 0x00000020 },
303 { 0x0020c0, 1, 0x04, 0x00000030 },
304 { 0x002100, 1, 0x04, 0x00000040 },
305 { 0x002140, 1, 0x04, 0x00000051 },
306 { 0x00200c, 6, 0x40, 0x00000001 },
307 { 0x002010, 1, 0x04, 0x00000000 },
308 { 0x002050, 1, 0x04, 0x00000000 },
309 { 0x002090, 1, 0x04, 0x00000001 },
310 { 0x0020d0, 1, 0x04, 0x00000002 },
311 { 0x002110, 1, 0x04, 0x00000003 },
312 { 0x002150, 1, 0x04, 0x00000004 },
313 { 0x000380, 4, 0x20, 0x00000000 },
314 { 0x000384, 4, 0x20, 0x00000000 },
315 { 0x000388, 4, 0x20, 0x00000000 },
316 { 0x00038c, 4, 0x20, 0x00000000 },
317 { 0x000700, 4, 0x10, 0x00000000 },
318 { 0x000704, 4, 0x10, 0x00000000 },
319 { 0x000708, 4, 0x10, 0x00000000 },
320 { 0x002800, 128, 0x04, 0x00000000 },
321 { 0x000a00, 16, 0x20, 0x00000000 },
322 { 0x000a04, 16, 0x20, 0x00000000 },
323 { 0x000a08, 16, 0x20, 0x00000000 },
324 { 0x000a0c, 16, 0x20, 0x00000000 },
325 { 0x000a10, 16, 0x20, 0x00000000 },
326 { 0x000a14, 16, 0x20, 0x00000000 },
327 { 0x000c00, 16, 0x10, 0x00000000 },
328 { 0x000c04, 16, 0x10, 0x00000000 },
329 { 0x000c08, 16, 0x10, 0x00000000 },
330 { 0x000c0c, 16, 0x10, 0x3f800000 },
331 { 0x000d00, 8, 0x08, 0xffff0000 },
332 { 0x000d04, 8, 0x08, 0xffff0000 },
333 { 0x000e00, 16, 0x10, 0x00000000 },
334 { 0x000e04, 16, 0x10, 0xffff0000 },
335 { 0x000e08, 16, 0x10, 0xffff0000 },
336 { 0x000d40, 4, 0x08, 0x00000000 },
337 { 0x000d44, 4, 0x08, 0x00000000 },
338 { 0x001e00, 8, 0x20, 0x00000001 },
339 { 0x001e04, 8, 0x20, 0x00000001 },
340 { 0x001e08, 8, 0x20, 0x00000002 },
341 { 0x001e0c, 8, 0x20, 0x00000001 },
342 { 0x001e10, 8, 0x20, 0x00000001 },
343 { 0x001e14, 8, 0x20, 0x00000002 },
344 { 0x001e18, 8, 0x20, 0x00000001 },
345 { 0x003400, 128, 0x04, 0x00000000 },
346 { 0x00030c, 1, 0x04, 0x00000001 },
347 { 0x001944, 1, 0x04, 0x00000000 },
348 { 0x001514, 1, 0x04, 0x00000000 },
349 { 0x000d68, 1, 0x04, 0x0000ffff },
350 { 0x00121c, 1, 0x04, 0x0fac6881 },
351 { 0x000fac, 1, 0x04, 0x00000001 },
352 { 0x001538, 1, 0x04, 0x00000001 },
353 { 0x000fe0, 2, 0x04, 0x00000000 },
354 { 0x000fe8, 1, 0x04, 0x00000014 },
355 { 0x000fec, 1, 0x04, 0x00000040 },
356 { 0x000ff0, 1, 0x04, 0x00000000 },
357 { 0x00179c, 1, 0x04, 0x00000000 },
358 { 0x001228, 1, 0x04, 0x00000400 },
359 { 0x00122c, 1, 0x04, 0x00000300 },
360 { 0x001230, 1, 0x04, 0x00010001 },
361 { 0x0007f8, 1, 0x04, 0x00000000 },
362 { 0x0015b4, 1, 0x04, 0x00000001 },
363 { 0x0015cc, 1, 0x04, 0x00000000 },
364 { 0x001534, 1, 0x04, 0x00000000 },
365 { 0x000fb0, 1, 0x04, 0x00000000 },
366 { 0x0015d0, 1, 0x04, 0x00000000 },
367 { 0x00153c, 1, 0x04, 0x00000000 },
368 { 0x0016b4, 1, 0x04, 0x00000003 },
369 { 0x000fbc, 4, 0x04, 0x0000ffff },
370 { 0x000df8, 2, 0x04, 0x00000000 },
371 { 0x001948, 1, 0x04, 0x00000000 },
372 { 0x001970, 1, 0x04, 0x00000001 },
373 { 0x00161c, 1, 0x04, 0x000009f0 },
374 { 0x000dcc, 1, 0x04, 0x00000010 },
375 { 0x00163c, 1, 0x04, 0x00000000 },
376 { 0x0015e4, 1, 0x04, 0x00000000 },
377 { 0x001160, 32, 0x04, 0x25e00040 },
378 { 0x001880, 32, 0x04, 0x00000000 },
379 { 0x000f84, 2, 0x04, 0x00000000 },
380 { 0x0017c8, 2, 0x04, 0x00000000 },
381 { 0x0017d0, 1, 0x04, 0x000000ff },
382 { 0x0017d4, 1, 0x04, 0xffffffff },
383 { 0x0017d8, 1, 0x04, 0x00000002 },
384 { 0x0017dc, 1, 0x04, 0x00000000 },
385 { 0x0015f4, 2, 0x04, 0x00000000 },
386 { 0x001434, 2, 0x04, 0x00000000 },
387 { 0x000d74, 1, 0x04, 0x00000000 },
388 { 0x000dec, 1, 0x04, 0x00000001 },
389 { 0x0013a4, 1, 0x04, 0x00000000 },
390 { 0x001318, 1, 0x04, 0x00000001 },
391 { 0x001644, 1, 0x04, 0x00000000 },
392 { 0x000748, 1, 0x04, 0x00000000 },
393 { 0x000de8, 1, 0x04, 0x00000000 },
394 { 0x001648, 1, 0x04, 0x00000000 },
395 { 0x0012a4, 1, 0x04, 0x00000000 },
396 { 0x001120, 4, 0x04, 0x00000000 },
397 { 0x001118, 1, 0x04, 0x00000000 },
398 { 0x00164c, 1, 0x04, 0x00000000 },
399 { 0x001658, 1, 0x04, 0x00000000 },
400 { 0x001910, 1, 0x04, 0x00000290 },
401 { 0x001518, 1, 0x04, 0x00000000 },
402 { 0x00165c, 1, 0x04, 0x00000001 },
403 { 0x001520, 1, 0x04, 0x00000000 },
404 { 0x001604, 1, 0x04, 0x00000000 },
405 { 0x001570, 1, 0x04, 0x00000000 },
406 { 0x0013b0, 2, 0x04, 0x3f800000 },
407 { 0x00020c, 1, 0x04, 0x00000000 },
408 { 0x001670, 1, 0x04, 0x30201000 },
409 { 0x001674, 1, 0x04, 0x70605040 },
410 { 0x001678, 1, 0x04, 0xb8a89888 },
411 { 0x00167c, 1, 0x04, 0xf8e8d8c8 },
412 { 0x00166c, 1, 0x04, 0x00000000 },
413 { 0x001680, 1, 0x04, 0x00ffff00 },
414 { 0x0012d0, 1, 0x04, 0x00000003 },
415 { 0x0012d4, 1, 0x04, 0x00000002 },
416 { 0x001684, 2, 0x04, 0x00000000 },
417 { 0x000dac, 2, 0x04, 0x00001b02 },
418 { 0x000db4, 1, 0x04, 0x00000000 },
419 { 0x00168c, 1, 0x04, 0x00000000 },
420 { 0x0015bc, 1, 0x04, 0x00000000 },
421 { 0x00156c, 1, 0x04, 0x00000000 },
422 { 0x00187c, 1, 0x04, 0x00000000 },
423 { 0x001110, 1, 0x04, 0x00000001 },
424 { 0x000dc0, 3, 0x04, 0x00000000 },
425 { 0x001234, 1, 0x04, 0x00000000 },
426 { 0x001690, 1, 0x04, 0x00000000 },
427 { 0x0012ac, 1, 0x04, 0x00000001 },
428 { 0x000790, 5, 0x04, 0x00000000 },
429 { 0x00077c, 1, 0x04, 0x00000000 },
430 { 0x001000, 1, 0x04, 0x00000010 },
431 { 0x0010fc, 1, 0x04, 0x00000000 },
432 { 0x001290, 1, 0x04, 0x00000000 },
433 { 0x000218, 1, 0x04, 0x00000010 },
434 { 0x0012d8, 1, 0x04, 0x00000000 },
435 { 0x0012dc, 1, 0x04, 0x00000010 },
436 { 0x000d94, 1, 0x04, 0x00000001 },
437 { 0x00155c, 2, 0x04, 0x00000000 },
438 { 0x001564, 1, 0x04, 0x00000fff },
439 { 0x001574, 2, 0x04, 0x00000000 },
440 { 0x00157c, 1, 0x04, 0x000fffff },
441 { 0x001354, 1, 0x04, 0x00000000 },
442 { 0x001610, 1, 0x04, 0x00000012 },
443 { 0x001608, 2, 0x04, 0x00000000 },
444 { 0x00260c, 1, 0x04, 0x00000000 },
445 { 0x0007ac, 1, 0x04, 0x00000000 },
446 { 0x00162c, 1, 0x04, 0x00000003 },
447 { 0x000210, 1, 0x04, 0x00000000 },
448 { 0x000320, 1, 0x04, 0x00000000 },
449 { 0x000324, 6, 0x04, 0x3f800000 },
450 { 0x000750, 1, 0x04, 0x00000000 },
451 { 0x000760, 1, 0x04, 0x39291909 },
452 { 0x000764, 1, 0x04, 0x79695949 },
453 { 0x000768, 1, 0x04, 0xb9a99989 },
454 { 0x00076c, 1, 0x04, 0xf9e9d9c9 },
455 { 0x000770, 1, 0x04, 0x30201000 },
456 { 0x000774, 1, 0x04, 0x70605040 },
457 { 0x000778, 1, 0x04, 0x00009080 },
458 { 0x000780, 1, 0x04, 0x39291909 },
459 { 0x000784, 1, 0x04, 0x79695949 },
460 { 0x000788, 1, 0x04, 0xb9a99989 },
461 { 0x00078c, 1, 0x04, 0xf9e9d9c9 },
462 { 0x0007d0, 1, 0x04, 0x30201000 },
463 { 0x0007d4, 1, 0x04, 0x70605040 },
464 { 0x0007d8, 1, 0x04, 0x00009080 },
465 { 0x00037c, 1, 0x04, 0x00000001 },
466 { 0x000740, 2, 0x04, 0x00000000 },
467 { 0x002600, 1, 0x04, 0x00000000 },
468 { 0x001918, 1, 0x04, 0x00000000 },
469 { 0x00191c, 1, 0x04, 0x00000900 },
470 { 0x001920, 1, 0x04, 0x00000405 },
471 { 0x001308, 1, 0x04, 0x00000001 },
472 { 0x001924, 1, 0x04, 0x00000000 },
473 { 0x0013ac, 1, 0x04, 0x00000000 },
474 { 0x00192c, 1, 0x04, 0x00000001 },
475 { 0x00193c, 1, 0x04, 0x00002c1c },
476 { 0x000d7c, 1, 0x04, 0x00000000 },
477 { 0x000f8c, 1, 0x04, 0x00000000 },
478 { 0x0002c0, 1, 0x04, 0x00000001 },
479 { 0x001510, 1, 0x04, 0x00000000 },
480 { 0x001940, 1, 0x04, 0x00000000 },
481 { 0x000ff4, 2, 0x04, 0x00000000 },
482 { 0x00194c, 2, 0x04, 0x00000000 },
483 { 0x001968, 1, 0x04, 0x00000000 },
484 { 0x001590, 1, 0x04, 0x0000003f },
485 { 0x0007e8, 4, 0x04, 0x00000000 },
486 { 0x00196c, 1, 0x04, 0x00000011 },
487 { 0x0002e4, 1, 0x04, 0x0000b001 },
488 { 0x00036c, 2, 0x04, 0x00000000 },
489 { 0x00197c, 1, 0x04, 0x00000000 },
490 { 0x000fcc, 2, 0x04, 0x00000000 },
491 { 0x0002d8, 1, 0x04, 0x00000040 },
492 { 0x001980, 1, 0x04, 0x00000080 },
493 { 0x001504, 1, 0x04, 0x00000080 },
494 { 0x001984, 1, 0x04, 0x00000000 },
495 { 0x000300, 1, 0x04, 0x00000001 },
496 { 0x0013a8, 1, 0x04, 0x00000000 },
497 { 0x0012ec, 1, 0x04, 0x00000000 },
498 { 0x001310, 1, 0x04, 0x00000000 },
499 { 0x001314, 1, 0x04, 0x00000001 },
500 { 0x001380, 1, 0x04, 0x00000000 },
501 { 0x001384, 4, 0x04, 0x00000001 },
502 { 0x001394, 1, 0x04, 0x00000000 },
503 { 0x00139c, 1, 0x04, 0x00000000 },
504 { 0x001398, 1, 0x04, 0x00000000 },
505 { 0x001594, 1, 0x04, 0x00000000 },
506 { 0x001598, 4, 0x04, 0x00000001 },
507 { 0x000f54, 3, 0x04, 0x00000000 },
508 { 0x0019bc, 1, 0x04, 0x00000000 },
509 { 0x000f9c, 2, 0x04, 0x00000000 },
510 { 0x0012cc, 1, 0x04, 0x00000000 },
511 { 0x0012e8, 1, 0x04, 0x00000000 },
512 { 0x00130c, 1, 0x04, 0x00000001 },
513 { 0x001360, 8, 0x04, 0x00000000 },
514 { 0x00133c, 2, 0x04, 0x00000001 },
515 { 0x001344, 1, 0x04, 0x00000002 },
516 { 0x001348, 2, 0x04, 0x00000001 },
517 { 0x001350, 1, 0x04, 0x00000002 },
518 { 0x001358, 1, 0x04, 0x00000001 },
519 { 0x0012e4, 1, 0x04, 0x00000000 },
520 { 0x00131c, 1, 0x04, 0x00000000 },
521 { 0x001320, 3, 0x04, 0x00000000 },
522 { 0x0019c0, 1, 0x04, 0x00000000 },
523 { 0x001140, 1, 0x04, 0x00000000 },
524 { 0x0019c4, 1, 0x04, 0x00000000 },
525 { 0x0019c8, 1, 0x04, 0x00001500 },
526 { 0x00135c, 1, 0x04, 0x00000000 },
527 { 0x000f90, 1, 0x04, 0x00000000 },
528 { 0x0019e0, 8, 0x04, 0x00000001 },
529 { 0x0019cc, 1, 0x04, 0x00000001 },
530 { 0x0015b8, 1, 0x04, 0x00000000 },
531 { 0x001a00, 1, 0x04, 0x00001111 },
532 { 0x001a04, 7, 0x04, 0x00000000 },
533 { 0x000d6c, 2, 0x04, 0xffff0000 },
534 { 0x0010f8, 1, 0x04, 0x00001010 },
535 { 0x000d80, 5, 0x04, 0x00000000 },
536 { 0x000da0, 1, 0x04, 0x00000000 },
537 { 0x0007a4, 2, 0x04, 0x00000000 },
538 { 0x001508, 1, 0x04, 0x80000000 },
539 { 0x00150c, 1, 0x04, 0x40000000 },
540 { 0x001668, 1, 0x04, 0x00000000 },
541 { 0x000318, 2, 0x04, 0x00000008 },
542 { 0x000d9c, 1, 0x04, 0x00000001 },
543 { 0x000374, 1, 0x04, 0x00000000 },
544 { 0x000378, 1, 0x04, 0x00000020 },
545 { 0x0007dc, 1, 0x04, 0x00000000 },
546 { 0x00074c, 1, 0x04, 0x00000055 },
547 { 0x001420, 1, 0x04, 0x00000003 },
548 { 0x0017bc, 2, 0x04, 0x00000000 },
549 { 0x0017c4, 1, 0x04, 0x00000001 },
550 { 0x001008, 1, 0x04, 0x00000008 },
551 { 0x00100c, 1, 0x04, 0x00000040 },
552 { 0x001010, 1, 0x04, 0x0000012c },
553 { 0x000d60, 1, 0x04, 0x00000040 },
554 { 0x00075c, 1, 0x04, 0x00000003 },
555 { 0x001018, 1, 0x04, 0x00000020 },
556 { 0x00101c, 1, 0x04, 0x00000001 },
557 { 0x001020, 1, 0x04, 0x00000020 },
558 { 0x001024, 1, 0x04, 0x00000001 },
559 { 0x001444, 3, 0x04, 0x00000000 },
560 { 0x000360, 1, 0x04, 0x20164010 },
561 { 0x000364, 1, 0x04, 0x00000020 },
562 { 0x000368, 1, 0x04, 0x00000000 },
563 { 0x000de4, 1, 0x04, 0x00000000 },
564 { 0x000204, 1, 0x04, 0x00000006 },
565 { 0x000208, 1, 0x04, 0x00000000 },
566 { 0x0002cc, 2, 0x04, 0x003fffff },
567 { 0x001220, 1, 0x04, 0x00000005 },
568 { 0x000fdc, 1, 0x04, 0x00000000 },
569 { 0x000f98, 1, 0x04, 0x00400008 },
570 { 0x001284, 1, 0x04, 0x08000080 },
571 { 0x001450, 1, 0x04, 0x00400008 },
572 { 0x001454, 1, 0x04, 0x08000080 },
573 { 0x000214, 1, 0x04, 0x00000000 },
574 {}
575};
576
577static struct nvc0_graph_init
578nve4_grctx_init_unk40xx[] = {
579 { 0x404010, 5, 0x04, 0x00000000 },
580 { 0x404024, 1, 0x04, 0x0000e000 },
581 { 0x404028, 1, 0x04, 0x00000000 },
582 { 0x4040a8, 1, 0x04, 0x00000000 },
583 { 0x4040ac, 7, 0x04, 0x00000000 },
584 { 0x4040c8, 1, 0x04, 0xf800008f },
585 { 0x4040d0, 6, 0x04, 0x00000000 },
586 { 0x4040e8, 1, 0x04, 0x00001000 },
587 { 0x4040f8, 1, 0x04, 0x00000000 },
588 { 0x404130, 1, 0x04, 0x00000000 },
589 { 0x404134, 1, 0x04, 0x00000000 },
590 { 0x404138, 1, 0x04, 0x20000040 },
591 { 0x404150, 1, 0x04, 0x0000002e },
592 { 0x404154, 1, 0x04, 0x00000400 },
593 { 0x404158, 1, 0x04, 0x00000200 },
594 { 0x404164, 1, 0x04, 0x00000055 },
595 { 0x4041a0, 4, 0x04, 0x00000000 },
596 { 0x404200, 4, 0x04, 0x00000000 },
597 {}
598};
599
600struct nvc0_graph_init
601nve4_grctx_init_unk46xx[] = {
602 { 0x404604, 1, 0x04, 0x00000014 },
603 { 0x404608, 1, 0x04, 0x00000000 },
604 { 0x40460c, 1, 0x04, 0x00003fff },
605 { 0x404610, 1, 0x04, 0x00000100 },
606 { 0x404618, 4, 0x04, 0x00000000 },
607 { 0x40462c, 2, 0x04, 0x00000000 },
608 { 0x404640, 1, 0x04, 0x00000000 },
609 { 0x404654, 1, 0x04, 0x00000000 },
610 { 0x404660, 1, 0x04, 0x00000000 },
611 { 0x404678, 1, 0x04, 0x00000000 },
612 { 0x40467c, 1, 0x04, 0x00000002 },
613 { 0x404680, 8, 0x04, 0x00000000 },
614 { 0x4046a0, 1, 0x04, 0x007f0080 },
615 { 0x4046a4, 8, 0x04, 0x00000000 },
616 { 0x4046c8, 3, 0x04, 0x00000000 },
617 {}
618};
619
620struct nvc0_graph_init
621nve4_grctx_init_unk47xx[] = {
622 { 0x404700, 3, 0x04, 0x00000000 },
623 { 0x404718, 7, 0x04, 0x00000000 },
624 { 0x404734, 1, 0x04, 0x00000100 },
625 { 0x404738, 2, 0x04, 0x00000000 },
626 { 0x404744, 2, 0x04, 0x00000000 },
627 { 0x404754, 1, 0x04, 0x00000000 },
628 {}
629};
630
631struct nvc0_graph_init
632nve4_grctx_init_unk58xx[] = {
633 { 0x405800, 1, 0x04, 0x0f8000bf },
634 { 0x405830, 1, 0x04, 0x02180648 },
635 { 0x405834, 1, 0x04, 0x08000000 },
636 { 0x405838, 1, 0x04, 0x00000000 },
637 { 0x405854, 1, 0x04, 0x00000000 },
638 { 0x405870, 4, 0x04, 0x00000001 },
639 { 0x405a00, 2, 0x04, 0x00000000 },
640 { 0x405a18, 1, 0x04, 0x00000000 },
641 {}
642};
643
644static struct nvc0_graph_init
645nve4_grctx_init_unk5bxx[] = {
646 { 0x405b00, 1, 0x04, 0x00000000 },
647 { 0x405b10, 1, 0x04, 0x00001000 },
648 {}
649};
650
651static struct nvc0_graph_init
652nve4_grctx_init_unk60xx[] = {
653 { 0x406020, 1, 0x04, 0x004103c1 },
654 { 0x406028, 4, 0x04, 0x00000001 },
655 {}
656};
657
658static struct nvc0_graph_init
659nve4_grctx_init_unk64xx[] = {
660 { 0x4064a8, 1, 0x04, 0x00000000 },
661 { 0x4064ac, 1, 0x04, 0x00003fff },
662 { 0x4064b4, 2, 0x04, 0x00000000 },
663 { 0x4064c0, 1, 0x04, 0x801a00f0 },
664 { 0x4064c4, 1, 0x04, 0x0192ffff },
665 { 0x4064c8, 1, 0x04, 0x01800600 },
666 { 0x4064cc, 9, 0x04, 0x00000000 },
667 { 0x4064fc, 1, 0x04, 0x0000022a },
668 {}
669};
670
671static struct nvc0_graph_init
672nve4_grctx_init_unk70xx[] = {
673 { 0x407040, 1, 0x04, 0x00000000 },
674 {}
675};
676
677struct nvc0_graph_init
678nve4_grctx_init_unk80xx[] = {
679 { 0x408000, 2, 0x04, 0x00000000 },
680 { 0x408008, 1, 0x04, 0x00000030 },
681 { 0x40800c, 2, 0x04, 0x00000000 },
682 { 0x408014, 1, 0x04, 0x00000069 },
683 { 0x408018, 1, 0x04, 0xe100e100 },
684 { 0x408064, 1, 0x04, 0x00000000 },
685 {}
686};
687
688static struct nvc0_graph_init
689nve4_grctx_init_rop[] = {
690 { 0x408800, 1, 0x04, 0x02802a3c },
691 { 0x408804, 1, 0x04, 0x00000040 },
692 { 0x408808, 1, 0x04, 0x1043e005 },
693 { 0x408840, 1, 0x04, 0x0000000b },
694 { 0x408900, 1, 0x04, 0x3080b801 },
695 { 0x408904, 1, 0x04, 0x62000001 },
696 { 0x408908, 1, 0x04, 0x00c8102f },
697 { 0x408980, 1, 0x04, 0x0000011d },
698 {}
699};
700
701static struct nvc0_graph_init
702nve4_grctx_init_gpc_0[] = {
703 { 0x418380, 1, 0x04, 0x00000016 },
704 { 0x418400, 1, 0x04, 0x38004e00 },
705 { 0x418404, 1, 0x04, 0x71e0ffff },
706 { 0x41840c, 1, 0x04, 0x00001008 },
707 { 0x418410, 1, 0x04, 0x0fff0fff },
708 { 0x418414, 1, 0x04, 0x02200fff },
709 { 0x418450, 6, 0x04, 0x00000000 },
710 { 0x418468, 1, 0x04, 0x00000001 },
711 { 0x41846c, 2, 0x04, 0x00000000 },
712 { 0x418600, 1, 0x04, 0x0000001f },
713 { 0x418684, 1, 0x04, 0x0000000f },
714 { 0x418700, 1, 0x04, 0x00000002 },
715 { 0x418704, 1, 0x04, 0x00000080 },
716 { 0x418708, 3, 0x04, 0x00000000 },
717 { 0x418800, 1, 0x04, 0x7006860a },
718 { 0x418808, 3, 0x04, 0x00000000 },
719 { 0x418828, 1, 0x04, 0x00000044 },
720 { 0x418830, 1, 0x04, 0x10000001 },
721 { 0x4188d8, 1, 0x04, 0x00000008 },
722 { 0x4188e0, 1, 0x04, 0x01000000 },
723 { 0x4188e8, 5, 0x04, 0x00000000 },
724 { 0x4188fc, 1, 0x04, 0x20100018 },
725 { 0x41891c, 1, 0x04, 0x00ff00ff },
726 { 0x418924, 1, 0x04, 0x00000000 },
727 { 0x418928, 1, 0x04, 0x00ffff00 },
728 { 0x41892c, 1, 0x04, 0x0000ff00 },
729 { 0x418b00, 1, 0x04, 0x00000006 },
730 { 0x418b08, 1, 0x04, 0x0a418820 },
731 { 0x418b0c, 1, 0x04, 0x062080e6 },
732 { 0x418b10, 1, 0x04, 0x020398a4 },
733 { 0x418b14, 1, 0x04, 0x0e629062 },
734 { 0x418b18, 1, 0x04, 0x0a418820 },
735 { 0x418b1c, 1, 0x04, 0x000000e6 },
736 { 0x418bb8, 1, 0x04, 0x00000103 },
737 { 0x418c08, 1, 0x04, 0x00000001 },
738 { 0x418c10, 8, 0x04, 0x00000000 },
739 { 0x418c40, 1, 0x04, 0xffffffff },
740 { 0x418c6c, 1, 0x04, 0x00000001 },
741 { 0x418c80, 1, 0x04, 0x20200004 },
742 { 0x418c8c, 1, 0x04, 0x00000001 },
743 { 0x419000, 1, 0x04, 0x00000780 },
744 { 0x419004, 2, 0x04, 0x00000000 },
745 { 0x419014, 1, 0x04, 0x00000004 },
746 {}
747};
748
749static struct nvc0_graph_init
750nve4_grctx_init_tpc[] = {
751 { 0x419848, 1, 0x04, 0x00000000 },
752 { 0x419864, 1, 0x04, 0x00000129 },
753 { 0x419888, 1, 0x04, 0x00000000 },
754 { 0x419a00, 1, 0x04, 0x000000f0 },
755 { 0x419a04, 1, 0x04, 0x00000001 },
756 { 0x419a08, 1, 0x04, 0x00000021 },
757 { 0x419a0c, 1, 0x04, 0x00020000 },
758 { 0x419a10, 1, 0x04, 0x00000000 },
759 { 0x419a14, 1, 0x04, 0x00000200 },
760 { 0x419a1c, 1, 0x04, 0x0000c000 },
761 { 0x419a20, 1, 0x04, 0x00000800 },
762 { 0x419a30, 1, 0x04, 0x00000001 },
763 { 0x419ac4, 1, 0x04, 0x0037f440 },
764 { 0x419c00, 1, 0x04, 0x0000000a },
765 { 0x419c04, 1, 0x04, 0x80000006 },
766 { 0x419c08, 1, 0x04, 0x00000002 },
767 { 0x419c20, 1, 0x04, 0x00000000 },
768 { 0x419c24, 1, 0x04, 0x00084210 },
769 { 0x419c28, 1, 0x04, 0x3efbefbe },
770 { 0x419ce8, 1, 0x04, 0x00000000 },
771 { 0x419cf4, 1, 0x04, 0x00003203 },
772 { 0x419e04, 3, 0x04, 0x00000000 },
773 { 0x419e10, 1, 0x04, 0x00000402 },
774 { 0x419e44, 1, 0x04, 0x0013eff2 },
775 { 0x419e48, 1, 0x04, 0x00000000 },
776 { 0x419e4c, 1, 0x04, 0x0000007f },
777 { 0x419e50, 19, 0x04, 0x00000000 },
778 { 0x419eac, 1, 0x04, 0x00001f8f },
779 { 0x419eb0, 1, 0x04, 0x00000d3f },
780 { 0x419ec8, 1, 0x04, 0x0001304f },
781 { 0x419f30, 8, 0x04, 0x00000000 },
782 { 0x419f58, 1, 0x04, 0x00000000 },
783 { 0x419f70, 1, 0x04, 0x00000000 },
784 { 0x419f78, 1, 0x04, 0x0000000b },
785 { 0x419f7c, 1, 0x04, 0x0000027a },
786 {}
787};
788
789static struct nvc0_graph_init
790nve4_grctx_init_unk[] = {
791 { 0x41be24, 1, 0x04, 0x00000006 },
792 { 0x41bec0, 1, 0x04, 0x12180000 },
793 { 0x41bec4, 1, 0x04, 0x00037f7f },
794 { 0x41bee4, 1, 0x04, 0x06480430 },
795 { 0x41bf00, 1, 0x04, 0x0a418820 },
796 { 0x41bf04, 1, 0x04, 0x062080e6 },
797 { 0x41bf08, 1, 0x04, 0x020398a4 },
798 { 0x41bf0c, 1, 0x04, 0x0e629062 },
799 { 0x41bf10, 1, 0x04, 0x0a418820 },
800 { 0x41bf14, 1, 0x04, 0x000000e6 },
801 { 0x41bfd0, 1, 0x04, 0x00900103 },
802 { 0x41bfe0, 1, 0x04, 0x00400001 },
803 { 0x41bfe4, 1, 0x04, 0x00000000 },
804 {}
805};
806
807static void
808nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
809{
810 u32 magic[GPC_MAX][2];
811 u32 offset;
812 int gpc;
813
814 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
815 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
816 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
817 mmio_list(0x40800c, 0x00000000, 8, 1);
818 mmio_list(0x408010, 0x80000000, 0, 0);
819 mmio_list(0x419004, 0x00000000, 8, 1);
820 mmio_list(0x419008, 0x00000000, 0, 0);
821 mmio_list(0x4064cc, 0x80000000, 0, 0);
822 mmio_list(0x408004, 0x00000000, 8, 0);
823 mmio_list(0x408008, 0x80000030, 0, 0);
824 mmio_list(0x418808, 0x00000000, 8, 0);
825 mmio_list(0x41880c, 0x80000030, 0, 0);
826 mmio_list(0x4064c8, 0x01800600, 0, 0);
827 mmio_list(0x418810, 0x80000000, 12, 2);
828 mmio_list(0x419848, 0x10000000, 12, 2);
829
830 mmio_list(0x405830, 0x02180648, 0, 0);
831 mmio_list(0x4064c4, 0x0192ffff, 0, 0);
832
833 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
834 u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
835 u16 magic1 = 0x0648 * priv->tpc_nr[gpc];
836 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
837 magic[gpc][1] = 0x00000000 | (magic1 << 16);
838 offset += 0x0324 * priv->tpc_nr[gpc];
839 }
840
841 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
842 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
843 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
844 offset += 0x07ff * priv->tpc_nr[gpc];
845 }
846
847 mmio_list(0x17e91c, 0x06060609, 0, 0);
848 mmio_list(0x17e920, 0x00090a05, 0, 0);
849}
850
851void
852nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
853{
854 nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
855 nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
856 nv_mask(priv, 0x41be08, 0x00000004, 0x00000004);
857 nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
858 nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
859 nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
860}
861
862void
863nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
864{
865 u32 data[6] = {}, data2[2] = {};
866 u8 tpcnr[GPC_MAX];
867 u8 shift, ntpcv;
868 int gpc, tpc, i;
869
870 /* calculate first set of magics */
871 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
872
873 gpc = -1;
874 for (tpc = 0; tpc < priv->tpc_total; tpc++) {
875 do {
876 gpc = (gpc + 1) % priv->gpc_nr;
877 } while (!tpcnr[gpc]);
878 tpcnr[gpc]--;
879
880 data[tpc / 6] |= gpc << ((tpc % 6) * 5);
881 }
882
883 for (; tpc < 32; tpc++)
884 data[tpc / 6] |= 7 << ((tpc % 6) * 5);
885
886 /* and the second... */
887 shift = 0;
888 ntpcv = priv->tpc_total;
889 while (!(ntpcv & (1 << 4))) {
890 ntpcv <<= 1;
891 shift++;
892 }
893
894 data2[0] = (ntpcv << 16);
895 data2[0] |= (shift << 21);
896 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
897 for (i = 1; i < 7; i++)
898 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
899
900 /* GPC_BROADCAST */
901 nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
902 priv->magic_not_rop_nr);
903 for (i = 0; i < 6; i++)
904 nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
905
906 /* GPC_BROADCAST.TP_BROADCAST */
907 nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) |
908 priv->magic_not_rop_nr | data2[0]);
909 nv_wr32(priv, 0x41bfe4, data2[1]);
910 for (i = 0; i < 6; i++)
911 nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
912
913 /* UNK78xx */
914 nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
915 priv->magic_not_rop_nr);
916 for (i = 0; i < 6; i++)
917 nv_wr32(priv, 0x40780c + (i * 4), data[i]);
918}
919
920void
921nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
922{
923 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
924 int i;
925
926 nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
927
928 for (i = 0; oclass->hub[i]; i++)
929 nvc0_graph_mmio(priv, oclass->hub[i]);
930 for (i = 0; oclass->gpc[i]; i++)
931 nvc0_graph_mmio(priv, oclass->gpc[i]);
932
933 nv_wr32(priv, 0x404154, 0x00000000);
934
935 oclass->mods(priv, info);
936 oclass->unkn(priv);
937
938 nvc0_grctx_generate_tpcid(priv);
939 nvc0_grctx_generate_r406028(priv);
940 nve4_grctx_generate_r418bb8(priv);
941 nvc0_grctx_generate_r406800(priv);
942
943 for (i = 0; i < 8; i++)
944 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
945
946 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
947 if (priv->gpc_nr == 1) {
948 nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
949 nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
950 } else {
951 nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
952 nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
953 }
954 nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
955
956 nvc0_graph_icmd(priv, oclass->icmd);
957 nv_wr32(priv, 0x404154, 0x00000400);
958 nvc0_graph_mthd(priv, oclass->mthd);
959 nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
960
961 nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
962 nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
963}
964
965static struct nvc0_graph_init *
966nve4_grctx_init_hub[] = {
967 nvc0_grctx_init_base,
968 nve4_grctx_init_unk40xx,
969 nvc0_grctx_init_unk44xx,
970 nve4_grctx_init_unk46xx,
971 nve4_grctx_init_unk47xx,
972 nve4_grctx_init_unk58xx,
973 nve4_grctx_init_unk5bxx,
974 nve4_grctx_init_unk60xx,
975 nve4_grctx_init_unk64xx,
976 nve4_grctx_init_unk70xx,
977 nvc0_grctx_init_unk78xx,
978 nve4_grctx_init_unk80xx,
979 nve4_grctx_init_rop,
980 NULL
981};
982
983struct nvc0_graph_init *
984nve4_grctx_init_gpc[] = {
985 nve4_grctx_init_gpc_0,
986 nvc0_grctx_init_gpc_1,
987 nve4_grctx_init_tpc,
988 nve4_grctx_init_unk,
989 NULL
990};
991
992static struct nvc0_graph_mthd
993nve4_grctx_init_mthd[] = {
994 { 0xa097, nve4_grctx_init_a097, },
995 { 0x902d, nvc0_grctx_init_902d, },
996 { 0x902d, nvc0_grctx_init_mthd_magic, },
997 {}
998};
999
1000struct nouveau_oclass *
1001nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
1002 .base.handle = NV_ENGCTX(GR, 0xe4),
1003 .base.ofuncs = &(struct nouveau_ofuncs) {
1004 .ctor = nvc0_graph_context_ctor,
1005 .dtor = nvc0_graph_context_dtor,
1006 .init = _nouveau_graph_context_init,
1007 .fini = _nouveau_graph_context_fini,
1008 .rd32 = _nouveau_graph_context_rd32,
1009 .wr32 = _nouveau_graph_context_wr32,
1010 },
1011 .main = nve4_grctx_generate_main,
1012 .mods = nve4_grctx_generate_mods,
1013 .unkn = nve4_grctx_generate_unkn,
1014 .hub = nve4_grctx_init_hub,
1015 .gpc = nve4_grctx_init_gpc,
1016 .icmd = nve4_grctx_init_icmd,
1017 .mthd = nve4_grctx_init_mthd,
1018}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
new file mode 100644
index 000000000000..dcb2ebb8c29d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
@@ -0,0 +1,328 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27static struct nvc0_graph_init
28nvf0_grctx_init_unk40xx[] = {
29 { 0x404004, 8, 0x04, 0x00000000 },
30 { 0x404024, 1, 0x04, 0x0000e000 },
31 { 0x404028, 8, 0x04, 0x00000000 },
32 { 0x4040a8, 8, 0x04, 0x00000000 },
33 { 0x4040c8, 1, 0x04, 0xf800008f },
34 { 0x4040d0, 6, 0x04, 0x00000000 },
35 { 0x4040e8, 1, 0x04, 0x00001000 },
36 { 0x4040f8, 1, 0x04, 0x00000000 },
37 { 0x404100, 10, 0x04, 0x00000000 },
38 { 0x404130, 2, 0x04, 0x00000000 },
39 { 0x404138, 1, 0x04, 0x20000040 },
40 { 0x404150, 1, 0x04, 0x0000002e },
41 { 0x404154, 1, 0x04, 0x00000400 },
42 { 0x404158, 1, 0x04, 0x00000200 },
43 { 0x404164, 1, 0x04, 0x00000055 },
44 { 0x40417c, 2, 0x04, 0x00000000 },
45 { 0x4041a0, 4, 0x04, 0x00000000 },
46 { 0x404200, 1, 0x04, 0x0000a197 },
47 { 0x404204, 1, 0x04, 0x0000a1c0 },
48 { 0x404208, 1, 0x04, 0x0000a140 },
49 { 0x40420c, 1, 0x04, 0x0000902d },
50 {}
51};
52
53static struct nvc0_graph_init
54nvf0_grctx_init_unk44xx[] = {
55 { 0x404404, 12, 0x04, 0x00000000 },
56 { 0x404438, 1, 0x04, 0x00000000 },
57 { 0x404460, 2, 0x04, 0x00000000 },
58 { 0x404468, 1, 0x04, 0x00ffffff },
59 { 0x40446c, 1, 0x04, 0x00000000 },
60 { 0x404480, 1, 0x04, 0x00000001 },
61 { 0x404498, 1, 0x04, 0x00000001 },
62 {}
63};
64
65static struct nvc0_graph_init
66nvf0_grctx_init_unk5bxx[] = {
67 { 0x405b00, 1, 0x04, 0x00000000 },
68 { 0x405b10, 1, 0x04, 0x00001000 },
69 { 0x405b20, 1, 0x04, 0x04000000 },
70 {}
71};
72
73static struct nvc0_graph_init
74nvf0_grctx_init_unk60xx[] = {
75 { 0x406020, 1, 0x04, 0x034103c1 },
76 { 0x406028, 4, 0x04, 0x00000001 },
77 {}
78};
79
80static struct nvc0_graph_init
81nvf0_grctx_init_unk64xx[] = {
82 { 0x4064a8, 1, 0x04, 0x00000000 },
83 { 0x4064ac, 1, 0x04, 0x00003fff },
84 { 0x4064b0, 3, 0x04, 0x00000000 },
85 { 0x4064c0, 1, 0x04, 0x802000f0 },
86 { 0x4064c4, 1, 0x04, 0x0192ffff },
87 { 0x4064c8, 1, 0x04, 0x018007c0 },
88 { 0x4064cc, 9, 0x04, 0x00000000 },
89 { 0x4064fc, 1, 0x04, 0x0000022a },
90 {}
91};
92
93static struct nvc0_graph_init
94nvf0_grctx_init_unk88xx[] = {
95 { 0x408800, 1, 0x04, 0x12802a3c },
96 { 0x408804, 1, 0x04, 0x00000040 },
97 { 0x408808, 1, 0x04, 0x1003e005 },
98 { 0x408840, 1, 0x04, 0x0000000b },
99 { 0x408900, 1, 0x04, 0x3080b801 },
100 { 0x408904, 1, 0x04, 0x62000001 },
101 { 0x408908, 1, 0x04, 0x00c8102f },
102 { 0x408980, 1, 0x04, 0x0000011d },
103 {}
104};
105
106static struct nvc0_graph_init
107nvf0_grctx_init_gpc_0[] = {
108 { 0x418380, 1, 0x04, 0x00000016 },
109 { 0x418400, 1, 0x04, 0x38004e00 },
110 { 0x418404, 1, 0x04, 0x71e0ffff },
111 { 0x41840c, 1, 0x04, 0x00001008 },
112 { 0x418410, 1, 0x04, 0x0fff0fff },
113 { 0x418414, 1, 0x04, 0x02200fff },
114 { 0x418450, 6, 0x04, 0x00000000 },
115 { 0x418468, 1, 0x04, 0x00000001 },
116 { 0x41846c, 2, 0x04, 0x00000000 },
117 { 0x418600, 1, 0x04, 0x0000001f },
118 { 0x418684, 1, 0x04, 0x0000000f },
119 { 0x418700, 1, 0x04, 0x00000002 },
120 { 0x418704, 1, 0x04, 0x00000080 },
121 { 0x418708, 3, 0x04, 0x00000000 },
122 { 0x418800, 1, 0x04, 0x7006860a },
123 { 0x418808, 1, 0x04, 0x00000000 },
124 { 0x41880c, 1, 0x04, 0x00000030 },
125 { 0x418810, 1, 0x04, 0x00000000 },
126 { 0x418828, 1, 0x04, 0x00000044 },
127 { 0x418830, 1, 0x04, 0x10000001 },
128 { 0x4188d8, 1, 0x04, 0x00000008 },
129 { 0x4188e0, 1, 0x04, 0x01000000 },
130 { 0x4188e8, 5, 0x04, 0x00000000 },
131 { 0x4188fc, 1, 0x04, 0x20100018 },
132 { 0x41891c, 1, 0x04, 0x00ff00ff },
133 { 0x418924, 1, 0x04, 0x00000000 },
134 { 0x418928, 1, 0x04, 0x00ffff00 },
135 { 0x41892c, 1, 0x04, 0x0000ff00 },
136 { 0x418b00, 1, 0x04, 0x00000006 },
137 { 0x418b08, 1, 0x04, 0x0a418820 },
138 { 0x418b0c, 1, 0x04, 0x062080e6 },
139 { 0x418b10, 1, 0x04, 0x020398a4 },
140 { 0x418b14, 1, 0x04, 0x0e629062 },
141 { 0x418b18, 1, 0x04, 0x0a418820 },
142 { 0x418b1c, 1, 0x04, 0x000000e6 },
143 { 0x418bb8, 1, 0x04, 0x00000103 },
144 { 0x418c08, 1, 0x04, 0x00000001 },
145 { 0x418c10, 8, 0x04, 0x00000000 },
146 { 0x418c40, 1, 0x04, 0xffffffff },
147 { 0x418c6c, 1, 0x04, 0x00000001 },
148 { 0x418c80, 1, 0x04, 0x20200004 },
149 { 0x418c8c, 1, 0x04, 0x00000001 },
150 { 0x418d24, 1, 0x04, 0x00000000 },
151 { 0x419000, 1, 0x04, 0x00000780 },
152 { 0x419004, 2, 0x04, 0x00000000 },
153 { 0x419014, 1, 0x04, 0x00000004 },
154 {}
155};
156
157static struct nvc0_graph_init
158nvf0_grctx_init_tpc[] = {
159 { 0x419848, 1, 0x04, 0x00000000 },
160 { 0x419864, 1, 0x04, 0x00000129 },
161 { 0x419888, 1, 0x04, 0x00000000 },
162 { 0x419a00, 1, 0x04, 0x000000f0 },
163 { 0x419a04, 1, 0x04, 0x00000001 },
164 { 0x419a08, 1, 0x04, 0x00000021 },
165 { 0x419a0c, 1, 0x04, 0x00020000 },
166 { 0x419a10, 1, 0x04, 0x00000000 },
167 { 0x419a14, 1, 0x04, 0x00000200 },
168 { 0x419a1c, 1, 0x04, 0x0000c000 },
169 { 0x419a20, 1, 0x04, 0x00020800 },
170 { 0x419a30, 1, 0x04, 0x00000001 },
171 { 0x419ac4, 1, 0x04, 0x0037f440 },
172 { 0x419c00, 1, 0x04, 0x0000001a },
173 { 0x419c04, 1, 0x04, 0x80000006 },
174 { 0x419c08, 1, 0x04, 0x00000002 },
175 { 0x419c20, 1, 0x04, 0x00000000 },
176 { 0x419c24, 1, 0x04, 0x00084210 },
177 { 0x419c28, 1, 0x04, 0x3efbefbe },
178 { 0x419ce8, 1, 0x04, 0x00000000 },
179 { 0x419cf4, 1, 0x04, 0x00000203 },
180 { 0x419e04, 1, 0x04, 0x00000000 },
181 { 0x419e08, 1, 0x04, 0x0000001d },
182 { 0x419e0c, 1, 0x04, 0x00000000 },
183 { 0x419e10, 1, 0x04, 0x00001c02 },
184 { 0x419e44, 1, 0x04, 0x0013eff2 },
185 { 0x419e48, 1, 0x04, 0x00000000 },
186 { 0x419e4c, 1, 0x04, 0x0000007f },
187 { 0x419e50, 2, 0x04, 0x00000000 },
188 { 0x419e58, 1, 0x04, 0x00000001 },
189 { 0x419e5c, 3, 0x04, 0x00000000 },
190 { 0x419e68, 1, 0x04, 0x00000002 },
191 { 0x419e6c, 12, 0x04, 0x00000000 },
192 { 0x419eac, 1, 0x04, 0x00001fcf },
193 { 0x419eb0, 1, 0x04, 0x0db00da0 },
194 { 0x419eb8, 1, 0x04, 0x00000000 },
195 { 0x419ec8, 1, 0x04, 0x0001304f },
196 { 0x419f30, 4, 0x04, 0x00000000 },
197 { 0x419f40, 1, 0x04, 0x00000018 },
198 { 0x419f44, 3, 0x04, 0x00000000 },
199 { 0x419f58, 1, 0x04, 0x00000000 },
200 { 0x419f70, 1, 0x04, 0x00007300 },
201 { 0x419f78, 1, 0x04, 0x000000eb },
202 { 0x419f7c, 1, 0x04, 0x00000404 },
203 {}
204};
205
206static struct nvc0_graph_init
207nvf0_grctx_init_unk[] = {
208 { 0x41be24, 1, 0x04, 0x00000006 },
209 { 0x41bec0, 1, 0x04, 0x10000000 },
210 { 0x41bec4, 1, 0x04, 0x00037f7f },
211 { 0x41bee4, 1, 0x04, 0x00000000 },
212 { 0x41bf00, 1, 0x04, 0x0a418820 },
213 { 0x41bf04, 1, 0x04, 0x062080e6 },
214 { 0x41bf08, 1, 0x04, 0x020398a4 },
215 { 0x41bf0c, 1, 0x04, 0x0e629062 },
216 { 0x41bf10, 1, 0x04, 0x0a418820 },
217 { 0x41bf14, 1, 0x04, 0x000000e6 },
218 { 0x41bfd0, 1, 0x04, 0x00900103 },
219 { 0x41bfe0, 1, 0x04, 0x00400001 },
220 { 0x41bfe4, 1, 0x04, 0x00000000 },
221 {}
222};
223
224static void
225nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
226{
227 u32 magic[GPC_MAX][4];
228 u32 offset;
229 int gpc;
230
231 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
232 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
233 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
234 mmio_list(0x40800c, 0x00000000, 8, 1);
235 mmio_list(0x408010, 0x80000000, 0, 0);
236 mmio_list(0x419004, 0x00000000, 8, 1);
237 mmio_list(0x419008, 0x00000000, 0, 0);
238 mmio_list(0x4064cc, 0x80000000, 0, 0);
239 mmio_list(0x408004, 0x00000000, 8, 0);
240 mmio_list(0x408008, 0x80000030, 0, 0);
241 mmio_list(0x418808, 0x00000000, 8, 0);
242 mmio_list(0x41880c, 0x80000030, 0, 0);
243 mmio_list(0x4064c8, 0x01800600, 0, 0);
244 mmio_list(0x418810, 0x80000000, 12, 2);
245 mmio_list(0x419848, 0x10000000, 12, 2);
246
247 mmio_list(0x405830, 0x02180648, 0, 0);
248 mmio_list(0x4064c4, 0x0192ffff, 0, 0);
249
250 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
251 u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1);
252 u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1);
253 u16 magic2 = 0x0218;
254 u16 magic3 = 0x0648;
255 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
256 magic[gpc][1] = 0x00000000 | (magic1 << 16);
257 offset += 0x0324 * (priv->tpc_nr[gpc] - 1);;
258 magic[gpc][2] = 0x10000000 | (magic2 << 16) | offset;
259 magic[gpc][3] = 0x00000000 | (magic3 << 16);
260 offset += 0x0324;
261 }
262
263 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
264 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
265 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
266 offset += 0x07ff * (priv->tpc_nr[gpc] - 1);
267 mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0);
268 mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0);
269 offset += 0x07ff;
270 }
271
272 mmio_list(0x17e91c, 0x06060609, 0, 0);
273 mmio_list(0x17e920, 0x00090a05, 0, 0);
274}
275
276static struct nvc0_graph_init *
277nvf0_grctx_init_hub[] = {
278 nvc0_grctx_init_base,
279 nvf0_grctx_init_unk40xx,
280 nvf0_grctx_init_unk44xx,
281 nve4_grctx_init_unk46xx,
282 nve4_grctx_init_unk47xx,
283 nve4_grctx_init_unk58xx,
284 nvf0_grctx_init_unk5bxx,
285 nvf0_grctx_init_unk60xx,
286 nvf0_grctx_init_unk64xx,
287 nve4_grctx_init_unk80xx,
288 nvf0_grctx_init_unk88xx,
289 nvd9_grctx_init_rop,
290 NULL
291};
292
293struct nvc0_graph_init *
294nvf0_grctx_init_gpc[] = {
295 nvf0_grctx_init_gpc_0,
296 nvc0_grctx_init_gpc_1,
297 nvf0_grctx_init_tpc,
298 nvf0_grctx_init_unk,
299 NULL
300};
301
302static struct nvc0_graph_mthd
303nvf0_grctx_init_mthd[] = {
304 { 0xa197, nvc1_grctx_init_9097, },
305 { 0x902d, nvc0_grctx_init_902d, },
306 { 0x902d, nvc0_grctx_init_mthd_magic, },
307 {}
308};
309
310struct nouveau_oclass *
311nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
312 .base.handle = NV_ENGCTX(GR, 0xf0),
313 .base.ofuncs = &(struct nouveau_ofuncs) {
314 .ctor = nvc0_graph_context_ctor,
315 .dtor = nvc0_graph_context_dtor,
316 .init = _nouveau_graph_context_init,
317 .fini = _nouveau_graph_context_fini,
318 .rd32 = _nouveau_graph_context_rd32,
319 .wr32 = _nouveau_graph_context_wr32,
320 },
321 .main = nve4_grctx_generate_main,
322 .mods = nvf0_grctx_generate_mods,
323 .unkn = nve4_grctx_generate_unkn,
324 .hub = nvf0_grctx_init_hub,
325 .gpc = nvf0_grctx_init_gpc,
326 .icmd = nvc0_grctx_init_icmd,
327 .mthd = nvf0_grctx_init_mthd,
328}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
index da18885c559c..5d24b6de16cc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
@@ -149,13 +149,9 @@ watchdog_clear:
149// 149//
150wait_donez: 150wait_donez:
151 trace_set(T_WAIT); 151 trace_set(T_WAIT);
152 mov $r8 0x818 152 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
153 shl b32 $r8 6
154 iowr I[$r8 + 0x000] $r10
155 wait_donez_ne: 153 wait_donez_ne:
156 mov $r8 0x400 154 nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
157 shl b32 $r8 6
158 iord $r8 I[$r8 + 0x000]
159 xbit $r8 $r8 $r10 155 xbit $r8 $r8 $r10
160 bra ne #wait_donez_ne 156 bra ne #wait_donez_ne
161 trace_clr(T_WAIT) 157 trace_clr(T_WAIT)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
index 4770e8c99432..b52f4a8b8699 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -29,16 +29,26 @@
29 */ 29 */
30 30
31#ifdef INCLUDE_DATA 31#ifdef INCLUDE_DATA
32gpc_mmio_list_head: .b32 #mmio_list_base
33gpc_mmio_list_tail:
34tpc_mmio_list_head: .b32 #mmio_list_base
35tpc_mmio_list_tail:
36unk_mmio_list_head: .b32 #mmio_list_base
37unk_mmio_list_tail: .b32 #mmio_list_base
38
32gpc_id: .b32 0 39gpc_id: .b32 0
33gpc_mmio_list_head: .b32 0
34gpc_mmio_list_tail: .b32 0
35 40
36tpc_count: .b32 0 41tpc_count: .b32 0
37tpc_mask: .b32 0 42tpc_mask: .b32 0
38tpc_mmio_list_head: .b32 0 43
39tpc_mmio_list_tail: .b32 0 44#if NV_PGRAPH_GPCX_UNK__SIZE > 0
45unk_count: .b32 0
46unk_mask: .b32 0
47#endif
40 48
41cmd_queue: queue_init 49cmd_queue: queue_init
50
51mmio_list_base:
42#endif 52#endif
43 53
44#ifdef INCLUDE_CODE 54#ifdef INCLUDE_CODE
@@ -61,7 +71,6 @@ error:
61// fall through to main loop after completion. 71// fall through to main loop after completion.
62// 72//
63// Input: 73// Input:
64// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
65// CC_SCRATCH[1]: context base 74// CC_SCRATCH[1]: context base
66// 75//
67// Output: 76// Output:
@@ -106,26 +115,33 @@ init:
106 iord $r2 I[$r1 + 0x000] // MYINDEX 115 iord $r2 I[$r1 + 0x000] // MYINDEX
107 st b32 D[$r0 + #gpc_id] $r2 116 st b32 D[$r0 + #gpc_id] $r2
108 117
109 // find context data for this chipset 118#if NV_PGRAPH_GPCX_UNK__SIZE > 0
110 mov $r2 0x800 119 // figure out which, and how many, UNKs are actually present
111 shl b32 $r2 6 120 mov $r14 0x0c30
112 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0] 121 sethi $r14 0x500000
113 mov $r1 #chipsets - 12 122 clear b32 $r2
114 init_find_chipset: 123 clear b32 $r3
115 add b32 $r1 12 124 clear b32 $r4
116 ld b32 $r3 D[$r1 + 0x00] 125 init_unk_loop:
117 cmpu b32 $r3 $r2 126 call #nv_rd32
118 bra e #init_context 127 cmp b32 $r15 0
119 cmpu b32 $r3 0 128 bra z #init_unk_next
120 bra ne #init_find_chipset 129 mov $r15 1
121 // unknown chipset 130 shl b32 $r15 $r2
122 ret 131 or $r4 $r15
132 add b32 $r3 1
133 init_unk_next:
134 add b32 $r2 1
135 add b32 $r14 4
136 cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
137 bra ne #init_unk_loop
138 init_unk_done:
139 st b32 D[$r0 + #unk_count] $r3
140 st b32 D[$r0 + #unk_mask] $r4
141#endif
123 142
124 // initialise context base, and size tracking 143 // initialise context base, and size tracking
125 init_context: 144 nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
126 mov $r2 0x800
127 shl b32 $r2 6
128 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
129 clear b32 $r3 // track GPC context size here 145 clear b32 $r3 // track GPC context size here
130 146
131 // set mmctx base addresses now so we don't have to do it later, 147 // set mmctx base addresses now so we don't have to do it later,
@@ -136,30 +152,33 @@ init:
136 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE 152 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
137 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE 153 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
138 154
139 // calculate GPC mmio context size, store the chipset-specific 155 // calculate GPC mmio context size
140 // mmio list pointers somewhere we can get at them later without 156 ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
141 // re-parsing the chipset list 157 ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
142 clear b32 $r14
143 clear b32 $r15
144 ld b16 $r14 D[$r1 + 4]
145 ld b16 $r15 D[$r1 + 6]
146 st b16 D[$r0 + #gpc_mmio_list_head] $r14
147 st b16 D[$r0 + #gpc_mmio_list_tail] $r15
148 call #mmctx_size 158 call #mmctx_size
149 add b32 $r2 $r15 159 add b32 $r2 $r15
150 add b32 $r3 $r15 160 add b32 $r3 $r15
151 161
152 // calculate per-TPC mmio context size, store the list pointers 162 // calculate per-TPC mmio context size
153 ld b16 $r14 D[$r1 + 8] 163 ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
154 ld b16 $r15 D[$r1 + 10] 164 ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
155 st b16 D[$r0 + #tpc_mmio_list_head] $r14
156 st b16 D[$r0 + #tpc_mmio_list_tail] $r15
157 call #mmctx_size 165 call #mmctx_size
158 ld b32 $r14 D[$r0 + #tpc_count] 166 ld b32 $r14 D[$r0 + #tpc_count]
159 mulu $r14 $r15 167 mulu $r14 $r15
160 add b32 $r2 $r14 168 add b32 $r2 $r14
161 add b32 $r3 $r14 169 add b32 $r3 $r14
162 170
171#if NV_PGRAPH_GPCX_UNK__SIZE > 0
172 // calculate per-UNK mmio context size
173 ld b32 $r14 D[$r0 + #unk_mmio_list_head]
174 ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
175 call #mmctx_size
176 ld b32 $r14 D[$r0 + #unk_count]
177 mulu $r14 $r15
178 add b32 $r2 $r14
179 add b32 $r3 $r14
180#endif
181
163 // round up base/size to 256 byte boundary (for strand SWBASE) 182 // round up base/size to 256 byte boundary (for strand SWBASE)
164 add b32 $r4 0x1300 183 add b32 $r4 0x1300
165 shr b32 $r3 2 184 shr b32 $r3 2
@@ -177,13 +196,10 @@ init:
177 add b32 $r3 $r15 196 add b32 $r3 $r15
178 197
179 // save context size, and tell HUB we're done 198 // save context size, and tell HUB we're done
180 mov $r1 0x800 199 nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
181 shl b32 $r1 6
182 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
183 add b32 $r1 0x800
184 clear b32 $r2 200 clear b32 $r2
185 bset $r2 31 201 bset $r2 31
186 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 202 nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
187 203
188// Main program loop, very simple, sleeps until woken up by the interrupt 204// Main program loop, very simple, sleeps until woken up by the interrupt
189// handler, pulls a command from the queue and executes its handler 205// handler, pulls a command from the queue and executes its handler
@@ -228,6 +244,7 @@ ih:
228 push $r13 244 push $r13
229 push $r14 245 push $r14
230 push $r15 246 push $r15
247 clear b32 $r0
231 248
232 // incoming fifo command? 249 // incoming fifo command?
233 iord $r10 I[$r0 + 0x200] // INTR 250 iord $r10 I[$r0 + 0x200] // INTR
@@ -335,7 +352,6 @@ ctx_xfer:
335 352
336 // per-TPC mmio context 353 // per-TPC mmio context
337 xbit $r10 $flags $p1 // direction 354 xbit $r10 $flags $p1 // direction
338 or $r10 4 // last
339 mov $r11 0x4000 355 mov $r11 0x4000
340 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 356 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
341 ld b32 $r12 D[$r0 + #gpc_id] 357 ld b32 $r12 D[$r0 + #gpc_id]
@@ -347,6 +363,22 @@ ctx_xfer:
347 mov $r14 0x800 // stride = 0x800 363 mov $r14 0x800 // stride = 0x800
348 call #mmctx_xfer 364 call #mmctx_xfer
349 365
366#if NV_PGRAPH_GPCX_UNK__SIZE > 0
367 // per-UNK mmio context
368 xbit $r10 $flags $p1 // direction
369 or $r10 4 // last
370 mov $r11 0x3000
371 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0
372 ld b32 $r12 D[$r0 + #gpc_id]
373 shl b32 $r12 15
374 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
375 ld b32 $r12 D[$r0 + #unk_mmio_list_head]
376 ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
377 ld b32 $r15 D[$r0 + #unk_mask]
378 mov $r14 0x200 // stride = 0x200
379 call #mmctx_xfer
380#endif
381
350 // wait for strands to finish 382 // wait for strands to finish
351 call #strand_wait 383 call #strand_wait
352 384
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index c2d9e59bb58f..5ae06a2d64c9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -22,127 +22,15 @@
22 * Authors: Ben Skeggs <bskeggs@redhat.com> 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */ 23 */
24 24
25#define NVGF 25#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000
26
27#define CHIPSET GF100
26#include "macros.fuc" 28#include "macros.fuc"
27 29
28.section #nvc0_grgpc_data 30.section #nvc0_grgpc_data
29#define INCLUDE_DATA 31#define INCLUDE_DATA
30#include "com.fuc" 32#include "com.fuc"
31#include "gpc.fuc" 33#include "gpc.fuc"
32
33chipsets:
34.b8 0xc0 0 0 0
35.b16 #nvc0_gpc_mmio_head
36.b16 #nvc0_gpc_mmio_tail
37.b16 #nvc0_tpc_mmio_head
38.b16 #nvc0_tpc_mmio_tail
39.b8 0xc1 0 0 0
40.b16 #nvc0_gpc_mmio_head
41.b16 #nvc1_gpc_mmio_tail
42.b16 #nvc0_tpc_mmio_head
43.b16 #nvc1_tpc_mmio_tail
44.b8 0xc3 0 0 0
45.b16 #nvc0_gpc_mmio_head
46.b16 #nvc0_gpc_mmio_tail
47.b16 #nvc0_tpc_mmio_head
48.b16 #nvc3_tpc_mmio_tail
49.b8 0xc4 0 0 0
50.b16 #nvc0_gpc_mmio_head
51.b16 #nvc0_gpc_mmio_tail
52.b16 #nvc0_tpc_mmio_head
53.b16 #nvc3_tpc_mmio_tail
54.b8 0xc8 0 0 0
55.b16 #nvc0_gpc_mmio_head
56.b16 #nvc0_gpc_mmio_tail
57.b16 #nvc0_tpc_mmio_head
58.b16 #nvc0_tpc_mmio_tail
59.b8 0xce 0 0 0
60.b16 #nvc0_gpc_mmio_head
61.b16 #nvc0_gpc_mmio_tail
62.b16 #nvc0_tpc_mmio_head
63.b16 #nvc3_tpc_mmio_tail
64.b8 0xcf 0 0 0
65.b16 #nvc0_gpc_mmio_head
66.b16 #nvc0_gpc_mmio_tail
67.b16 #nvc0_tpc_mmio_head
68.b16 #nvc3_tpc_mmio_tail
69.b8 0xd9 0 0 0
70.b16 #nvd9_gpc_mmio_head
71.b16 #nvc1_gpc_mmio_tail
72.b16 #nvc0_tpc_mmio_head
73.b16 #nvd9_tpc_mmio_tail
74.b8 0xd7 0 0 0
75.b16 #nvd9_gpc_mmio_head
76.b16 #nvc1_gpc_mmio_tail
77.b16 #nvc0_tpc_mmio_head
78.b16 #nvd9_tpc_mmio_tail
79.b8 0 0 0 0
80
81// GPC mmio lists
82nvc0_gpc_mmio_head:
83mmctx_data(0x000408, 1)
84nvd9_gpc_mmio_head:
85mmctx_data(0x000380, 1)
86mmctx_data(0x000400, 2);
87mmctx_data(0x00040c, 3);
88mmctx_data(0x000450, 9)
89mmctx_data(0x000600, 1)
90mmctx_data(0x000684, 1)
91mmctx_data(0x000700, 5)
92mmctx_data(0x000800, 1)
93mmctx_data(0x000808, 3)
94mmctx_data(0x000828, 1)
95mmctx_data(0x000830, 1)
96mmctx_data(0x0008d8, 1)
97mmctx_data(0x0008e0, 1)
98mmctx_data(0x0008e8, 6)
99mmctx_data(0x00091c, 1)
100mmctx_data(0x000924, 3)
101mmctx_data(0x000b00, 1)
102mmctx_data(0x000b08, 6)
103mmctx_data(0x000bb8, 1)
104mmctx_data(0x000c08, 1)
105mmctx_data(0x000c10, 8)
106mmctx_data(0x000c80, 1)
107mmctx_data(0x000c8c, 1)
108mmctx_data(0x001000, 3)
109mmctx_data(0x001014, 1)
110nvc0_gpc_mmio_tail:
111mmctx_data(0x000c6c, 1);
112nvc1_gpc_mmio_tail:
113
114// TPC mmio lists
115nvc0_tpc_mmio_head:
116mmctx_data(0x000018, 1)
117mmctx_data(0x00003c, 1)
118mmctx_data(0x000048, 1)
119mmctx_data(0x000064, 1)
120mmctx_data(0x000088, 1)
121mmctx_data(0x000200, 6)
122mmctx_data(0x000300, 6)
123mmctx_data(0x0003d0, 1)
124mmctx_data(0x0003e0, 2)
125mmctx_data(0x000400, 3)
126mmctx_data(0x000420, 1)
127mmctx_data(0x0004b0, 1)
128mmctx_data(0x0004e8, 1)
129mmctx_data(0x0004f4, 1)
130mmctx_data(0x000520, 2)
131mmctx_data(0x000604, 4)
132mmctx_data(0x000644, 20)
133mmctx_data(0x000698, 1)
134mmctx_data(0x000750, 2)
135nvc0_tpc_mmio_tail:
136mmctx_data(0x00021c, 2)
137mmctx_data(0x0002c4, 1)
138mmctx_data(0x000730, 8)
139mmctx_data(0x000758, 1)
140nvc3_tpc_mmio_tail:
141mmctx_data(0x000544, 1)
142nvc1_tpc_mmio_tail:
143mmctx_data(0x000424, 2);
144mmctx_data(0x0006e0, 1);
145nvd9_tpc_mmio_tail:
146#undef INCLUDE_DATA 34#undef INCLUDE_DATA
147 35
148.section #nvc0_grgpc_code 36.section #nvc0_grgpc_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index 66ec1acaadee..2afe75ce89e9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -1,17 +1,19 @@
1uint32_t nvc0_grgpc_data[] = { 1uint32_t nvc0_grgpc_data[] = {
2/* 0x0000: gpc_id */ 2/* 0x0000: gpc_mmio_list_head */
3 0x00000000, 3 0x00000064,
4/* 0x0004: gpc_mmio_list_head */ 4/* 0x0004: gpc_mmio_list_tail */
5 0x00000000, 5/* 0x0004: tpc_mmio_list_head */
6/* 0x0008: gpc_mmio_list_tail */ 6 0x00000064,
7 0x00000000, 7/* 0x0008: tpc_mmio_list_tail */
8/* 0x000c: tpc_count */ 8/* 0x0008: unk_mmio_list_head */
9 0x00000000, 9 0x00000064,
10/* 0x0010: tpc_mask */ 10/* 0x000c: unk_mmio_list_tail */
11 0x00000064,
12/* 0x0010: gpc_id */
11 0x00000000, 13 0x00000000,
12/* 0x0014: tpc_mmio_list_head */ 14/* 0x0014: tpc_count */
13 0x00000000, 15 0x00000000,
14/* 0x0018: tpc_mmio_list_tail */ 16/* 0x0018: tpc_mask */
15 0x00000000, 17 0x00000000,
16/* 0x001c: cmd_queue */ 18/* 0x001c: cmd_queue */
17 0x00000000, 19 0x00000000,
@@ -32,107 +34,17 @@ uint32_t nvc0_grgpc_data[] = {
32 0x00000000, 34 0x00000000,
33 0x00000000, 35 0x00000000,
34 0x00000000, 36 0x00000000,
35/* 0x0064: chipsets */
36 0x000000c0,
37 0x013c00d4,
38 0x018c0140,
39 0x000000c1,
40 0x014000d4,
41 0x01a00140,
42 0x000000c3,
43 0x013c00d4,
44 0x019c0140,
45 0x000000c4,
46 0x013c00d4,
47 0x019c0140,
48 0x000000c8,
49 0x013c00d4,
50 0x018c0140,
51 0x000000ce,
52 0x013c00d4,
53 0x019c0140,
54 0x000000cf,
55 0x013c00d4,
56 0x019c0140,
57 0x000000d9,
58 0x014000d8,
59 0x01a80140,
60 0x000000d7,
61 0x014000d8,
62 0x01a80140,
63 0x00000000,
64/* 0x00d4: nvc0_gpc_mmio_head */
65 0x00000408,
66/* 0x00d8: nvd9_gpc_mmio_head */
67 0x00000380,
68 0x04000400,
69 0x0800040c,
70 0x20000450,
71 0x00000600,
72 0x00000684,
73 0x10000700,
74 0x00000800,
75 0x08000808,
76 0x00000828,
77 0x00000830,
78 0x000008d8,
79 0x000008e0,
80 0x140008e8,
81 0x0000091c,
82 0x08000924,
83 0x00000b00,
84 0x14000b08,
85 0x00000bb8,
86 0x00000c08,
87 0x1c000c10,
88 0x00000c80,
89 0x00000c8c,
90 0x08001000,
91 0x00001014,
92/* 0x013c: nvc0_gpc_mmio_tail */
93 0x00000c6c,
94/* 0x0140: nvc1_gpc_mmio_tail */
95/* 0x0140: nvc0_tpc_mmio_head */
96 0x00000018,
97 0x0000003c,
98 0x00000048,
99 0x00000064,
100 0x00000088,
101 0x14000200,
102 0x14000300,
103 0x000003d0,
104 0x040003e0,
105 0x08000400,
106 0x00000420,
107 0x000004b0,
108 0x000004e8,
109 0x000004f4,
110 0x04000520,
111 0x0c000604,
112 0x4c000644,
113 0x00000698,
114 0x04000750,
115/* 0x018c: nvc0_tpc_mmio_tail */
116 0x0400021c,
117 0x000002c4,
118 0x1c000730,
119 0x00000758,
120/* 0x019c: nvc3_tpc_mmio_tail */
121 0x00000544,
122/* 0x01a0: nvc1_tpc_mmio_tail */
123 0x04000424,
124 0x000006e0,
125}; 37};
126 38
127uint32_t nvc0_grgpc_code[] = { 39uint32_t nvc0_grgpc_code[] = {
128 0x03060ef5, 40 0x03180ef5,
129/* 0x0004: queue_put */ 41/* 0x0004: queue_put */
130 0x9800d898, 42 0x9800d898,
131 0x86f001d9, 43 0x86f001d9,
132 0x0489b808, 44 0x0489b808,
133 0xf00c1bf4, 45 0xf00c1bf4,
134 0x21f502f7, 46 0x21f502f7,
135 0x00f802ec, 47 0x00f802fe,
136/* 0x001c: queue_put_next */ 48/* 0x001c: queue_put_next */
137 0xb60798c4, 49 0xb60798c4,
138 0x8dbb0384, 50 0x8dbb0384,
@@ -164,7 +76,7 @@ uint32_t nvc0_grgpc_code[] = {
164 0xc800bccf, 76 0xc800bccf,
165 0x1bf41fcc, 77 0x1bf41fcc,
166 0x06a7f0fa, 78 0x06a7f0fa,
167 0x010321f5, 79 0x010921f5,
168 0xf840bfcf, 80 0xf840bfcf,
169/* 0x008d: nv_wr32 */ 81/* 0x008d: nv_wr32 */
170 0x28b7f100, 82 0x28b7f100,
@@ -186,63 +98,66 @@ uint32_t nvc0_grgpc_code[] = {
186 0x0684b604, 98 0x0684b604,
187 0xf80080d0, 99 0xf80080d0,
188/* 0x00c9: wait_donez */ 100/* 0x00c9: wait_donez */
189 0x3c87f100, 101 0xf094bd00,
190 0x0684b608, 102 0x07f10099,
191 0x99f094bd, 103 0x03f00f00,
192 0x0089d000, 104 0x0009d002,
193 0x081887f1, 105 0x07f104bd,
194 0xd00684b6, 106 0x03f00600,
195/* 0x00e2: wait_donez_ne */ 107 0x000ad002,
196 0x87f1008a, 108/* 0x00e6: wait_donez_ne */
197 0x84b60400, 109 0x87f104bd,
198 0x0088cf06, 110 0x83f00000,
111 0x0088cf01,
199 0xf4888aff, 112 0xf4888aff,
200 0x87f1f31b, 113 0x94bdf31b,
201 0x84b6085c, 114 0xf10099f0,
202 0xf094bd06, 115 0xf0170007,
203 0x89d00099, 116 0x09d00203,
204/* 0x0103: wait_doneo */ 117 0xf804bd00,
205 0xf100f800, 118/* 0x0109: wait_doneo */
206 0xb6083c87, 119 0xf094bd00,
207 0x94bd0684, 120 0x07f10099,
208 0xd00099f0, 121 0x03f00f00,
209 0x87f10089, 122 0x0009d002,
123 0x87f104bd,
210 0x84b60818, 124 0x84b60818,
211 0x008ad006, 125 0x008ad006,
212/* 0x011c: wait_doneo_e */ 126/* 0x0124: wait_doneo_e */
213 0x040087f1, 127 0x040087f1,
214 0xcf0684b6, 128 0xcf0684b6,
215 0x8aff0088, 129 0x8aff0088,
216 0xf30bf488, 130 0xf30bf488,
217 0x085c87f1, 131 0x99f094bd,
218 0xbd0684b6, 132 0x0007f100,
219 0x0099f094, 133 0x0203f017,
220 0xf80089d0, 134 0xbd0009d0,
221/* 0x013d: mmctx_size */ 135/* 0x0147: mmctx_size */
222/* 0x013f: nv_mmctx_size_loop */ 136 0xbd00f804,
223 0x9894bd00, 137/* 0x0149: nv_mmctx_size_loop */
224 0x85b600e8, 138 0x00e89894,
225 0x0180b61a, 139 0xb61a85b6,
226 0xbb0284b6, 140 0x84b60180,
227 0xe0b60098, 141 0x0098bb02,
228 0x04efb804, 142 0xb804e0b6,
229 0xb9eb1bf4, 143 0x1bf404ef,
230 0x00f8029f, 144 0x029fb9eb,
231/* 0x015c: mmctx_xfer */ 145/* 0x0166: mmctx_xfer */
232 0x083c87f1, 146 0x94bd00f8,
233 0xbd0684b6, 147 0xf10199f0,
234 0x0199f094, 148 0xf00f0007,
235 0xf10089d0, 149 0x09d00203,
150 0xf104bd00,
236 0xb6071087, 151 0xb6071087,
237 0x94bd0684, 152 0x94bd0684,
238 0xf405bbfd, 153 0xf405bbfd,
239 0x8bd0090b, 154 0x8bd0090b,
240 0x0099f000, 155 0x0099f000,
241/* 0x0180: mmctx_base_disabled */ 156/* 0x018c: mmctx_base_disabled */
242 0xf405eefd, 157 0xf405eefd,
243 0x8ed00c0b, 158 0x8ed00c0b,
244 0xc08fd080, 159 0xc08fd080,
245/* 0x018f: mmctx_multi_disabled */ 160/* 0x019b: mmctx_multi_disabled */
246 0xb70199f0, 161 0xb70199f0,
247 0xc8010080, 162 0xc8010080,
248 0xb4b600ab, 163 0xb4b600ab,
@@ -250,8 +165,8 @@ uint32_t nvc0_grgpc_code[] = {
250 0xb601aec8, 165 0xb601aec8,
251 0xbefd11e4, 166 0xbefd11e4,
252 0x008bd005, 167 0x008bd005,
253/* 0x01a8: mmctx_exec_loop */ 168/* 0x01b4: mmctx_exec_loop */
254/* 0x01a8: mmctx_wait_free */ 169/* 0x01b4: mmctx_wait_free */
255 0xf0008ecf, 170 0xf0008ecf,
256 0x0bf41fe4, 171 0x0bf41fe4,
257 0x00ce98fa, 172 0x00ce98fa,
@@ -260,76 +175,77 @@ uint32_t nvc0_grgpc_code[] = {
260 0x04cdb804, 175 0x04cdb804,
261 0xc8e81bf4, 176 0xc8e81bf4,
262 0x1bf402ab, 177 0x1bf402ab,
263/* 0x01c9: mmctx_fini_wait */ 178/* 0x01d5: mmctx_fini_wait */
264 0x008bcf18, 179 0x008bcf18,
265 0xb01fb4f0, 180 0xb01fb4f0,
266 0x1bf410b4, 181 0x1bf410b4,
267 0x02a7f0f7, 182 0x02a7f0f7,
268 0xf4c921f4, 183 0xf4c921f4,
269/* 0x01de: mmctx_stop */ 184/* 0x01ea: mmctx_stop */
270 0xabc81b0e, 185 0xabc81b0e,
271 0x10b4b600, 186 0x10b4b600,
272 0xf00cb9f0, 187 0xf00cb9f0,
273 0x8bd012b9, 188 0x8bd012b9,
274/* 0x01ed: mmctx_stop_wait */ 189/* 0x01f9: mmctx_stop_wait */
275 0x008bcf00, 190 0x008bcf00,
276 0xf412bbc8, 191 0xf412bbc8,
277/* 0x01f6: mmctx_done */ 192/* 0x0202: mmctx_done */
278 0x87f1fa1b, 193 0x94bdfa1b,
279 0x84b6085c, 194 0xf10199f0,
280 0xf094bd06, 195 0xf0170007,
281 0x89d00199, 196 0x09d00203,
282/* 0x0207: strand_wait */ 197 0xf804bd00,
283 0xf900f800, 198/* 0x0215: strand_wait */
284 0x02a7f0a0, 199 0xf0a0f900,
285 0xfcc921f4, 200 0x21f402a7,
286/* 0x0213: strand_pre */ 201 0xf8a0fcc9,
287 0xf100f8a0, 202/* 0x0221: strand_pre */
288 0xf04afc87, 203 0xfc87f100,
289 0x97f00283, 204 0x0283f04a,
290 0x0089d00c, 205 0xd00c97f0,
291 0x020721f5,
292/* 0x0226: strand_post */
293 0x87f100f8,
294 0x83f04afc,
295 0x0d97f002,
296 0xf50089d0,
297 0xf8020721,
298/* 0x0239: strand_set */
299 0xfca7f100,
300 0x02a3f04f,
301 0x0500aba2,
302 0xd00fc7f0,
303 0xc7f000ac,
304 0x00bcd00b,
305 0x020721f5,
306 0xf000aed0,
307 0xbcd00ac7,
308 0x0721f500,
309/* 0x0263: strand_ctx_init */
310 0xf100f802,
311 0xb6083c87,
312 0x94bd0684,
313 0xd00399f0,
314 0x21f50089, 206 0x21f50089,
315 0xe7f00213, 207 0x00f80215,
316 0x3921f503, 208/* 0x0234: strand_post */
209 0x4afc87f1,
210 0xf00283f0,
211 0x89d00d97,
212 0x1521f500,
213/* 0x0247: strand_set */
214 0xf100f802,
215 0xf04ffca7,
216 0xaba202a3,
217 0xc7f00500,
218 0x00acd00f,
219 0xd00bc7f0,
220 0x21f500bc,
221 0xaed00215,
222 0x0ac7f000,
223 0xf500bcd0,
224 0xf8021521,
225/* 0x0271: strand_ctx_init */
226 0xf094bd00,
227 0x07f10399,
228 0x03f00f00,
229 0x0009d002,
230 0x21f504bd,
231 0xe7f00221,
232 0x4721f503,
317 0xfca7f102, 233 0xfca7f102,
318 0x02a3f046, 234 0x02a3f046,
319 0x0400aba0, 235 0x0400aba0,
320 0xf040a0d0, 236 0xf040a0d0,
321 0xbcd001c7, 237 0xbcd001c7,
322 0x0721f500, 238 0x1521f500,
323 0x010c9202, 239 0x010c9202,
324 0xf000acd0, 240 0xf000acd0,
325 0xbcd002c7, 241 0xbcd002c7,
326 0x0721f500, 242 0x1521f500,
327 0x2621f502, 243 0x3421f502,
328 0x8087f102, 244 0x8087f102,
329 0x0684b608, 245 0x0684b608,
330 0xb70089cf, 246 0xb70089cf,
331 0x95220080, 247 0x95220080,
332/* 0x02ba: ctx_init_strand_loop */ 248/* 0x02ca: ctx_init_strand_loop */
333 0x8ed008fe, 249 0x8ed008fe,
334 0x408ed000, 250 0x408ed000,
335 0xb6808acf, 251 0xb6808acf,
@@ -338,86 +254,74 @@ uint32_t nvc0_grgpc_code[] = {
338 0xb60480b6, 254 0xb60480b6,
339 0x1bf40192, 255 0x1bf40192,
340 0x08e4b6e8, 256 0x08e4b6e8,
341 0xf1f2efbc, 257 0xbdf2efbc,
342 0xb6085c87, 258 0x0399f094,
343 0x94bd0684, 259 0x170007f1,
344 0xd00399f0, 260 0xd00203f0,
345 0x00f80089, 261 0x04bd0009,
346/* 0x02ec: error */ 262/* 0x02fe: error */
347 0xe7f1e0f9, 263 0xe0f900f8,
348 0xe3f09814, 264 0x9814e7f1,
349 0x8d21f440, 265 0xf440e3f0,
350 0x041ce0b7, 266 0xe0b78d21,
351 0xf401f7f0, 267 0xf7f0041c,
352 0xe0fc8d21, 268 0x8d21f401,
353/* 0x0306: init */ 269 0x00f8e0fc,
354 0x04bd00f8, 270/* 0x0318: init */
355 0xf10004fe, 271 0x04fe04bd,
356 0xf0120017, 272 0x0017f100,
357 0x12d00227, 273 0x0227f012,
358 0x3e17f100, 274 0xf10012d0,
359 0x0010fe04, 275 0xfe042617,
360 0x040017f1, 276 0x17f10010,
361 0xf0c010d0, 277 0x10d00400,
362 0x12d00427, 278 0x0427f0c0,
363 0x1031f400, 279 0xf40012d0,
364 0x060817f1, 280 0x17f11031,
365 0xcf0614b6, 281 0x14b60608,
366 0x37f00012, 282 0x0012cf06,
367 0x1f24f001, 283 0xf00137f0,
368 0xb60432bb, 284 0x32bb1f24,
369 0x02800132, 285 0x0132b604,
370 0x04038003, 286 0x80050280,
371 0x040010b7, 287 0x10b70603,
372 0x800012cf, 288 0x12cf0400,
373 0x27f10002, 289 0x04028000,
374 0x24b60800, 290 0x010027f1,
375 0x0022cf06, 291 0xcf0223f0,
376/* 0x035f: init_find_chipset */ 292 0x34bd0022,
377 0xb65817f0, 293 0x070047f1,
378 0x13980c10, 294 0x950644b6,
379 0x0432b800, 295 0x45d00825,
380 0xb00b0bf4, 296 0x4045d000,
381 0x1bf40034, 297 0x98000e98,
382/* 0x0373: init_context */ 298 0x21f5010f,
383 0xf100f8f1, 299 0x2fbb0147,
384 0xb6080027, 300 0x003fbb00,
385 0x22cf0624, 301 0x98010e98,
386 0xf134bd40, 302 0x21f5020f,
387 0xb6070047, 303 0x0e980147,
388 0x25950644, 304 0x00effd05,
389 0x0045d008, 305 0xbb002ebb,
390 0xbd4045d0, 306 0x40b7003e,
391 0x58f4bde4, 307 0x35b61300,
392 0x1f58021e, 308 0x0043d002,
393 0x020e4003, 309 0xb60825b6,
394 0xf5040f40, 310 0x20b60635,
395 0xbb013d21, 311 0x0130b601,
396 0x3fbb002f, 312 0xb60824b6,
397 0x041e5800, 313 0x2fb90834,
398 0x40051f58, 314 0x7121f502,
399 0x0f400a0e, 315 0x003fbb02,
400 0x3d21f50c, 316 0x010007f1,
401 0x030e9801, 317 0xd00203f0,
402 0xbb00effd, 318 0x04bd0003,
403 0x3ebb002e, 319 0x29f024bd,
404 0x0040b700, 320 0x0007f11f,
405 0x0235b613, 321 0x0203f008,
406 0xb60043d0, 322 0xbd0002d0,
407 0x35b60825, 323/* 0x03e9: main */
408 0x0120b606, 324 0x0031f404,
409 0xb60130b6,
410 0x34b60824,
411 0x022fb908,
412 0x026321f5,
413 0xf1003fbb,
414 0xb6080017,
415 0x13d00614,
416 0x0010b740,
417 0xf024bd08,
418 0x12d01f29,
419/* 0x0401: main */
420 0x0031f400,
421 0xf00028f4, 325 0xf00028f4,
422 0x21f41cd7, 326 0x21f41cd7,
423 0xf401f439, 327 0xf401f439,
@@ -428,94 +332,100 @@ uint32_t nvc0_grgpc_code[] = {
428 0x01e4b604, 332 0x01e4b604,
429 0xfe051efd, 333 0xfe051efd,
430 0x21f50018, 334 0x21f50018,
431 0x0ef404c3, 335 0x0ef404ad,
432/* 0x0431: main_not_ctx_xfer */ 336/* 0x0419: main_not_ctx_xfer */
433 0x10ef94d3, 337 0x10ef94d3,
434 0xf501f5f0, 338 0xf501f5f0,
435 0xf402ec21, 339 0xf402fe21,
436/* 0x043e: ih */ 340/* 0x0426: ih */
437 0x80f9c60e, 341 0x80f9c60e,
438 0xf90188fe, 342 0xf90188fe,
439 0xf990f980, 343 0xf990f980,
440 0xf9b0f9a0, 344 0xf9b0f9a0,
441 0xf9e0f9d0, 345 0xf9e0f9d0,
442 0x800acff0, 346 0xcf04bdf0,
443 0xf404abc4, 347 0xabc4800a,
444 0xb7f11d0b, 348 0x1d0bf404,
445 0xd7f01900, 349 0x1900b7f1,
446 0x40becf1c, 350 0xcf1cd7f0,
447 0xf400bfcf, 351 0xbfcf40be,
448 0xb0b70421, 352 0x0421f400,
449 0xe7f00400, 353 0x0400b0b7,
450 0x00bed001, 354 0xd001e7f0,
451/* 0x0474: ih_no_fifo */ 355/* 0x045e: ih_no_fifo */
452 0xfc400ad0, 356 0x0ad000be,
453 0xfce0fcf0, 357 0xfcf0fc40,
454 0xfcb0fcd0, 358 0xfcd0fce0,
455 0xfc90fca0, 359 0xfca0fcb0,
456 0x0088fe80, 360 0xfe80fc90,
457 0x32f480fc, 361 0x80fc0088,
458/* 0x048f: hub_barrier_done */ 362 0xf80032f4,
459 0xf001f800, 363/* 0x0479: hub_barrier_done */
460 0x0e9801f7, 364 0x01f7f001,
461 0x04febb00, 365 0xbb040e98,
462 0x9418e7f1, 366 0xe7f104fe,
463 0xf440e3f0, 367 0xe3f09418,
464 0x00f88d21, 368 0x8d21f440,
465/* 0x04a4: ctx_redswitch */ 369/* 0x048e: ctx_redswitch */
466 0x0614e7f1, 370 0xe7f100f8,
467 0xf006e4b6, 371 0xe4b60614,
468 0xefd020f7, 372 0x20f7f006,
469 0x08f7f000, 373 0xf000efd0,
470/* 0x04b4: ctx_redswitch_delay */ 374/* 0x049e: ctx_redswitch_delay */
471 0xf401f2b6, 375 0xf2b608f7,
472 0xf7f1fd1b, 376 0xfd1bf401,
473 0xefd00a20, 377 0x0a20f7f1,
474/* 0x04c3: ctx_xfer */ 378 0xf800efd0,
475 0xf100f800, 379/* 0x04ad: ctx_xfer */
476 0xb60a0417, 380 0x0417f100,
477 0x1fd00614, 381 0x0614b60a,
478 0x0711f400, 382 0xf4001fd0,
479 0x04a421f5, 383 0x21f50711,
480/* 0x04d4: ctx_xfer_not_load */ 384/* 0x04be: ctx_xfer_not_load */
481 0x4afc17f1, 385 0x17f1048e,
482 0xf00213f0, 386 0x13f04afc,
483 0x12d00c27, 387 0x0c27f002,
484 0x0721f500, 388 0xf50012d0,
485 0xfc27f102, 389 0xf1021521,
486 0x0223f047, 390 0xf047fc27,
487 0xf00020d0, 391 0x20d00223,
488 0x20b6012c, 392 0x012cf000,
489 0x0012d003, 393 0xd00320b6,
490 0xf001acf0, 394 0xacf00012,
491 0xb7f002a5, 395 0x02a5f001,
492 0x50b3f000, 396 0xf000b7f0,
493 0xb6000c98, 397 0x0c9850b3,
494 0xbcbb0fc4, 398 0x0fc4b604,
495 0x010c9800, 399 0x9800bcbb,
496 0xf0020d98, 400 0x0d98000c,
497 0x21f500e7, 401 0x00e7f001,
498 0xacf0015c, 402 0x016621f5,
499 0x04a5f001, 403 0xf101acf0,
500 0x4000b7f1, 404 0xf04000b7,
501 0x9850b3f0, 405 0x0c9850b3,
502 0xc4b6000c, 406 0x0fc4b604,
503 0x00bcbb0f, 407 0x9800bcbb,
504 0x98050c98, 408 0x0d98010c,
505 0x0f98060d, 409 0x060f9802,
506 0x00e7f104, 410 0x0800e7f1,
507 0x5c21f508, 411 0x016621f5,
508 0x0721f501, 412 0x021521f5,
509 0x0601f402, 413 0xf40601f4,
510/* 0x054b: ctx_xfer_post */ 414/* 0x0532: ctx_xfer_post */
511 0xf11412f4, 415 0x17f11412,
512 0xf04afc17, 416 0x13f04afc,
513 0x27f00213, 417 0x0d27f002,
514 0x0012d00d, 418 0xf50012d0,
515 0x020721f5, 419/* 0x0543: ctx_xfer_done */
516/* 0x055c: ctx_xfer_done */ 420 0xf5021521,
517 0x048f21f5, 421 0xf8047921,
518 0x000000f8, 422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
519 0x00000000, 429 0x00000000,
520 0x00000000, 430 0x00000000,
521 0x00000000, 431 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
new file mode 100644
index 000000000000..c2f754edbd7d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
26
27#define CHIPSET GF117
28#include "macros.fuc"
29
30.section #nvd7_grgpc_data
31#define INCLUDE_DATA
32#include "com.fuc"
33#include "gpc.fuc"
34#undef INCLUDE_DATA
35
36.section #nvd7_grgpc_code
37#define INCLUDE_CODE
38bra #init
39#include "com.fuc"
40#include "gpc.fuc"
41.align 256
42#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
new file mode 100644
index 000000000000..dd346c2a1624
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
@@ -0,0 +1,475 @@
1uint32_t nvd7_grgpc_data[] = {
2/* 0x0000: gpc_mmio_list_head */
3 0x0000006c,
4/* 0x0004: gpc_mmio_list_tail */
5/* 0x0004: tpc_mmio_list_head */
6 0x0000006c,
7/* 0x0008: tpc_mmio_list_tail */
8/* 0x0008: unk_mmio_list_head */
9 0x0000006c,
10/* 0x000c: unk_mmio_list_tail */
11 0x0000006c,
12/* 0x0010: gpc_id */
13 0x00000000,
14/* 0x0014: tpc_count */
15 0x00000000,
16/* 0x0018: tpc_mask */
17 0x00000000,
18/* 0x001c: unk_count */
19 0x00000000,
20/* 0x0020: unk_mask */
21 0x00000000,
22/* 0x0024: cmd_queue */
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41};
42
43uint32_t nvd7_grgpc_code[] = {
44 0x03180ef5,
45/* 0x0004: queue_put */
46 0x9800d898,
47 0x86f001d9,
48 0x0489b808,
49 0xf00c1bf4,
50 0x21f502f7,
51 0x00f802fe,
52/* 0x001c: queue_put_next */
53 0xb60798c4,
54 0x8dbb0384,
55 0x0880b600,
56 0x80008e80,
57 0x90b6018f,
58 0x0f94f001,
59 0xf801d980,
60/* 0x0039: queue_get */
61 0x0131f400,
62 0x9800d898,
63 0x89b801d9,
64 0x210bf404,
65 0xb60789c4,
66 0x9dbb0394,
67 0x0890b600,
68 0x98009e98,
69 0x80b6019f,
70 0x0f84f001,
71 0xf400d880,
72/* 0x0066: queue_get_done */
73 0x00f80132,
74/* 0x0068: nv_rd32 */
75 0x0728b7f1,
76 0xb906b4b6,
77 0xc9f002ec,
78 0x00bcd01f,
79/* 0x0078: nv_rd32_wait */
80 0xc800bccf,
81 0x1bf41fcc,
82 0x06a7f0fa,
83 0x010921f5,
84 0xf840bfcf,
85/* 0x008d: nv_wr32 */
86 0x28b7f100,
87 0x06b4b607,
88 0xb980bfd0,
89 0xc9f002ec,
90 0x1ec9f01f,
91/* 0x00a3: nv_wr32_wait */
92 0xcf00bcd0,
93 0xccc800bc,
94 0xfa1bf41f,
95/* 0x00ae: watchdog_reset */
96 0x87f100f8,
97 0x84b60430,
98 0x1ff9f006,
99 0xf8008fd0,
100/* 0x00bd: watchdog_clear */
101 0x3087f100,
102 0x0684b604,
103 0xf80080d0,
104/* 0x00c9: wait_donez */
105 0xf094bd00,
106 0x07f10099,
107 0x03f00f00,
108 0x0009d002,
109 0x07f104bd,
110 0x03f00600,
111 0x000ad002,
112/* 0x00e6: wait_donez_ne */
113 0x87f104bd,
114 0x83f00000,
115 0x0088cf01,
116 0xf4888aff,
117 0x94bdf31b,
118 0xf10099f0,
119 0xf0170007,
120 0x09d00203,
121 0xf804bd00,
122/* 0x0109: wait_doneo */
123 0xf094bd00,
124 0x07f10099,
125 0x03f00f00,
126 0x0009d002,
127 0x87f104bd,
128 0x84b60818,
129 0x008ad006,
130/* 0x0124: wait_doneo_e */
131 0x040087f1,
132 0xcf0684b6,
133 0x8aff0088,
134 0xf30bf488,
135 0x99f094bd,
136 0x0007f100,
137 0x0203f017,
138 0xbd0009d0,
139/* 0x0147: mmctx_size */
140 0xbd00f804,
141/* 0x0149: nv_mmctx_size_loop */
142 0x00e89894,
143 0xb61a85b6,
144 0x84b60180,
145 0x0098bb02,
146 0xb804e0b6,
147 0x1bf404ef,
148 0x029fb9eb,
149/* 0x0166: mmctx_xfer */
150 0x94bd00f8,
151 0xf10199f0,
152 0xf00f0007,
153 0x09d00203,
154 0xf104bd00,
155 0xb6071087,
156 0x94bd0684,
157 0xf405bbfd,
158 0x8bd0090b,
159 0x0099f000,
160/* 0x018c: mmctx_base_disabled */
161 0xf405eefd,
162 0x8ed00c0b,
163 0xc08fd080,
164/* 0x019b: mmctx_multi_disabled */
165 0xb70199f0,
166 0xc8010080,
167 0xb4b600ab,
168 0x0cb9f010,
169 0xb601aec8,
170 0xbefd11e4,
171 0x008bd005,
172/* 0x01b4: mmctx_exec_loop */
173/* 0x01b4: mmctx_wait_free */
174 0xf0008ecf,
175 0x0bf41fe4,
176 0x00ce98fa,
177 0xd005e9fd,
178 0xc0b6c08e,
179 0x04cdb804,
180 0xc8e81bf4,
181 0x1bf402ab,
182/* 0x01d5: mmctx_fini_wait */
183 0x008bcf18,
184 0xb01fb4f0,
185 0x1bf410b4,
186 0x02a7f0f7,
187 0xf4c921f4,
188/* 0x01ea: mmctx_stop */
189 0xabc81b0e,
190 0x10b4b600,
191 0xf00cb9f0,
192 0x8bd012b9,
193/* 0x01f9: mmctx_stop_wait */
194 0x008bcf00,
195 0xf412bbc8,
196/* 0x0202: mmctx_done */
197 0x94bdfa1b,
198 0xf10199f0,
199 0xf0170007,
200 0x09d00203,
201 0xf804bd00,
202/* 0x0215: strand_wait */
203 0xf0a0f900,
204 0x21f402a7,
205 0xf8a0fcc9,
206/* 0x0221: strand_pre */
207 0xfc87f100,
208 0x0283f04a,
209 0xd00c97f0,
210 0x21f50089,
211 0x00f80215,
212/* 0x0234: strand_post */
213 0x4afc87f1,
214 0xf00283f0,
215 0x89d00d97,
216 0x1521f500,
217/* 0x0247: strand_set */
218 0xf100f802,
219 0xf04ffca7,
220 0xaba202a3,
221 0xc7f00500,
222 0x00acd00f,
223 0xd00bc7f0,
224 0x21f500bc,
225 0xaed00215,
226 0x0ac7f000,
227 0xf500bcd0,
228 0xf8021521,
229/* 0x0271: strand_ctx_init */
230 0xf094bd00,
231 0x07f10399,
232 0x03f00f00,
233 0x0009d002,
234 0x21f504bd,
235 0xe7f00221,
236 0x4721f503,
237 0xfca7f102,
238 0x02a3f046,
239 0x0400aba0,
240 0xf040a0d0,
241 0xbcd001c7,
242 0x1521f500,
243 0x010c9202,
244 0xf000acd0,
245 0xbcd002c7,
246 0x1521f500,
247 0x3421f502,
248 0x8087f102,
249 0x0684b608,
250 0xb70089cf,
251 0x95220080,
252/* 0x02ca: ctx_init_strand_loop */
253 0x8ed008fe,
254 0x408ed000,
255 0xb6808acf,
256 0xa0b606a5,
257 0x00eabb01,
258 0xb60480b6,
259 0x1bf40192,
260 0x08e4b6e8,
261 0xbdf2efbc,
262 0x0399f094,
263 0x170007f1,
264 0xd00203f0,
265 0x04bd0009,
266/* 0x02fe: error */
267 0xe0f900f8,
268 0x9814e7f1,
269 0xf440e3f0,
270 0xe0b78d21,
271 0xf7f0041c,
272 0x8d21f401,
273 0x00f8e0fc,
274/* 0x0318: init */
275 0x04fe04bd,
276 0x0017f100,
277 0x0227f012,
278 0xf10012d0,
279 0xfe047017,
280 0x17f10010,
281 0x10d00400,
282 0x0427f0c0,
283 0xf40012d0,
284 0x17f11031,
285 0x14b60608,
286 0x0012cf06,
287 0xf00137f0,
288 0x32bb1f24,
289 0x0132b604,
290 0x80050280,
291 0x10b70603,
292 0x12cf0400,
293 0x04028000,
294 0x0c30e7f1,
295 0xbd50e3f0,
296 0xbd34bd24,
297/* 0x0371: init_unk_loop */
298 0x6821f444,
299 0xf400f6b0,
300 0xf7f00f0b,
301 0x04f2bb01,
302 0xb6054ffd,
303/* 0x0386: init_unk_next */
304 0x20b60130,
305 0x04e0b601,
306 0xf40126b0,
307/* 0x0392: init_unk_done */
308 0x0380e21b,
309 0x08048007,
310 0x010027f1,
311 0xcf0223f0,
312 0x34bd0022,
313 0x070047f1,
314 0x950644b6,
315 0x45d00825,
316 0x4045d000,
317 0x98000e98,
318 0x21f5010f,
319 0x2fbb0147,
320 0x003fbb00,
321 0x98010e98,
322 0x21f5020f,
323 0x0e980147,
324 0x00effd05,
325 0xbb002ebb,
326 0x0e98003e,
327 0x030f9802,
328 0x014721f5,
329 0xfd070e98,
330 0x2ebb00ef,
331 0x003ebb00,
332 0x130040b7,
333 0xd00235b6,
334 0x25b60043,
335 0x0635b608,
336 0xb60120b6,
337 0x24b60130,
338 0x0834b608,
339 0xf5022fb9,
340 0xbb027121,
341 0x07f1003f,
342 0x03f00100,
343 0x0003d002,
344 0x24bd04bd,
345 0xf11f29f0,
346 0xf0080007,
347 0x02d00203,
348/* 0x0433: main */
349 0xf404bd00,
350 0x28f40031,
351 0x24d7f000,
352 0xf43921f4,
353 0xe4b0f401,
354 0x1e18f404,
355 0xf00181fe,
356 0x20bd0627,
357 0xb60412fd,
358 0x1efd01e4,
359 0x0018fe05,
360 0x04f721f5,
361/* 0x0463: main_not_ctx_xfer */
362 0x94d30ef4,
363 0xf5f010ef,
364 0xfe21f501,
365 0xc60ef402,
366/* 0x0470: ih */
367 0x88fe80f9,
368 0xf980f901,
369 0xf9a0f990,
370 0xf9d0f9b0,
371 0xbdf0f9e0,
372 0x800acf04,
373 0xf404abc4,
374 0xb7f11d0b,
375 0xd7f01900,
376 0x40becf24,
377 0xf400bfcf,
378 0xb0b70421,
379 0xe7f00400,
380 0x00bed001,
381/* 0x04a8: ih_no_fifo */
382 0xfc400ad0,
383 0xfce0fcf0,
384 0xfcb0fcd0,
385 0xfc90fca0,
386 0x0088fe80,
387 0x32f480fc,
388/* 0x04c3: hub_barrier_done */
389 0xf001f800,
390 0x0e9801f7,
391 0x04febb04,
392 0x9418e7f1,
393 0xf440e3f0,
394 0x00f88d21,
395/* 0x04d8: ctx_redswitch */
396 0x0614e7f1,
397 0xf006e4b6,
398 0xefd020f7,
399 0x08f7f000,
400/* 0x04e8: ctx_redswitch_delay */
401 0xf401f2b6,
402 0xf7f1fd1b,
403 0xefd00a20,
404/* 0x04f7: ctx_xfer */
405 0xf100f800,
406 0xb60a0417,
407 0x1fd00614,
408 0x0711f400,
409 0x04d821f5,
410/* 0x0508: ctx_xfer_not_load */
411 0x4afc17f1,
412 0xf00213f0,
413 0x12d00c27,
414 0x1521f500,
415 0xfc27f102,
416 0x0223f047,
417 0xf00020d0,
418 0x20b6012c,
419 0x0012d003,
420 0xf001acf0,
421 0xb7f002a5,
422 0x50b3f000,
423 0xb6040c98,
424 0xbcbb0fc4,
425 0x000c9800,
426 0xf0010d98,
427 0x21f500e7,
428 0xacf00166,
429 0x00b7f101,
430 0x50b3f040,
431 0xb6040c98,
432 0xbcbb0fc4,
433 0x010c9800,
434 0x98020d98,
435 0xe7f1060f,
436 0x21f50800,
437 0xacf00166,
438 0x04a5f001,
439 0x3000b7f1,
440 0x9850b3f0,
441 0xc4b6040c,
442 0x00bcbb0f,
443 0x98020c98,
444 0x0f98030d,
445 0x00e7f108,
446 0x6621f502,
447 0x1521f501,
448 0x0601f402,
449/* 0x05a3: ctx_xfer_post */
450 0xf11412f4,
451 0xf04afc17,
452 0x27f00213,
453 0x0012d00d,
454 0x021521f5,
455/* 0x05b4: ctx_xfer_done */
456 0x04c321f5,
457 0x000000f8,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index 2fc585eeff95..6b906cd2a31f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -22,150 +22,15 @@
22 * Authors: Ben Skeggs <bskeggs@redhat.com> 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */ 23 */
24 24
25#define NVGK 25#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
26
27#define CHIPSET GK100
26#include "macros.fuc" 28#include "macros.fuc"
27 29
28.section #nve0_grgpc_data 30.section #nve0_grgpc_data
29#define INCLUDE_DATA 31#define INCLUDE_DATA
30#include "com.fuc" 32#include "com.fuc"
31#include "gpc.fuc" 33#include "gpc.fuc"
32
33chipsets:
34.b8 0xe4 0 0 0
35.b16 #nve4_gpc_mmio_head
36.b16 #nve4_gpc_mmio_tail
37.b16 #nve4_tpc_mmio_head
38.b16 #nve4_tpc_mmio_tail
39.b8 0xe7 0 0 0
40.b16 #nve4_gpc_mmio_head
41.b16 #nve4_gpc_mmio_tail
42.b16 #nve4_tpc_mmio_head
43.b16 #nve4_tpc_mmio_tail
44.b8 0xe6 0 0 0
45.b16 #nve4_gpc_mmio_head
46.b16 #nve4_gpc_mmio_tail
47.b16 #nve4_tpc_mmio_head
48.b16 #nve4_tpc_mmio_tail
49.b8 0xf0 0 0 0
50.b16 #nvf0_gpc_mmio_head
51.b16 #nvf0_gpc_mmio_tail
52.b16 #nvf0_tpc_mmio_head
53.b16 #nvf0_tpc_mmio_tail
54.b8 0 0 0 0
55
56// GPC mmio lists
57nve4_gpc_mmio_head:
58mmctx_data(0x000380, 1)
59mmctx_data(0x000400, 2)
60mmctx_data(0x00040c, 3)
61mmctx_data(0x000450, 9)
62mmctx_data(0x000600, 1)
63mmctx_data(0x000684, 1)
64mmctx_data(0x000700, 5)
65mmctx_data(0x000800, 1)
66mmctx_data(0x000808, 3)
67mmctx_data(0x000828, 1)
68mmctx_data(0x000830, 1)
69mmctx_data(0x0008d8, 1)
70mmctx_data(0x0008e0, 1)
71mmctx_data(0x0008e8, 6)
72mmctx_data(0x00091c, 1)
73mmctx_data(0x000924, 3)
74mmctx_data(0x000b00, 1)
75mmctx_data(0x000b08, 6)
76mmctx_data(0x000bb8, 1)
77mmctx_data(0x000c08, 1)
78mmctx_data(0x000c10, 8)
79mmctx_data(0x000c40, 1)
80mmctx_data(0x000c6c, 1)
81mmctx_data(0x000c80, 1)
82mmctx_data(0x000c8c, 1)
83mmctx_data(0x001000, 3)
84mmctx_data(0x001014, 1)
85mmctx_data(0x003024, 1)
86mmctx_data(0x0030c0, 2)
87mmctx_data(0x0030e4, 1)
88mmctx_data(0x003100, 6)
89mmctx_data(0x0031d0, 1)
90mmctx_data(0x0031e0, 2)
91nve4_gpc_mmio_tail:
92
93nvf0_gpc_mmio_head:
94mmctx_data(0x000380, 1)
95mmctx_data(0x000400, 2)
96mmctx_data(0x00040c, 3)
97mmctx_data(0x000450, 9)
98mmctx_data(0x000600, 1)
99mmctx_data(0x000684, 1)
100mmctx_data(0x000700, 5)
101mmctx_data(0x000800, 1)
102mmctx_data(0x000808, 3)
103mmctx_data(0x000828, 1)
104mmctx_data(0x000830, 1)
105mmctx_data(0x0008d8, 1)
106mmctx_data(0x0008e0, 1)
107mmctx_data(0x0008e8, 6)
108mmctx_data(0x00091c, 1)
109mmctx_data(0x000924, 3)
110mmctx_data(0x000b00, 1)
111mmctx_data(0x000b08, 6)
112mmctx_data(0x000bb8, 1)
113mmctx_data(0x000c08, 1)
114mmctx_data(0x000c10, 8)
115mmctx_data(0x000c40, 1)
116mmctx_data(0x000c6c, 1)
117mmctx_data(0x000c80, 1)
118mmctx_data(0x000c8c, 1)
119mmctx_data(0x000d24, 1)
120mmctx_data(0x001000, 3)
121mmctx_data(0x001014, 1)
122nvf0_gpc_mmio_tail:
123
124// TPC mmio lists
125nve4_tpc_mmio_head:
126mmctx_data(0x000048, 1)
127mmctx_data(0x000064, 1)
128mmctx_data(0x000088, 1)
129mmctx_data(0x000200, 6)
130mmctx_data(0x00021c, 2)
131mmctx_data(0x000230, 1)
132mmctx_data(0x0002c4, 1)
133mmctx_data(0x000400, 3)
134mmctx_data(0x000420, 3)
135mmctx_data(0x0004e8, 1)
136mmctx_data(0x0004f4, 1)
137mmctx_data(0x000604, 4)
138mmctx_data(0x000644, 22)
139mmctx_data(0x0006ac, 2)
140mmctx_data(0x0006c8, 1)
141mmctx_data(0x000730, 8)
142mmctx_data(0x000758, 1)
143mmctx_data(0x000770, 1)
144mmctx_data(0x000778, 2)
145nve4_tpc_mmio_tail:
146
147nvf0_tpc_mmio_head:
148mmctx_data(0x000048, 1)
149mmctx_data(0x000064, 1)
150mmctx_data(0x000088, 1)
151mmctx_data(0x000200, 6)
152mmctx_data(0x00021c, 2)
153mmctx_data(0x000230, 1)
154mmctx_data(0x0002c4, 1)
155mmctx_data(0x000400, 3)
156mmctx_data(0x000420, 3)
157mmctx_data(0x0004e8, 1)
158mmctx_data(0x0004f4, 1)
159mmctx_data(0x000604, 4)
160mmctx_data(0x000644, 22)
161mmctx_data(0x0006ac, 2)
162mmctx_data(0x0006b8, 1)
163mmctx_data(0x0006c8, 1)
164mmctx_data(0x000730, 8)
165mmctx_data(0x000758, 1)
166mmctx_data(0x000770, 1)
167mmctx_data(0x000778, 2)
168nvf0_tpc_mmio_tail:
169#undef INCLUDE_DATA 34#undef INCLUDE_DATA
170 35
171.section #nve0_grgpc_code 36.section #nve0_grgpc_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 504ae96cd3dd..7ff5ef6b0804 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -1,169 +1,54 @@
1uint32_t nve0_grgpc_data[] = { 1uint32_t nve0_grgpc_data[] = {
2/* 0x0000: gpc_id */ 2/* 0x0000: gpc_mmio_list_head */
3 0x0000006c,
4/* 0x0004: gpc_mmio_list_tail */
5/* 0x0004: tpc_mmio_list_head */
6 0x0000006c,
7/* 0x0008: tpc_mmio_list_tail */
8/* 0x0008: unk_mmio_list_head */
9 0x0000006c,
10/* 0x000c: unk_mmio_list_tail */
11 0x0000006c,
12/* 0x0010: gpc_id */
13 0x00000000,
14/* 0x0014: tpc_count */
15 0x00000000,
16/* 0x0018: tpc_mask */
17 0x00000000,
18/* 0x001c: unk_count */
19 0x00000000,
20/* 0x0020: unk_mask */
21 0x00000000,
22/* 0x0024: cmd_queue */
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
3 0x00000000, 38 0x00000000,
4/* 0x0004: gpc_mmio_list_head */
5 0x00000000, 39 0x00000000,
6/* 0x0008: gpc_mmio_list_tail */
7 0x00000000, 40 0x00000000,
8/* 0x000c: tpc_count */
9 0x00000000,
10/* 0x0010: tpc_mask */
11 0x00000000,
12/* 0x0014: tpc_mmio_list_head */
13 0x00000000,
14/* 0x0018: tpc_mmio_list_tail */
15 0x00000000,
16/* 0x001c: cmd_queue */
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35/* 0x0064: chipsets */
36 0x000000e4,
37 0x011c0098,
38 0x01d8018c,
39 0x000000e7,
40 0x011c0098,
41 0x01d8018c,
42 0x000000e6,
43 0x011c0098,
44 0x01d8018c,
45 0x000000f0,
46 0x018c011c,
47 0x022801d8,
48 0x00000000,
49/* 0x0098: nve4_gpc_mmio_head */
50 0x00000380,
51 0x04000400,
52 0x0800040c,
53 0x20000450,
54 0x00000600,
55 0x00000684,
56 0x10000700,
57 0x00000800,
58 0x08000808,
59 0x00000828,
60 0x00000830,
61 0x000008d8,
62 0x000008e0,
63 0x140008e8,
64 0x0000091c,
65 0x08000924,
66 0x00000b00,
67 0x14000b08,
68 0x00000bb8,
69 0x00000c08,
70 0x1c000c10,
71 0x00000c40,
72 0x00000c6c,
73 0x00000c80,
74 0x00000c8c,
75 0x08001000,
76 0x00001014,
77 0x00003024,
78 0x040030c0,
79 0x000030e4,
80 0x14003100,
81 0x000031d0,
82 0x040031e0,
83/* 0x011c: nve4_gpc_mmio_tail */
84/* 0x011c: nvf0_gpc_mmio_head */
85 0x00000380,
86 0x04000400,
87 0x0800040c,
88 0x20000450,
89 0x00000600,
90 0x00000684,
91 0x10000700,
92 0x00000800,
93 0x08000808,
94 0x00000828,
95 0x00000830,
96 0x000008d8,
97 0x000008e0,
98 0x140008e8,
99 0x0000091c,
100 0x08000924,
101 0x00000b00,
102 0x14000b08,
103 0x00000bb8,
104 0x00000c08,
105 0x1c000c10,
106 0x00000c40,
107 0x00000c6c,
108 0x00000c80,
109 0x00000c8c,
110 0x00000d24,
111 0x08001000,
112 0x00001014,
113/* 0x018c: nvf0_gpc_mmio_tail */
114/* 0x018c: nve4_tpc_mmio_head */
115 0x00000048,
116 0x00000064,
117 0x00000088,
118 0x14000200,
119 0x0400021c,
120 0x00000230,
121 0x000002c4,
122 0x08000400,
123 0x08000420,
124 0x000004e8,
125 0x000004f4,
126 0x0c000604,
127 0x54000644,
128 0x040006ac,
129 0x000006c8,
130 0x1c000730,
131 0x00000758,
132 0x00000770,
133 0x04000778,
134/* 0x01d8: nve4_tpc_mmio_tail */
135/* 0x01d8: nvf0_tpc_mmio_head */
136 0x00000048,
137 0x00000064,
138 0x00000088,
139 0x14000200,
140 0x0400021c,
141 0x00000230,
142 0x000002c4,
143 0x08000400,
144 0x08000420,
145 0x000004e8,
146 0x000004f4,
147 0x0c000604,
148 0x54000644,
149 0x040006ac,
150 0x000006b8,
151 0x000006c8,
152 0x1c000730,
153 0x00000758,
154 0x00000770,
155 0x04000778,
156}; 41};
157 42
158uint32_t nve0_grgpc_code[] = { 43uint32_t nve0_grgpc_code[] = {
159 0x03060ef5, 44 0x03180ef5,
160/* 0x0004: queue_put */ 45/* 0x0004: queue_put */
161 0x9800d898, 46 0x9800d898,
162 0x86f001d9, 47 0x86f001d9,
163 0x0489b808, 48 0x0489b808,
164 0xf00c1bf4, 49 0xf00c1bf4,
165 0x21f502f7, 50 0x21f502f7,
166 0x00f802ec, 51 0x00f802fe,
167/* 0x001c: queue_put_next */ 52/* 0x001c: queue_put_next */
168 0xb60798c4, 53 0xb60798c4,
169 0x8dbb0384, 54 0x8dbb0384,
@@ -195,7 +80,7 @@ uint32_t nve0_grgpc_code[] = {
195 0xc800bccf, 80 0xc800bccf,
196 0x1bf41fcc, 81 0x1bf41fcc,
197 0x06a7f0fa, 82 0x06a7f0fa,
198 0x010321f5, 83 0x010921f5,
199 0xf840bfcf, 84 0xf840bfcf,
200/* 0x008d: nv_wr32 */ 85/* 0x008d: nv_wr32 */
201 0x28b7f100, 86 0x28b7f100,
@@ -217,63 +102,66 @@ uint32_t nve0_grgpc_code[] = {
217 0x0684b604, 102 0x0684b604,
218 0xf80080d0, 103 0xf80080d0,
219/* 0x00c9: wait_donez */ 104/* 0x00c9: wait_donez */
220 0x3c87f100, 105 0xf094bd00,
221 0x0684b608, 106 0x07f10099,
222 0x99f094bd, 107 0x03f00f00,
223 0x0089d000, 108 0x0009d002,
224 0x081887f1, 109 0x07f104bd,
225 0xd00684b6, 110 0x03f00600,
226/* 0x00e2: wait_donez_ne */ 111 0x000ad002,
227 0x87f1008a, 112/* 0x00e6: wait_donez_ne */
228 0x84b60400, 113 0x87f104bd,
229 0x0088cf06, 114 0x83f00000,
115 0x0088cf01,
230 0xf4888aff, 116 0xf4888aff,
231 0x87f1f31b, 117 0x94bdf31b,
232 0x84b6085c, 118 0xf10099f0,
233 0xf094bd06, 119 0xf0170007,
234 0x89d00099, 120 0x09d00203,
235/* 0x0103: wait_doneo */ 121 0xf804bd00,
236 0xf100f800, 122/* 0x0109: wait_doneo */
237 0xb6083c87, 123 0xf094bd00,
238 0x94bd0684, 124 0x07f10099,
239 0xd00099f0, 125 0x03f00f00,
240 0x87f10089, 126 0x0009d002,
127 0x87f104bd,
241 0x84b60818, 128 0x84b60818,
242 0x008ad006, 129 0x008ad006,
243/* 0x011c: wait_doneo_e */ 130/* 0x0124: wait_doneo_e */
244 0x040087f1, 131 0x040087f1,
245 0xcf0684b6, 132 0xcf0684b6,
246 0x8aff0088, 133 0x8aff0088,
247 0xf30bf488, 134 0xf30bf488,
248 0x085c87f1, 135 0x99f094bd,
249 0xbd0684b6, 136 0x0007f100,
250 0x0099f094, 137 0x0203f017,
251 0xf80089d0, 138 0xbd0009d0,
252/* 0x013d: mmctx_size */ 139/* 0x0147: mmctx_size */
253/* 0x013f: nv_mmctx_size_loop */ 140 0xbd00f804,
254 0x9894bd00, 141/* 0x0149: nv_mmctx_size_loop */
255 0x85b600e8, 142 0x00e89894,
256 0x0180b61a, 143 0xb61a85b6,
257 0xbb0284b6, 144 0x84b60180,
258 0xe0b60098, 145 0x0098bb02,
259 0x04efb804, 146 0xb804e0b6,
260 0xb9eb1bf4, 147 0x1bf404ef,
261 0x00f8029f, 148 0x029fb9eb,
262/* 0x015c: mmctx_xfer */ 149/* 0x0166: mmctx_xfer */
263 0x083c87f1, 150 0x94bd00f8,
264 0xbd0684b6, 151 0xf10199f0,
265 0x0199f094, 152 0xf00f0007,
266 0xf10089d0, 153 0x09d00203,
154 0xf104bd00,
267 0xb6071087, 155 0xb6071087,
268 0x94bd0684, 156 0x94bd0684,
269 0xf405bbfd, 157 0xf405bbfd,
270 0x8bd0090b, 158 0x8bd0090b,
271 0x0099f000, 159 0x0099f000,
272/* 0x0180: mmctx_base_disabled */ 160/* 0x018c: mmctx_base_disabled */
273 0xf405eefd, 161 0xf405eefd,
274 0x8ed00c0b, 162 0x8ed00c0b,
275 0xc08fd080, 163 0xc08fd080,
276/* 0x018f: mmctx_multi_disabled */ 164/* 0x019b: mmctx_multi_disabled */
277 0xb70199f0, 165 0xb70199f0,
278 0xc8010080, 166 0xc8010080,
279 0xb4b600ab, 167 0xb4b600ab,
@@ -281,8 +169,8 @@ uint32_t nve0_grgpc_code[] = {
281 0xb601aec8, 169 0xb601aec8,
282 0xbefd11e4, 170 0xbefd11e4,
283 0x008bd005, 171 0x008bd005,
284/* 0x01a8: mmctx_exec_loop */ 172/* 0x01b4: mmctx_exec_loop */
285/* 0x01a8: mmctx_wait_free */ 173/* 0x01b4: mmctx_wait_free */
286 0xf0008ecf, 174 0xf0008ecf,
287 0x0bf41fe4, 175 0x0bf41fe4,
288 0x00ce98fa, 176 0x00ce98fa,
@@ -291,76 +179,77 @@ uint32_t nve0_grgpc_code[] = {
291 0x04cdb804, 179 0x04cdb804,
292 0xc8e81bf4, 180 0xc8e81bf4,
293 0x1bf402ab, 181 0x1bf402ab,
294/* 0x01c9: mmctx_fini_wait */ 182/* 0x01d5: mmctx_fini_wait */
295 0x008bcf18, 183 0x008bcf18,
296 0xb01fb4f0, 184 0xb01fb4f0,
297 0x1bf410b4, 185 0x1bf410b4,
298 0x02a7f0f7, 186 0x02a7f0f7,
299 0xf4c921f4, 187 0xf4c921f4,
300/* 0x01de: mmctx_stop */ 188/* 0x01ea: mmctx_stop */
301 0xabc81b0e, 189 0xabc81b0e,
302 0x10b4b600, 190 0x10b4b600,
303 0xf00cb9f0, 191 0xf00cb9f0,
304 0x8bd012b9, 192 0x8bd012b9,
305/* 0x01ed: mmctx_stop_wait */ 193/* 0x01f9: mmctx_stop_wait */
306 0x008bcf00, 194 0x008bcf00,
307 0xf412bbc8, 195 0xf412bbc8,
308/* 0x01f6: mmctx_done */ 196/* 0x0202: mmctx_done */
309 0x87f1fa1b, 197 0x94bdfa1b,
310 0x84b6085c, 198 0xf10199f0,
311 0xf094bd06, 199 0xf0170007,
312 0x89d00199, 200 0x09d00203,
313/* 0x0207: strand_wait */ 201 0xf804bd00,
314 0xf900f800, 202/* 0x0215: strand_wait */
315 0x02a7f0a0, 203 0xf0a0f900,
316 0xfcc921f4, 204 0x21f402a7,
317/* 0x0213: strand_pre */ 205 0xf8a0fcc9,
318 0xf100f8a0, 206/* 0x0221: strand_pre */
319 0xf04afc87, 207 0xfc87f100,
320 0x97f00283, 208 0x0283f04a,
321 0x0089d00c, 209 0xd00c97f0,
322 0x020721f5,
323/* 0x0226: strand_post */
324 0x87f100f8,
325 0x83f04afc,
326 0x0d97f002,
327 0xf50089d0,
328 0xf8020721,
329/* 0x0239: strand_set */
330 0xfca7f100,
331 0x02a3f04f,
332 0x0500aba2,
333 0xd00fc7f0,
334 0xc7f000ac,
335 0x00bcd00b,
336 0x020721f5,
337 0xf000aed0,
338 0xbcd00ac7,
339 0x0721f500,
340/* 0x0263: strand_ctx_init */
341 0xf100f802,
342 0xb6083c87,
343 0x94bd0684,
344 0xd00399f0,
345 0x21f50089, 210 0x21f50089,
346 0xe7f00213, 211 0x00f80215,
347 0x3921f503, 212/* 0x0234: strand_post */
213 0x4afc87f1,
214 0xf00283f0,
215 0x89d00d97,
216 0x1521f500,
217/* 0x0247: strand_set */
218 0xf100f802,
219 0xf04ffca7,
220 0xaba202a3,
221 0xc7f00500,
222 0x00acd00f,
223 0xd00bc7f0,
224 0x21f500bc,
225 0xaed00215,
226 0x0ac7f000,
227 0xf500bcd0,
228 0xf8021521,
229/* 0x0271: strand_ctx_init */
230 0xf094bd00,
231 0x07f10399,
232 0x03f00f00,
233 0x0009d002,
234 0x21f504bd,
235 0xe7f00221,
236 0x4721f503,
348 0xfca7f102, 237 0xfca7f102,
349 0x02a3f046, 238 0x02a3f046,
350 0x0400aba0, 239 0x0400aba0,
351 0xf040a0d0, 240 0xf040a0d0,
352 0xbcd001c7, 241 0xbcd001c7,
353 0x0721f500, 242 0x1521f500,
354 0x010c9202, 243 0x010c9202,
355 0xf000acd0, 244 0xf000acd0,
356 0xbcd002c7, 245 0xbcd002c7,
357 0x0721f500, 246 0x1521f500,
358 0x2621f502, 247 0x3421f502,
359 0x8087f102, 248 0x8087f102,
360 0x0684b608, 249 0x0684b608,
361 0xb70089cf, 250 0xb70089cf,
362 0x95220080, 251 0x95220080,
363/* 0x02ba: ctx_init_strand_loop */ 252/* 0x02ca: ctx_init_strand_loop */
364 0x8ed008fe, 253 0x8ed008fe,
365 0x408ed000, 254 0x408ed000,
366 0xb6808acf, 255 0xb6808acf,
@@ -369,150 +258,160 @@ uint32_t nve0_grgpc_code[] = {
369 0xb60480b6, 258 0xb60480b6,
370 0x1bf40192, 259 0x1bf40192,
371 0x08e4b6e8, 260 0x08e4b6e8,
372 0xf1f2efbc, 261 0xbdf2efbc,
373 0xb6085c87, 262 0x0399f094,
374 0x94bd0684, 263 0x170007f1,
375 0xd00399f0, 264 0xd00203f0,
376 0x00f80089, 265 0x04bd0009,
377/* 0x02ec: error */ 266/* 0x02fe: error */
378 0xe7f1e0f9, 267 0xe0f900f8,
379 0xe3f09814, 268 0x9814e7f1,
380 0x8d21f440, 269 0xf440e3f0,
381 0x041ce0b7, 270 0xe0b78d21,
382 0xf401f7f0, 271 0xf7f0041c,
383 0xe0fc8d21, 272 0x8d21f401,
384/* 0x0306: init */ 273 0x00f8e0fc,
385 0x04bd00f8, 274/* 0x0318: init */
386 0xf10004fe, 275 0x04fe04bd,
387 0xf0120017, 276 0x0017f100,
388 0x12d00227, 277 0x0227f012,
389 0x3e17f100, 278 0xf10012d0,
390 0x0010fe04, 279 0xfe047017,
391 0x040017f1, 280 0x17f10010,
392 0xf0c010d0, 281 0x10d00400,
393 0x12d00427, 282 0x0427f0c0,
394 0x1031f400, 283 0xf40012d0,
395 0x060817f1, 284 0x17f11031,
396 0xcf0614b6, 285 0x14b60608,
397 0x37f00012, 286 0x0012cf06,
398 0x1f24f001, 287 0xf00137f0,
399 0xb60432bb, 288 0x32bb1f24,
400 0x02800132, 289 0x0132b604,
401 0x04038003, 290 0x80050280,
402 0x040010b7, 291 0x10b70603,
403 0x800012cf, 292 0x12cf0400,
404 0x27f10002, 293 0x04028000,
405 0x24b60800, 294 0x0c30e7f1,
406 0x0022cf06, 295 0xbd50e3f0,
407/* 0x035f: init_find_chipset */ 296 0xbd34bd24,
408 0xb65817f0, 297/* 0x0371: init_unk_loop */
409 0x13980c10, 298 0x6821f444,
410 0x0432b800, 299 0xf400f6b0,
411 0xb00b0bf4, 300 0xf7f00f0b,
412 0x1bf40034, 301 0x04f2bb01,
413/* 0x0373: init_context */ 302 0xb6054ffd,
414 0xf100f8f1, 303/* 0x0386: init_unk_next */
415 0xb6080027, 304 0x20b60130,
416 0x22cf0624, 305 0x04e0b601,
417 0xf134bd40, 306 0xf40126b0,
418 0xb6070047, 307/* 0x0392: init_unk_done */
419 0x25950644, 308 0x0380e21b,
420 0x0045d008, 309 0x08048007,
421 0xbd4045d0, 310 0x010027f1,
422 0x58f4bde4, 311 0xcf0223f0,
423 0x1f58021e, 312 0x34bd0022,
424 0x020e4003, 313 0x070047f1,
425 0xf5040f40, 314 0x950644b6,
426 0xbb013d21, 315 0x45d00825,
427 0x3fbb002f, 316 0x4045d000,
428 0x041e5800, 317 0x98000e98,
429 0x40051f58, 318 0x21f5010f,
430 0x0f400a0e, 319 0x2fbb0147,
431 0x3d21f50c, 320 0x003fbb00,
432 0x030e9801, 321 0x98010e98,
433 0xbb00effd, 322 0x21f5020f,
434 0x3ebb002e, 323 0x0e980147,
435 0x0040b700, 324 0x00effd05,
436 0x0235b613, 325 0xbb002ebb,
437 0xb60043d0, 326 0x0e98003e,
438 0x35b60825, 327 0x030f9802,
439 0x0120b606, 328 0x014721f5,
440 0xb60130b6, 329 0xfd070e98,
441 0x34b60824, 330 0x2ebb00ef,
442 0x022fb908, 331 0x003ebb00,
443 0x026321f5, 332 0x130040b7,
444 0xf1003fbb, 333 0xd00235b6,
445 0xb6080017, 334 0x25b60043,
446 0x13d00614, 335 0x0635b608,
447 0x0010b740, 336 0xb60120b6,
448 0xf024bd08, 337 0x24b60130,
449 0x12d01f29, 338 0x0834b608,
450/* 0x0401: main */ 339 0xf5022fb9,
451 0x0031f400, 340 0xbb027121,
452 0xf00028f4, 341 0x07f1003f,
453 0x21f41cd7, 342 0x03f00100,
454 0xf401f439, 343 0x0003d002,
455 0xf404e4b0, 344 0x24bd04bd,
456 0x81fe1e18, 345 0xf11f29f0,
457 0x0627f001, 346 0xf0080007,
458 0x12fd20bd, 347 0x02d00203,
459 0x01e4b604, 348/* 0x0433: main */
460 0xfe051efd, 349 0xf404bd00,
461 0x21f50018, 350 0x28f40031,
462 0x0ef404c3, 351 0x24d7f000,
463/* 0x0431: main_not_ctx_xfer */ 352 0xf43921f4,
464 0x10ef94d3, 353 0xe4b0f401,
465 0xf501f5f0, 354 0x1e18f404,
466 0xf402ec21, 355 0xf00181fe,
467/* 0x043e: ih */ 356 0x20bd0627,
468 0x80f9c60e, 357 0xb60412fd,
469 0xf90188fe, 358 0x1efd01e4,
470 0xf990f980, 359 0x0018fe05,
471 0xf9b0f9a0, 360 0x04f721f5,
472 0xf9e0f9d0, 361/* 0x0463: main_not_ctx_xfer */
473 0x800acff0, 362 0x94d30ef4,
363 0xf5f010ef,
364 0xfe21f501,
365 0xc60ef402,
366/* 0x0470: ih */
367 0x88fe80f9,
368 0xf980f901,
369 0xf9a0f990,
370 0xf9d0f9b0,
371 0xbdf0f9e0,
372 0x800acf04,
474 0xf404abc4, 373 0xf404abc4,
475 0xb7f11d0b, 374 0xb7f11d0b,
476 0xd7f01900, 375 0xd7f01900,
477 0x40becf1c, 376 0x40becf24,
478 0xf400bfcf, 377 0xf400bfcf,
479 0xb0b70421, 378 0xb0b70421,
480 0xe7f00400, 379 0xe7f00400,
481 0x00bed001, 380 0x00bed001,
482/* 0x0474: ih_no_fifo */ 381/* 0x04a8: ih_no_fifo */
483 0xfc400ad0, 382 0xfc400ad0,
484 0xfce0fcf0, 383 0xfce0fcf0,
485 0xfcb0fcd0, 384 0xfcb0fcd0,
486 0xfc90fca0, 385 0xfc90fca0,
487 0x0088fe80, 386 0x0088fe80,
488 0x32f480fc, 387 0x32f480fc,
489/* 0x048f: hub_barrier_done */ 388/* 0x04c3: hub_barrier_done */
490 0xf001f800, 389 0xf001f800,
491 0x0e9801f7, 390 0x0e9801f7,
492 0x04febb00, 391 0x04febb04,
493 0x9418e7f1, 392 0x9418e7f1,
494 0xf440e3f0, 393 0xf440e3f0,
495 0x00f88d21, 394 0x00f88d21,
496/* 0x04a4: ctx_redswitch */ 395/* 0x04d8: ctx_redswitch */
497 0x0614e7f1, 396 0x0614e7f1,
498 0xf006e4b6, 397 0xf006e4b6,
499 0xefd020f7, 398 0xefd020f7,
500 0x08f7f000, 399 0x08f7f000,
501/* 0x04b4: ctx_redswitch_delay */ 400/* 0x04e8: ctx_redswitch_delay */
502 0xf401f2b6, 401 0xf401f2b6,
503 0xf7f1fd1b, 402 0xf7f1fd1b,
504 0xefd00a20, 403 0xefd00a20,
505/* 0x04c3: ctx_xfer */ 404/* 0x04f7: ctx_xfer */
506 0xf100f800, 405 0xf100f800,
507 0xb60a0417, 406 0xb60a0417,
508 0x1fd00614, 407 0x1fd00614,
509 0x0711f400, 408 0x0711f400,
510 0x04a421f5, 409 0x04d821f5,
511/* 0x04d4: ctx_xfer_not_load */ 410/* 0x0508: ctx_xfer_not_load */
512 0x4afc17f1, 411 0x4afc17f1,
513 0xf00213f0, 412 0xf00213f0,
514 0x12d00c27, 413 0x12d00c27,
515 0x0721f500, 414 0x1521f500,
516 0xfc27f102, 415 0xfc27f102,
517 0x0223f047, 416 0x0223f047,
518 0xf00020d0, 417 0xf00020d0,
@@ -521,31 +420,40 @@ uint32_t nve0_grgpc_code[] = {
521 0xf001acf0, 420 0xf001acf0,
522 0xb7f002a5, 421 0xb7f002a5,
523 0x50b3f000, 422 0x50b3f000,
524 0xb6000c98, 423 0xb6040c98,
525 0xbcbb0fc4, 424 0xbcbb0fc4,
526 0x010c9800, 425 0x000c9800,
527 0xf0020d98, 426 0xf0010d98,
528 0x21f500e7, 427 0x21f500e7,
529 0xacf0015c, 428 0xacf00166,
429 0x00b7f101,
430 0x50b3f040,
431 0xb6040c98,
432 0xbcbb0fc4,
433 0x010c9800,
434 0x98020d98,
435 0xe7f1060f,
436 0x21f50800,
437 0xacf00166,
530 0x04a5f001, 438 0x04a5f001,
531 0x4000b7f1, 439 0x3000b7f1,
532 0x9850b3f0, 440 0x9850b3f0,
533 0xc4b6000c, 441 0xc4b6040c,
534 0x00bcbb0f, 442 0x00bcbb0f,
535 0x98050c98, 443 0x98020c98,
536 0x0f98060d, 444 0x0f98030d,
537 0x00e7f104, 445 0x00e7f108,
538 0x5c21f508, 446 0x6621f502,
539 0x0721f501, 447 0x1521f501,
540 0x0601f402, 448 0x0601f402,
541/* 0x054b: ctx_xfer_post */ 449/* 0x05a3: ctx_xfer_post */
542 0xf11412f4, 450 0xf11412f4,
543 0xf04afc17, 451 0xf04afc17,
544 0x27f00213, 452 0x27f00213,
545 0x0012d00d, 453 0x0012d00d,
546 0x020721f5, 454 0x021521f5,
547/* 0x055c: ctx_xfer_done */ 455/* 0x05b4: ctx_xfer_done */
548 0x048f21f5, 456 0x04c321f5,
549 0x000000f8, 457 0x000000f8,
550 0x00000000, 458 0x00000000,
551 0x00000000, 459 0x00000000,
@@ -564,26 +472,4 @@ uint32_t nve0_grgpc_code[] = {
564 0x00000000, 472 0x00000000,
565 0x00000000, 473 0x00000000,
566 0x00000000, 474 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0x00000000,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589}; 475};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
new file mode 100644
index 000000000000..90bbe525b626
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002
26
27#define CHIPSET GK110
28#include "macros.fuc"
29
30.section #nvf0_grgpc_data
31#define INCLUDE_DATA
32#include "com.fuc"
33#include "gpc.fuc"
34#undef INCLUDE_DATA
35
36.section #nvf0_grgpc_code
37#define INCLUDE_CODE
38bra #init
39#include "com.fuc"
40#include "gpc.fuc"
41.align 256
42#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
new file mode 100644
index 000000000000..f870507be880
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
@@ -0,0 +1,475 @@
1uint32_t nvf0_grgpc_data[] = {
2/* 0x0000: gpc_mmio_list_head */
3 0x0000006c,
4/* 0x0004: gpc_mmio_list_tail */
5/* 0x0004: tpc_mmio_list_head */
6 0x0000006c,
7/* 0x0008: tpc_mmio_list_tail */
8/* 0x0008: unk_mmio_list_head */
9 0x0000006c,
10/* 0x000c: unk_mmio_list_tail */
11 0x0000006c,
12/* 0x0010: gpc_id */
13 0x00000000,
14/* 0x0014: tpc_count */
15 0x00000000,
16/* 0x0018: tpc_mask */
17 0x00000000,
18/* 0x001c: unk_count */
19 0x00000000,
20/* 0x0020: unk_mask */
21 0x00000000,
22/* 0x0024: cmd_queue */
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41};
42
43uint32_t nvf0_grgpc_code[] = {
44 0x03180ef5,
45/* 0x0004: queue_put */
46 0x9800d898,
47 0x86f001d9,
48 0x0489b808,
49 0xf00c1bf4,
50 0x21f502f7,
51 0x00f802fe,
52/* 0x001c: queue_put_next */
53 0xb60798c4,
54 0x8dbb0384,
55 0x0880b600,
56 0x80008e80,
57 0x90b6018f,
58 0x0f94f001,
59 0xf801d980,
60/* 0x0039: queue_get */
61 0x0131f400,
62 0x9800d898,
63 0x89b801d9,
64 0x210bf404,
65 0xb60789c4,
66 0x9dbb0394,
67 0x0890b600,
68 0x98009e98,
69 0x80b6019f,
70 0x0f84f001,
71 0xf400d880,
72/* 0x0066: queue_get_done */
73 0x00f80132,
74/* 0x0068: nv_rd32 */
75 0x0728b7f1,
76 0xb906b4b6,
77 0xc9f002ec,
78 0x00bcd01f,
79/* 0x0078: nv_rd32_wait */
80 0xc800bccf,
81 0x1bf41fcc,
82 0x06a7f0fa,
83 0x010921f5,
84 0xf840bfcf,
85/* 0x008d: nv_wr32 */
86 0x28b7f100,
87 0x06b4b607,
88 0xb980bfd0,
89 0xc9f002ec,
90 0x1ec9f01f,
91/* 0x00a3: nv_wr32_wait */
92 0xcf00bcd0,
93 0xccc800bc,
94 0xfa1bf41f,
95/* 0x00ae: watchdog_reset */
96 0x87f100f8,
97 0x84b60430,
98 0x1ff9f006,
99 0xf8008fd0,
100/* 0x00bd: watchdog_clear */
101 0x3087f100,
102 0x0684b604,
103 0xf80080d0,
104/* 0x00c9: wait_donez */
105 0xf094bd00,
106 0x07f10099,
107 0x03f03700,
108 0x0009d002,
109 0x07f104bd,
110 0x03f00600,
111 0x000ad002,
112/* 0x00e6: wait_donez_ne */
113 0x87f104bd,
114 0x83f00000,
115 0x0088cf01,
116 0xf4888aff,
117 0x94bdf31b,
118 0xf10099f0,
119 0xf0170007,
120 0x09d00203,
121 0xf804bd00,
122/* 0x0109: wait_doneo */
123 0xf094bd00,
124 0x07f10099,
125 0x03f03700,
126 0x0009d002,
127 0x87f104bd,
128 0x84b60818,
129 0x008ad006,
130/* 0x0124: wait_doneo_e */
131 0x040087f1,
132 0xcf0684b6,
133 0x8aff0088,
134 0xf30bf488,
135 0x99f094bd,
136 0x0007f100,
137 0x0203f017,
138 0xbd0009d0,
139/* 0x0147: mmctx_size */
140 0xbd00f804,
141/* 0x0149: nv_mmctx_size_loop */
142 0x00e89894,
143 0xb61a85b6,
144 0x84b60180,
145 0x0098bb02,
146 0xb804e0b6,
147 0x1bf404ef,
148 0x029fb9eb,
149/* 0x0166: mmctx_xfer */
150 0x94bd00f8,
151 0xf10199f0,
152 0xf0370007,
153 0x09d00203,
154 0xf104bd00,
155 0xb6071087,
156 0x94bd0684,
157 0xf405bbfd,
158 0x8bd0090b,
159 0x0099f000,
160/* 0x018c: mmctx_base_disabled */
161 0xf405eefd,
162 0x8ed00c0b,
163 0xc08fd080,
164/* 0x019b: mmctx_multi_disabled */
165 0xb70199f0,
166 0xc8010080,
167 0xb4b600ab,
168 0x0cb9f010,
169 0xb601aec8,
170 0xbefd11e4,
171 0x008bd005,
172/* 0x01b4: mmctx_exec_loop */
173/* 0x01b4: mmctx_wait_free */
174 0xf0008ecf,
175 0x0bf41fe4,
176 0x00ce98fa,
177 0xd005e9fd,
178 0xc0b6c08e,
179 0x04cdb804,
180 0xc8e81bf4,
181 0x1bf402ab,
182/* 0x01d5: mmctx_fini_wait */
183 0x008bcf18,
184 0xb01fb4f0,
185 0x1bf410b4,
186 0x02a7f0f7,
187 0xf4c921f4,
188/* 0x01ea: mmctx_stop */
189 0xabc81b0e,
190 0x10b4b600,
191 0xf00cb9f0,
192 0x8bd012b9,
193/* 0x01f9: mmctx_stop_wait */
194 0x008bcf00,
195 0xf412bbc8,
196/* 0x0202: mmctx_done */
197 0x94bdfa1b,
198 0xf10199f0,
199 0xf0170007,
200 0x09d00203,
201 0xf804bd00,
202/* 0x0215: strand_wait */
203 0xf0a0f900,
204 0x21f402a7,
205 0xf8a0fcc9,
206/* 0x0221: strand_pre */
207 0xfc87f100,
208 0x0283f04a,
209 0xd00c97f0,
210 0x21f50089,
211 0x00f80215,
212/* 0x0234: strand_post */
213 0x4afc87f1,
214 0xf00283f0,
215 0x89d00d97,
216 0x1521f500,
217/* 0x0247: strand_set */
218 0xf100f802,
219 0xf04ffca7,
220 0xaba202a3,
221 0xc7f00500,
222 0x00acd00f,
223 0xd00bc7f0,
224 0x21f500bc,
225 0xaed00215,
226 0x0ac7f000,
227 0xf500bcd0,
228 0xf8021521,
229/* 0x0271: strand_ctx_init */
230 0xf094bd00,
231 0x07f10399,
232 0x03f03700,
233 0x0009d002,
234 0x21f504bd,
235 0xe7f00221,
236 0x4721f503,
237 0xfca7f102,
238 0x02a3f046,
239 0x0400aba0,
240 0xf040a0d0,
241 0xbcd001c7,
242 0x1521f500,
243 0x010c9202,
244 0xf000acd0,
245 0xbcd002c7,
246 0x1521f500,
247 0x3421f502,
248 0x8087f102,
249 0x0684b608,
250 0xb70089cf,
251 0x95220080,
252/* 0x02ca: ctx_init_strand_loop */
253 0x8ed008fe,
254 0x408ed000,
255 0xb6808acf,
256 0xa0b606a5,
257 0x00eabb01,
258 0xb60480b6,
259 0x1bf40192,
260 0x08e4b6e8,
261 0xbdf2efbc,
262 0x0399f094,
263 0x170007f1,
264 0xd00203f0,
265 0x04bd0009,
266/* 0x02fe: error */
267 0xe0f900f8,
268 0x9814e7f1,
269 0xf440e3f0,
270 0xe0b78d21,
271 0xf7f0041c,
272 0x8d21f401,
273 0x00f8e0fc,
274/* 0x0318: init */
275 0x04fe04bd,
276 0x0017f100,
277 0x0227f012,
278 0xf10012d0,
279 0xfe047017,
280 0x17f10010,
281 0x10d00400,
282 0x0427f0c0,
283 0xf40012d0,
284 0x17f11031,
285 0x14b60608,
286 0x0012cf06,
287 0xf00137f0,
288 0x32bb1f24,
289 0x0132b604,
290 0x80050280,
291 0x10b70603,
292 0x12cf0400,
293 0x04028000,
294 0x0c30e7f1,
295 0xbd50e3f0,
296 0xbd34bd24,
297/* 0x0371: init_unk_loop */
298 0x6821f444,
299 0xf400f6b0,
300 0xf7f00f0b,
301 0x04f2bb01,
302 0xb6054ffd,
303/* 0x0386: init_unk_next */
304 0x20b60130,
305 0x04e0b601,
306 0xf40226b0,
307/* 0x0392: init_unk_done */
308 0x0380e21b,
309 0x08048007,
310 0x010027f1,
311 0xcf0223f0,
312 0x34bd0022,
313 0x070047f1,
314 0x950644b6,
315 0x45d00825,
316 0x4045d000,
317 0x98000e98,
318 0x21f5010f,
319 0x2fbb0147,
320 0x003fbb00,
321 0x98010e98,
322 0x21f5020f,
323 0x0e980147,
324 0x00effd05,
325 0xbb002ebb,
326 0x0e98003e,
327 0x030f9802,
328 0x014721f5,
329 0xfd070e98,
330 0x2ebb00ef,
331 0x003ebb00,
332 0x130040b7,
333 0xd00235b6,
334 0x25b60043,
335 0x0635b608,
336 0xb60120b6,
337 0x24b60130,
338 0x0834b608,
339 0xf5022fb9,
340 0xbb027121,
341 0x07f1003f,
342 0x03f00100,
343 0x0003d002,
344 0x24bd04bd,
345 0xf11f29f0,
346 0xf0300007,
347 0x02d00203,
348/* 0x0433: main */
349 0xf404bd00,
350 0x28f40031,
351 0x24d7f000,
352 0xf43921f4,
353 0xe4b0f401,
354 0x1e18f404,
355 0xf00181fe,
356 0x20bd0627,
357 0xb60412fd,
358 0x1efd01e4,
359 0x0018fe05,
360 0x04f721f5,
361/* 0x0463: main_not_ctx_xfer */
362 0x94d30ef4,
363 0xf5f010ef,
364 0xfe21f501,
365 0xc60ef402,
366/* 0x0470: ih */
367 0x88fe80f9,
368 0xf980f901,
369 0xf9a0f990,
370 0xf9d0f9b0,
371 0xbdf0f9e0,
372 0x800acf04,
373 0xf404abc4,
374 0xb7f11d0b,
375 0xd7f01900,
376 0x40becf24,
377 0xf400bfcf,
378 0xb0b70421,
379 0xe7f00400,
380 0x00bed001,
381/* 0x04a8: ih_no_fifo */
382 0xfc400ad0,
383 0xfce0fcf0,
384 0xfcb0fcd0,
385 0xfc90fca0,
386 0x0088fe80,
387 0x32f480fc,
388/* 0x04c3: hub_barrier_done */
389 0xf001f800,
390 0x0e9801f7,
391 0x04febb04,
392 0x9418e7f1,
393 0xf440e3f0,
394 0x00f88d21,
395/* 0x04d8: ctx_redswitch */
396 0x0614e7f1,
397 0xf006e4b6,
398 0xefd020f7,
399 0x08f7f000,
400/* 0x04e8: ctx_redswitch_delay */
401 0xf401f2b6,
402 0xf7f1fd1b,
403 0xefd00a20,
404/* 0x04f7: ctx_xfer */
405 0xf100f800,
406 0xb60a0417,
407 0x1fd00614,
408 0x0711f400,
409 0x04d821f5,
410/* 0x0508: ctx_xfer_not_load */
411 0x4afc17f1,
412 0xf00213f0,
413 0x12d00c27,
414 0x1521f500,
415 0xfc27f102,
416 0x0223f047,
417 0xf00020d0,
418 0x20b6012c,
419 0x0012d003,
420 0xf001acf0,
421 0xb7f002a5,
422 0x50b3f000,
423 0xb6040c98,
424 0xbcbb0fc4,
425 0x000c9800,
426 0xf0010d98,
427 0x21f500e7,
428 0xacf00166,
429 0x00b7f101,
430 0x50b3f040,
431 0xb6040c98,
432 0xbcbb0fc4,
433 0x010c9800,
434 0x98020d98,
435 0xe7f1060f,
436 0x21f50800,
437 0xacf00166,
438 0x04a5f001,
439 0x3000b7f1,
440 0x9850b3f0,
441 0xc4b6040c,
442 0x00bcbb0f,
443 0x98020c98,
444 0x0f98030d,
445 0x00e7f108,
446 0x6621f502,
447 0x1521f501,
448 0x0601f402,
449/* 0x05a3: ctx_xfer_post */
450 0xf11412f4,
451 0xf04afc17,
452 0x27f00213,
453 0x0012d00d,
454 0x021521f5,
455/* 0x05b4: ctx_xfer_done */
456 0x04c321f5,
457 0x000000f8,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
index 5c68bf6d69aa..b82d2ae89917 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
@@ -24,11 +24,12 @@
24 */ 24 */
25 25
26#ifdef INCLUDE_DATA 26#ifdef INCLUDE_DATA
27hub_mmio_list_head: .b32 #hub_mmio_list_base
28hub_mmio_list_tail: .b32 #hub_mmio_list_next
29
27gpc_count: .b32 0 30gpc_count: .b32 0
28rop_count: .b32 0 31rop_count: .b32 0
29cmd_queue: queue_init 32cmd_queue: queue_init
30hub_mmio_list_head: .b32 0
31hub_mmio_list_tail: .b32 0
32 33
33ctx_current: .b32 0 34ctx_current: .b32 0
34 35
@@ -40,6 +41,9 @@ chan_mmio_address: .b32 0
40.align 256 41.align 256
41xfer_data: .skip 256 42xfer_data: .skip 256
42 43
44hub_mmio_list_base:
45.b32 0x0417e91c // 0x17e91c, 2
46hub_mmio_list_next:
43#endif 47#endif
44 48
45#ifdef INCLUDE_CODE 49#ifdef INCLUDE_CODE
@@ -48,23 +52,14 @@ xfer_data: .skip 256
48// In: $r15 error code (see nvc0.fuc) 52// In: $r15 error code (see nvc0.fuc)
49// 53//
50error: 54error:
51 push $r14 55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
52 mov $r14 0x814
53 shl b32 $r14 6
54 iowr I[$r14 + 0x000] $r15 // CC_SCRATCH[5] = error code
55 mov $r14 0xc1c
56 shl b32 $r14 6
57 mov $r15 1 56 mov $r15 1
58 iowr I[$r14 + 0x000] $r15 // INTR_UP_SET 57 nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
59 pop $r14
60 ret 58 ret
61 59
62// HUB fuc initialisation, executed by triggering ucode start, will 60// HUB fuc initialisation, executed by triggering ucode start, will
63// fall through to main loop after completion. 61// fall through to main loop after completion.
64// 62//
65// Input:
66// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
67//
68// Output: 63// Output:
69// CC_SCRATCH[0]: 64// CC_SCRATCH[0]:
70// 31:31: set to signal completion 65// 31:31: set to signal completion
@@ -141,31 +136,12 @@ init:
141 iowr I[$r2 + 0x000] $r1 136 iowr I[$r2 + 0x000] $r1
142 iowr I[$r2 + 0x100] $r1 137 iowr I[$r2 + 0x100] $r1
143 138
144 // find context data for this chipset
145 mov $r2 0x800
146 shl b32 $r2 6
147 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
148 mov $r15 #chipsets - 8
149 init_find_chipset:
150 add b32 $r15 8
151 ld b32 $r3 D[$r15 + 0x00]
152 cmpu b32 $r3 $r2
153 bra e #init_context
154 cmpu b32 $r3 0
155 bra ne #init_find_chipset
156 // unknown chipset
157 ret
158
159 // context size calculation, reserve first 256 bytes for use by fuc 139 // context size calculation, reserve first 256 bytes for use by fuc
160 init_context:
161 mov $r1 256 140 mov $r1 256
162 141
163 // calculate size of mmio context data 142 // calculate size of mmio context data
164 ld b16 $r14 D[$r15 + 4] 143 ld b32 $r14 D[$r0 + #hub_mmio_list_head]
165 ld b16 $r15 D[$r15 + 6] 144 ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
166 sethi $r14 0
167 st b32 D[$r0 + #hub_mmio_list_head] $r14
168 st b32 D[$r0 + #hub_mmio_list_tail] $r15
169 call #mmctx_size 145 call #mmctx_size
170 146
171 // set mmctx base addresses now so we don't have to do it later, 147 // set mmctx base addresses now so we don't have to do it later,
@@ -204,9 +180,6 @@ init:
204 add b32 $r14 $r4 0x804 180 add b32 $r14 $r4 0x804
205 mov b32 $r15 $r1 181 mov b32 $r15 $r1
206 call #nv_wr32 // CC_SCRATCH[1] = ctx offset 182 call #nv_wr32 // CC_SCRATCH[1] = ctx offset
207 add b32 $r14 $r4 0x800
208 mov b32 $r15 $r2
209 call #nv_wr32 // CC_SCRATCH[0] = chipset
210 add b32 $r14 $r4 0x10c 183 add b32 $r14 $r4 0x10c
211 clear b32 $r15 184 clear b32 $r15
212 call #nv_wr32 185 call #nv_wr32
@@ -232,13 +205,10 @@ init:
232 bra ne #init_gpc 205 bra ne #init_gpc
233 206
234 // save context size, and tell host we're ready 207 // save context size, and tell host we're ready
235 mov $r2 0x800 208 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
236 shl b32 $r2 6
237 iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size
238 add b32 $r2 0x800
239 clear b32 $r1 209 clear b32 $r1
240 bset $r1 31 210 bset $r1 31
241 iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000 211 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
242 212
243// Main program loop, very simple, sleeps until woken up by the interrupt 213// Main program loop, very simple, sleeps until woken up by the interrupt
244// handler, pulls a command from the queue and executes its handler 214// handler, pulls a command from the queue and executes its handler
@@ -330,11 +300,9 @@ main:
330 bra #main 300 bra #main
331 301
332 main_done: 302 main_done:
333 mov $r1 0x820
334 shl b32 $r1 6
335 clear b32 $r2 303 clear b32 $r2
336 bset $r2 31 304 bset $r2 31
337 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 305 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
338 bra #main 306 bra #main
339 307
340// interrupt handler 308// interrupt handler
@@ -348,6 +316,7 @@ ih:
348 push $r13 316 push $r13
349 push $r14 317 push $r14
350 push $r15 318 push $r15
319 clear b32 $r0
351 320
352 // incoming fifo command? 321 // incoming fifo command?
353 iord $r10 I[$r0 + 0x200] // INTR 322 iord $r10 I[$r0 + 0x200] // INTR
@@ -398,7 +367,7 @@ ih:
398 bclr $flags $p0 367 bclr $flags $p0
399 iret 368 iret
400 369
401#ifdef NVGF 370#if CHIPSET < GK100
402// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done 371// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
403ctx_4160s: 372ctx_4160s:
404 mov $r14 0x4160 373 mov $r14 0x4160
@@ -562,7 +531,7 @@ ctx_load:
562// In: $r2 channel address 531// In: $r2 channel address
563// 532//
564ctx_chan: 533ctx_chan:
565#ifdef NVGF 534#if CHIPSET < GK100
566 call #ctx_4160s 535 call #ctx_4160s
567#endif 536#endif
568 call #ctx_load 537 call #ctx_load
@@ -576,7 +545,7 @@ ctx_chan:
576 iord $r2 I[$r1 + 0x000] 545 iord $r2 I[$r1 + 0x000]
577 or $r2 $r2 546 or $r2 $r2
578 bra ne #ctx_chan_wait 547 bra ne #ctx_chan_wait
579#ifdef NVGF 548#if CHIPSET < GK100
580 call #ctx_4160c 549 call #ctx_4160c
581#endif 550#endif
582 ret 551 ret
@@ -655,7 +624,7 @@ ctx_xfer:
655 ctx_xfer_pre: 624 ctx_xfer_pre:
656 mov $r15 0x10 625 mov $r15 0x10
657 call #ctx_86c 626 call #ctx_86c
658#ifdef NVGF 627#if CHIPSET < GK100
659 call #ctx_4160s 628 call #ctx_4160s
660#endif 629#endif
661 bra not $p1 #ctx_xfer_exec 630 bra not $p1 #ctx_xfer_exec
@@ -746,7 +715,7 @@ ctx_xfer:
746 call #ctx_mmio_exec 715 call #ctx_mmio_exec
747 716
748 ctx_xfer_no_post_mmio: 717 ctx_xfer_no_post_mmio:
749#ifdef NVGF 718#if CHIPSET < GK100
750 call #ctx_4160c 719 call #ctx_4160c
751#endif 720#endif
752 721
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index f144f665b807..3ff52badf932 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -22,92 +22,13 @@
22 * Authors: Ben Skeggs <bskeggs@redhat.com> 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */ 23 */
24 24
25#define NVGF 25#define CHIPSET GF100
26#include "macros.fuc" 26#include "macros.fuc"
27 27
28.section #nvc0_grhub_data 28.section #nvc0_grhub_data
29#define INCLUDE_DATA 29#define INCLUDE_DATA
30#include "com.fuc" 30#include "com.fuc"
31#include "hub.fuc" 31#include "hub.fuc"
32
33chipsets:
34.b8 0xc0 0 0 0
35.b16 #nvc0_hub_mmio_head
36.b16 #nvc0_hub_mmio_tail
37.b8 0xc1 0 0 0
38.b16 #nvc0_hub_mmio_head
39.b16 #nvc1_hub_mmio_tail
40.b8 0xc3 0 0 0
41.b16 #nvc0_hub_mmio_head
42.b16 #nvc0_hub_mmio_tail
43.b8 0xc4 0 0 0
44.b16 #nvc0_hub_mmio_head
45.b16 #nvc0_hub_mmio_tail
46.b8 0xc8 0 0 0
47.b16 #nvc0_hub_mmio_head
48.b16 #nvc0_hub_mmio_tail
49.b8 0xce 0 0 0
50.b16 #nvc0_hub_mmio_head
51.b16 #nvc0_hub_mmio_tail
52.b8 0xcf 0 0 0
53.b16 #nvc0_hub_mmio_head
54.b16 #nvc0_hub_mmio_tail
55.b8 0xd9 0 0 0
56.b16 #nvd9_hub_mmio_head
57.b16 #nvd9_hub_mmio_tail
58.b8 0xd7 0 0 0
59.b16 #nvd9_hub_mmio_head
60.b16 #nvd9_hub_mmio_tail
61.b8 0 0 0 0
62
63nvc0_hub_mmio_head:
64mmctx_data(0x40402c, 1)
65mmctx_data(0x404174, 1)
66nvd9_hub_mmio_head:
67mmctx_data(0x17e91c, 2)
68mmctx_data(0x400204, 2)
69mmctx_data(0x404004, 10)
70mmctx_data(0x404044, 1)
71mmctx_data(0x404094, 14)
72mmctx_data(0x4040d0, 7)
73mmctx_data(0x4040f8, 1)
74mmctx_data(0x404130, 3)
75mmctx_data(0x404150, 3)
76mmctx_data(0x404164, 2)
77mmctx_data(0x404178, 2)
78mmctx_data(0x404200, 8)
79mmctx_data(0x404404, 14)
80mmctx_data(0x404460, 4)
81mmctx_data(0x404480, 1)
82mmctx_data(0x404498, 1)
83mmctx_data(0x404604, 4)
84mmctx_data(0x404618, 32)
85mmctx_data(0x404698, 21)
86mmctx_data(0x4046f0, 2)
87mmctx_data(0x404700, 22)
88mmctx_data(0x405800, 1)
89mmctx_data(0x405830, 3)
90mmctx_data(0x405854, 1)
91mmctx_data(0x405870, 4)
92mmctx_data(0x405a00, 2)
93mmctx_data(0x405a18, 1)
94mmctx_data(0x406020, 1)
95mmctx_data(0x406028, 4)
96mmctx_data(0x4064a8, 2)
97mmctx_data(0x4064b4, 2)
98mmctx_data(0x407804, 1)
99mmctx_data(0x40780c, 6)
100mmctx_data(0x4078bc, 1)
101mmctx_data(0x408000, 7)
102mmctx_data(0x408064, 1)
103mmctx_data(0x408800, 3)
104mmctx_data(0x408900, 3)
105mmctx_data(0x408980, 1)
106nvc0_hub_mmio_tail:
107mmctx_data(0x4064c0, 2)
108nvc1_hub_mmio_tail:
109mmctx_data(0x4064bc, 3)
110nvd9_hub_mmio_tail:
111#undef INCLUDE_DATA 32#undef INCLUDE_DATA
112 33
113.section #nvc0_grhub_code 34.section #nvc0_grhub_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index d1bf23001830..b59f694c0423 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -1,9 +1,13 @@
1uint32_t nvc0_grhub_data[] = { 1uint32_t nvc0_grhub_data[] = {
2/* 0x0000: gpc_count */ 2/* 0x0000: hub_mmio_list_head */
3 0x00000300,
4/* 0x0004: hub_mmio_list_tail */
5 0x00000304,
6/* 0x0008: gpc_count */
3 0x00000000, 7 0x00000000,
4/* 0x0004: rop_count */ 8/* 0x000c: rop_count */
5 0x00000000, 9 0x00000000,
6/* 0x0008: cmd_queue */ 10/* 0x0010: cmd_queue */
7 0x00000000, 11 0x00000000,
8 0x00000000, 12 0x00000000,
9 0x00000000, 13 0x00000000,
@@ -22,10 +26,6 @@ uint32_t nvc0_grhub_data[] = {
22 0x00000000, 26 0x00000000,
23 0x00000000, 27 0x00000000,
24 0x00000000, 28 0x00000000,
25/* 0x0050: hub_mmio_list_head */
26 0x00000000,
27/* 0x0054: hub_mmio_list_tail */
28 0x00000000,
29/* 0x0058: ctx_current */ 29/* 0x0058: ctx_current */
30 0x00000000, 30 0x00000000,
31 0x00000000, 31 0x00000000,
@@ -201,84 +201,19 @@ uint32_t nvc0_grhub_data[] = {
201 0x00000000, 201 0x00000000,
202 0x00000000, 202 0x00000000,
203 0x00000000, 203 0x00000000,
204/* 0x0300: chipsets */ 204/* 0x0300: hub_mmio_list_base */
205 0x000000c0,
206 0x03f0034c,
207 0x000000c1,
208 0x03f4034c,
209 0x000000c3,
210 0x03f0034c,
211 0x000000c4,
212 0x03f0034c,
213 0x000000c8,
214 0x03f0034c,
215 0x000000ce,
216 0x03f0034c,
217 0x000000cf,
218 0x03f0034c,
219 0x000000d9,
220 0x03f80354,
221 0x000000d7,
222 0x03f80354,
223 0x00000000,
224/* 0x034c: nvc0_hub_mmio_head */
225 0x0040402c,
226 0x00404174,
227/* 0x0354: nvd9_hub_mmio_head */
228 0x0417e91c, 205 0x0417e91c,
229 0x04400204,
230 0x24404004,
231 0x00404044,
232 0x34404094,
233 0x184040d0,
234 0x004040f8,
235 0x08404130,
236 0x08404150,
237 0x04404164,
238 0x04404178,
239 0x1c404200,
240 0x34404404,
241 0x0c404460,
242 0x00404480,
243 0x00404498,
244 0x0c404604,
245 0x7c404618,
246 0x50404698,
247 0x044046f0,
248 0x54404700,
249 0x00405800,
250 0x08405830,
251 0x00405854,
252 0x0c405870,
253 0x04405a00,
254 0x00405a18,
255 0x00406020,
256 0x0c406028,
257 0x044064a8,
258 0x044064b4,
259 0x00407804,
260 0x1440780c,
261 0x004078bc,
262 0x18408000,
263 0x00408064,
264 0x08408800,
265 0x08408900,
266 0x00408980,
267/* 0x03f0: nvc0_hub_mmio_tail */
268 0x044064c0,
269/* 0x03f4: nvc1_hub_mmio_tail */
270 0x084064bc,
271}; 206};
272 207
273uint32_t nvc0_grhub_code[] = { 208uint32_t nvc0_grhub_code[] = {
274 0x03090ef5, 209 0x031b0ef5,
275/* 0x0004: queue_put */ 210/* 0x0004: queue_put */
276 0x9800d898, 211 0x9800d898,
277 0x86f001d9, 212 0x86f001d9,
278 0x0489b808, 213 0x0489b808,
279 0xf00c1bf4, 214 0xf00c1bf4,
280 0x21f502f7, 215 0x21f502f7,
281 0x00f802ec, 216 0x00f802fe,
282/* 0x001c: queue_put_next */ 217/* 0x001c: queue_put_next */
283 0xb60798c4, 218 0xb60798c4,
284 0x8dbb0384, 219 0x8dbb0384,
@@ -310,7 +245,7 @@ uint32_t nvc0_grhub_code[] = {
310 0xc800bccf, 245 0xc800bccf,
311 0x1bf41fcc, 246 0x1bf41fcc,
312 0x06a7f0fa, 247 0x06a7f0fa,
313 0x010321f5, 248 0x010921f5,
314 0xf840bfcf, 249 0xf840bfcf,
315/* 0x008d: nv_wr32 */ 250/* 0x008d: nv_wr32 */
316 0x28b7f100, 251 0x28b7f100,
@@ -332,63 +267,66 @@ uint32_t nvc0_grhub_code[] = {
332 0x0684b604, 267 0x0684b604,
333 0xf80080d0, 268 0xf80080d0,
334/* 0x00c9: wait_donez */ 269/* 0x00c9: wait_donez */
335 0x3c87f100, 270 0xf094bd00,
336 0x0684b608, 271 0x07f10099,
337 0x99f094bd, 272 0x03f00f00,
338 0x0089d000, 273 0x0009d002,
339 0x081887f1, 274 0x07f104bd,
340 0xd00684b6, 275 0x03f00600,
341/* 0x00e2: wait_donez_ne */ 276 0x000ad002,
342 0x87f1008a, 277/* 0x00e6: wait_donez_ne */
343 0x84b60400, 278 0x87f104bd,
344 0x0088cf06, 279 0x83f00000,
280 0x0088cf01,
345 0xf4888aff, 281 0xf4888aff,
346 0x87f1f31b, 282 0x94bdf31b,
347 0x84b6085c, 283 0xf10099f0,
348 0xf094bd06, 284 0xf0170007,
349 0x89d00099, 285 0x09d00203,
350/* 0x0103: wait_doneo */ 286 0xf804bd00,
351 0xf100f800, 287/* 0x0109: wait_doneo */
352 0xb6083c87, 288 0xf094bd00,
353 0x94bd0684, 289 0x07f10099,
354 0xd00099f0, 290 0x03f00f00,
355 0x87f10089, 291 0x0009d002,
292 0x87f104bd,
356 0x84b60818, 293 0x84b60818,
357 0x008ad006, 294 0x008ad006,
358/* 0x011c: wait_doneo_e */ 295/* 0x0124: wait_doneo_e */
359 0x040087f1, 296 0x040087f1,
360 0xcf0684b6, 297 0xcf0684b6,
361 0x8aff0088, 298 0x8aff0088,
362 0xf30bf488, 299 0xf30bf488,
363 0x085c87f1, 300 0x99f094bd,
364 0xbd0684b6, 301 0x0007f100,
365 0x0099f094, 302 0x0203f017,
366 0xf80089d0, 303 0xbd0009d0,
367/* 0x013d: mmctx_size */ 304/* 0x0147: mmctx_size */
368/* 0x013f: nv_mmctx_size_loop */ 305 0xbd00f804,
369 0x9894bd00, 306/* 0x0149: nv_mmctx_size_loop */
370 0x85b600e8, 307 0x00e89894,
371 0x0180b61a, 308 0xb61a85b6,
372 0xbb0284b6, 309 0x84b60180,
373 0xe0b60098, 310 0x0098bb02,
374 0x04efb804, 311 0xb804e0b6,
375 0xb9eb1bf4, 312 0x1bf404ef,
376 0x00f8029f, 313 0x029fb9eb,
377/* 0x015c: mmctx_xfer */ 314/* 0x0166: mmctx_xfer */
378 0x083c87f1, 315 0x94bd00f8,
379 0xbd0684b6, 316 0xf10199f0,
380 0x0199f094, 317 0xf00f0007,
381 0xf10089d0, 318 0x09d00203,
319 0xf104bd00,
382 0xb6071087, 320 0xb6071087,
383 0x94bd0684, 321 0x94bd0684,
384 0xf405bbfd, 322 0xf405bbfd,
385 0x8bd0090b, 323 0x8bd0090b,
386 0x0099f000, 324 0x0099f000,
387/* 0x0180: mmctx_base_disabled */ 325/* 0x018c: mmctx_base_disabled */
388 0xf405eefd, 326 0xf405eefd,
389 0x8ed00c0b, 327 0x8ed00c0b,
390 0xc08fd080, 328 0xc08fd080,
391/* 0x018f: mmctx_multi_disabled */ 329/* 0x019b: mmctx_multi_disabled */
392 0xb70199f0, 330 0xb70199f0,
393 0xc8010080, 331 0xc8010080,
394 0xb4b600ab, 332 0xb4b600ab,
@@ -396,8 +334,8 @@ uint32_t nvc0_grhub_code[] = {
396 0xb601aec8, 334 0xb601aec8,
397 0xbefd11e4, 335 0xbefd11e4,
398 0x008bd005, 336 0x008bd005,
399/* 0x01a8: mmctx_exec_loop */ 337/* 0x01b4: mmctx_exec_loop */
400/* 0x01a8: mmctx_wait_free */ 338/* 0x01b4: mmctx_wait_free */
401 0xf0008ecf, 339 0xf0008ecf,
402 0x0bf41fe4, 340 0x0bf41fe4,
403 0x00ce98fa, 341 0x00ce98fa,
@@ -406,76 +344,77 @@ uint32_t nvc0_grhub_code[] = {
406 0x04cdb804, 344 0x04cdb804,
407 0xc8e81bf4, 345 0xc8e81bf4,
408 0x1bf402ab, 346 0x1bf402ab,
409/* 0x01c9: mmctx_fini_wait */ 347/* 0x01d5: mmctx_fini_wait */
410 0x008bcf18, 348 0x008bcf18,
411 0xb01fb4f0, 349 0xb01fb4f0,
412 0x1bf410b4, 350 0x1bf410b4,
413 0x02a7f0f7, 351 0x02a7f0f7,
414 0xf4c921f4, 352 0xf4c921f4,
415/* 0x01de: mmctx_stop */ 353/* 0x01ea: mmctx_stop */
416 0xabc81b0e, 354 0xabc81b0e,
417 0x10b4b600, 355 0x10b4b600,
418 0xf00cb9f0, 356 0xf00cb9f0,
419 0x8bd012b9, 357 0x8bd012b9,
420/* 0x01ed: mmctx_stop_wait */ 358/* 0x01f9: mmctx_stop_wait */
421 0x008bcf00, 359 0x008bcf00,
422 0xf412bbc8, 360 0xf412bbc8,
423/* 0x01f6: mmctx_done */ 361/* 0x0202: mmctx_done */
424 0x87f1fa1b, 362 0x94bdfa1b,
425 0x84b6085c, 363 0xf10199f0,
426 0xf094bd06, 364 0xf0170007,
427 0x89d00199, 365 0x09d00203,
428/* 0x0207: strand_wait */ 366 0xf804bd00,
429 0xf900f800, 367/* 0x0215: strand_wait */
430 0x02a7f0a0, 368 0xf0a0f900,
431 0xfcc921f4, 369 0x21f402a7,
432/* 0x0213: strand_pre */ 370 0xf8a0fcc9,
433 0xf100f8a0, 371/* 0x0221: strand_pre */
434 0xf04afc87, 372 0xfc87f100,
435 0x97f00283, 373 0x0283f04a,
436 0x0089d00c, 374 0xd00c97f0,
437 0x020721f5,
438/* 0x0226: strand_post */
439 0x87f100f8,
440 0x83f04afc,
441 0x0d97f002,
442 0xf50089d0,
443 0xf8020721,
444/* 0x0239: strand_set */
445 0xfca7f100,
446 0x02a3f04f,
447 0x0500aba2,
448 0xd00fc7f0,
449 0xc7f000ac,
450 0x00bcd00b,
451 0x020721f5,
452 0xf000aed0,
453 0xbcd00ac7,
454 0x0721f500,
455/* 0x0263: strand_ctx_init */
456 0xf100f802,
457 0xb6083c87,
458 0x94bd0684,
459 0xd00399f0,
460 0x21f50089, 375 0x21f50089,
461 0xe7f00213, 376 0x00f80215,
462 0x3921f503, 377/* 0x0234: strand_post */
378 0x4afc87f1,
379 0xf00283f0,
380 0x89d00d97,
381 0x1521f500,
382/* 0x0247: strand_set */
383 0xf100f802,
384 0xf04ffca7,
385 0xaba202a3,
386 0xc7f00500,
387 0x00acd00f,
388 0xd00bc7f0,
389 0x21f500bc,
390 0xaed00215,
391 0x0ac7f000,
392 0xf500bcd0,
393 0xf8021521,
394/* 0x0271: strand_ctx_init */
395 0xf094bd00,
396 0x07f10399,
397 0x03f00f00,
398 0x0009d002,
399 0x21f504bd,
400 0xe7f00221,
401 0x4721f503,
463 0xfca7f102, 402 0xfca7f102,
464 0x02a3f046, 403 0x02a3f046,
465 0x0400aba0, 404 0x0400aba0,
466 0xf040a0d0, 405 0xf040a0d0,
467 0xbcd001c7, 406 0xbcd001c7,
468 0x0721f500, 407 0x1521f500,
469 0x010c9202, 408 0x010c9202,
470 0xf000acd0, 409 0xf000acd0,
471 0xbcd002c7, 410 0xbcd002c7,
472 0x0721f500, 411 0x1521f500,
473 0x2621f502, 412 0x3421f502,
474 0x8087f102, 413 0x8087f102,
475 0x0684b608, 414 0x0684b608,
476 0xb70089cf, 415 0xb70089cf,
477 0x95220080, 416 0x95220080,
478/* 0x02ba: ctx_init_strand_loop */ 417/* 0x02ca: ctx_init_strand_loop */
479 0x8ed008fe, 418 0x8ed008fe,
480 0x408ed000, 419 0x408ed000,
481 0xb6808acf, 420 0xb6808acf,
@@ -484,457 +423,451 @@ uint32_t nvc0_grhub_code[] = {
484 0xb60480b6, 423 0xb60480b6,
485 0x1bf40192, 424 0x1bf40192,
486 0x08e4b6e8, 425 0x08e4b6e8,
487 0xf1f2efbc, 426 0xbdf2efbc,
488 0xb6085c87, 427 0x0399f094,
489 0x94bd0684, 428 0x170007f1,
490 0xd00399f0, 429 0xd00203f0,
491 0x00f80089, 430 0x04bd0009,
492/* 0x02ec: error */ 431/* 0x02fe: error */
493 0xe7f1e0f9, 432 0x07f100f8,
494 0xe4b60814, 433 0x03f00500,
495 0x00efd006, 434 0x000fd002,
496 0x0c1ce7f1, 435 0xf7f004bd,
497 0xf006e4b6, 436 0x0007f101,
498 0xefd001f7, 437 0x0303f007,
499 0xf8e0fc00, 438 0xbd000fd0,
500/* 0x0309: init */ 439/* 0x031b: init */
501 0xfe04bd00, 440 0xbd00f804,
502 0x07fe0004, 441 0x0004fe04,
503 0x0017f100, 442 0xf10007fe,
504 0x0227f012, 443 0xf0120017,
505 0xf10012d0, 444 0x12d00227,
506 0xfe05ba17, 445 0xb117f100,
507 0x17f10010, 446 0x0010fe05,
508 0x10d00400, 447 0x040017f1,
509 0x0437f1c0, 448 0xf1c010d0,
510 0x0634b604, 449 0xb6040437,
511 0x200327f1, 450 0x27f10634,
512 0xf10032d0, 451 0x32d02003,
513 0xd0200427,
514 0x27f10132,
515 0x32d0200b,
516 0x0c27f102,
517 0x0732d020,
518 0x0c2427f1,
519 0xb90624b6,
520 0x23d00003,
521 0x0427f100, 452 0x0427f100,
522 0x0023f087, 453 0x0132d020,
523 0xb70012d0, 454 0x200b27f1,
524 0xf0010012, 455 0xf10232d0,
525 0x12d00427, 456 0xd0200c27,
526 0x1031f400, 457 0x27f10732,
527 0x9604e7f1, 458 0x24b60c24,
528 0xf440e3f0, 459 0x0003b906,
529 0xf1c76821, 460 0xf10023d0,
530 0x01018090, 461 0xf0870427,
531 0x801ff4f0, 462 0x12d00023,
532 0x17f0000f, 463 0x0012b700,
533 0x041fbb01, 464 0x0427f001,
534 0xf10112b6, 465 0xf40012d0,
535 0xb6040c27, 466 0xe7f11031,
536 0x21d00624, 467 0xe3f09604,
537 0x4021d000, 468 0x6821f440,
538 0x080027f1, 469 0x8090f1c7,
539 0xcf0624b6, 470 0xf4f00301,
540 0xf7f10022, 471 0x020f801f,
541/* 0x03aa: init_find_chipset */ 472 0xbb0117f0,
542 0xf0b602f8, 473 0x12b6041f,
543 0x00f39808, 474 0x0c27f101,
544 0xf40432b8, 475 0x0624b604,
545 0x34b00b0b, 476 0xd00021d0,
546 0xf11bf400, 477 0x17f14021,
547/* 0x03be: init_context */ 478 0x0e980100,
548 0x17f100f8, 479 0x010f9800,
549 0xfe580100, 480 0x014721f5,
550 0x03ff5802, 481 0x070037f1,
551 0x8000e3f0, 482 0x950634b6,
552 0x0f80140e, 483 0x34d00814,
553 0x3d21f515, 484 0x4034d000,
554 0x0037f101, 485 0x130030b7,
555 0x0634b607, 486 0xb6001fbb,
556 0xd0081495, 487 0x3fd002f5,
557 0x34d00034, 488 0x0815b600,
558 0x0030b740, 489 0xb60110b6,
559 0x001fbb13, 490 0x1fb90814,
560 0xd002f5b6, 491 0x7121f502,
561 0x15b6003f, 492 0x001fbb02,
562 0x0110b608, 493 0xf1020398,
563 0xb90814b6, 494 0xf0200047,
564 0x21f5021f, 495/* 0x03f6: init_gpc */
565 0x1fbb0263, 496 0x4ea05043,
566 0x00039800, 497 0x1fb90804,
567 0x200047f1, 498 0x8d21f402,
568/* 0x040f: init_gpc */ 499 0x010c4ea0,
569 0xa05043f0, 500 0x21f4f4bd,
570 0xb908044e, 501 0x044ea08d,
571 0x21f4021f, 502 0x8d21f401,
572 0x004ea08d, 503 0x01004ea0,
573 0x022fb908, 504 0xf402f7f0,
574 0xa08d21f4, 505 0x4ea08d21,
575 0xbd010c4e, 506/* 0x041e: init_gpc_wait */
576 0x8d21f4f4, 507 0x21f40800,
577 0x01044ea0, 508 0x1fffc868,
578 0xa08d21f4, 509 0xa0fa0bf4,
579 0xf001004e, 510 0xf408044e,
580 0x21f402f7, 511 0x1fbb6821,
581 0x004ea08d, 512 0x0040b700,
582/* 0x0441: init_gpc_wait */ 513 0x0132b680,
583 0x6821f408, 514 0xf1be1bf4,
584 0xf41fffc8, 515 0xf0010007,
585 0x4ea0fa0b, 516 0x01d00203,
586 0x21f40804, 517 0xbd04bd00,
587 0x001fbb68, 518 0x1f19f014,
588 0x800040b7, 519 0x080007f1,
589 0xf40132b6, 520 0xd00203f0,
590 0x27f1b41b, 521 0x04bd0001,
591 0x24b60800, 522/* 0x0458: main */
592 0x4021d006,
593 0x080020b7,
594 0x19f014bd,
595 0x0021d01f,
596/* 0x0474: main */
597 0xf40031f4, 523 0xf40031f4,
598 0xd7f00028, 524 0xd7f00028,
599 0x3921f408, 525 0x3921f410,
600 0xb1f401f4, 526 0xb1f401f4,
601 0xf54001e4, 527 0xf54001e4,
602 0xf100d11b, 528 0xbd00de1b,
603 0xb6083c87, 529 0x0499f094,
604 0x94bd0684, 530 0x0f0007f1,
605 0xd00499f0, 531 0xd00203f0,
606 0x17f10089, 532 0x04bd0009,
607 0x14b60b00, 533 0x0b0017f1,
608 0x4012cf06, 534 0xcf0614b6,
609 0xc80011cf, 535 0x11cf4012,
610 0x0bf41f13, 536 0x1f13c800,
611 0x1f23c87e, 537 0x00870bf5,
612 0xf95a0bf4,
613 0x0212b920,
614 0x083c87f1,
615 0xbd0684b6,
616 0x0799f094,
617 0xf40089d0,
618 0x31f40132,
619 0x2a21f502,
620 0x5c87f108,
621 0x0684b608,
622 0x99f094bd,
623 0x0089d007,
624 0x87f120fc,
625 0x84b6083c,
626 0xf094bd06,
627 0x89d00699,
628 0x0131f400,
629 0x082a21f5,
630 0x085c87f1,
631 0xbd0684b6,
632 0x0699f094,
633 0xf40089d0,
634/* 0x050a: chsw_prev_no_next */
635 0x20f9310e,
636 0xf40212b9,
637 0x32f40132,
638 0x2a21f502,
639 0xf120fc08,
640 0xb60b0017,
641 0x12d00614,
642 0x130ef400,
643/* 0x0528: chsw_no_prev */
644 0xf41f23c8, 538 0xf41f23c8,
645 0x31f40d0b, 539 0x20f9620b,
540 0xbd0212b9,
541 0x0799f094,
542 0x0f0007f1,
543 0xd00203f0,
544 0x04bd0009,
545 0xf40132f4,
546 0x21f50231,
547 0x94bd082f,
548 0xf10799f0,
549 0xf0170007,
550 0x09d00203,
551 0xfc04bd00,
552 0xf094bd20,
553 0x07f10699,
554 0x03f00f00,
555 0x0009d002,
556 0x31f404bd,
557 0x2f21f501,
558 0xf094bd08,
559 0x07f10699,
560 0x03f01700,
561 0x0009d002,
562 0x0ef404bd,
563/* 0x04f9: chsw_prev_no_next */
564 0xb920f931,
565 0x32f40212,
646 0x0232f401, 566 0x0232f401,
647 0x082a21f5, 567 0x082f21f5,
648/* 0x0538: chsw_done */ 568 0x17f120fc,
649 0x0b0c17f1, 569 0x14b60b00,
650 0xf00614b6, 570 0x0012d006,
651 0x12d00127, 571/* 0x0517: chsw_no_prev */
652 0x5c87f100, 572 0xc8130ef4,
653 0x0684b608, 573 0x0bf41f23,
654 0x99f094bd, 574 0x0131f40d,
655 0x0089d004,
656 0xff200ef5,
657/* 0x0558: main_not_ctx_switch */
658 0xf401e4b0,
659 0xf2b90d1b,
660 0xb621f502,
661 0x420ef407,
662/* 0x0568: main_not_ctx_chan */
663 0xf402e4b0,
664 0x87f12e1b,
665 0x84b6083c,
666 0xf094bd06,
667 0x89d00799,
668 0x0132f400,
669 0xf50232f4, 575 0xf50232f4,
670 0xf1082a21, 576/* 0x0527: chsw_done */
671 0xb6085c87, 577 0xf1082f21,
672 0x94bd0684, 578 0xb60b0c17,
673 0xd00799f0, 579 0x27f00614,
674 0x0ef40089, 580 0x0012d001,
675/* 0x0599: main_not_ctx_save */ 581 0x99f094bd,
676 0x10ef9411, 582 0x0007f104,
677 0xf501f5f0, 583 0x0203f017,
678 0xf502ec21, 584 0xbd0009d0,
679/* 0x05a7: main_done */ 585 0x130ef504,
680 0xf1fed10e, 586/* 0x0549: main_not_ctx_switch */
681 0xb6082017, 587 0x01e4b0ff,
682 0x24bd0614, 588 0xb90d1bf4,
683 0xd01f29f0, 589 0x21f502f2,
684 0x0ef50012, 590 0x0ef407bb,
685/* 0x05ba: ih */ 591/* 0x0559: main_not_ctx_chan */
686 0x80f9febe, 592 0x02e4b046,
687 0xf90188fe, 593 0xbd321bf4,
688 0xf990f980, 594 0x0799f094,
689 0xf9b0f9a0, 595 0x0f0007f1,
690 0xf9e0f9d0, 596 0xd00203f0,
691 0x800acff0, 597 0x04bd0009,
692 0xf404abc4, 598 0xf40132f4,
693 0xb7f11d0b, 599 0x21f50232,
694 0xd7f01900, 600 0x94bd082f,
695 0x40becf08, 601 0xf10799f0,
696 0xf400bfcf, 602 0xf0170007,
697 0xb0b70421, 603 0x09d00203,
698 0xe7f00400, 604 0xf404bd00,
699 0x00bed001, 605/* 0x058e: main_not_ctx_save */
700/* 0x05f0: ih_no_fifo */ 606 0xef94110e,
701 0x0100abe4, 607 0x01f5f010,
702 0xf00d0bf4, 608 0x02fe21f5,
703 0xe7f108d7, 609 0xfec00ef5,
704 0x21f44001, 610/* 0x059c: main_done */
705/* 0x0601: ih_no_ctxsw */ 611 0x29f024bd,
706 0x04b7f104, 612 0x0007f11f,
707 0xffb0bd01, 613 0x0203f008,
708 0x0bf4b4ab, 614 0xbd0002d0,
709 0x1ca7f10d, 615 0xab0ef504,
710 0x06a4b60c, 616/* 0x05b1: ih */
711/* 0x0617: ih_no_other */ 617 0xfe80f9fe,
712 0xd000abd0, 618 0x80f90188,
713 0xf0fc400a, 619 0xa0f990f9,
714 0xd0fce0fc, 620 0xd0f9b0f9,
715 0xa0fcb0fc, 621 0xf0f9e0f9,
716 0x80fc90fc, 622 0x0acf04bd,
717 0xfc0088fe, 623 0x04abc480,
718 0x0032f480, 624 0xf11d0bf4,
719/* 0x0632: ctx_4160s */ 625 0xf01900b7,
720 0xe7f101f8, 626 0xbecf10d7,
721 0xe3f04160, 627 0x00bfcf40,
722 0x01f7f040, 628 0xb70421f4,
723/* 0x063f: ctx_4160s_wait */ 629 0xf00400b0,
724 0xf48d21f4, 630 0xbed001e7,
725 0xffc86821, 631/* 0x05e9: ih_no_fifo */
726 0xfa0bf404, 632 0x00abe400,
727/* 0x064a: ctx_4160c */ 633 0x0d0bf401,
728 0xe7f100f8, 634 0xf110d7f0,
729 0xe3f04160, 635 0xf44001e7,
730 0xf4f4bd40, 636/* 0x05fa: ih_no_ctxsw */
637 0xb7f10421,
638 0xb0bd0104,
639 0xf4b4abff,
640 0xa7f10d0b,
641 0xa4b60c1c,
642 0x00abd006,
643/* 0x0610: ih_no_other */
644 0xfc400ad0,
645 0xfce0fcf0,
646 0xfcb0fcd0,
647 0xfc90fca0,
648 0x0088fe80,
649 0x32f480fc,
650/* 0x062b: ctx_4160s */
651 0xf101f800,
652 0xf04160e7,
653 0xf7f040e3,
654 0x8d21f401,
655/* 0x0638: ctx_4160s_wait */
656 0xc86821f4,
657 0x0bf404ff,
658/* 0x0643: ctx_4160c */
659 0xf100f8fa,
660 0xf04160e7,
661 0xf4bd40e3,
662 0xf88d21f4,
663/* 0x0651: ctx_4170s */
664 0x70e7f100,
665 0x40e3f041,
666 0xf410f5f0,
731 0x00f88d21, 667 0x00f88d21,
732/* 0x0658: ctx_4170s */ 668/* 0x0660: ctx_4170w */
733 0x4170e7f1, 669 0x4170e7f1,
734 0xf040e3f0, 670 0xf440e3f0,
735 0x21f410f5, 671 0xf4f06821,
736/* 0x0667: ctx_4170w */ 672 0xf31bf410,
737 0xf100f88d, 673/* 0x0672: ctx_redswitch */
738 0xf04170e7, 674 0xe7f100f8,
739 0x21f440e3, 675 0xe4b60614,
740 0x10f4f068, 676 0x70f7f106,
741 0xf8f31bf4, 677 0x00efd002,
742/* 0x0679: ctx_redswitch */ 678/* 0x0683: ctx_redswitch_delay */
743 0x14e7f100, 679 0xb608f7f0,
744 0x06e4b606, 680 0x1bf401f2,
745 0x0270f7f1, 681 0x70f7f1fd,
746 0xf000efd0, 682 0x00efd007,
747/* 0x068a: ctx_redswitch_delay */ 683/* 0x0692: ctx_86c */
748 0xf2b608f7, 684 0xe7f100f8,
749 0xfd1bf401, 685 0xe4b6086c,
750 0x0770f7f1, 686 0x00efd006,
751 0xf800efd0, 687 0x8a14e7f1,
752/* 0x0699: ctx_86c */ 688 0xf440e3f0,
753 0x6ce7f100, 689 0xe7f18d21,
754 0x06e4b608, 690 0xe3f0a86c,
755 0xf100efd0, 691 0x8d21f441,
756 0xf08a14e7, 692/* 0x06b2: ctx_load */
757 0x21f440e3, 693 0x94bd00f8,
758 0x6ce7f18d, 694 0xf10599f0,
759 0x41e3f0a8, 695 0xf00f0007,
760 0xf88d21f4, 696 0x09d00203,
761/* 0x06b9: ctx_load */ 697 0xf004bd00,
762 0x3c87f100, 698 0x21f40ca7,
763 0x0684b608, 699 0x2417f1c9,
700 0x0614b60a,
701 0xf10010d0,
702 0xb60b0037,
703 0x32d00634,
704 0x0c17f140,
705 0x0614b60a,
706 0xd00747f0,
707 0x14d00012,
708/* 0x06ed: ctx_chan_wait_0 */
709 0x4014cf40,
710 0xf41f44f0,
711 0x32d0fa1b,
712 0x000bfe00,
713 0xb61f2af0,
714 0x20b60424,
715 0xf094bd02,
716 0x07f10899,
717 0x03f00f00,
718 0x0009d002,
719 0x17f104bd,
720 0x14b60a04,
721 0x0012d006,
722 0x0a2017f1,
723 0xf00614b6,
724 0x23f10227,
725 0x12d08000,
726 0x1017f000,
727 0x020027f1,
728 0xfa0223f0,
729 0x03f80512,
764 0x99f094bd, 730 0x99f094bd,
765 0x0089d005, 731 0x0007f108,
766 0xf40ca7f0, 732 0x0203f017,
767 0x17f1c921, 733 0xbd0009d0,
768 0x14b60a24, 734 0x81019804,
769 0x0010d006, 735 0x981814b6,
770 0x0b0037f1, 736 0x25b68002,
771 0xd00634b6, 737 0x0512fd08,
772 0x17f14032, 738 0xbd160180,
773 0x14b60a0c, 739 0x0999f094,
774 0x0747f006, 740 0x0f0007f1,
775 0xd00012d0, 741 0xd00203f0,
776/* 0x06f2: ctx_chan_wait_0 */ 742 0x04bd0009,
777 0x14cf4014, 743 0x0a0427f1,
778 0x1f44f040, 744 0xd00624b6,
779 0xd0fa1bf4, 745 0x27f00021,
780 0x0bfe0032, 746 0x2017f101,
781 0x1f2af000,
782 0xb60424b6,
783 0x87f10220,
784 0x84b6083c,
785 0xf094bd06,
786 0x89d00899,
787 0x0417f100,
788 0x0614b60a, 747 0x0614b60a,
789 0xf10012d0, 748 0xf10012d0,
790 0xb60a2017, 749 0xf0010017,
791 0x27f00614, 750 0x01fa0613,
792 0x0023f102, 751 0xbd03f805,
793 0x0012d080,
794 0xf11017f0,
795 0xf0020027,
796 0x12fa0223,
797 0xf103f805,
798 0xb6085c87,
799 0x94bd0684,
800 0xd00899f0,
801 0x01980089,
802 0x1814b681,
803 0xb6800298,
804 0x12fd0825,
805 0x16018005,
806 0x083c87f1,
807 0xbd0684b6,
808 0x0999f094, 752 0x0999f094,
809 0xf10089d0, 753 0x170007f1,
810 0xb60a0427, 754 0xd00203f0,
811 0x21d00624, 755 0x04bd0009,
812 0x0127f000,
813 0x0a2017f1,
814 0xd00614b6,
815 0x17f10012,
816 0x13f00100,
817 0x0501fa06,
818 0x87f103f8,
819 0x84b6085c,
820 0xf094bd06,
821 0x89d00999,
822 0x5c87f100,
823 0x0684b608,
824 0x99f094bd, 756 0x99f094bd,
825 0x0089d005, 757 0x0007f105,
826/* 0x07b6: ctx_chan */ 758 0x0203f017,
827 0x21f500f8, 759 0xbd0009d0,
828 0x21f50632, 760/* 0x07bb: ctx_chan */
829 0xa7f006b9, 761 0xf500f804,
830 0xc921f40c, 762 0xf5062b21,
831 0x0a1017f1, 763 0xf006b221,
832 0xf00614b6, 764 0x21f40ca7,
833 0x12d00527, 765 0x1017f1c9,
834/* 0x07d1: ctx_chan_wait */ 766 0x0614b60a,
835 0x0012cf00, 767 0xd00527f0,
836 0xf40522fd, 768/* 0x07d6: ctx_chan_wait */
837 0x21f5fa1b, 769 0x12cf0012,
838 0x00f8064a, 770 0x0522fd00,
839/* 0x07e0: ctx_mmio_exec */ 771 0xf5fa1bf4,
840 0xf1410398, 772 0xf8064321,
841 0xb60a0427, 773/* 0x07e5: ctx_mmio_exec */
842 0x23d00624, 774 0x41039800,
843/* 0x07ef: ctx_mmio_loop */ 775 0x0a0427f1,
844 0xc434bd00, 776 0xd00624b6,
845 0x1bf4ff34, 777 0x34bd0023,
846 0x0057f10f, 778/* 0x07f4: ctx_mmio_loop */
847 0x0653f002, 779 0xf4ff34c4,
848 0xf80535fa, 780 0x57f10f1b,
849/* 0x0801: ctx_mmio_pull */ 781 0x53f00200,
850 0x804e9803, 782 0x0535fa06,
851 0xf4814f98, 783/* 0x0806: ctx_mmio_pull */
852 0x30b68d21, 784 0x4e9803f8,
853 0x0112b608, 785 0x814f9880,
854/* 0x0813: ctx_mmio_done */ 786 0xb68d21f4,
855 0x98df1bf4, 787 0x12b60830,
856 0x23d01603, 788 0xdf1bf401,
857 0x40008000, 789/* 0x0818: ctx_mmio_done */
858 0x010017f1, 790 0xd0160398,
859 0xfa0613f0, 791 0x00800023,
860 0x03f80601, 792 0x0017f140,
861/* 0x082a: ctx_xfer */ 793 0x0613f001,
862 0xf7f100f8, 794 0xf80601fa,
863 0xf4b60c00, 795/* 0x082f: ctx_xfer */
864 0x04e7f006, 796 0xf100f803,
865/* 0x0837: ctx_xfer_idle */ 797 0xb60c00f7,
866 0xcf80fed0, 798 0xe7f006f4,
867 0xe4f100fe, 799 0x80fed004,
868 0x1bf42000, 800/* 0x083c: ctx_xfer_idle */
869 0x0611f4f9, 801 0xf100fecf,
870/* 0x0847: ctx_xfer_pre */ 802 0xf42000e4,
871 0xf01102f4, 803 0x11f4f91b,
872 0x21f510f7, 804 0x1102f406,
873 0x21f50699, 805/* 0x084c: ctx_xfer_pre */
874 0x11f40632, 806 0xf510f7f0,
875/* 0x0855: ctx_xfer_pre_load */ 807 0xf5069221,
876 0x02f7f01c, 808 0xf4062b21,
877 0x065821f5, 809/* 0x085a: ctx_xfer_pre_load */
878 0x066721f5, 810 0xf7f01c11,
879 0x067921f5, 811 0x5121f502,
880 0x21f5f4bd, 812 0x6021f506,
881 0x21f50658, 813 0x7221f506,
882/* 0x086e: ctx_xfer_exec */ 814 0xf5f4bd06,
883 0x019806b9, 815 0xf5065121,
884 0x1427f116, 816/* 0x0873: ctx_xfer_exec */
885 0x0624b604, 817 0x9806b221,
886 0xf10020d0, 818 0x27f11601,
887 0xf0a500e7, 819 0x24b60414,
888 0x1fb941e3, 820 0x0020d006,
889 0x8d21f402, 821 0xa500e7f1,
890 0xf004e0b6, 822 0xb941e3f0,
891 0x2cf001fc, 823 0x21f4021f,
892 0x0124b602, 824 0x04e0b68d,
893 0xf405f2fd, 825 0xf001fcf0,
894 0x17f18d21, 826 0x24b6022c,
895 0x13f04afc, 827 0x05f2fd01,
896 0x0c27f002, 828 0xf18d21f4,
897 0xf50012d0, 829 0xf04afc17,
898 0xf1020721, 830 0x27f00213,
899 0xf047fc27, 831 0x0012d00c,
900 0x20d00223, 832 0x021521f5,
901 0x012cf000, 833 0x47fc27f1,
902 0xd00320b6, 834 0xd00223f0,
903 0xacf00012, 835 0x2cf00020,
904 0x06a5f001, 836 0x0320b601,
905 0x9800b7f0, 837 0xf00012d0,
906 0x0d98140c, 838 0xa5f001ac,
907 0x00e7f015, 839 0x00b7f006,
908 0x015c21f5, 840 0x98000c98,
909 0xf508a7f0, 841 0xe7f0010d,
910 0xf5010321, 842 0x6621f500,
911 0xf4020721, 843 0x08a7f001,
912 0xa7f02201, 844 0x010921f5,
913 0xc921f40c, 845 0x021521f5,
914 0x0a1017f1, 846 0xf02201f4,
915 0xf00614b6, 847 0x21f40ca7,
916 0x12d00527, 848 0x1017f1c9,
917/* 0x08f5: ctx_xfer_post_save_wait */ 849 0x0614b60a,
918 0x0012cf00, 850 0xd00527f0,
919 0xf40522fd, 851/* 0x08fa: ctx_xfer_post_save_wait */
920 0x02f4fa1b, 852 0x12cf0012,
921/* 0x0901: ctx_xfer_post */ 853 0x0522fd00,
922 0x02f7f032, 854 0xf4fa1bf4,
923 0x065821f5, 855/* 0x0906: ctx_xfer_post */
924 0x21f5f4bd, 856 0xf7f03202,
925 0x21f50699, 857 0x5121f502,
926 0x21f50226, 858 0xf5f4bd06,
927 0xf4bd0667, 859 0xf5069221,
928 0x065821f5, 860 0xf5023421,
929 0x981011f4, 861 0xbd066021,
930 0x11fd4001, 862 0x5121f5f4,
931 0x070bf405, 863 0x1011f406,
932 0x07e021f5, 864 0xfd400198,
933/* 0x092c: ctx_xfer_no_post_mmio */ 865 0x0bf40511,
934 0x064a21f5, 866 0xe521f507,
935/* 0x0930: ctx_xfer_done */ 867/* 0x0931: ctx_xfer_no_post_mmio */
936 0x000000f8, 868 0x4321f507,
937 0x00000000, 869/* 0x0935: ctx_xfer_done */
870 0x0000f806,
938 0x00000000, 871 0x00000000,
939 0x00000000, 872 0x00000000,
940 0x00000000, 873 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
new file mode 100644
index 000000000000..afbe03ac9077
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#define CHIPSET GF117
26#include "macros.fuc"
27
28.section #nvd7_grhub_data
29#define INCLUDE_DATA
30#include "com.fuc"
31#include "hub.fuc"
32#undef INCLUDE_DATA
33
34.section #nvd7_grhub_code
35#define INCLUDE_CODE
36bra #init
37#include "com.fuc"
38#include "hub.fuc"
39.align 256
40#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
new file mode 100644
index 000000000000..a1b9f763996a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
@@ -0,0 +1,921 @@
1uint32_t nvd7_grhub_data[] = {
2/* 0x0000: hub_mmio_list_head */
3 0x00000300,
4/* 0x0004: hub_mmio_list_tail */
5 0x00000304,
6/* 0x0008: gpc_count */
7 0x00000000,
8/* 0x000c: rop_count */
9 0x00000000,
10/* 0x0010: cmd_queue */
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29/* 0x0058: ctx_current */
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x00000000,
71 0x00000000,
72/* 0x0100: chan_data */
73/* 0x0100: chan_mmio_count */
74 0x00000000,
75/* 0x0104: chan_mmio_address */
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x00000000,
93 0x00000000,
94 0x00000000,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139/* 0x0200: xfer_data */
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204/* 0x0300: hub_mmio_list_base */
205 0x0417e91c,
206};
207
208uint32_t nvd7_grhub_code[] = {
209 0x031b0ef5,
210/* 0x0004: queue_put */
211 0x9800d898,
212 0x86f001d9,
213 0x0489b808,
214 0xf00c1bf4,
215 0x21f502f7,
216 0x00f802fe,
217/* 0x001c: queue_put_next */
218 0xb60798c4,
219 0x8dbb0384,
220 0x0880b600,
221 0x80008e80,
222 0x90b6018f,
223 0x0f94f001,
224 0xf801d980,
225/* 0x0039: queue_get */
226 0x0131f400,
227 0x9800d898,
228 0x89b801d9,
229 0x210bf404,
230 0xb60789c4,
231 0x9dbb0394,
232 0x0890b600,
233 0x98009e98,
234 0x80b6019f,
235 0x0f84f001,
236 0xf400d880,
237/* 0x0066: queue_get_done */
238 0x00f80132,
239/* 0x0068: nv_rd32 */
240 0x0728b7f1,
241 0xb906b4b6,
242 0xc9f002ec,
243 0x00bcd01f,
244/* 0x0078: nv_rd32_wait */
245 0xc800bccf,
246 0x1bf41fcc,
247 0x06a7f0fa,
248 0x010921f5,
249 0xf840bfcf,
250/* 0x008d: nv_wr32 */
251 0x28b7f100,
252 0x06b4b607,
253 0xb980bfd0,
254 0xc9f002ec,
255 0x1ec9f01f,
256/* 0x00a3: nv_wr32_wait */
257 0xcf00bcd0,
258 0xccc800bc,
259 0xfa1bf41f,
260/* 0x00ae: watchdog_reset */
261 0x87f100f8,
262 0x84b60430,
263 0x1ff9f006,
264 0xf8008fd0,
265/* 0x00bd: watchdog_clear */
266 0x3087f100,
267 0x0684b604,
268 0xf80080d0,
269/* 0x00c9: wait_donez */
270 0xf094bd00,
271 0x07f10099,
272 0x03f00f00,
273 0x0009d002,
274 0x07f104bd,
275 0x03f00600,
276 0x000ad002,
277/* 0x00e6: wait_donez_ne */
278 0x87f104bd,
279 0x83f00000,
280 0x0088cf01,
281 0xf4888aff,
282 0x94bdf31b,
283 0xf10099f0,
284 0xf0170007,
285 0x09d00203,
286 0xf804bd00,
287/* 0x0109: wait_doneo */
288 0xf094bd00,
289 0x07f10099,
290 0x03f00f00,
291 0x0009d002,
292 0x87f104bd,
293 0x84b60818,
294 0x008ad006,
295/* 0x0124: wait_doneo_e */
296 0x040087f1,
297 0xcf0684b6,
298 0x8aff0088,
299 0xf30bf488,
300 0x99f094bd,
301 0x0007f100,
302 0x0203f017,
303 0xbd0009d0,
304/* 0x0147: mmctx_size */
305 0xbd00f804,
306/* 0x0149: nv_mmctx_size_loop */
307 0x00e89894,
308 0xb61a85b6,
309 0x84b60180,
310 0x0098bb02,
311 0xb804e0b6,
312 0x1bf404ef,
313 0x029fb9eb,
314/* 0x0166: mmctx_xfer */
315 0x94bd00f8,
316 0xf10199f0,
317 0xf00f0007,
318 0x09d00203,
319 0xf104bd00,
320 0xb6071087,
321 0x94bd0684,
322 0xf405bbfd,
323 0x8bd0090b,
324 0x0099f000,
325/* 0x018c: mmctx_base_disabled */
326 0xf405eefd,
327 0x8ed00c0b,
328 0xc08fd080,
329/* 0x019b: mmctx_multi_disabled */
330 0xb70199f0,
331 0xc8010080,
332 0xb4b600ab,
333 0x0cb9f010,
334 0xb601aec8,
335 0xbefd11e4,
336 0x008bd005,
337/* 0x01b4: mmctx_exec_loop */
338/* 0x01b4: mmctx_wait_free */
339 0xf0008ecf,
340 0x0bf41fe4,
341 0x00ce98fa,
342 0xd005e9fd,
343 0xc0b6c08e,
344 0x04cdb804,
345 0xc8e81bf4,
346 0x1bf402ab,
347/* 0x01d5: mmctx_fini_wait */
348 0x008bcf18,
349 0xb01fb4f0,
350 0x1bf410b4,
351 0x02a7f0f7,
352 0xf4c921f4,
353/* 0x01ea: mmctx_stop */
354 0xabc81b0e,
355 0x10b4b600,
356 0xf00cb9f0,
357 0x8bd012b9,
358/* 0x01f9: mmctx_stop_wait */
359 0x008bcf00,
360 0xf412bbc8,
361/* 0x0202: mmctx_done */
362 0x94bdfa1b,
363 0xf10199f0,
364 0xf0170007,
365 0x09d00203,
366 0xf804bd00,
367/* 0x0215: strand_wait */
368 0xf0a0f900,
369 0x21f402a7,
370 0xf8a0fcc9,
371/* 0x0221: strand_pre */
372 0xfc87f100,
373 0x0283f04a,
374 0xd00c97f0,
375 0x21f50089,
376 0x00f80215,
377/* 0x0234: strand_post */
378 0x4afc87f1,
379 0xf00283f0,
380 0x89d00d97,
381 0x1521f500,
382/* 0x0247: strand_set */
383 0xf100f802,
384 0xf04ffca7,
385 0xaba202a3,
386 0xc7f00500,
387 0x00acd00f,
388 0xd00bc7f0,
389 0x21f500bc,
390 0xaed00215,
391 0x0ac7f000,
392 0xf500bcd0,
393 0xf8021521,
394/* 0x0271: strand_ctx_init */
395 0xf094bd00,
396 0x07f10399,
397 0x03f00f00,
398 0x0009d002,
399 0x21f504bd,
400 0xe7f00221,
401 0x4721f503,
402 0xfca7f102,
403 0x02a3f046,
404 0x0400aba0,
405 0xf040a0d0,
406 0xbcd001c7,
407 0x1521f500,
408 0x010c9202,
409 0xf000acd0,
410 0xbcd002c7,
411 0x1521f500,
412 0x3421f502,
413 0x8087f102,
414 0x0684b608,
415 0xb70089cf,
416 0x95220080,
417/* 0x02ca: ctx_init_strand_loop */
418 0x8ed008fe,
419 0x408ed000,
420 0xb6808acf,
421 0xa0b606a5,
422 0x00eabb01,
423 0xb60480b6,
424 0x1bf40192,
425 0x08e4b6e8,
426 0xbdf2efbc,
427 0x0399f094,
428 0x170007f1,
429 0xd00203f0,
430 0x04bd0009,
431/* 0x02fe: error */
432 0x07f100f8,
433 0x03f00500,
434 0x000fd002,
435 0xf7f004bd,
436 0x0007f101,
437 0x0303f007,
438 0xbd000fd0,
439/* 0x031b: init */
440 0xbd00f804,
441 0x0004fe04,
442 0xf10007fe,
443 0xf0120017,
444 0x12d00227,
445 0xb117f100,
446 0x0010fe05,
447 0x040017f1,
448 0xf1c010d0,
449 0xb6040437,
450 0x27f10634,
451 0x32d02003,
452 0x0427f100,
453 0x0132d020,
454 0x200b27f1,
455 0xf10232d0,
456 0xd0200c27,
457 0x27f10732,
458 0x24b60c24,
459 0x0003b906,
460 0xf10023d0,
461 0xf0870427,
462 0x12d00023,
463 0x0012b700,
464 0x0427f001,
465 0xf40012d0,
466 0xe7f11031,
467 0xe3f09604,
468 0x6821f440,
469 0x8090f1c7,
470 0xf4f00301,
471 0x020f801f,
472 0xbb0117f0,
473 0x12b6041f,
474 0x0c27f101,
475 0x0624b604,
476 0xd00021d0,
477 0x17f14021,
478 0x0e980100,
479 0x010f9800,
480 0x014721f5,
481 0x070037f1,
482 0x950634b6,
483 0x34d00814,
484 0x4034d000,
485 0x130030b7,
486 0xb6001fbb,
487 0x3fd002f5,
488 0x0815b600,
489 0xb60110b6,
490 0x1fb90814,
491 0x7121f502,
492 0x001fbb02,
493 0xf1020398,
494 0xf0200047,
495/* 0x03f6: init_gpc */
496 0x4ea05043,
497 0x1fb90804,
498 0x8d21f402,
499 0x010c4ea0,
500 0x21f4f4bd,
501 0x044ea08d,
502 0x8d21f401,
503 0x01004ea0,
504 0xf402f7f0,
505 0x4ea08d21,
506/* 0x041e: init_gpc_wait */
507 0x21f40800,
508 0x1fffc868,
509 0xa0fa0bf4,
510 0xf408044e,
511 0x1fbb6821,
512 0x0040b700,
513 0x0132b680,
514 0xf1be1bf4,
515 0xf0010007,
516 0x01d00203,
517 0xbd04bd00,
518 0x1f19f014,
519 0x080007f1,
520 0xd00203f0,
521 0x04bd0001,
522/* 0x0458: main */
523 0xf40031f4,
524 0xd7f00028,
525 0x3921f410,
526 0xb1f401f4,
527 0xf54001e4,
528 0xbd00de1b,
529 0x0499f094,
530 0x0f0007f1,
531 0xd00203f0,
532 0x04bd0009,
533 0x0b0017f1,
534 0xcf0614b6,
535 0x11cf4012,
536 0x1f13c800,
537 0x00870bf5,
538 0xf41f23c8,
539 0x20f9620b,
540 0xbd0212b9,
541 0x0799f094,
542 0x0f0007f1,
543 0xd00203f0,
544 0x04bd0009,
545 0xf40132f4,
546 0x21f50231,
547 0x94bd082f,
548 0xf10799f0,
549 0xf0170007,
550 0x09d00203,
551 0xfc04bd00,
552 0xf094bd20,
553 0x07f10699,
554 0x03f00f00,
555 0x0009d002,
556 0x31f404bd,
557 0x2f21f501,
558 0xf094bd08,
559 0x07f10699,
560 0x03f01700,
561 0x0009d002,
562 0x0ef404bd,
563/* 0x04f9: chsw_prev_no_next */
564 0xb920f931,
565 0x32f40212,
566 0x0232f401,
567 0x082f21f5,
568 0x17f120fc,
569 0x14b60b00,
570 0x0012d006,
571/* 0x0517: chsw_no_prev */
572 0xc8130ef4,
573 0x0bf41f23,
574 0x0131f40d,
575 0xf50232f4,
576/* 0x0527: chsw_done */
577 0xf1082f21,
578 0xb60b0c17,
579 0x27f00614,
580 0x0012d001,
581 0x99f094bd,
582 0x0007f104,
583 0x0203f017,
584 0xbd0009d0,
585 0x130ef504,
586/* 0x0549: main_not_ctx_switch */
587 0x01e4b0ff,
588 0xb90d1bf4,
589 0x21f502f2,
590 0x0ef407bb,
591/* 0x0559: main_not_ctx_chan */
592 0x02e4b046,
593 0xbd321bf4,
594 0x0799f094,
595 0x0f0007f1,
596 0xd00203f0,
597 0x04bd0009,
598 0xf40132f4,
599 0x21f50232,
600 0x94bd082f,
601 0xf10799f0,
602 0xf0170007,
603 0x09d00203,
604 0xf404bd00,
605/* 0x058e: main_not_ctx_save */
606 0xef94110e,
607 0x01f5f010,
608 0x02fe21f5,
609 0xfec00ef5,
610/* 0x059c: main_done */
611 0x29f024bd,
612 0x0007f11f,
613 0x0203f008,
614 0xbd0002d0,
615 0xab0ef504,
616/* 0x05b1: ih */
617 0xfe80f9fe,
618 0x80f90188,
619 0xa0f990f9,
620 0xd0f9b0f9,
621 0xf0f9e0f9,
622 0x0acf04bd,
623 0x04abc480,
624 0xf11d0bf4,
625 0xf01900b7,
626 0xbecf10d7,
627 0x00bfcf40,
628 0xb70421f4,
629 0xf00400b0,
630 0xbed001e7,
631/* 0x05e9: ih_no_fifo */
632 0x00abe400,
633 0x0d0bf401,
634 0xf110d7f0,
635 0xf44001e7,
636/* 0x05fa: ih_no_ctxsw */
637 0xb7f10421,
638 0xb0bd0104,
639 0xf4b4abff,
640 0xa7f10d0b,
641 0xa4b60c1c,
642 0x00abd006,
643/* 0x0610: ih_no_other */
644 0xfc400ad0,
645 0xfce0fcf0,
646 0xfcb0fcd0,
647 0xfc90fca0,
648 0x0088fe80,
649 0x32f480fc,
650/* 0x062b: ctx_4160s */
651 0xf101f800,
652 0xf04160e7,
653 0xf7f040e3,
654 0x8d21f401,
655/* 0x0638: ctx_4160s_wait */
656 0xc86821f4,
657 0x0bf404ff,
658/* 0x0643: ctx_4160c */
659 0xf100f8fa,
660 0xf04160e7,
661 0xf4bd40e3,
662 0xf88d21f4,
663/* 0x0651: ctx_4170s */
664 0x70e7f100,
665 0x40e3f041,
666 0xf410f5f0,
667 0x00f88d21,
668/* 0x0660: ctx_4170w */
669 0x4170e7f1,
670 0xf440e3f0,
671 0xf4f06821,
672 0xf31bf410,
673/* 0x0672: ctx_redswitch */
674 0xe7f100f8,
675 0xe4b60614,
676 0x70f7f106,
677 0x00efd002,
678/* 0x0683: ctx_redswitch_delay */
679 0xb608f7f0,
680 0x1bf401f2,
681 0x70f7f1fd,
682 0x00efd007,
683/* 0x0692: ctx_86c */
684 0xe7f100f8,
685 0xe4b6086c,
686 0x00efd006,
687 0x8a14e7f1,
688 0xf440e3f0,
689 0xe7f18d21,
690 0xe3f0a86c,
691 0x8d21f441,
692/* 0x06b2: ctx_load */
693 0x94bd00f8,
694 0xf10599f0,
695 0xf00f0007,
696 0x09d00203,
697 0xf004bd00,
698 0x21f40ca7,
699 0x2417f1c9,
700 0x0614b60a,
701 0xf10010d0,
702 0xb60b0037,
703 0x32d00634,
704 0x0c17f140,
705 0x0614b60a,
706 0xd00747f0,
707 0x14d00012,
708/* 0x06ed: ctx_chan_wait_0 */
709 0x4014cf40,
710 0xf41f44f0,
711 0x32d0fa1b,
712 0x000bfe00,
713 0xb61f2af0,
714 0x20b60424,
715 0xf094bd02,
716 0x07f10899,
717 0x03f00f00,
718 0x0009d002,
719 0x17f104bd,
720 0x14b60a04,
721 0x0012d006,
722 0x0a2017f1,
723 0xf00614b6,
724 0x23f10227,
725 0x12d08000,
726 0x1017f000,
727 0x020027f1,
728 0xfa0223f0,
729 0x03f80512,
730 0x99f094bd,
731 0x0007f108,
732 0x0203f017,
733 0xbd0009d0,
734 0x81019804,
735 0x981814b6,
736 0x25b68002,
737 0x0512fd08,
738 0xbd160180,
739 0x0999f094,
740 0x0f0007f1,
741 0xd00203f0,
742 0x04bd0009,
743 0x0a0427f1,
744 0xd00624b6,
745 0x27f00021,
746 0x2017f101,
747 0x0614b60a,
748 0xf10012d0,
749 0xf0010017,
750 0x01fa0613,
751 0xbd03f805,
752 0x0999f094,
753 0x170007f1,
754 0xd00203f0,
755 0x04bd0009,
756 0x99f094bd,
757 0x0007f105,
758 0x0203f017,
759 0xbd0009d0,
760/* 0x07bb: ctx_chan */
761 0xf500f804,
762 0xf5062b21,
763 0xf006b221,
764 0x21f40ca7,
765 0x1017f1c9,
766 0x0614b60a,
767 0xd00527f0,
768/* 0x07d6: ctx_chan_wait */
769 0x12cf0012,
770 0x0522fd00,
771 0xf5fa1bf4,
772 0xf8064321,
773/* 0x07e5: ctx_mmio_exec */
774 0x41039800,
775 0x0a0427f1,
776 0xd00624b6,
777 0x34bd0023,
778/* 0x07f4: ctx_mmio_loop */
779 0xf4ff34c4,
780 0x57f10f1b,
781 0x53f00200,
782 0x0535fa06,
783/* 0x0806: ctx_mmio_pull */
784 0x4e9803f8,
785 0x814f9880,
786 0xb68d21f4,
787 0x12b60830,
788 0xdf1bf401,
789/* 0x0818: ctx_mmio_done */
790 0xd0160398,
791 0x00800023,
792 0x0017f140,
793 0x0613f001,
794 0xf80601fa,
795/* 0x082f: ctx_xfer */
796 0xf100f803,
797 0xb60c00f7,
798 0xe7f006f4,
799 0x80fed004,
800/* 0x083c: ctx_xfer_idle */
801 0xf100fecf,
802 0xf42000e4,
803 0x11f4f91b,
804 0x1102f406,
805/* 0x084c: ctx_xfer_pre */
806 0xf510f7f0,
807 0xf5069221,
808 0xf4062b21,
809/* 0x085a: ctx_xfer_pre_load */
810 0xf7f01c11,
811 0x5121f502,
812 0x6021f506,
813 0x7221f506,
814 0xf5f4bd06,
815 0xf5065121,
816/* 0x0873: ctx_xfer_exec */
817 0x9806b221,
818 0x27f11601,
819 0x24b60414,
820 0x0020d006,
821 0xa500e7f1,
822 0xb941e3f0,
823 0x21f4021f,
824 0x04e0b68d,
825 0xf001fcf0,
826 0x24b6022c,
827 0x05f2fd01,
828 0xf18d21f4,
829 0xf04afc17,
830 0x27f00213,
831 0x0012d00c,
832 0x021521f5,
833 0x47fc27f1,
834 0xd00223f0,
835 0x2cf00020,
836 0x0320b601,
837 0xf00012d0,
838 0xa5f001ac,
839 0x00b7f006,
840 0x98000c98,
841 0xe7f0010d,
842 0x6621f500,
843 0x08a7f001,
844 0x010921f5,
845 0x021521f5,
846 0xf02201f4,
847 0x21f40ca7,
848 0x1017f1c9,
849 0x0614b60a,
850 0xd00527f0,
851/* 0x08fa: ctx_xfer_post_save_wait */
852 0x12cf0012,
853 0x0522fd00,
854 0xf4fa1bf4,
855/* 0x0906: ctx_xfer_post */
856 0xf7f03202,
857 0x5121f502,
858 0xf5f4bd06,
859 0xf5069221,
860 0xf5023421,
861 0xbd066021,
862 0x5121f5f4,
863 0x1011f406,
864 0xfd400198,
865 0x0bf40511,
866 0xe521f507,
867/* 0x0931: ctx_xfer_no_post_mmio */
868 0x4321f507,
869/* 0x0935: ctx_xfer_done */
870 0x0000f806,
871 0x00000000,
872 0x00000000,
873 0x00000000,
874 0x00000000,
875 0x00000000,
876 0x00000000,
877 0x00000000,
878 0x00000000,
879 0x00000000,
880 0x00000000,
881 0x00000000,
882 0x00000000,
883 0x00000000,
884 0x00000000,
885 0x00000000,
886 0x00000000,
887 0x00000000,
888 0x00000000,
889 0x00000000,
890 0x00000000,
891 0x00000000,
892 0x00000000,
893 0x00000000,
894 0x00000000,
895 0x00000000,
896 0x00000000,
897 0x00000000,
898 0x00000000,
899 0x00000000,
900 0x00000000,
901 0x00000000,
902 0x00000000,
903 0x00000000,
904 0x00000000,
905 0x00000000,
906 0x00000000,
907 0x00000000,
908 0x00000000,
909 0x00000000,
910 0x00000000,
911 0x00000000,
912 0x00000000,
913 0x00000000,
914 0x00000000,
915 0x00000000,
916 0x00000000,
917 0x00000000,
918 0x00000000,
919 0x00000000,
920 0x00000000,
921};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
index c7225db6486c..d4840f1879fd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
@@ -22,138 +22,13 @@
22 * Authors: Ben Skeggs <bskeggs@redhat.com> 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */ 23 */
24 24
25#define NVGK 25#define CHIPSET GK100
26#include "macros.fuc" 26#include "macros.fuc"
27 27
28.section #nve0_grhub_data 28.section #nve0_grhub_data
29#define INCLUDE_DATA 29#define INCLUDE_DATA
30#include "com.fuc" 30#include "com.fuc"
31#include "hub.fuc" 31#include "hub.fuc"
32
33chipsets:
34.b8 0xe4 0 0 0
35.b16 #nve4_hub_mmio_head
36.b16 #nve4_hub_mmio_tail
37.b8 0xe7 0 0 0
38.b16 #nve4_hub_mmio_head
39.b16 #nve4_hub_mmio_tail
40.b8 0xe6 0 0 0
41.b16 #nve4_hub_mmio_head
42.b16 #nve4_hub_mmio_tail
43.b8 0xf0 0 0 0
44.b16 #nvf0_hub_mmio_head
45.b16 #nvf0_hub_mmio_tail
46.b8 0 0 0 0
47
48nve4_hub_mmio_head:
49mmctx_data(0x17e91c, 2)
50mmctx_data(0x400204, 2)
51mmctx_data(0x404010, 7)
52mmctx_data(0x4040a8, 9)
53mmctx_data(0x4040d0, 7)
54mmctx_data(0x4040f8, 1)
55mmctx_data(0x404130, 3)
56mmctx_data(0x404150, 3)
57mmctx_data(0x404164, 1)
58mmctx_data(0x4041a0, 4)
59mmctx_data(0x404200, 4)
60mmctx_data(0x404404, 14)
61mmctx_data(0x404460, 4)
62mmctx_data(0x404480, 1)
63mmctx_data(0x404498, 1)
64mmctx_data(0x404604, 4)
65mmctx_data(0x404618, 4)
66mmctx_data(0x40462c, 2)
67mmctx_data(0x404640, 1)
68mmctx_data(0x404654, 1)
69mmctx_data(0x404660, 1)
70mmctx_data(0x404678, 19)
71mmctx_data(0x4046c8, 3)
72mmctx_data(0x404700, 3)
73mmctx_data(0x404718, 10)
74mmctx_data(0x404744, 2)
75mmctx_data(0x404754, 1)
76mmctx_data(0x405800, 1)
77mmctx_data(0x405830, 3)
78mmctx_data(0x405854, 1)
79mmctx_data(0x405870, 4)
80mmctx_data(0x405a00, 2)
81mmctx_data(0x405a18, 1)
82mmctx_data(0x405b00, 1)
83mmctx_data(0x405b10, 1)
84mmctx_data(0x406020, 1)
85mmctx_data(0x406028, 4)
86mmctx_data(0x4064a8, 2)
87mmctx_data(0x4064b4, 2)
88mmctx_data(0x4064c0, 12)
89mmctx_data(0x4064fc, 1)
90mmctx_data(0x407040, 1)
91mmctx_data(0x407804, 1)
92mmctx_data(0x40780c, 6)
93mmctx_data(0x4078bc, 1)
94mmctx_data(0x408000, 7)
95mmctx_data(0x408064, 1)
96mmctx_data(0x408800, 3)
97mmctx_data(0x408840, 1)
98mmctx_data(0x408900, 3)
99mmctx_data(0x408980, 1)
100nve4_hub_mmio_tail:
101
102nvf0_hub_mmio_head:
103mmctx_data(0x17e91c, 2)
104mmctx_data(0x400204, 2)
105mmctx_data(0x404004, 17)
106mmctx_data(0x4040a8, 9)
107mmctx_data(0x4040d0, 7)
108mmctx_data(0x4040f8, 1)
109mmctx_data(0x404100, 10)
110mmctx_data(0x404130, 3)
111mmctx_data(0x404150, 3)
112mmctx_data(0x404164, 1)
113mmctx_data(0x40417c, 2)
114mmctx_data(0x4041a0, 4)
115mmctx_data(0x404200, 4)
116mmctx_data(0x404404, 12)
117mmctx_data(0x404438, 1)
118mmctx_data(0x404460, 4)
119mmctx_data(0x404480, 1)
120mmctx_data(0x404498, 1)
121mmctx_data(0x404604, 4)
122mmctx_data(0x404618, 4)
123mmctx_data(0x40462c, 2)
124mmctx_data(0x404640, 1)
125mmctx_data(0x404654, 1)
126mmctx_data(0x404660, 1)
127mmctx_data(0x404678, 19)
128mmctx_data(0x4046c8, 3)
129mmctx_data(0x404700, 3)
130mmctx_data(0x404718, 10)
131mmctx_data(0x404744, 2)
132mmctx_data(0x404754, 1)
133mmctx_data(0x405800, 1)
134mmctx_data(0x405830, 3)
135mmctx_data(0x405854, 1)
136mmctx_data(0x405870, 4)
137mmctx_data(0x405a00, 2)
138mmctx_data(0x405a18, 1)
139mmctx_data(0x405b00, 1)
140mmctx_data(0x405b10, 1)
141mmctx_data(0x405b20, 1)
142mmctx_data(0x406020, 1)
143mmctx_data(0x406028, 4)
144mmctx_data(0x4064a8, 5)
145mmctx_data(0x4064c0, 12)
146mmctx_data(0x4064fc, 1)
147mmctx_data(0x407804, 1)
148mmctx_data(0x40780c, 6)
149mmctx_data(0x4078bc, 1)
150mmctx_data(0x408000, 7)
151mmctx_data(0x408064, 1)
152mmctx_data(0x408800, 3)
153mmctx_data(0x408840, 1)
154mmctx_data(0x408900, 3)
155mmctx_data(0x408980, 1)
156nvf0_hub_mmio_tail:
157#undef INCLUDE_DATA 32#undef INCLUDE_DATA
158 33
159.section #nve0_grhub_code 34.section #nve0_grhub_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index 623e8698ace1..eb7bc0e9576e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -1,9 +1,13 @@
1uint32_t nve0_grhub_data[] = { 1uint32_t nve0_grhub_data[] = {
2/* 0x0000: gpc_count */ 2/* 0x0000: hub_mmio_list_head */
3 0x00000300,
4/* 0x0004: hub_mmio_list_tail */
5 0x00000304,
6/* 0x0008: gpc_count */
3 0x00000000, 7 0x00000000,
4/* 0x0004: rop_count */ 8/* 0x000c: rop_count */
5 0x00000000, 9 0x00000000,
6/* 0x0008: cmd_queue */ 10/* 0x0010: cmd_queue */
7 0x00000000, 11 0x00000000,
8 0x00000000, 12 0x00000000,
9 0x00000000, 13 0x00000000,
@@ -22,10 +26,6 @@ uint32_t nve0_grhub_data[] = {
22 0x00000000, 26 0x00000000,
23 0x00000000, 27 0x00000000,
24 0x00000000, 28 0x00000000,
25/* 0x0050: hub_mmio_list_head */
26 0x00000000,
27/* 0x0054: hub_mmio_list_tail */
28 0x00000000,
29/* 0x0058: ctx_current */ 29/* 0x0058: ctx_current */
30 0x00000000, 30 0x00000000,
31 0x00000000, 31 0x00000000,
@@ -201,134 +201,19 @@ uint32_t nve0_grhub_data[] = {
201 0x00000000, 201 0x00000000,
202 0x00000000, 202 0x00000000,
203 0x00000000, 203 0x00000000,
204/* 0x0300: chipsets */ 204/* 0x0300: hub_mmio_list_base */
205 0x000000e4,
206 0x03f00324,
207 0x000000e7,
208 0x03f00324,
209 0x000000e6,
210 0x03f00324,
211 0x000000f0,
212 0x04c403f0,
213 0x00000000,
214/* 0x0324: nve4_hub_mmio_head */
215 0x0417e91c,
216 0x04400204,
217 0x18404010,
218 0x204040a8,
219 0x184040d0,
220 0x004040f8,
221 0x08404130,
222 0x08404150,
223 0x00404164,
224 0x0c4041a0,
225 0x0c404200,
226 0x34404404,
227 0x0c404460,
228 0x00404480,
229 0x00404498,
230 0x0c404604,
231 0x0c404618,
232 0x0440462c,
233 0x00404640,
234 0x00404654,
235 0x00404660,
236 0x48404678,
237 0x084046c8,
238 0x08404700,
239 0x24404718,
240 0x04404744,
241 0x00404754,
242 0x00405800,
243 0x08405830,
244 0x00405854,
245 0x0c405870,
246 0x04405a00,
247 0x00405a18,
248 0x00405b00,
249 0x00405b10,
250 0x00406020,
251 0x0c406028,
252 0x044064a8,
253 0x044064b4,
254 0x2c4064c0,
255 0x004064fc,
256 0x00407040,
257 0x00407804,
258 0x1440780c,
259 0x004078bc,
260 0x18408000,
261 0x00408064,
262 0x08408800,
263 0x00408840,
264 0x08408900,
265 0x00408980,
266/* 0x03f0: nve4_hub_mmio_tail */
267/* 0x03f0: nvf0_hub_mmio_head */
268 0x0417e91c, 205 0x0417e91c,
269 0x04400204,
270 0x40404004,
271 0x204040a8,
272 0x184040d0,
273 0x004040f8,
274 0x24404100,
275 0x08404130,
276 0x08404150,
277 0x00404164,
278 0x0440417c,
279 0x0c4041a0,
280 0x0c404200,
281 0x2c404404,
282 0x00404438,
283 0x0c404460,
284 0x00404480,
285 0x00404498,
286 0x0c404604,
287 0x0c404618,
288 0x0440462c,
289 0x00404640,
290 0x00404654,
291 0x00404660,
292 0x48404678,
293 0x084046c8,
294 0x08404700,
295 0x24404718,
296 0x04404744,
297 0x00404754,
298 0x00405800,
299 0x08405830,
300 0x00405854,
301 0x0c405870,
302 0x04405a00,
303 0x00405a18,
304 0x00405b00,
305 0x00405b10,
306 0x00405b20,
307 0x00406020,
308 0x0c406028,
309 0x104064a8,
310 0x2c4064c0,
311 0x004064fc,
312 0x00407804,
313 0x1440780c,
314 0x004078bc,
315 0x18408000,
316 0x00408064,
317 0x08408800,
318 0x00408840,
319 0x08408900,
320 0x00408980,
321}; 206};
322 207
323uint32_t nve0_grhub_code[] = { 208uint32_t nve0_grhub_code[] = {
324 0x03090ef5, 209 0x031b0ef5,
325/* 0x0004: queue_put */ 210/* 0x0004: queue_put */
326 0x9800d898, 211 0x9800d898,
327 0x86f001d9, 212 0x86f001d9,
328 0x0489b808, 213 0x0489b808,
329 0xf00c1bf4, 214 0xf00c1bf4,
330 0x21f502f7, 215 0x21f502f7,
331 0x00f802ec, 216 0x00f802fe,
332/* 0x001c: queue_put_next */ 217/* 0x001c: queue_put_next */
333 0xb60798c4, 218 0xb60798c4,
334 0x8dbb0384, 219 0x8dbb0384,
@@ -360,7 +245,7 @@ uint32_t nve0_grhub_code[] = {
360 0xc800bccf, 245 0xc800bccf,
361 0x1bf41fcc, 246 0x1bf41fcc,
362 0x06a7f0fa, 247 0x06a7f0fa,
363 0x010321f5, 248 0x010921f5,
364 0xf840bfcf, 249 0xf840bfcf,
365/* 0x008d: nv_wr32 */ 250/* 0x008d: nv_wr32 */
366 0x28b7f100, 251 0x28b7f100,
@@ -382,63 +267,66 @@ uint32_t nve0_grhub_code[] = {
382 0x0684b604, 267 0x0684b604,
383 0xf80080d0, 268 0xf80080d0,
384/* 0x00c9: wait_donez */ 269/* 0x00c9: wait_donez */
385 0x3c87f100, 270 0xf094bd00,
386 0x0684b608, 271 0x07f10099,
387 0x99f094bd, 272 0x03f00f00,
388 0x0089d000, 273 0x0009d002,
389 0x081887f1, 274 0x07f104bd,
390 0xd00684b6, 275 0x03f00600,
391/* 0x00e2: wait_donez_ne */ 276 0x000ad002,
392 0x87f1008a, 277/* 0x00e6: wait_donez_ne */
393 0x84b60400, 278 0x87f104bd,
394 0x0088cf06, 279 0x83f00000,
280 0x0088cf01,
395 0xf4888aff, 281 0xf4888aff,
396 0x87f1f31b, 282 0x94bdf31b,
397 0x84b6085c, 283 0xf10099f0,
398 0xf094bd06, 284 0xf0170007,
399 0x89d00099, 285 0x09d00203,
400/* 0x0103: wait_doneo */ 286 0xf804bd00,
401 0xf100f800, 287/* 0x0109: wait_doneo */
402 0xb6083c87, 288 0xf094bd00,
403 0x94bd0684, 289 0x07f10099,
404 0xd00099f0, 290 0x03f00f00,
405 0x87f10089, 291 0x0009d002,
292 0x87f104bd,
406 0x84b60818, 293 0x84b60818,
407 0x008ad006, 294 0x008ad006,
408/* 0x011c: wait_doneo_e */ 295/* 0x0124: wait_doneo_e */
409 0x040087f1, 296 0x040087f1,
410 0xcf0684b6, 297 0xcf0684b6,
411 0x8aff0088, 298 0x8aff0088,
412 0xf30bf488, 299 0xf30bf488,
413 0x085c87f1, 300 0x99f094bd,
414 0xbd0684b6, 301 0x0007f100,
415 0x0099f094, 302 0x0203f017,
416 0xf80089d0, 303 0xbd0009d0,
417/* 0x013d: mmctx_size */ 304/* 0x0147: mmctx_size */
418/* 0x013f: nv_mmctx_size_loop */ 305 0xbd00f804,
419 0x9894bd00, 306/* 0x0149: nv_mmctx_size_loop */
420 0x85b600e8, 307 0x00e89894,
421 0x0180b61a, 308 0xb61a85b6,
422 0xbb0284b6, 309 0x84b60180,
423 0xe0b60098, 310 0x0098bb02,
424 0x04efb804, 311 0xb804e0b6,
425 0xb9eb1bf4, 312 0x1bf404ef,
426 0x00f8029f, 313 0x029fb9eb,
427/* 0x015c: mmctx_xfer */ 314/* 0x0166: mmctx_xfer */
428 0x083c87f1, 315 0x94bd00f8,
429 0xbd0684b6, 316 0xf10199f0,
430 0x0199f094, 317 0xf00f0007,
431 0xf10089d0, 318 0x09d00203,
319 0xf104bd00,
432 0xb6071087, 320 0xb6071087,
433 0x94bd0684, 321 0x94bd0684,
434 0xf405bbfd, 322 0xf405bbfd,
435 0x8bd0090b, 323 0x8bd0090b,
436 0x0099f000, 324 0x0099f000,
437/* 0x0180: mmctx_base_disabled */ 325/* 0x018c: mmctx_base_disabled */
438 0xf405eefd, 326 0xf405eefd,
439 0x8ed00c0b, 327 0x8ed00c0b,
440 0xc08fd080, 328 0xc08fd080,
441/* 0x018f: mmctx_multi_disabled */ 329/* 0x019b: mmctx_multi_disabled */
442 0xb70199f0, 330 0xb70199f0,
443 0xc8010080, 331 0xc8010080,
444 0xb4b600ab, 332 0xb4b600ab,
@@ -446,8 +334,8 @@ uint32_t nve0_grhub_code[] = {
446 0xb601aec8, 334 0xb601aec8,
447 0xbefd11e4, 335 0xbefd11e4,
448 0x008bd005, 336 0x008bd005,
449/* 0x01a8: mmctx_exec_loop */ 337/* 0x01b4: mmctx_exec_loop */
450/* 0x01a8: mmctx_wait_free */ 338/* 0x01b4: mmctx_wait_free */
451 0xf0008ecf, 339 0xf0008ecf,
452 0x0bf41fe4, 340 0x0bf41fe4,
453 0x00ce98fa, 341 0x00ce98fa,
@@ -456,76 +344,77 @@ uint32_t nve0_grhub_code[] = {
456 0x04cdb804, 344 0x04cdb804,
457 0xc8e81bf4, 345 0xc8e81bf4,
458 0x1bf402ab, 346 0x1bf402ab,
459/* 0x01c9: mmctx_fini_wait */ 347/* 0x01d5: mmctx_fini_wait */
460 0x008bcf18, 348 0x008bcf18,
461 0xb01fb4f0, 349 0xb01fb4f0,
462 0x1bf410b4, 350 0x1bf410b4,
463 0x02a7f0f7, 351 0x02a7f0f7,
464 0xf4c921f4, 352 0xf4c921f4,
465/* 0x01de: mmctx_stop */ 353/* 0x01ea: mmctx_stop */
466 0xabc81b0e, 354 0xabc81b0e,
467 0x10b4b600, 355 0x10b4b600,
468 0xf00cb9f0, 356 0xf00cb9f0,
469 0x8bd012b9, 357 0x8bd012b9,
470/* 0x01ed: mmctx_stop_wait */ 358/* 0x01f9: mmctx_stop_wait */
471 0x008bcf00, 359 0x008bcf00,
472 0xf412bbc8, 360 0xf412bbc8,
473/* 0x01f6: mmctx_done */ 361/* 0x0202: mmctx_done */
474 0x87f1fa1b, 362 0x94bdfa1b,
475 0x84b6085c, 363 0xf10199f0,
476 0xf094bd06, 364 0xf0170007,
477 0x89d00199, 365 0x09d00203,
478/* 0x0207: strand_wait */ 366 0xf804bd00,
479 0xf900f800, 367/* 0x0215: strand_wait */
480 0x02a7f0a0, 368 0xf0a0f900,
481 0xfcc921f4, 369 0x21f402a7,
482/* 0x0213: strand_pre */ 370 0xf8a0fcc9,
483 0xf100f8a0, 371/* 0x0221: strand_pre */
484 0xf04afc87, 372 0xfc87f100,
485 0x97f00283, 373 0x0283f04a,
486 0x0089d00c, 374 0xd00c97f0,
487 0x020721f5,
488/* 0x0226: strand_post */
489 0x87f100f8,
490 0x83f04afc,
491 0x0d97f002,
492 0xf50089d0,
493 0xf8020721,
494/* 0x0239: strand_set */
495 0xfca7f100,
496 0x02a3f04f,
497 0x0500aba2,
498 0xd00fc7f0,
499 0xc7f000ac,
500 0x00bcd00b,
501 0x020721f5,
502 0xf000aed0,
503 0xbcd00ac7,
504 0x0721f500,
505/* 0x0263: strand_ctx_init */
506 0xf100f802,
507 0xb6083c87,
508 0x94bd0684,
509 0xd00399f0,
510 0x21f50089, 375 0x21f50089,
511 0xe7f00213, 376 0x00f80215,
512 0x3921f503, 377/* 0x0234: strand_post */
378 0x4afc87f1,
379 0xf00283f0,
380 0x89d00d97,
381 0x1521f500,
382/* 0x0247: strand_set */
383 0xf100f802,
384 0xf04ffca7,
385 0xaba202a3,
386 0xc7f00500,
387 0x00acd00f,
388 0xd00bc7f0,
389 0x21f500bc,
390 0xaed00215,
391 0x0ac7f000,
392 0xf500bcd0,
393 0xf8021521,
394/* 0x0271: strand_ctx_init */
395 0xf094bd00,
396 0x07f10399,
397 0x03f00f00,
398 0x0009d002,
399 0x21f504bd,
400 0xe7f00221,
401 0x4721f503,
513 0xfca7f102, 402 0xfca7f102,
514 0x02a3f046, 403 0x02a3f046,
515 0x0400aba0, 404 0x0400aba0,
516 0xf040a0d0, 405 0xf040a0d0,
517 0xbcd001c7, 406 0xbcd001c7,
518 0x0721f500, 407 0x1521f500,
519 0x010c9202, 408 0x010c9202,
520 0xf000acd0, 409 0xf000acd0,
521 0xbcd002c7, 410 0xbcd002c7,
522 0x0721f500, 411 0x1521f500,
523 0x2621f502, 412 0x3421f502,
524 0x8087f102, 413 0x8087f102,
525 0x0684b608, 414 0x0684b608,
526 0xb70089cf, 415 0xb70089cf,
527 0x95220080, 416 0x95220080,
528/* 0x02ba: ctx_init_strand_loop */ 417/* 0x02ca: ctx_init_strand_loop */
529 0x8ed008fe, 418 0x8ed008fe,
530 0x408ed000, 419 0x408ed000,
531 0xb6808acf, 420 0xb6808acf,
@@ -534,438 +423,496 @@ uint32_t nve0_grhub_code[] = {
534 0xb60480b6, 423 0xb60480b6,
535 0x1bf40192, 424 0x1bf40192,
536 0x08e4b6e8, 425 0x08e4b6e8,
537 0xf1f2efbc, 426 0xbdf2efbc,
538 0xb6085c87, 427 0x0399f094,
539 0x94bd0684, 428 0x170007f1,
540 0xd00399f0, 429 0xd00203f0,
541 0x00f80089, 430 0x04bd0009,
542/* 0x02ec: error */ 431/* 0x02fe: error */
543 0xe7f1e0f9, 432 0x07f100f8,
544 0xe4b60814, 433 0x03f00500,
545 0x00efd006, 434 0x000fd002,
546 0x0c1ce7f1, 435 0xf7f004bd,
547 0xf006e4b6, 436 0x0007f101,
548 0xefd001f7, 437 0x0303f007,
549 0xf8e0fc00, 438 0xbd000fd0,
550/* 0x0309: init */ 439/* 0x031b: init */
551 0xfe04bd00, 440 0xbd00f804,
552 0x07fe0004, 441 0x0004fe04,
553 0x0017f100, 442 0xf10007fe,
554 0x0227f012, 443 0xf0120017,
555 0xf10012d0, 444 0x12d00227,
556 0xfe05ba17, 445 0xb117f100,
557 0x17f10010, 446 0x0010fe05,
558 0x10d00400, 447 0x040017f1,
559 0x0437f1c0, 448 0xf1c010d0,
560 0x0634b604, 449 0xb6040437,
561 0x200327f1, 450 0x27f10634,
562 0xf10032d0, 451 0x32d02003,
563 0xd0200427,
564 0x27f10132,
565 0x32d0200b,
566 0x0c27f102,
567 0x0732d020,
568 0x0c2427f1,
569 0xb90624b6,
570 0x23d00003,
571 0x0427f100, 452 0x0427f100,
572 0x0023f087, 453 0x0132d020,
573 0xb70012d0, 454 0x200b27f1,
574 0xf0010012, 455 0xf10232d0,
575 0x12d00427, 456 0xd0200c27,
576 0x1031f400, 457 0x27f10732,
577 0x9604e7f1, 458 0x24b60c24,
578 0xf440e3f0, 459 0x0003b906,
579 0xf1c76821, 460 0xf10023d0,
580 0x01018090, 461 0xf0870427,
581 0x801ff4f0, 462 0x12d00023,
582 0x17f0000f, 463 0x0012b700,
583 0x041fbb01, 464 0x0427f001,
584 0xf10112b6, 465 0xf40012d0,
585 0xb6040c27, 466 0xe7f11031,
586 0x21d00624, 467 0xe3f09604,
587 0x4021d000, 468 0x6821f440,
588 0x080027f1, 469 0x8090f1c7,
589 0xcf0624b6, 470 0xf4f00301,
590 0xf7f10022, 471 0x020f801f,
591/* 0x03aa: init_find_chipset */ 472 0xbb0117f0,
592 0xf0b602f8, 473 0x12b6041f,
593 0x00f39808, 474 0x0c27f101,
594 0xf40432b8, 475 0x0624b604,
595 0x34b00b0b, 476 0xd00021d0,
596 0xf11bf400, 477 0x17f14021,
597/* 0x03be: init_context */ 478 0x0e980100,
598 0x17f100f8, 479 0x010f9800,
599 0xfe580100, 480 0x014721f5,
600 0x03ff5802, 481 0x070037f1,
601 0x8000e3f0, 482 0x950634b6,
602 0x0f80140e, 483 0x34d00814,
603 0x3d21f515, 484 0x4034d000,
604 0x0037f101, 485 0x130030b7,
605 0x0634b607, 486 0xb6001fbb,
606 0xd0081495, 487 0x3fd002f5,
607 0x34d00034, 488 0x0815b600,
608 0x0030b740, 489 0xb60110b6,
609 0x001fbb13, 490 0x1fb90814,
610 0xd002f5b6, 491 0x7121f502,
611 0x15b6003f, 492 0x001fbb02,
612 0x0110b608, 493 0xf1020398,
613 0xb90814b6, 494 0xf0200047,
614 0x21f5021f, 495/* 0x03f6: init_gpc */
615 0x1fbb0263, 496 0x4ea05043,
616 0x00039800, 497 0x1fb90804,
617 0x200047f1, 498 0x8d21f402,
618/* 0x040f: init_gpc */ 499 0x010c4ea0,
619 0xa05043f0, 500 0x21f4f4bd,
620 0xb908044e, 501 0x044ea08d,
621 0x21f4021f, 502 0x8d21f401,
622 0x004ea08d, 503 0x01004ea0,
623 0x022fb908, 504 0xf402f7f0,
624 0xa08d21f4, 505 0x4ea08d21,
625 0xbd010c4e, 506/* 0x041e: init_gpc_wait */
626 0x8d21f4f4, 507 0x21f40800,
627 0x01044ea0, 508 0x1fffc868,
628 0xa08d21f4, 509 0xa0fa0bf4,
629 0xf001004e, 510 0xf408044e,
630 0x21f402f7, 511 0x1fbb6821,
631 0x004ea08d, 512 0x0040b700,
632/* 0x0441: init_gpc_wait */ 513 0x0132b680,
633 0x6821f408, 514 0xf1be1bf4,
634 0xf41fffc8, 515 0xf0010007,
635 0x4ea0fa0b, 516 0x01d00203,
636 0x21f40804, 517 0xbd04bd00,
637 0x001fbb68, 518 0x1f19f014,
638 0x800040b7, 519 0x080007f1,
639 0xf40132b6, 520 0xd00203f0,
640 0x27f1b41b, 521 0x04bd0001,
641 0x24b60800, 522/* 0x0458: main */
642 0x4021d006,
643 0x080020b7,
644 0x19f014bd,
645 0x0021d01f,
646/* 0x0474: main */
647 0xf40031f4, 523 0xf40031f4,
648 0xd7f00028, 524 0xd7f00028,
649 0x3921f408, 525 0x3921f410,
650 0xb1f401f4, 526 0xb1f401f4,
651 0xf54001e4, 527 0xf54001e4,
652 0xf100d11b, 528 0xbd00de1b,
653 0xb6083c87, 529 0x0499f094,
654 0x94bd0684, 530 0x0f0007f1,
655 0xd00499f0, 531 0xd00203f0,
656 0x17f10089, 532 0x04bd0009,
657 0x14b60b00, 533 0x0b0017f1,
658 0x4012cf06, 534 0xcf0614b6,
659 0xc80011cf, 535 0x11cf4012,
660 0x0bf41f13, 536 0x1f13c800,
661 0x1f23c87e, 537 0x00870bf5,
662 0xf95a0bf4,
663 0x0212b920,
664 0x083c87f1,
665 0xbd0684b6,
666 0x0799f094,
667 0xf40089d0,
668 0x31f40132,
669 0xfc21f502,
670 0x5c87f107,
671 0x0684b608,
672 0x99f094bd,
673 0x0089d007,
674 0x87f120fc,
675 0x84b6083c,
676 0xf094bd06,
677 0x89d00699,
678 0x0131f400,
679 0x07fc21f5,
680 0x085c87f1,
681 0xbd0684b6,
682 0x0699f094,
683 0xf40089d0,
684/* 0x050a: chsw_prev_no_next */
685 0x20f9310e,
686 0xf40212b9,
687 0x32f40132,
688 0xfc21f502,
689 0xf120fc07,
690 0xb60b0017,
691 0x12d00614,
692 0x130ef400,
693/* 0x0528: chsw_no_prev */
694 0xf41f23c8, 538 0xf41f23c8,
695 0x31f40d0b, 539 0x20f9620b,
540 0xbd0212b9,
541 0x0799f094,
542 0x0f0007f1,
543 0xd00203f0,
544 0x04bd0009,
545 0xf40132f4,
546 0x21f50231,
547 0x94bd0801,
548 0xf10799f0,
549 0xf0170007,
550 0x09d00203,
551 0xfc04bd00,
552 0xf094bd20,
553 0x07f10699,
554 0x03f00f00,
555 0x0009d002,
556 0x31f404bd,
557 0x0121f501,
558 0xf094bd08,
559 0x07f10699,
560 0x03f01700,
561 0x0009d002,
562 0x0ef404bd,
563/* 0x04f9: chsw_prev_no_next */
564 0xb920f931,
565 0x32f40212,
696 0x0232f401, 566 0x0232f401,
697 0x07fc21f5, 567 0x080121f5,
698/* 0x0538: chsw_done */ 568 0x17f120fc,
699 0x0b0c17f1, 569 0x14b60b00,
700 0xf00614b6, 570 0x0012d006,
701 0x12d00127, 571/* 0x0517: chsw_no_prev */
702 0x5c87f100, 572 0xc8130ef4,
703 0x0684b608, 573 0x0bf41f23,
704 0x99f094bd, 574 0x0131f40d,
705 0x0089d004,
706 0xff200ef5,
707/* 0x0558: main_not_ctx_switch */
708 0xf401e4b0,
709 0xf2b90d1b,
710 0x9021f502,
711 0x420ef407,
712/* 0x0568: main_not_ctx_chan */
713 0xf402e4b0,
714 0x87f12e1b,
715 0x84b6083c,
716 0xf094bd06,
717 0x89d00799,
718 0x0132f400,
719 0xf50232f4, 575 0xf50232f4,
720 0xf107fc21, 576/* 0x0527: chsw_done */
721 0xb6085c87, 577 0xf1080121,
722 0x94bd0684, 578 0xb60b0c17,
723 0xd00799f0, 579 0x27f00614,
724 0x0ef40089, 580 0x0012d001,
725/* 0x0599: main_not_ctx_save */ 581 0x99f094bd,
726 0x10ef9411, 582 0x0007f104,
727 0xf501f5f0, 583 0x0203f017,
728 0xf502ec21, 584 0xbd0009d0,
729/* 0x05a7: main_done */ 585 0x130ef504,
730 0xf1fed10e, 586/* 0x0549: main_not_ctx_switch */
731 0xb6082017, 587 0x01e4b0ff,
732 0x24bd0614, 588 0xb90d1bf4,
733 0xd01f29f0, 589 0x21f502f2,
734 0x0ef50012, 590 0x0ef40795,
735/* 0x05ba: ih */ 591/* 0x0559: main_not_ctx_chan */
736 0x80f9febe, 592 0x02e4b046,
737 0xf90188fe, 593 0xbd321bf4,
738 0xf990f980, 594 0x0799f094,
739 0xf9b0f9a0, 595 0x0f0007f1,
740 0xf9e0f9d0, 596 0xd00203f0,
741 0x800acff0, 597 0x04bd0009,
742 0xf404abc4, 598 0xf40132f4,
743 0xb7f11d0b, 599 0x21f50232,
744 0xd7f01900, 600 0x94bd0801,
745 0x40becf08, 601 0xf10799f0,
746 0xf400bfcf, 602 0xf0170007,
747 0xb0b70421, 603 0x09d00203,
748 0xe7f00400, 604 0xf404bd00,
749 0x00bed001, 605/* 0x058e: main_not_ctx_save */
750/* 0x05f0: ih_no_fifo */ 606 0xef94110e,
751 0x0100abe4, 607 0x01f5f010,
752 0xf00d0bf4, 608 0x02fe21f5,
753 0xe7f108d7, 609 0xfec00ef5,
754 0x21f44001, 610/* 0x059c: main_done */
755/* 0x0601: ih_no_ctxsw */ 611 0x29f024bd,
756 0x04b7f104, 612 0x0007f11f,
757 0xffb0bd01, 613 0x0203f008,
758 0x0bf4b4ab, 614 0xbd0002d0,
759 0x1ca7f10d, 615 0xab0ef504,
760 0x06a4b60c, 616/* 0x05b1: ih */
761/* 0x0617: ih_no_other */ 617 0xfe80f9fe,
762 0xd000abd0, 618 0x80f90188,
763 0xf0fc400a, 619 0xa0f990f9,
764 0xd0fce0fc, 620 0xd0f9b0f9,
765 0xa0fcb0fc, 621 0xf0f9e0f9,
766 0x80fc90fc, 622 0x0acf04bd,
767 0xfc0088fe, 623 0x04abc480,
768 0x0032f480, 624 0xf11d0bf4,
769/* 0x0632: ctx_4170s */ 625 0xf01900b7,
770 0xe7f101f8, 626 0xbecf10d7,
627 0x00bfcf40,
628 0xb70421f4,
629 0xf00400b0,
630 0xbed001e7,
631/* 0x05e9: ih_no_fifo */
632 0x00abe400,
633 0x0d0bf401,
634 0xf110d7f0,
635 0xf44001e7,
636/* 0x05fa: ih_no_ctxsw */
637 0xb7f10421,
638 0xb0bd0104,
639 0xf4b4abff,
640 0xa7f10d0b,
641 0xa4b60c1c,
642 0x00abd006,
643/* 0x0610: ih_no_other */
644 0xfc400ad0,
645 0xfce0fcf0,
646 0xfcb0fcd0,
647 0xfc90fca0,
648 0x0088fe80,
649 0x32f480fc,
650/* 0x062b: ctx_4170s */
651 0xf101f800,
652 0xf04170e7,
653 0xf5f040e3,
654 0x8d21f410,
655/* 0x063a: ctx_4170w */
656 0xe7f100f8,
771 0xe3f04170, 657 0xe3f04170,
772 0x10f5f040, 658 0x6821f440,
773 0xf88d21f4, 659 0xf410f4f0,
774/* 0x0641: ctx_4170w */ 660 0x00f8f31b,
775 0x70e7f100, 661/* 0x064c: ctx_redswitch */
776 0x40e3f041, 662 0x0614e7f1,
777 0xf06821f4, 663 0xf106e4b6,
778 0x1bf410f4, 664 0xd00270f7,
779/* 0x0653: ctx_redswitch */ 665 0xf7f000ef,
780 0xf100f8f3, 666/* 0x065d: ctx_redswitch_delay */
781 0xb60614e7, 667 0x01f2b608,
782 0xf7f106e4, 668 0xf1fd1bf4,
783 0xefd00270, 669 0xd00770f7,
784 0x08f7f000, 670 0x00f800ef,
785/* 0x0664: ctx_redswitch_delay */ 671/* 0x066c: ctx_86c */
786 0xf401f2b6, 672 0x086ce7f1,
787 0xf7f1fd1b, 673 0xd006e4b6,
788 0xefd00770, 674 0xe7f100ef,
789/* 0x0673: ctx_86c */ 675 0xe3f08a14,
790 0xf100f800, 676 0x8d21f440,
791 0xb6086ce7, 677 0xa86ce7f1,
792 0xefd006e4, 678 0xf441e3f0,
793 0x14e7f100, 679 0x00f88d21,
794 0x40e3f08a, 680/* 0x068c: ctx_load */
795 0xf18d21f4,
796 0xf0a86ce7,
797 0x21f441e3,
798/* 0x0693: ctx_load */
799 0xf100f88d,
800 0xb6083c87,
801 0x94bd0684,
802 0xd00599f0,
803 0xa7f00089,
804 0xc921f40c,
805 0x0a2417f1,
806 0xd00614b6,
807 0x37f10010,
808 0x34b60b00,
809 0x4032d006,
810 0x0a0c17f1,
811 0xf00614b6,
812 0x12d00747,
813 0x4014d000,
814/* 0x06cc: ctx_chan_wait_0 */
815 0xf04014cf,
816 0x1bf41f44,
817 0x0032d0fa,
818 0xf0000bfe,
819 0x24b61f2a,
820 0x0220b604,
821 0x083c87f1,
822 0xbd0684b6,
823 0x0899f094,
824 0xf10089d0,
825 0xb60a0417,
826 0x12d00614,
827 0x2017f100,
828 0x0614b60a,
829 0xf10227f0,
830 0xd0800023,
831 0x17f00012,
832 0x0027f110,
833 0x0223f002,
834 0xf80512fa,
835 0x5c87f103,
836 0x0684b608,
837 0x99f094bd, 681 0x99f094bd,
838 0x0089d008, 682 0x0007f105,
839 0xb6810198, 683 0x0203f00f,
840 0x02981814, 684 0xbd0009d0,
841 0x0825b680, 685 0x0ca7f004,
842 0x800512fd, 686 0xf1c921f4,
843 0x87f11601, 687 0xb60a2417,
844 0x84b6083c, 688 0x10d00614,
845 0xf094bd06, 689 0x0037f100,
846 0x89d00999, 690 0x0634b60b,
847 0x0427f100, 691 0xf14032d0,
848 0x0624b60a, 692 0xb60a0c17,
849 0xf00021d0, 693 0x47f00614,
850 0x17f10127, 694 0x0012d007,
695/* 0x06c7: ctx_chan_wait_0 */
696 0xcf4014d0,
697 0x44f04014,
698 0xfa1bf41f,
699 0xfe0032d0,
700 0x2af0000b,
701 0x0424b61f,
702 0xbd0220b6,
703 0x0899f094,
704 0x0f0007f1,
705 0xd00203f0,
706 0x04bd0009,
707 0x0a0417f1,
708 0xd00614b6,
709 0x17f10012,
851 0x14b60a20, 710 0x14b60a20,
852 0x0012d006, 711 0x0227f006,
853 0x010017f1, 712 0x800023f1,
854 0xfa0613f0, 713 0xf00012d0,
855 0x03f80501, 714 0x27f11017,
856 0x085c87f1, 715 0x23f00200,
857 0xbd0684b6, 716 0x0512fa02,
858 0x0999f094, 717 0x94bd03f8,
859 0xf10089d0, 718 0xf10899f0,
860 0xb6085c87, 719 0xf0170007,
861 0x94bd0684, 720 0x09d00203,
862 0xd00599f0, 721 0x9804bd00,
863 0x00f80089, 722 0x14b68101,
864/* 0x0790: ctx_chan */ 723 0x80029818,
865 0x069321f5, 724 0xfd0825b6,
866 0xf40ca7f0, 725 0x01800512,
867 0x17f1c921, 726 0xf094bd16,
868 0x14b60a10, 727 0x07f10999,
869 0x0527f006, 728 0x03f00f00,
870/* 0x07a7: ctx_chan_wait */ 729 0x0009d002,
871 0xcf0012d0, 730 0x27f104bd,
872 0x22fd0012, 731 0x24b60a04,
873 0xfa1bf405, 732 0x0021d006,
874/* 0x07b2: ctx_mmio_exec */ 733 0xf10127f0,
875 0x039800f8, 734 0xb60a2017,
876 0x0427f141, 735 0x12d00614,
877 0x0624b60a, 736 0x0017f100,
878 0xbd0023d0, 737 0x0613f001,
879/* 0x07c1: ctx_mmio_loop */ 738 0xf80501fa,
880 0xff34c434, 739 0xf094bd03,
881 0xf10f1bf4, 740 0x07f10999,
882 0xf0020057, 741 0x03f01700,
883 0x35fa0653, 742 0x0009d002,
884/* 0x07d3: ctx_mmio_pull */ 743 0x94bd04bd,
885 0x9803f805, 744 0xf10599f0,
886 0x4f98804e, 745 0xf0170007,
887 0x8d21f481, 746 0x09d00203,
888 0xb60830b6, 747 0xf804bd00,
889 0x1bf40112, 748/* 0x0795: ctx_chan */
890/* 0x07e5: ctx_mmio_done */ 749 0x8c21f500,
891 0x160398df, 750 0x0ca7f006,
892 0x800023d0, 751 0xf1c921f4,
893 0x17f14000, 752 0xb60a1017,
894 0x13f00100, 753 0x27f00614,
895 0x0601fa06, 754 0x0012d005,
896 0x00f803f8, 755/* 0x07ac: ctx_chan_wait */
897/* 0x07fc: ctx_xfer */ 756 0xfd0012cf,
898 0x0c00f7f1, 757 0x1bf40522,
899 0xf006f4b6, 758/* 0x07b7: ctx_mmio_exec */
900 0xfed004e7, 759 0x9800f8fa,
901/* 0x0809: ctx_xfer_idle */ 760 0x27f14103,
902 0x00fecf80, 761 0x24b60a04,
903 0x2000e4f1, 762 0x0023d006,
904 0xf4f91bf4, 763/* 0x07c6: ctx_mmio_loop */
905 0x02f40611, 764 0x34c434bd,
906/* 0x0819: ctx_xfer_pre */ 765 0x0f1bf4ff,
907 0x10f7f00d, 766 0x020057f1,
908 0x067321f5, 767 0xfa0653f0,
909/* 0x0823: ctx_xfer_pre_load */ 768 0x03f80535,
910 0xf01c11f4, 769/* 0x07d8: ctx_mmio_pull */
911 0x21f502f7, 770 0x98804e98,
912 0x21f50632, 771 0x21f4814f,
913 0x21f50641, 772 0x0830b68d,
914 0xf4bd0653, 773 0xf40112b6,
915 0x063221f5, 774/* 0x07ea: ctx_mmio_done */
916 0x069321f5, 775 0x0398df1b,
917/* 0x083c: ctx_xfer_exec */ 776 0x0023d016,
918 0xf1160198, 777 0xf1400080,
919 0xb6041427, 778 0xf0010017,
920 0x20d00624, 779 0x01fa0613,
921 0x00e7f100, 780 0xf803f806,
922 0x41e3f0a5, 781/* 0x0801: ctx_xfer */
923 0xf4021fb9, 782 0x00f7f100,
924 0xe0b68d21, 783 0x06f4b60c,
925 0x01fcf004, 784 0xd004e7f0,
926 0xb6022cf0, 785/* 0x080e: ctx_xfer_idle */
927 0xf2fd0124, 786 0xfecf80fe,
928 0x8d21f405, 787 0x00e4f100,
929 0x4afc17f1, 788 0xf91bf420,
930 0xf00213f0, 789 0xf40611f4,
931 0x12d00c27, 790/* 0x081e: ctx_xfer_pre */
932 0x0721f500, 791 0xf7f00d02,
933 0xfc27f102, 792 0x6c21f510,
934 0x0223f047, 793 0x1c11f406,
935 0xf00020d0, 794/* 0x0828: ctx_xfer_pre_load */
936 0x20b6012c, 795 0xf502f7f0,
937 0x0012d003, 796 0xf5062b21,
938 0xf001acf0, 797 0xf5063a21,
939 0xb7f006a5, 798 0xbd064c21,
940 0x140c9800, 799 0x2b21f5f4,
941 0xf0150d98, 800 0x8c21f506,
942 0x21f500e7, 801/* 0x0841: ctx_xfer_exec */
943 0xa7f0015c, 802 0x16019806,
944 0x0321f508, 803 0x041427f1,
945 0x0721f501, 804 0xd00624b6,
946 0x2201f402, 805 0xe7f10020,
947 0xf40ca7f0, 806 0xe3f0a500,
948 0x17f1c921, 807 0x021fb941,
949 0x14b60a10, 808 0xb68d21f4,
950 0x0527f006, 809 0xfcf004e0,
951/* 0x08c3: ctx_xfer_post_save_wait */ 810 0x022cf001,
952 0xcf0012d0, 811 0xfd0124b6,
953 0x22fd0012, 812 0x21f405f2,
954 0xfa1bf405, 813 0xfc17f18d,
955/* 0x08cf: ctx_xfer_post */ 814 0x0213f04a,
956 0xf02e02f4, 815 0xd00c27f0,
957 0x21f502f7, 816 0x21f50012,
958 0xf4bd0632, 817 0x27f10215,
959 0x067321f5, 818 0x23f047fc,
960 0x022621f5, 819 0x0020d002,
961 0x064121f5, 820 0xb6012cf0,
962 0x21f5f4bd, 821 0x12d00320,
963 0x11f40632, 822 0x01acf000,
964 0x40019810, 823 0xf006a5f0,
965 0xf40511fd, 824 0x0c9800b7,
966 0x21f5070b, 825 0x010d9800,
967/* 0x08fa: ctx_xfer_no_post_mmio */ 826 0xf500e7f0,
968/* 0x08fa: ctx_xfer_done */ 827 0xf0016621,
969 0x00f807b2, 828 0x21f508a7,
829 0x21f50109,
830 0x01f40215,
831 0x0ca7f022,
832 0xf1c921f4,
833 0xb60a1017,
834 0x27f00614,
835 0x0012d005,
836/* 0x08c8: ctx_xfer_post_save_wait */
837 0xfd0012cf,
838 0x1bf40522,
839 0x2e02f4fa,
840/* 0x08d4: ctx_xfer_post */
841 0xf502f7f0,
842 0xbd062b21,
843 0x6c21f5f4,
844 0x3421f506,
845 0x3a21f502,
846 0xf5f4bd06,
847 0xf4062b21,
848 0x01981011,
849 0x0511fd40,
850 0xf5070bf4,
851/* 0x08ff: ctx_xfer_no_post_mmio */
852/* 0x08ff: ctx_xfer_done */
853 0xf807b721,
854 0x00000000,
855 0x00000000,
856 0x00000000,
857 0x00000000,
858 0x00000000,
859 0x00000000,
860 0x00000000,
861 0x00000000,
862 0x00000000,
863 0x00000000,
864 0x00000000,
865 0x00000000,
866 0x00000000,
867 0x00000000,
868 0x00000000,
869 0x00000000,
870 0x00000000,
871 0x00000000,
872 0x00000000,
873 0x00000000,
874 0x00000000,
875 0x00000000,
876 0x00000000,
877 0x00000000,
878 0x00000000,
879 0x00000000,
880 0x00000000,
881 0x00000000,
882 0x00000000,
883 0x00000000,
884 0x00000000,
885 0x00000000,
886 0x00000000,
887 0x00000000,
888 0x00000000,
889 0x00000000,
890 0x00000000,
891 0x00000000,
892 0x00000000,
893 0x00000000,
894 0x00000000,
895 0x00000000,
896 0x00000000,
897 0x00000000,
898 0x00000000,
899 0x00000000,
900 0x00000000,
901 0x00000000,
902 0x00000000,
903 0x00000000,
904 0x00000000,
905 0x00000000,
906 0x00000000,
907 0x00000000,
908 0x00000000,
909 0x00000000,
910 0x00000000,
911 0x00000000,
912 0x00000000,
913 0x00000000,
914 0x00000000,
915 0x00000000,
916 0x00000000,
970 0x00000000, 917 0x00000000,
971}; 918};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
new file mode 100644
index 000000000000..ec42ed29b50d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#define CHIPSET GK110
26#include "macros.fuc"
27
28.section #nvf0_grhub_data
29#define INCLUDE_DATA
30#include "com.fuc"
31#include "hub.fuc"
32#undef INCLUDE_DATA
33
34.section #nvf0_grhub_code
35#define INCLUDE_CODE
36bra #init
37#include "com.fuc"
38#include "hub.fuc"
39.align 256
40#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
new file mode 100644
index 000000000000..438506d14749
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
@@ -0,0 +1,918 @@
1uint32_t nvf0_grhub_data[] = {
2/* 0x0000: hub_mmio_list_head */
3 0x00000300,
4/* 0x0004: hub_mmio_list_tail */
5 0x00000304,
6/* 0x0008: gpc_count */
7 0x00000000,
8/* 0x000c: rop_count */
9 0x00000000,
10/* 0x0010: cmd_queue */
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29/* 0x0058: ctx_current */
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x00000000,
71 0x00000000,
72/* 0x0100: chan_data */
73/* 0x0100: chan_mmio_count */
74 0x00000000,
75/* 0x0104: chan_mmio_address */
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x00000000,
93 0x00000000,
94 0x00000000,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139/* 0x0200: xfer_data */
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204/* 0x0300: hub_mmio_list_base */
205 0x0417e91c,
206};
207
208uint32_t nvf0_grhub_code[] = {
209 0x031b0ef5,
210/* 0x0004: queue_put */
211 0x9800d898,
212 0x86f001d9,
213 0x0489b808,
214 0xf00c1bf4,
215 0x21f502f7,
216 0x00f802fe,
217/* 0x001c: queue_put_next */
218 0xb60798c4,
219 0x8dbb0384,
220 0x0880b600,
221 0x80008e80,
222 0x90b6018f,
223 0x0f94f001,
224 0xf801d980,
225/* 0x0039: queue_get */
226 0x0131f400,
227 0x9800d898,
228 0x89b801d9,
229 0x210bf404,
230 0xb60789c4,
231 0x9dbb0394,
232 0x0890b600,
233 0x98009e98,
234 0x80b6019f,
235 0x0f84f001,
236 0xf400d880,
237/* 0x0066: queue_get_done */
238 0x00f80132,
239/* 0x0068: nv_rd32 */
240 0x0728b7f1,
241 0xb906b4b6,
242 0xc9f002ec,
243 0x00bcd01f,
244/* 0x0078: nv_rd32_wait */
245 0xc800bccf,
246 0x1bf41fcc,
247 0x06a7f0fa,
248 0x010921f5,
249 0xf840bfcf,
250/* 0x008d: nv_wr32 */
251 0x28b7f100,
252 0x06b4b607,
253 0xb980bfd0,
254 0xc9f002ec,
255 0x1ec9f01f,
256/* 0x00a3: nv_wr32_wait */
257 0xcf00bcd0,
258 0xccc800bc,
259 0xfa1bf41f,
260/* 0x00ae: watchdog_reset */
261 0x87f100f8,
262 0x84b60430,
263 0x1ff9f006,
264 0xf8008fd0,
265/* 0x00bd: watchdog_clear */
266 0x3087f100,
267 0x0684b604,
268 0xf80080d0,
269/* 0x00c9: wait_donez */
270 0xf094bd00,
271 0x07f10099,
272 0x03f03700,
273 0x0009d002,
274 0x07f104bd,
275 0x03f00600,
276 0x000ad002,
277/* 0x00e6: wait_donez_ne */
278 0x87f104bd,
279 0x83f00000,
280 0x0088cf01,
281 0xf4888aff,
282 0x94bdf31b,
283 0xf10099f0,
284 0xf0170007,
285 0x09d00203,
286 0xf804bd00,
287/* 0x0109: wait_doneo */
288 0xf094bd00,
289 0x07f10099,
290 0x03f03700,
291 0x0009d002,
292 0x87f104bd,
293 0x84b60818,
294 0x008ad006,
295/* 0x0124: wait_doneo_e */
296 0x040087f1,
297 0xcf0684b6,
298 0x8aff0088,
299 0xf30bf488,
300 0x99f094bd,
301 0x0007f100,
302 0x0203f017,
303 0xbd0009d0,
304/* 0x0147: mmctx_size */
305 0xbd00f804,
306/* 0x0149: nv_mmctx_size_loop */
307 0x00e89894,
308 0xb61a85b6,
309 0x84b60180,
310 0x0098bb02,
311 0xb804e0b6,
312 0x1bf404ef,
313 0x029fb9eb,
314/* 0x0166: mmctx_xfer */
315 0x94bd00f8,
316 0xf10199f0,
317 0xf0370007,
318 0x09d00203,
319 0xf104bd00,
320 0xb6071087,
321 0x94bd0684,
322 0xf405bbfd,
323 0x8bd0090b,
324 0x0099f000,
325/* 0x018c: mmctx_base_disabled */
326 0xf405eefd,
327 0x8ed00c0b,
328 0xc08fd080,
329/* 0x019b: mmctx_multi_disabled */
330 0xb70199f0,
331 0xc8010080,
332 0xb4b600ab,
333 0x0cb9f010,
334 0xb601aec8,
335 0xbefd11e4,
336 0x008bd005,
337/* 0x01b4: mmctx_exec_loop */
338/* 0x01b4: mmctx_wait_free */
339 0xf0008ecf,
340 0x0bf41fe4,
341 0x00ce98fa,
342 0xd005e9fd,
343 0xc0b6c08e,
344 0x04cdb804,
345 0xc8e81bf4,
346 0x1bf402ab,
347/* 0x01d5: mmctx_fini_wait */
348 0x008bcf18,
349 0xb01fb4f0,
350 0x1bf410b4,
351 0x02a7f0f7,
352 0xf4c921f4,
353/* 0x01ea: mmctx_stop */
354 0xabc81b0e,
355 0x10b4b600,
356 0xf00cb9f0,
357 0x8bd012b9,
358/* 0x01f9: mmctx_stop_wait */
359 0x008bcf00,
360 0xf412bbc8,
361/* 0x0202: mmctx_done */
362 0x94bdfa1b,
363 0xf10199f0,
364 0xf0170007,
365 0x09d00203,
366 0xf804bd00,
367/* 0x0215: strand_wait */
368 0xf0a0f900,
369 0x21f402a7,
370 0xf8a0fcc9,
371/* 0x0221: strand_pre */
372 0xfc87f100,
373 0x0283f04a,
374 0xd00c97f0,
375 0x21f50089,
376 0x00f80215,
377/* 0x0234: strand_post */
378 0x4afc87f1,
379 0xf00283f0,
380 0x89d00d97,
381 0x1521f500,
382/* 0x0247: strand_set */
383 0xf100f802,
384 0xf04ffca7,
385 0xaba202a3,
386 0xc7f00500,
387 0x00acd00f,
388 0xd00bc7f0,
389 0x21f500bc,
390 0xaed00215,
391 0x0ac7f000,
392 0xf500bcd0,
393 0xf8021521,
394/* 0x0271: strand_ctx_init */
395 0xf094bd00,
396 0x07f10399,
397 0x03f03700,
398 0x0009d002,
399 0x21f504bd,
400 0xe7f00221,
401 0x4721f503,
402 0xfca7f102,
403 0x02a3f046,
404 0x0400aba0,
405 0xf040a0d0,
406 0xbcd001c7,
407 0x1521f500,
408 0x010c9202,
409 0xf000acd0,
410 0xbcd002c7,
411 0x1521f500,
412 0x3421f502,
413 0x8087f102,
414 0x0684b608,
415 0xb70089cf,
416 0x95220080,
417/* 0x02ca: ctx_init_strand_loop */
418 0x8ed008fe,
419 0x408ed000,
420 0xb6808acf,
421 0xa0b606a5,
422 0x00eabb01,
423 0xb60480b6,
424 0x1bf40192,
425 0x08e4b6e8,
426 0xbdf2efbc,
427 0x0399f094,
428 0x170007f1,
429 0xd00203f0,
430 0x04bd0009,
431/* 0x02fe: error */
432 0x07f100f8,
433 0x03f00500,
434 0x000fd002,
435 0xf7f004bd,
436 0x0007f101,
437 0x0303f007,
438 0xbd000fd0,
439/* 0x031b: init */
440 0xbd00f804,
441 0x0004fe04,
442 0xf10007fe,
443 0xf0120017,
444 0x12d00227,
445 0xb117f100,
446 0x0010fe05,
447 0x040017f1,
448 0xf1c010d0,
449 0xb6040437,
450 0x27f10634,
451 0x32d02003,
452 0x0427f100,
453 0x0132d020,
454 0x200b27f1,
455 0xf10232d0,
456 0xd0200c27,
457 0x27f10732,
458 0x24b60c24,
459 0x0003b906,
460 0xf10023d0,
461 0xf0870427,
462 0x12d00023,
463 0x0012b700,
464 0x0427f001,
465 0xf40012d0,
466 0xe7f11031,
467 0xe3f09604,
468 0x6821f440,
469 0x8090f1c7,
470 0xf4f00301,
471 0x020f801f,
472 0xbb0117f0,
473 0x12b6041f,
474 0x0c27f101,
475 0x0624b604,
476 0xd00021d0,
477 0x17f14021,
478 0x0e980100,
479 0x010f9800,
480 0x014721f5,
481 0x070037f1,
482 0x950634b6,
483 0x34d00814,
484 0x4034d000,
485 0x130030b7,
486 0xb6001fbb,
487 0x3fd002f5,
488 0x0815b600,
489 0xb60110b6,
490 0x1fb90814,
491 0x7121f502,
492 0x001fbb02,
493 0xf1020398,
494 0xf0200047,
495/* 0x03f6: init_gpc */
496 0x4ea05043,
497 0x1fb90804,
498 0x8d21f402,
499 0x010c4ea0,
500 0x21f4f4bd,
501 0x044ea08d,
502 0x8d21f401,
503 0x01004ea0,
504 0xf402f7f0,
505 0x4ea08d21,
506/* 0x041e: init_gpc_wait */
507 0x21f40800,
508 0x1fffc868,
509 0xa0fa0bf4,
510 0xf408044e,
511 0x1fbb6821,
512 0x0040b700,
513 0x0132b680,
514 0xf1be1bf4,
515 0xf0010007,
516 0x01d00203,
517 0xbd04bd00,
518 0x1f19f014,
519 0x300007f1,
520 0xd00203f0,
521 0x04bd0001,
522/* 0x0458: main */
523 0xf40031f4,
524 0xd7f00028,
525 0x3921f410,
526 0xb1f401f4,
527 0xf54001e4,
528 0xbd00de1b,
529 0x0499f094,
530 0x370007f1,
531 0xd00203f0,
532 0x04bd0009,
533 0x0b0017f1,
534 0xcf0614b6,
535 0x11cf4012,
536 0x1f13c800,
537 0x00870bf5,
538 0xf41f23c8,
539 0x20f9620b,
540 0xbd0212b9,
541 0x0799f094,
542 0x370007f1,
543 0xd00203f0,
544 0x04bd0009,
545 0xf40132f4,
546 0x21f50231,
547 0x94bd0801,
548 0xf10799f0,
549 0xf0170007,
550 0x09d00203,
551 0xfc04bd00,
552 0xf094bd20,
553 0x07f10699,
554 0x03f03700,
555 0x0009d002,
556 0x31f404bd,
557 0x0121f501,
558 0xf094bd08,
559 0x07f10699,
560 0x03f01700,
561 0x0009d002,
562 0x0ef404bd,
563/* 0x04f9: chsw_prev_no_next */
564 0xb920f931,
565 0x32f40212,
566 0x0232f401,
567 0x080121f5,
568 0x17f120fc,
569 0x14b60b00,
570 0x0012d006,
571/* 0x0517: chsw_no_prev */
572 0xc8130ef4,
573 0x0bf41f23,
574 0x0131f40d,
575 0xf50232f4,
576/* 0x0527: chsw_done */
577 0xf1080121,
578 0xb60b0c17,
579 0x27f00614,
580 0x0012d001,
581 0x99f094bd,
582 0x0007f104,
583 0x0203f017,
584 0xbd0009d0,
585 0x130ef504,
586/* 0x0549: main_not_ctx_switch */
587 0x01e4b0ff,
588 0xb90d1bf4,
589 0x21f502f2,
590 0x0ef40795,
591/* 0x0559: main_not_ctx_chan */
592 0x02e4b046,
593 0xbd321bf4,
594 0x0799f094,
595 0x370007f1,
596 0xd00203f0,
597 0x04bd0009,
598 0xf40132f4,
599 0x21f50232,
600 0x94bd0801,
601 0xf10799f0,
602 0xf0170007,
603 0x09d00203,
604 0xf404bd00,
605/* 0x058e: main_not_ctx_save */
606 0xef94110e,
607 0x01f5f010,
608 0x02fe21f5,
609 0xfec00ef5,
610/* 0x059c: main_done */
611 0x29f024bd,
612 0x0007f11f,
613 0x0203f030,
614 0xbd0002d0,
615 0xab0ef504,
616/* 0x05b1: ih */
617 0xfe80f9fe,
618 0x80f90188,
619 0xa0f990f9,
620 0xd0f9b0f9,
621 0xf0f9e0f9,
622 0x0acf04bd,
623 0x04abc480,
624 0xf11d0bf4,
625 0xf01900b7,
626 0xbecf10d7,
627 0x00bfcf40,
628 0xb70421f4,
629 0xf00400b0,
630 0xbed001e7,
631/* 0x05e9: ih_no_fifo */
632 0x00abe400,
633 0x0d0bf401,
634 0xf110d7f0,
635 0xf44001e7,
636/* 0x05fa: ih_no_ctxsw */
637 0xb7f10421,
638 0xb0bd0104,
639 0xf4b4abff,
640 0xa7f10d0b,
641 0xa4b60c1c,
642 0x00abd006,
643/* 0x0610: ih_no_other */
644 0xfc400ad0,
645 0xfce0fcf0,
646 0xfcb0fcd0,
647 0xfc90fca0,
648 0x0088fe80,
649 0x32f480fc,
650/* 0x062b: ctx_4170s */
651 0xf101f800,
652 0xf04170e7,
653 0xf5f040e3,
654 0x8d21f410,
655/* 0x063a: ctx_4170w */
656 0xe7f100f8,
657 0xe3f04170,
658 0x6821f440,
659 0xf410f4f0,
660 0x00f8f31b,
661/* 0x064c: ctx_redswitch */
662 0x0614e7f1,
663 0xf106e4b6,
664 0xd00270f7,
665 0xf7f000ef,
666/* 0x065d: ctx_redswitch_delay */
667 0x01f2b608,
668 0xf1fd1bf4,
669 0xd00770f7,
670 0x00f800ef,
671/* 0x066c: ctx_86c */
672 0x086ce7f1,
673 0xd006e4b6,
674 0xe7f100ef,
675 0xe3f08a14,
676 0x8d21f440,
677 0xa86ce7f1,
678 0xf441e3f0,
679 0x00f88d21,
680/* 0x068c: ctx_load */
681 0x99f094bd,
682 0x0007f105,
683 0x0203f037,
684 0xbd0009d0,
685 0x0ca7f004,
686 0xf1c921f4,
687 0xb60a2417,
688 0x10d00614,
689 0x0037f100,
690 0x0634b60b,
691 0xf14032d0,
692 0xb60a0c17,
693 0x47f00614,
694 0x0012d007,
695/* 0x06c7: ctx_chan_wait_0 */
696 0xcf4014d0,
697 0x44f04014,
698 0xfa1bf41f,
699 0xfe0032d0,
700 0x2af0000b,
701 0x0424b61f,
702 0xbd0220b6,
703 0x0899f094,
704 0x370007f1,
705 0xd00203f0,
706 0x04bd0009,
707 0x0a0417f1,
708 0xd00614b6,
709 0x17f10012,
710 0x14b60a20,
711 0x0227f006,
712 0x800023f1,
713 0xf00012d0,
714 0x27f11017,
715 0x23f00200,
716 0x0512fa02,
717 0x94bd03f8,
718 0xf10899f0,
719 0xf0170007,
720 0x09d00203,
721 0x9804bd00,
722 0x14b68101,
723 0x80029818,
724 0xfd0825b6,
725 0x01800512,
726 0xf094bd16,
727 0x07f10999,
728 0x03f03700,
729 0x0009d002,
730 0x27f104bd,
731 0x24b60a04,
732 0x0021d006,
733 0xf10127f0,
734 0xb60a2017,
735 0x12d00614,
736 0x0017f100,
737 0x0613f001,
738 0xf80501fa,
739 0xf094bd03,
740 0x07f10999,
741 0x03f01700,
742 0x0009d002,
743 0x94bd04bd,
744 0xf10599f0,
745 0xf0170007,
746 0x09d00203,
747 0xf804bd00,
748/* 0x0795: ctx_chan */
749 0x8c21f500,
750 0x0ca7f006,
751 0xf1c921f4,
752 0xb60a1017,
753 0x27f00614,
754 0x0012d005,
755/* 0x07ac: ctx_chan_wait */
756 0xfd0012cf,
757 0x1bf40522,
758/* 0x07b7: ctx_mmio_exec */
759 0x9800f8fa,
760 0x27f14103,
761 0x24b60a04,
762 0x0023d006,
763/* 0x07c6: ctx_mmio_loop */
764 0x34c434bd,
765 0x0f1bf4ff,
766 0x020057f1,
767 0xfa0653f0,
768 0x03f80535,
769/* 0x07d8: ctx_mmio_pull */
770 0x98804e98,
771 0x21f4814f,
772 0x0830b68d,
773 0xf40112b6,
774/* 0x07ea: ctx_mmio_done */
775 0x0398df1b,
776 0x0023d016,
777 0xf1400080,
778 0xf0010017,
779 0x01fa0613,
780 0xf803f806,
781/* 0x0801: ctx_xfer */
782 0x00f7f100,
783 0x06f4b60c,
784 0xd004e7f0,
785/* 0x080e: ctx_xfer_idle */
786 0xfecf80fe,
787 0x00e4f100,
788 0xf91bf420,
789 0xf40611f4,
790/* 0x081e: ctx_xfer_pre */
791 0xf7f00d02,
792 0x6c21f510,
793 0x1c11f406,
794/* 0x0828: ctx_xfer_pre_load */
795 0xf502f7f0,
796 0xf5062b21,
797 0xf5063a21,
798 0xbd064c21,
799 0x2b21f5f4,
800 0x8c21f506,
801/* 0x0841: ctx_xfer_exec */
802 0x16019806,
803 0x041427f1,
804 0xd00624b6,
805 0xe7f10020,
806 0xe3f0a500,
807 0x021fb941,
808 0xb68d21f4,
809 0xfcf004e0,
810 0x022cf001,
811 0xfd0124b6,
812 0x21f405f2,
813 0xfc17f18d,
814 0x0213f04a,
815 0xd00c27f0,
816 0x21f50012,
817 0x27f10215,
818 0x23f047fc,
819 0x0020d002,
820 0xb6012cf0,
821 0x12d00320,
822 0x01acf000,
823 0xf006a5f0,
824 0x0c9800b7,
825 0x010d9800,
826 0xf500e7f0,
827 0xf0016621,
828 0x21f508a7,
829 0x21f50109,
830 0x01f40215,
831 0x0ca7f022,
832 0xf1c921f4,
833 0xb60a1017,
834 0x27f00614,
835 0x0012d005,
836/* 0x08c8: ctx_xfer_post_save_wait */
837 0xfd0012cf,
838 0x1bf40522,
839 0x2e02f4fa,
840/* 0x08d4: ctx_xfer_post */
841 0xf502f7f0,
842 0xbd062b21,
843 0x6c21f5f4,
844 0x3421f506,
845 0x3a21f502,
846 0xf5f4bd06,
847 0xf4062b21,
848 0x01981011,
849 0x0511fd40,
850 0xf5070bf4,
851/* 0x08ff: ctx_xfer_no_post_mmio */
852/* 0x08ff: ctx_xfer_done */
853 0xf807b721,
854 0x00000000,
855 0x00000000,
856 0x00000000,
857 0x00000000,
858 0x00000000,
859 0x00000000,
860 0x00000000,
861 0x00000000,
862 0x00000000,
863 0x00000000,
864 0x00000000,
865 0x00000000,
866 0x00000000,
867 0x00000000,
868 0x00000000,
869 0x00000000,
870 0x00000000,
871 0x00000000,
872 0x00000000,
873 0x00000000,
874 0x00000000,
875 0x00000000,
876 0x00000000,
877 0x00000000,
878 0x00000000,
879 0x00000000,
880 0x00000000,
881 0x00000000,
882 0x00000000,
883 0x00000000,
884 0x00000000,
885 0x00000000,
886 0x00000000,
887 0x00000000,
888 0x00000000,
889 0x00000000,
890 0x00000000,
891 0x00000000,
892 0x00000000,
893 0x00000000,
894 0x00000000,
895 0x00000000,
896 0x00000000,
897 0x00000000,
898 0x00000000,
899 0x00000000,
900 0x00000000,
901 0x00000000,
902 0x00000000,
903 0x00000000,
904 0x00000000,
905 0x00000000,
906 0x00000000,
907 0x00000000,
908 0x00000000,
909 0x00000000,
910 0x00000000,
911 0x00000000,
912 0x00000000,
913 0x00000000,
914 0x00000000,
915 0x00000000,
916 0x00000000,
917 0x00000000,
918};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
index 43a0b9476efd..33a5a82eccbd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
@@ -24,6 +24,33 @@
24 24
25#include "os.h" 25#include "os.h"
26 26
27#define GF100 0xc0
28#define GF117 0xd7
29#define GK100 0xe0
30#define GK110 0xf0
31
32#define NV_PGRAPH_FECS_SIGNAL 0x409400
33#if CHIPSET < GK110
34#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
35#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820)
36#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
37#else
38#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
39#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
40#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0)
41#endif
42#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c
43
44#if CHIPSET < GK110
45#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
46#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820)
47#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
48#else
49#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
50#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
51#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0)
52#endif
53
27#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) 54#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
28#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) 55#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
29 56
@@ -38,16 +65,25 @@
38#define T_LCHAN 8 65#define T_LCHAN 8
39#define T_LCTXH 9 66#define T_LCTXH 9
40 67
68#define nv_mkmm(rv,r) /*
69*/ movw rv ((r) & 0x0000fffc) /*
70*/ sethi rv ((r) & 0x00ff0000)
71#define nv_mkio(rv,r,i) /*
72*/ nv_mkmm(rv, (((r) & 0xffc) << 6) | ((i) << 2))
73
74#define nv_iord(rv,r,i) /*
75*/ nv_mkio(rv,r,i) /*
76*/ iord rv I[rv]
77#define nv_iowr(r,i,rv) /*
78*/ nv_mkio($r0,r,i) /*
79*/ iowr I[$r0] rv /*
80*/ clear b32 $r0
81
41#define trace_set(bit) /* 82#define trace_set(bit) /*
42*/ mov $r8 0x83c /*
43*/ shl b32 $r8 6 /*
44*/ clear b32 $r9 /* 83*/ clear b32 $r9 /*
45*/ bset $r9 bit /* 84*/ bset $r9 bit /*
46*/ iowr I[$r8 + 0x000] $r9 85*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
47
48#define trace_clr(bit) /* 86#define trace_clr(bit) /*
49*/ mov $r8 0x85c /*
50*/ shl b32 $r8 6 /*
51*/ clear b32 $r9 /* 87*/ clear b32 $r9 /*
52*/ bset $r9 bit /* 88*/ bset $r9 bit /*
53*/ iowr I[$r8 + 0x000] $r9 89*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index d61c833be09f..3f4f35cc3848 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -23,14 +23,12 @@
23 */ 23 */
24 24
25#include "nvc0.h" 25#include "nvc0.h"
26#include "fuc/hubnvc0.fuc.h"
27#include "fuc/gpcnvc0.fuc.h"
28 26
29/******************************************************************************* 27/*******************************************************************************
30 * Graphics object classes 28 * Graphics object classes
31 ******************************************************************************/ 29 ******************************************************************************/
32 30
33static struct nouveau_oclass 31struct nouveau_oclass
34nvc0_graph_sclass[] = { 32nvc0_graph_sclass[] = {
35 { 0x902d, &nouveau_object_ofuncs }, 33 { 0x902d, &nouveau_object_ofuncs },
36 { 0x9039, &nouveau_object_ofuncs }, 34 { 0x9039, &nouveau_object_ofuncs },
@@ -39,40 +37,6 @@ nvc0_graph_sclass[] = {
39 {} 37 {}
40}; 38};
41 39
42static struct nouveau_oclass
43nvc1_graph_sclass[] = {
44 { 0x902d, &nouveau_object_ofuncs },
45 { 0x9039, &nouveau_object_ofuncs },
46 { 0x9097, &nouveau_object_ofuncs },
47 { 0x90c0, &nouveau_object_ofuncs },
48 { 0x9197, &nouveau_object_ofuncs },
49 {}
50};
51
52static struct nouveau_oclass
53nvc8_graph_sclass[] = {
54 { 0x902d, &nouveau_object_ofuncs },
55 { 0x9039, &nouveau_object_ofuncs },
56 { 0x9097, &nouveau_object_ofuncs },
57 { 0x90c0, &nouveau_object_ofuncs },
58 { 0x9197, &nouveau_object_ofuncs },
59 { 0x9297, &nouveau_object_ofuncs },
60 {}
61};
62
63u64
64nvc0_graph_units(struct nouveau_graph *graph)
65{
66 struct nvc0_graph_priv *priv = (void *)graph;
67 u64 cfg;
68
69 cfg = (u32)priv->gpc_nr;
70 cfg |= (u32)priv->tpc_total << 8;
71 cfg |= (u64)priv->rop_nr << 32;
72
73 return cfg;
74}
75
76/******************************************************************************* 40/*******************************************************************************
77 * PGRAPH context 41 * PGRAPH context
78 ******************************************************************************/ 42 ******************************************************************************/
@@ -181,60 +145,271 @@ nvc0_graph_context_dtor(struct nouveau_object *object)
181 nouveau_graph_context_destroy(&chan->base); 145 nouveau_graph_context_destroy(&chan->base);
182} 146}
183 147
184static struct nouveau_oclass
185nvc0_graph_cclass = {
186 .ofuncs = &(struct nouveau_ofuncs) {
187 .ctor = nvc0_graph_context_ctor,
188 .dtor = nvc0_graph_context_dtor,
189 .init = _nouveau_graph_context_init,
190 .fini = _nouveau_graph_context_fini,
191 .rd32 = _nouveau_graph_context_rd32,
192 .wr32 = _nouveau_graph_context_wr32,
193 },
194};
195
196/******************************************************************************* 148/*******************************************************************************
197 * PGRAPH engine/subdev functions 149 * PGRAPH engine/subdev functions
198 ******************************************************************************/ 150 ******************************************************************************/
199 151
200static void 152struct nvc0_graph_init
201nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) 153nvc0_graph_init_regs[] = {
154 { 0x400080, 1, 0x04, 0x003083c2 },
155 { 0x400088, 1, 0x04, 0x00006fe7 },
156 { 0x40008c, 1, 0x04, 0x00000000 },
157 { 0x400090, 1, 0x04, 0x00000030 },
158 { 0x40013c, 1, 0x04, 0x013901f7 },
159 { 0x400140, 1, 0x04, 0x00000100 },
160 { 0x400144, 1, 0x04, 0x00000000 },
161 { 0x400148, 1, 0x04, 0x00000110 },
162 { 0x400138, 1, 0x04, 0x00000000 },
163 { 0x400130, 2, 0x04, 0x00000000 },
164 { 0x400124, 1, 0x04, 0x00000002 },
165 {}
166};
167
168struct nvc0_graph_init
169nvc0_graph_init_unk40xx[] = {
170 { 0x40415c, 1, 0x04, 0x00000000 },
171 { 0x404170, 1, 0x04, 0x00000000 },
172 {}
173};
174
175struct nvc0_graph_init
176nvc0_graph_init_unk44xx[] = {
177 { 0x404488, 2, 0x04, 0x00000000 },
178 {}
179};
180
181struct nvc0_graph_init
182nvc0_graph_init_unk78xx[] = {
183 { 0x407808, 1, 0x04, 0x00000000 },
184 {}
185};
186
187struct nvc0_graph_init
188nvc0_graph_init_unk60xx[] = {
189 { 0x406024, 1, 0x04, 0x00000000 },
190 {}
191};
192
193struct nvc0_graph_init
194nvc0_graph_init_unk58xx[] = {
195 { 0x405844, 1, 0x04, 0x00ffffff },
196 { 0x405850, 1, 0x04, 0x00000000 },
197 { 0x405908, 1, 0x04, 0x00000000 },
198 {}
199};
200
201struct nvc0_graph_init
202nvc0_graph_init_unk80xx[] = {
203 { 0x40803c, 1, 0x04, 0x00000000 },
204 {}
205};
206
207struct nvc0_graph_init
208nvc0_graph_init_gpc[] = {
209 { 0x4184a0, 1, 0x04, 0x00000000 },
210 { 0x418604, 1, 0x04, 0x00000000 },
211 { 0x418680, 1, 0x04, 0x00000000 },
212 { 0x418714, 1, 0x04, 0x80000000 },
213 { 0x418384, 1, 0x04, 0x00000000 },
214 { 0x418814, 3, 0x04, 0x00000000 },
215 { 0x418b04, 1, 0x04, 0x00000000 },
216 { 0x4188c8, 1, 0x04, 0x80000000 },
217 { 0x4188cc, 1, 0x04, 0x00000000 },
218 { 0x4188d0, 1, 0x04, 0x00010000 },
219 { 0x4188d4, 1, 0x04, 0x00000001 },
220 { 0x418910, 1, 0x04, 0x00010001 },
221 { 0x418914, 1, 0x04, 0x00000301 },
222 { 0x418918, 1, 0x04, 0x00800000 },
223 { 0x418980, 1, 0x04, 0x77777770 },
224 { 0x418984, 3, 0x04, 0x77777777 },
225 { 0x418c04, 1, 0x04, 0x00000000 },
226 { 0x418c88, 1, 0x04, 0x00000000 },
227 { 0x418d00, 1, 0x04, 0x00000000 },
228 { 0x418f08, 1, 0x04, 0x00000000 },
229 { 0x418e00, 1, 0x04, 0x00000050 },
230 { 0x418e08, 1, 0x04, 0x00000000 },
231 { 0x41900c, 1, 0x04, 0x00000000 },
232 { 0x419018, 1, 0x04, 0x00000000 },
233 {}
234};
235
236static struct nvc0_graph_init
237nvc0_graph_init_tpc[] = {
238 { 0x419d08, 2, 0x04, 0x00000000 },
239 { 0x419d10, 1, 0x04, 0x00000014 },
240 { 0x419ab0, 1, 0x04, 0x00000000 },
241 { 0x419ab8, 1, 0x04, 0x000000e7 },
242 { 0x419abc, 2, 0x04, 0x00000000 },
243 { 0x41980c, 3, 0x04, 0x00000000 },
244 { 0x419844, 1, 0x04, 0x00000000 },
245 { 0x41984c, 1, 0x04, 0x00005bc5 },
246 { 0x419850, 4, 0x04, 0x00000000 },
247 { 0x419c98, 1, 0x04, 0x00000000 },
248 { 0x419ca8, 1, 0x04, 0x80000000 },
249 { 0x419cb4, 1, 0x04, 0x00000000 },
250 { 0x419cb8, 1, 0x04, 0x00008bf4 },
251 { 0x419cbc, 1, 0x04, 0x28137606 },
252 { 0x419cc0, 2, 0x04, 0x00000000 },
253 { 0x419bd4, 1, 0x04, 0x00800000 },
254 { 0x419bdc, 1, 0x04, 0x00000000 },
255 { 0x419d2c, 1, 0x04, 0x00000000 },
256 { 0x419c0c, 1, 0x04, 0x00000000 },
257 { 0x419e00, 1, 0x04, 0x00000000 },
258 { 0x419ea0, 1, 0x04, 0x00000000 },
259 { 0x419ea4, 1, 0x04, 0x00000100 },
260 { 0x419ea8, 1, 0x04, 0x00001100 },
261 { 0x419eac, 1, 0x04, 0x11100702 },
262 { 0x419eb0, 1, 0x04, 0x00000003 },
263 { 0x419eb4, 4, 0x04, 0x00000000 },
264 { 0x419ec8, 1, 0x04, 0x06060618 },
265 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
266 { 0x419ed4, 1, 0x04, 0x011104f1 },
267 { 0x419edc, 1, 0x04, 0x00000000 },
268 { 0x419f00, 1, 0x04, 0x00000000 },
269 { 0x419f2c, 1, 0x04, 0x00000000 },
270 {}
271};
272
273struct nvc0_graph_init
274nvc0_graph_init_unk88xx[] = {
275 { 0x40880c, 1, 0x04, 0x00000000 },
276 { 0x408910, 9, 0x04, 0x00000000 },
277 { 0x408950, 1, 0x04, 0x00000000 },
278 { 0x408954, 1, 0x04, 0x0000ffff },
279 { 0x408984, 1, 0x04, 0x00000000 },
280 { 0x408988, 1, 0x04, 0x08040201 },
281 { 0x40898c, 1, 0x04, 0x80402010 },
282 {}
283};
284
285struct nvc0_graph_init
286nvc0_graph_tpc_0[] = {
287 { 0x50405c, 1, 0x04, 0x00000001 },
288 {}
289};
290
291void
292nvc0_graph_mmio(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
202{ 293{
203 nv_error(priv, "%06x - done 0x%08x\n", base, 294 for (; init && init->count; init++) {
204 nv_rd32(priv, base + 0x400)); 295 u32 addr = init->addr, i;
205 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 296 for (i = 0; i < init->count; i++) {
206 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), 297 nv_wr32(priv, addr, init->data);
207 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); 298 addr += init->pitch;
208 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 299 }
209 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), 300 }
210 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
211} 301}
212 302
213void 303void
214nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) 304nvc0_graph_icmd(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
215{ 305{
216 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; 306 u32 addr, data;
217 u32 gpc; 307 int i, j;
308
309 nv_wr32(priv, 0x400208, 0x80000000);
310 for (i = 0; init->count; init++, i++) {
311 if (!i || data != init->data) {
312 nv_wr32(priv, 0x400204, init->data);
313 data = init->data;
314 }
218 315
219 nvc0_graph_ctxctl_debug_unit(priv, 0x409000); 316 addr = init->addr;
220 for (gpc = 0; gpc < gpcnr; gpc++) 317 for (j = 0; j < init->count; j++) {
221 nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); 318 nv_wr32(priv, 0x400200, addr);
319 addr += init->pitch;
320 while (nv_rd32(priv, 0x400700) & 0x00000002) {}
321 }
322 }
323 nv_wr32(priv, 0x400208, 0x00000000);
324}
325
326void
327nvc0_graph_mthd(struct nvc0_graph_priv *priv, struct nvc0_graph_mthd *mthds)
328{
329 struct nvc0_graph_mthd *mthd;
330 struct nvc0_graph_init *init;
331 int i = 0, j;
332 u32 data;
333
334 while ((mthd = &mthds[i++]) && (init = mthd->init)) {
335 u32 addr = 0x80000000 | mthd->oclass;
336 for (data = 0; init->count; init++) {
337 if (data != init->data) {
338 nv_wr32(priv, 0x40448c, init->data);
339 data = init->data;
340 }
341
342 addr = (addr & 0x8000ffff) | (init->addr << 14);
343 for (j = 0; j < init->count; j++) {
344 nv_wr32(priv, 0x404488, addr);
345 addr += init->pitch << 14;
346 }
347 }
348 }
349}
350
351u64
352nvc0_graph_units(struct nouveau_graph *graph)
353{
354 struct nvc0_graph_priv *priv = (void *)graph;
355 u64 cfg;
356
357 cfg = (u32)priv->gpc_nr;
358 cfg |= (u32)priv->tpc_total << 8;
359 cfg |= (u64)priv->rop_nr << 32;
360
361 return cfg;
222} 362}
223 363
364static const struct nouveau_enum nve0_sked_error[] = {
365 { 7, "CONSTANT_BUFFER_SIZE" },
366 { 9, "LOCAL_MEMORY_SIZE_POS" },
367 { 10, "LOCAL_MEMORY_SIZE_NEG" },
368 { 11, "WARP_CSTACK_SIZE" },
369 { 12, "TOTAL_TEMP_SIZE" },
370 { 13, "REGISTER_COUNT" },
371 { 18, "TOTAL_THREADS" },
372 { 20, "PROGRAM_OFFSET" },
373 { 21, "SHARED_MEMORY_SIZE" },
374 { 25, "SHARED_CONFIG_TOO_SMALL" },
375 { 26, "TOTAL_REGISTER_COUNT" },
376 {}
377};
378
379static const struct nouveau_enum nvc0_gpc_rop_error[] = {
380 { 1, "RT_PITCH_OVERRUN" },
381 { 4, "RT_WIDTH_OVERRUN" },
382 { 5, "RT_HEIGHT_OVERRUN" },
383 { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
384 { 8, "RT_STORAGE_TYPE_MISMATCH" },
385 { 10, "RT_LINEAR_MISMATCH" },
386 {}
387};
388
224static void 389static void
225nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) 390nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc)
226{ 391{
227 u32 ustat = nv_rd32(priv, 0x409c18); 392 u32 trap[4];
393 int i;
228 394
229 if (ustat & 0x00000001) 395 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
230 nv_error(priv, "CTXCTRL ucode error\n"); 396 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
231 if (ustat & 0x00080000) 397 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
232 nv_error(priv, "CTXCTRL watchdog timeout\n"); 398 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
233 if (ustat & ~0x00080001)
234 nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
235 399
236 nvc0_graph_ctxctl_debug(priv); 400 nv_error(priv, "GPC%d/PROP trap:", gpc);
237 nv_wr32(priv, 0x409c20, ustat); 401 for (i = 0; i <= 29; ++i) {
402 if (!(trap[0] & (1 << i)))
403 continue;
404 pr_cont(" ");
405 nouveau_enum_print(nvc0_gpc_rop_error, i);
406 }
407 pr_cont("\n");
408
409 nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
410 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
411 trap[3] & 0xff);
412 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
238} 413}
239 414
240static const struct nouveau_enum nvc0_mp_warp_error[] = { 415static const struct nouveau_enum nvc0_mp_warp_error[] = {
@@ -283,13 +458,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
283 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); 458 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
284 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); 459 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
285 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 460 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
286 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000001);
287 stat &= ~0x00000001; 461 stat &= ~0x00000001;
288 } 462 }
289 463
290 if (stat & 0x00000002) { 464 if (stat & 0x00000002) {
291 nvc0_graph_trap_mp(priv, gpc, tpc); 465 nvc0_graph_trap_mp(priv, gpc, tpc);
292 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000002);
293 stat &= ~0x00000002; 466 stat &= ~0x00000002;
294 } 467 }
295 468
@@ -297,7 +470,6 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
297 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); 470 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
298 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); 471 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
299 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 472 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
300 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000004);
301 stat &= ~0x00000004; 473 stat &= ~0x00000004;
302 } 474 }
303 475
@@ -305,13 +477,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
305 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); 477 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
306 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); 478 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
307 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 479 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
308 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000008);
309 stat &= ~0x00000008; 480 stat &= ~0x00000008;
310 } 481 }
311 482
312 if (stat) { 483 if (stat) {
313 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); 484 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
314 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), stat);
315 } 485 }
316} 486}
317 487
@@ -322,10 +492,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
322 int tpc; 492 int tpc;
323 493
324 if (stat & 0x00000001) { 494 if (stat & 0x00000001) {
325 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); 495 nvc0_graph_trap_gpc_rop(priv, gpc);
326 nv_error(priv, "GPC%d/PROP: 0x%08x\n", gpc, trap);
327 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
328 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000001);
329 stat &= ~0x00000001; 496 stat &= ~0x00000001;
330 } 497 }
331 498
@@ -333,7 +500,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
333 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); 500 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
334 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); 501 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
335 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); 502 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
336 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000002);
337 stat &= ~0x00000002; 503 stat &= ~0x00000002;
338 } 504 }
339 505
@@ -341,7 +507,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
341 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); 507 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
342 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); 508 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
343 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); 509 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
344 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000004);
345 stat &= ~0x00000004; 510 stat &= ~0x00000004;
346 } 511 }
347 512
@@ -349,7 +514,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
349 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); 514 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
350 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); 515 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
351 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); 516 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
352 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000008);
353 stat &= ~0x00000009; 517 stat &= ~0x00000009;
354 } 518 }
355 519
@@ -364,7 +528,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
364 528
365 if (stat) { 529 if (stat) {
366 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); 530 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
367 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), stat);
368 } 531 }
369} 532}
370 533
@@ -372,7 +535,7 @@ static void
372nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) 535nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
373{ 536{
374 u32 trap = nv_rd32(priv, 0x400108); 537 u32 trap = nv_rd32(priv, 0x400108);
375 int rop, gpc; 538 int rop, gpc, i;
376 539
377 if (trap & 0x00000001) { 540 if (trap & 0x00000001) {
378 u32 stat = nv_rd32(priv, 0x404000); 541 u32 stat = nv_rd32(priv, 0x404000);
@@ -422,6 +585,24 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
422 trap &= ~0x00000080; 585 trap &= ~0x00000080;
423 } 586 }
424 587
588 if (trap & 0x00000100) {
589 u32 stat = nv_rd32(priv, 0x407020);
590
591 nv_error(priv, "SKED:");
592 for (i = 0; i <= 29; ++i) {
593 if (!(stat & (1 << i)))
594 continue;
595 pr_cont(" ");
596 nouveau_enum_print(nve0_sked_error, i);
597 }
598 pr_cont("\n");
599
600 if (stat & 0x3fffffff)
601 nv_wr32(priv, 0x407020, 0x40000000);
602 nv_wr32(priv, 0x400108, 0x00000100);
603 trap &= ~0x00000100;
604 }
605
425 if (trap & 0x01000000) { 606 if (trap & 0x01000000) {
426 u32 stat = nv_rd32(priv, 0x400118); 607 u32 stat = nv_rd32(priv, 0x400118);
427 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { 608 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
@@ -456,6 +637,46 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
456} 637}
457 638
458static void 639static void
640nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
641{
642 nv_error(priv, "%06x - done 0x%08x\n", base,
643 nv_rd32(priv, base + 0x400));
644 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
645 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
646 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
647 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
648 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
649 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
650}
651
652void
653nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
654{
655 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
656 u32 gpc;
657
658 nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
659 for (gpc = 0; gpc < gpcnr; gpc++)
660 nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
661}
662
663static void
664nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
665{
666 u32 ustat = nv_rd32(priv, 0x409c18);
667
668 if (ustat & 0x00000001)
669 nv_error(priv, "CTXCTL ucode error\n");
670 if (ustat & 0x00080000)
671 nv_error(priv, "CTXCTL watchdog timeout\n");
672 if (ustat & ~0x00080001)
673 nv_error(priv, "CTXCTL 0x%08x\n", ustat);
674
675 nvc0_graph_ctxctl_debug(priv);
676 nv_wr32(priv, 0x409c20, ustat);
677}
678
679static void
459nvc0_graph_intr(struct nouveau_subdev *subdev) 680nvc0_graph_intr(struct nouveau_subdev *subdev)
460{ 681{
461 struct nouveau_fifo *pfifo = nouveau_fifo(subdev); 682 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
@@ -531,828 +752,6 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
531 nouveau_engctx_put(engctx); 752 nouveau_engctx_put(engctx);
532} 753}
533 754
534int
535nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
536 struct nvc0_graph_fuc *fuc)
537{
538 struct nouveau_device *device = nv_device(priv);
539 const struct firmware *fw;
540 char f[32];
541 int ret;
542
543 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
544 ret = request_firmware(&fw, f, &device->pdev->dev);
545 if (ret) {
546 snprintf(f, sizeof(f), "nouveau/%s", fwname);
547 ret = request_firmware(&fw, f, &device->pdev->dev);
548 if (ret) {
549 nv_error(priv, "failed to load %s\n", fwname);
550 return ret;
551 }
552 }
553
554 fuc->size = fw->size;
555 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
556 release_firmware(fw);
557 return (fuc->data != NULL) ? 0 : -ENOMEM;
558}
559
560static int
561nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
562 struct nouveau_oclass *oclass, void *data, u32 size,
563 struct nouveau_object **pobject)
564{
565 struct nouveau_device *device = nv_device(parent);
566 struct nvc0_graph_priv *priv;
567 bool enable = device->chipset != 0xd7;
568 int ret, i;
569
570 ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
571 *pobject = nv_object(priv);
572 if (ret)
573 return ret;
574
575 nv_subdev(priv)->unit = 0x18001000;
576 nv_subdev(priv)->intr = nvc0_graph_intr;
577 nv_engine(priv)->cclass = &nvc0_graph_cclass;
578
579 priv->base.units = nvc0_graph_units;
580
581 if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
582 nv_info(priv, "using external firmware\n");
583 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
584 nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
585 nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
586 nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
587 return -EINVAL;
588 priv->firmware = true;
589 }
590
591 switch (nvc0_graph_class(priv)) {
592 case 0x9097:
593 nv_engine(priv)->sclass = nvc0_graph_sclass;
594 break;
595 case 0x9197:
596 nv_engine(priv)->sclass = nvc1_graph_sclass;
597 break;
598 case 0x9297:
599 nv_engine(priv)->sclass = nvc8_graph_sclass;
600 break;
601 }
602
603 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
604 &priv->unk4188b4);
605 if (ret)
606 return ret;
607
608 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
609 &priv->unk4188b8);
610 if (ret)
611 return ret;
612
613 for (i = 0; i < 0x1000; i += 4) {
614 nv_wo32(priv->unk4188b4, i, 0x00000010);
615 nv_wo32(priv->unk4188b8, i, 0x00000010);
616 }
617
618 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
619 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
620 for (i = 0; i < priv->gpc_nr; i++) {
621 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
622 priv->tpc_total += priv->tpc_nr[i];
623 }
624
625 /*XXX: these need figuring out... though it might not even matter */
626 switch (nv_device(priv)->chipset) {
627 case 0xc0:
628 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
629 priv->magic_not_rop_nr = 0x07;
630 } else
631 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
632 priv->magic_not_rop_nr = 0x05;
633 } else
634 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
635 priv->magic_not_rop_nr = 0x06;
636 }
637 break;
638 case 0xc3: /* 450, 4/0/0/0, 2 */
639 priv->magic_not_rop_nr = 0x03;
640 break;
641 case 0xc4: /* 460, 3/4/0/0, 4 */
642 priv->magic_not_rop_nr = 0x01;
643 break;
644 case 0xc1: /* 2/0/0/0, 1 */
645 priv->magic_not_rop_nr = 0x01;
646 break;
647 case 0xc8: /* 4/4/3/4, 5 */
648 priv->magic_not_rop_nr = 0x06;
649 break;
650 case 0xce: /* 4/4/0/0, 4 */
651 priv->magic_not_rop_nr = 0x03;
652 break;
653 case 0xcf: /* 4/0/0/0, 3 */
654 priv->magic_not_rop_nr = 0x03;
655 break;
656 case 0xd9: /* 1/0/0/0, 1 */
657 priv->magic_not_rop_nr = 0x01;
658 break;
659 }
660
661 return 0;
662}
663
664static void
665nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
666{
667 kfree(fuc->data);
668 fuc->data = NULL;
669}
670
671void
672nvc0_graph_dtor(struct nouveau_object *object)
673{
674 struct nvc0_graph_priv *priv = (void *)object;
675
676 kfree(priv->data);
677
678 nvc0_graph_dtor_fw(&priv->fuc409c);
679 nvc0_graph_dtor_fw(&priv->fuc409d);
680 nvc0_graph_dtor_fw(&priv->fuc41ac);
681 nvc0_graph_dtor_fw(&priv->fuc41ad);
682
683 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
684 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
685
686 nouveau_graph_destroy(&priv->base);
687}
688
689static void
690nvc0_graph_init_obj418880(struct nvc0_graph_priv *priv)
691{
692 int i;
693
694 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
695 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
696 for (i = 0; i < 4; i++)
697 nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
698 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
699 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
700}
701
702static void
703nvc0_graph_init_regs(struct nvc0_graph_priv *priv)
704{
705 nv_wr32(priv, 0x400080, 0x003083c2);
706 nv_wr32(priv, 0x400088, 0x00006fe7);
707 nv_wr32(priv, 0x40008c, 0x00000000);
708 nv_wr32(priv, 0x400090, 0x00000030);
709 nv_wr32(priv, 0x40013c, 0x013901f7);
710 nv_wr32(priv, 0x400140, 0x00000100);
711 nv_wr32(priv, 0x400144, 0x00000000);
712 nv_wr32(priv, 0x400148, 0x00000110);
713 nv_wr32(priv, 0x400138, 0x00000000);
714 nv_wr32(priv, 0x400130, 0x00000000);
715 nv_wr32(priv, 0x400134, 0x00000000);
716 nv_wr32(priv, 0x400124, 0x00000002);
717}
718
719static void
720nvc0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
721{
722 nv_wr32(priv, 0x40415c, 0x00000000);
723 nv_wr32(priv, 0x404170, 0x00000000);
724}
725
726static void
727nvc0_graph_init_unk44xx(struct nvc0_graph_priv *priv)
728{
729 nv_wr32(priv, 0x404488, 0x00000000);
730 nv_wr32(priv, 0x40448c, 0x00000000);
731}
732
733static void
734nvc0_graph_init_unk78xx(struct nvc0_graph_priv *priv)
735{
736 nv_wr32(priv, 0x407808, 0x00000000);
737}
738
739static void
740nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
741{
742 nv_wr32(priv, 0x406024, 0x00000000);
743}
744
745static void
746nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
747{
748 switch (nv_device(priv)->chipset) {
749 case 0xd9:
750 case 0xd7:
751 nv_wr32(priv, 0x4064f0, 0x00000000);
752 nv_wr32(priv, 0x4064f4, 0x00000000);
753 nv_wr32(priv, 0x4064f8, 0x00000000);
754 break;
755 case 0xc0:
756 case 0xc3:
757 case 0xc4:
758 case 0xc1:
759 case 0xc8:
760 case 0xce:
761 case 0xcf:
762 break;
763 default:
764 BUG_ON(1);
765 break;
766 }
767}
768
769static void
770nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
771{
772 nv_wr32(priv, 0x405844, 0x00ffffff);
773 nv_wr32(priv, 0x405850, 0x00000000);
774 switch (nv_device(priv)->chipset) {
775 case 0xc3:
776 case 0xc4:
777 case 0xc1:
778 case 0xce:
779 case 0xcf:
780 case 0xd9:
781 case 0xd7:
782 nv_wr32(priv, 0x405900, 0x00002834);
783 break;
784 case 0xc0:
785 case 0xc8:
786 break;
787 default:
788 BUG_ON(1);
789 break;
790 }
791 nv_wr32(priv, 0x405908, 0x00000000);
792 switch (nv_device(priv)->chipset) {
793 case 0xd9:
794 case 0xd7:
795 nv_wr32(priv, 0x405928, 0x00000000);
796 nv_wr32(priv, 0x40592c, 0x00000000);
797 break;
798 case 0xc0:
799 case 0xc3:
800 case 0xc4:
801 case 0xc1:
802 case 0xc8:
803 case 0xce:
804 case 0xcf:
805 break;
806 default:
807 BUG_ON(1);
808 break;
809 }
810}
811
812static void
813nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
814{
815 nv_wr32(priv, 0x40803c, 0x00000000);
816}
817
818static void
819nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
820{
821 switch (nv_device(priv)->chipset) {
822 case 0xd9:
823 case 0xd7:
824 nv_wr32(priv, 0x418408, 0x00000000);
825 break;
826 case 0xc0:
827 case 0xc3:
828 case 0xc4:
829 case 0xc1:
830 case 0xc8:
831 case 0xce:
832 case 0xcf:
833 break;
834 default:
835 BUG_ON(1);
836 break;
837 }
838 nv_wr32(priv, 0x4184a0, 0x00000000);
839 switch (nv_device(priv)->chipset) {
840 case 0xd9:
841 case 0xd7:
842 nv_wr32(priv, 0x4184a4, 0x00000000);
843 nv_wr32(priv, 0x4184a8, 0x00000000);
844 break;
845 case 0xc0:
846 case 0xc3:
847 case 0xc4:
848 case 0xc1:
849 case 0xc8:
850 case 0xce:
851 case 0xcf:
852 break;
853 default:
854 BUG_ON(1);
855 break;
856 }
857 nv_wr32(priv, 0x418604, 0x00000000);
858 nv_wr32(priv, 0x418680, 0x00000000);
859 switch (nv_device(priv)->chipset) {
860 case 0xd9:
861 case 0xd7:
862 case 0xc1:
863 nv_wr32(priv, 0x418714, 0x00000000);
864 break;
865 case 0xc0:
866 case 0xc3:
867 case 0xc4:
868 case 0xc8:
869 case 0xce:
870 case 0xcf:
871 nv_wr32(priv, 0x418714, 0x80000000);
872 break;
873 default:
874 BUG_ON(1);
875 break;
876 }
877 nv_wr32(priv, 0x418384, 0x00000000);
878 nv_wr32(priv, 0x418814, 0x00000000);
879 nv_wr32(priv, 0x418818, 0x00000000);
880 nv_wr32(priv, 0x41881c, 0x00000000);
881 nv_wr32(priv, 0x418b04, 0x00000000);
882 switch (nv_device(priv)->chipset) {
883 case 0xd9:
884 case 0xd7:
885 case 0xc1:
886 case 0xc8:
887 nv_wr32(priv, 0x4188c8, 0x00000000);
888 break;
889 case 0xc0:
890 case 0xc3:
891 case 0xc4:
892 case 0xce:
893 case 0xcf:
894 nv_wr32(priv, 0x4188c8, 0x80000000);
895 break;
896 default:
897 BUG_ON(1);
898 break;
899 }
900 nv_wr32(priv, 0x4188cc, 0x00000000);
901 nv_wr32(priv, 0x4188d0, 0x00010000);
902 nv_wr32(priv, 0x4188d4, 0x00000001);
903 nv_wr32(priv, 0x418910, 0x00010001);
904 nv_wr32(priv, 0x418914, 0x00000301);
905 nv_wr32(priv, 0x418918, 0x00800000);
906 nv_wr32(priv, 0x418980, 0x77777770);
907 nv_wr32(priv, 0x418984, 0x77777777);
908 nv_wr32(priv, 0x418988, 0x77777777);
909 nv_wr32(priv, 0x41898c, 0x77777777);
910 nv_wr32(priv, 0x418c04, 0x00000000);
911 switch (nv_device(priv)->chipset) {
912 case 0xd9:
913 case 0xd7:
914 nv_wr32(priv, 0x418c64, 0x00000000);
915 nv_wr32(priv, 0x418c68, 0x00000000);
916 break;
917 case 0xc0:
918 case 0xc3:
919 case 0xc4:
920 case 0xc1:
921 case 0xc8:
922 case 0xce:
923 case 0xcf:
924 break;
925 default:
926 BUG_ON(1);
927 break;
928 }
929 nv_wr32(priv, 0x418c88, 0x00000000);
930 switch (nv_device(priv)->chipset) {
931 case 0xd9:
932 case 0xd7:
933 nv_wr32(priv, 0x418cb4, 0x00000000);
934 nv_wr32(priv, 0x418cb8, 0x00000000);
935 break;
936 case 0xc0:
937 case 0xc3:
938 case 0xc4:
939 case 0xc1:
940 case 0xc8:
941 case 0xce:
942 case 0xcf:
943 break;
944 default:
945 BUG_ON(1);
946 break;
947 }
948 nv_wr32(priv, 0x418d00, 0x00000000);
949 switch (nv_device(priv)->chipset) {
950 case 0xd9:
951 case 0xd7:
952 nv_wr32(priv, 0x418d28, 0x00000000);
953 nv_wr32(priv, 0x418d2c, 0x00000000);
954 nv_wr32(priv, 0x418f00, 0x00000000);
955 break;
956 case 0xc0:
957 case 0xc3:
958 case 0xc4:
959 case 0xc1:
960 case 0xc8:
961 case 0xce:
962 case 0xcf:
963 break;
964 default:
965 BUG_ON(1);
966 break;
967 }
968 nv_wr32(priv, 0x418f08, 0x00000000);
969 switch (nv_device(priv)->chipset) {
970 case 0xd9:
971 case 0xd7:
972 nv_wr32(priv, 0x418f20, 0x00000000);
973 nv_wr32(priv, 0x418f24, 0x00000000);
974 /*fall-through*/
975 case 0xc1:
976 nv_wr32(priv, 0x418e00, 0x00000003);
977 break;
978 case 0xc0:
979 case 0xc3:
980 case 0xc4:
981 case 0xc8:
982 case 0xce:
983 case 0xcf:
984 nv_wr32(priv, 0x418e00, 0x00000050);
985 break;
986 default:
987 BUG_ON(1);
988 break;
989 }
990 nv_wr32(priv, 0x418e08, 0x00000000);
991 switch (nv_device(priv)->chipset) {
992 case 0xd9:
993 case 0xd7:
994 nv_wr32(priv, 0x418e1c, 0x00000000);
995 nv_wr32(priv, 0x418e20, 0x00000000);
996 break;
997 case 0xc0:
998 case 0xc3:
999 case 0xc4:
1000 case 0xc1:
1001 case 0xc8:
1002 case 0xce:
1003 case 0xcf:
1004 break;
1005 default:
1006 BUG_ON(1);
1007 break;
1008 }
1009 nv_wr32(priv, 0x41900c, 0x00000000);
1010 nv_wr32(priv, 0x419018, 0x00000000);
1011}
1012
1013static void
1014nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1015{
1016 nv_wr32(priv, 0x419d08, 0x00000000);
1017 nv_wr32(priv, 0x419d0c, 0x00000000);
1018 nv_wr32(priv, 0x419d10, 0x00000014);
1019 nv_wr32(priv, 0x419ab0, 0x00000000);
1020 switch (nv_device(priv)->chipset) {
1021 case 0xc3:
1022 case 0xc4:
1023 case 0xc1:
1024 case 0xce:
1025 case 0xcf:
1026 case 0xd9:
1027 case 0xd7:
1028 nv_wr32(priv, 0x419ac8, 0x00000000);
1029 break;
1030 case 0xc0:
1031 case 0xc8:
1032 break;
1033 default:
1034 BUG_ON(1);
1035 break;
1036 }
1037 nv_wr32(priv, 0x419ab8, 0x000000e7);
1038 nv_wr32(priv, 0x419abc, 0x00000000);
1039 nv_wr32(priv, 0x419ac0, 0x00000000);
1040 switch (nv_device(priv)->chipset) {
1041 case 0xd9:
1042 case 0xd7:
1043 nv_wr32(priv, 0x419ab4, 0x00000000);
1044 nv_wr32(priv, 0x41980c, 0x00000010);
1045 break;
1046 case 0xc0:
1047 case 0xc3:
1048 case 0xc4:
1049 case 0xc1:
1050 case 0xc8:
1051 case 0xce:
1052 case 0xcf:
1053 nv_wr32(priv, 0x41980c, 0x00000000);
1054 break;
1055 default:
1056 BUG_ON(1);
1057 break;
1058 }
1059 nv_wr32(priv, 0x419810, 0x00000000);
1060 switch (nv_device(priv)->chipset) {
1061 case 0xd9:
1062 case 0xd7:
1063 case 0xc1:
1064 nv_wr32(priv, 0x419814, 0x00000004);
1065 break;
1066 case 0xc0:
1067 case 0xc3:
1068 case 0xc4:
1069 case 0xc8:
1070 case 0xce:
1071 case 0xcf:
1072 nv_wr32(priv, 0x419814, 0x00000000);
1073 break;
1074 default:
1075 BUG_ON(1);
1076 break;
1077 }
1078 nv_wr32(priv, 0x419844, 0x00000000);
1079 switch (nv_device(priv)->chipset) {
1080 case 0xd9:
1081 case 0xd7:
1082 nv_wr32(priv, 0x41984c, 0x0000a918);
1083 break;
1084 case 0xc0:
1085 case 0xc3:
1086 case 0xc4:
1087 case 0xc1:
1088 case 0xc8:
1089 case 0xce:
1090 case 0xcf:
1091 nv_wr32(priv, 0x41984c, 0x00005bc5);
1092 break;
1093 default:
1094 BUG_ON(1);
1095 break;
1096 }
1097 nv_wr32(priv, 0x419850, 0x00000000);
1098 nv_wr32(priv, 0x419854, 0x00000000);
1099 nv_wr32(priv, 0x419858, 0x00000000);
1100 nv_wr32(priv, 0x41985c, 0x00000000);
1101 switch (nv_device(priv)->chipset) {
1102 case 0xc3:
1103 case 0xc4:
1104 case 0xc1:
1105 case 0xce:
1106 case 0xcf:
1107 case 0xd9:
1108 case 0xd7:
1109 nv_wr32(priv, 0x419880, 0x00000002);
1110 break;
1111 case 0xc0:
1112 case 0xc8:
1113 break;
1114 default:
1115 BUG_ON(1);
1116 break;
1117 }
1118 nv_wr32(priv, 0x419c98, 0x00000000);
1119 nv_wr32(priv, 0x419ca8, 0x80000000);
1120 nv_wr32(priv, 0x419cb4, 0x00000000);
1121 nv_wr32(priv, 0x419cb8, 0x00008bf4);
1122 nv_wr32(priv, 0x419cbc, 0x28137606);
1123 nv_wr32(priv, 0x419cc0, 0x00000000);
1124 nv_wr32(priv, 0x419cc4, 0x00000000);
1125 nv_wr32(priv, 0x419bd4, 0x00800000);
1126 nv_wr32(priv, 0x419bdc, 0x00000000);
1127 switch (nv_device(priv)->chipset) {
1128 case 0xd9:
1129 case 0xd7:
1130 nv_wr32(priv, 0x419bf8, 0x00000000);
1131 nv_wr32(priv, 0x419bfc, 0x00000000);
1132 break;
1133 case 0xc0:
1134 case 0xc3:
1135 case 0xc4:
1136 case 0xc1:
1137 case 0xc8:
1138 case 0xce:
1139 case 0xcf:
1140 break;
1141 default:
1142 BUG_ON(1);
1143 break;
1144 }
1145 nv_wr32(priv, 0x419d2c, 0x00000000);
1146 switch (nv_device(priv)->chipset) {
1147 case 0xd9:
1148 case 0xd7:
1149 nv_wr32(priv, 0x419d48, 0x00000000);
1150 nv_wr32(priv, 0x419d4c, 0x00000000);
1151 break;
1152 case 0xc0:
1153 case 0xc3:
1154 case 0xc4:
1155 case 0xc1:
1156 case 0xc8:
1157 case 0xce:
1158 case 0xcf:
1159 break;
1160 default:
1161 BUG_ON(1);
1162 break;
1163 }
1164 nv_wr32(priv, 0x419c0c, 0x00000000);
1165 nv_wr32(priv, 0x419e00, 0x00000000);
1166 nv_wr32(priv, 0x419ea0, 0x00000000);
1167 nv_wr32(priv, 0x419ea4, 0x00000100);
1168 switch (nv_device(priv)->chipset) {
1169 case 0xd9:
1170 case 0xd7:
1171 nv_wr32(priv, 0x419ea8, 0x02001100);
1172 break;
1173 case 0xc0:
1174 case 0xc3:
1175 case 0xc4:
1176 case 0xc1:
1177 case 0xc8:
1178 case 0xce:
1179 case 0xcf:
1180 nv_wr32(priv, 0x419ea8, 0x00001100);
1181 break;
1182 default:
1183 BUG_ON(1);
1184 break;
1185 }
1186
1187 switch (nv_device(priv)->chipset) {
1188 case 0xc8:
1189 nv_wr32(priv, 0x419eac, 0x11100f02);
1190 break;
1191 case 0xc0:
1192 case 0xc3:
1193 case 0xc4:
1194 case 0xc1:
1195 case 0xce:
1196 case 0xcf:
1197 case 0xd9:
1198 case 0xd7:
1199 nv_wr32(priv, 0x419eac, 0x11100702);
1200 break;
1201 default:
1202 BUG_ON(1);
1203 break;
1204 }
1205 nv_wr32(priv, 0x419eb0, 0x00000003);
1206 nv_wr32(priv, 0x419eb4, 0x00000000);
1207 nv_wr32(priv, 0x419eb8, 0x00000000);
1208 nv_wr32(priv, 0x419ebc, 0x00000000);
1209 nv_wr32(priv, 0x419ec0, 0x00000000);
1210 switch (nv_device(priv)->chipset) {
1211 case 0xc3:
1212 case 0xc4:
1213 case 0xc1:
1214 case 0xce:
1215 case 0xcf:
1216 case 0xd9:
1217 case 0xd7:
1218 nv_wr32(priv, 0x419ec8, 0x0e063818);
1219 nv_wr32(priv, 0x419ecc, 0x0e060e06);
1220 nv_wr32(priv, 0x419ed0, 0x00003818);
1221 break;
1222 case 0xc0:
1223 case 0xc8:
1224 nv_wr32(priv, 0x419ec8, 0x06060618);
1225 nv_wr32(priv, 0x419ed0, 0x0eff0e38);
1226 break;
1227 default:
1228 BUG_ON(1);
1229 break;
1230 }
1231 nv_wr32(priv, 0x419ed4, 0x011104f1);
1232 nv_wr32(priv, 0x419edc, 0x00000000);
1233 nv_wr32(priv, 0x419f00, 0x00000000);
1234 nv_wr32(priv, 0x419f2c, 0x00000000);
1235}
1236
1237static void
1238nvc0_graph_init_unk88xx(struct nvc0_graph_priv *priv)
1239{
1240 nv_wr32(priv, 0x40880c, 0x00000000);
1241 nv_wr32(priv, 0x408910, 0x00000000);
1242 nv_wr32(priv, 0x408914, 0x00000000);
1243 nv_wr32(priv, 0x408918, 0x00000000);
1244 nv_wr32(priv, 0x40891c, 0x00000000);
1245 nv_wr32(priv, 0x408920, 0x00000000);
1246 nv_wr32(priv, 0x408924, 0x00000000);
1247 nv_wr32(priv, 0x408928, 0x00000000);
1248 nv_wr32(priv, 0x40892c, 0x00000000);
1249 nv_wr32(priv, 0x408930, 0x00000000);
1250 nv_wr32(priv, 0x408950, 0x00000000);
1251 nv_wr32(priv, 0x408954, 0x0000ffff);
1252 nv_wr32(priv, 0x408984, 0x00000000);
1253 nv_wr32(priv, 0x408988, 0x08040201);
1254 nv_wr32(priv, 0x40898c, 0x80402010);
1255}
1256
1257static void
1258nvc0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
1259{
1260 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
1261 u32 data[TPC_MAX / 8];
1262 u8 tpcnr[GPC_MAX];
1263 int i, gpc, tpc;
1264
1265 nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
1266
1267 /*
1268 * TP ROP UNKVAL(magic_not_rop_nr)
1269 * 450: 4/0/0/0 2 3
1270 * 460: 3/4/0/0 4 1
1271 * 465: 3/4/4/0 4 7
1272 * 470: 3/3/4/4 5 5
1273 * 480: 3/4/4/4 6 6
1274 */
1275
1276 memset(data, 0x00, sizeof(data));
1277 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1278 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
1279 do {
1280 gpc = (gpc + 1) % priv->gpc_nr;
1281 } while (!tpcnr[gpc]);
1282 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
1283
1284 data[i / 8] |= tpc << ((i % 8) * 4);
1285 }
1286
1287 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
1288 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
1289 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
1290 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
1291
1292 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1293 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
1294 priv->tpc_nr[gpc]);
1295 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
1296 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
1297 }
1298
1299 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
1300 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
1301}
1302
1303static void
1304nvc0_graph_init_units(struct nvc0_graph_priv *priv)
1305{
1306 nv_wr32(priv, 0x409c24, 0x000f0000);
1307 nv_wr32(priv, 0x404000, 0xc0000000); /* DISPATCH */
1308 nv_wr32(priv, 0x404600, 0xc0000000); /* M2MF */
1309 nv_wr32(priv, 0x408030, 0xc0000000);
1310 nv_wr32(priv, 0x40601c, 0xc0000000);
1311 nv_wr32(priv, 0x404490, 0xc0000000); /* MACRO */
1312 nv_wr32(priv, 0x406018, 0xc0000000);
1313 nv_wr32(priv, 0x405840, 0xc0000000);
1314 nv_wr32(priv, 0x405844, 0x00ffffff);
1315 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
1316 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
1317}
1318
1319static void
1320nvc0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
1321{
1322 int gpc, tpc;
1323
1324 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1325 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1326 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1327 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1328 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1329 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
1330 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
1331 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
1332 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
1333 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
1334 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
1335 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
1336 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
1337 }
1338 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
1339 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
1340 }
1341}
1342
1343static void
1344nvc0_graph_init_rop(struct nvc0_graph_priv *priv)
1345{
1346 int rop;
1347
1348 for (rop = 0; rop < priv->rop_nr; rop++) {
1349 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
1350 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
1351 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
1352 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
1353 }
1354}
1355
1356void 755void
1357nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, 756nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
1358 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) 757 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
@@ -1371,9 +770,46 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
1371 } 770 }
1372} 771}
1373 772
1374static int 773static void
774nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
775 struct nvc0_graph_init *init,
776 u32 falcon, u32 starstar, u32 base)
777{
778 u32 addr = init->addr;
779 u32 next = addr;
780 u32 star, temp;
781
782 nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
783 star = nv_rd32(priv, falcon + 0x01c4);
784 temp = nv_rd32(priv, falcon + 0x01c4);
785 if (temp > star)
786 star = temp;
787 nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
788
789 do {
790 if (init->addr != next) {
791 while (addr < next) {
792 u32 nr = min((int)(next - addr) / 4, 32);
793 nv_wr32(priv, falcon + 0x01c4,
794 ((nr - 1) << 26) | (addr - base));
795 addr += nr * 4;
796 star += 4;
797 }
798 addr = next = init->addr;
799 }
800 next += init->count * 4;
801 } while ((init++)->count);
802
803 nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
804 nv_wr32(priv, falcon + 0x01c4, star);
805}
806
807int
1375nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) 808nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
1376{ 809{
810 struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
811 struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
812 struct nvc0_graph_init *init;
1377 u32 r000260; 813 u32 r000260;
1378 int i; 814 int i;
1379 815
@@ -1424,6 +860,38 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
1424 return -EBUSY; 860 return -EBUSY;
1425 } 861 }
1426 862
863 if (nv_device(priv)->chipset >= 0xe0) {
864 nv_wr32(priv, 0x409800, 0x00000000);
865 nv_wr32(priv, 0x409500, 0x00000001);
866 nv_wr32(priv, 0x409504, 0x00000030);
867 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
868 nv_error(priv, "fuc09 req 0x30 timeout\n");
869 return -EBUSY;
870 }
871
872 nv_wr32(priv, 0x409810, 0xb00095c8);
873 nv_wr32(priv, 0x409800, 0x00000000);
874 nv_wr32(priv, 0x409500, 0x00000001);
875 nv_wr32(priv, 0x409504, 0x00000031);
876 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
877 nv_error(priv, "fuc09 req 0x31 timeout\n");
878 return -EBUSY;
879 }
880
881 nv_wr32(priv, 0x409810, 0x00080420);
882 nv_wr32(priv, 0x409800, 0x00000000);
883 nv_wr32(priv, 0x409500, 0x00000001);
884 nv_wr32(priv, 0x409504, 0x00000032);
885 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
886 nv_error(priv, "fuc09 req 0x32 timeout\n");
887 return -EBUSY;
888 }
889
890 nv_wr32(priv, 0x409614, 0x00000070);
891 nv_wr32(priv, 0x409614, 0x00000770);
892 nv_wr32(priv, 0x40802c, 0x00000001);
893 }
894
1427 if (priv->data == NULL) { 895 if (priv->data == NULL) {
1428 int ret = nvc0_grctx_generate(priv); 896 int ret = nvc0_grctx_generate(priv);
1429 if (ret) { 897 if (ret) {
@@ -1438,31 +906,41 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
1438 /* load HUB microcode */ 906 /* load HUB microcode */
1439 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); 907 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
1440 nv_wr32(priv, 0x4091c0, 0x01000000); 908 nv_wr32(priv, 0x4091c0, 0x01000000);
1441 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++) 909 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
1442 nv_wr32(priv, 0x4091c4, nvc0_grhub_data[i]); 910 nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
1443 911
1444 nv_wr32(priv, 0x409180, 0x01000000); 912 nv_wr32(priv, 0x409180, 0x01000000);
1445 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) { 913 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
1446 if ((i & 0x3f) == 0) 914 if ((i & 0x3f) == 0)
1447 nv_wr32(priv, 0x409188, i >> 6); 915 nv_wr32(priv, 0x409188, i >> 6);
1448 nv_wr32(priv, 0x409184, nvc0_grhub_code[i]); 916 nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
917 }
918
919 for (i = 0; (init = cclass->hub[i]); i++) {
920 nvc0_graph_init_csdata(priv, init, 0x409000, 0x000, 0x000000);
1449 } 921 }
1450 922
1451 /* load GPC microcode */ 923 /* load GPC microcode */
1452 nv_wr32(priv, 0x41a1c0, 0x01000000); 924 nv_wr32(priv, 0x41a1c0, 0x01000000);
1453 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++) 925 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
1454 nv_wr32(priv, 0x41a1c4, nvc0_grgpc_data[i]); 926 nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
1455 927
1456 nv_wr32(priv, 0x41a180, 0x01000000); 928 nv_wr32(priv, 0x41a180, 0x01000000);
1457 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) { 929 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
1458 if ((i & 0x3f) == 0) 930 if ((i & 0x3f) == 0)
1459 nv_wr32(priv, 0x41a188, i >> 6); 931 nv_wr32(priv, 0x41a188, i >> 6);
1460 nv_wr32(priv, 0x41a184, nvc0_grgpc_code[i]); 932 nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
1461 } 933 }
1462 nv_wr32(priv, 0x000260, r000260); 934 nv_wr32(priv, 0x000260, r000260);
1463 935
936 if ((init = cclass->gpc[0]))
937 nvc0_graph_init_csdata(priv, init, 0x41a000, 0x000, 0x418000);
938 if ((init = cclass->gpc[2]))
939 nvc0_graph_init_csdata(priv, init, 0x41a000, 0x004, 0x419800);
940 if ((init = cclass->gpc[3]))
941 nvc0_graph_init_csdata(priv, init, 0x41a000, 0x008, 0x41be00);
942
1464 /* start HUB ucode running, it'll init the GPCs */ 943 /* start HUB ucode running, it'll init the GPCs */
1465 nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
1466 nv_wr32(priv, 0x40910c, 0x00000000); 944 nv_wr32(priv, 0x40910c, 0x00000000);
1467 nv_wr32(priv, 0x409100, 0x00000002); 945 nv_wr32(priv, 0x409100, 0x00000002);
1468 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { 946 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
@@ -1483,38 +961,104 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
1483 return 0; 961 return 0;
1484} 962}
1485 963
1486static int 964int
1487nvc0_graph_init(struct nouveau_object *object) 965nvc0_graph_init(struct nouveau_object *object)
1488{ 966{
967 struct nvc0_graph_oclass *oclass = (void *)object->oclass;
1489 struct nvc0_graph_priv *priv = (void *)object; 968 struct nvc0_graph_priv *priv = (void *)object;
1490 int ret; 969 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
970 u32 data[TPC_MAX / 8] = {};
971 u8 tpcnr[GPC_MAX];
972 int gpc, tpc, rop;
973 int ret, i;
1491 974
1492 ret = nouveau_graph_init(&priv->base); 975 ret = nouveau_graph_init(&priv->base);
1493 if (ret) 976 if (ret)
1494 return ret; 977 return ret;
1495 978
1496 nvc0_graph_init_obj418880(priv); 979 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
1497 nvc0_graph_init_regs(priv); 980 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
1498 nvc0_graph_init_unk40xx(priv); 981 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
1499 nvc0_graph_init_unk44xx(priv); 982 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
1500 nvc0_graph_init_unk78xx(priv); 983 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
1501 nvc0_graph_init_unk60xx(priv); 984 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
1502 nvc0_graph_init_unk64xx(priv); 985 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
1503 nvc0_graph_init_unk58xx(priv); 986 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
1504 nvc0_graph_init_unk80xx(priv); 987
1505 nvc0_graph_init_gpc(priv); 988 for (i = 0; oclass->mmio[i]; i++)
1506 nvc0_graph_init_tpc(priv); 989 nvc0_graph_mmio(priv, oclass->mmio[i]);
1507 nvc0_graph_init_unk88xx(priv); 990
1508 nvc0_graph_init_gpc_0(priv); 991 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1509 /*nvc0_graph_init_unitplemented_c242(priv);*/ 992 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
993 do {
994 gpc = (gpc + 1) % priv->gpc_nr;
995 } while (!tpcnr[gpc]);
996 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
997
998 data[i / 8] |= tpc << ((i % 8) * 4);
999 }
1000
1001 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
1002 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
1003 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
1004 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
1005
1006 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1007 nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
1008 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
1009 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
1010 priv->tpc_total);
1011 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
1012 }
1013
1014 if (nv_device(priv)->chipset != 0xd7)
1015 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
1016 else
1017 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
1018
1019 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
1510 1020
1511 nv_wr32(priv, 0x400500, 0x00010001); 1021 nv_wr32(priv, 0x400500, 0x00010001);
1022
1512 nv_wr32(priv, 0x400100, 0xffffffff); 1023 nv_wr32(priv, 0x400100, 0xffffffff);
1513 nv_wr32(priv, 0x40013c, 0xffffffff); 1024 nv_wr32(priv, 0x40013c, 0xffffffff);
1514 1025
1515 nvc0_graph_init_units(priv); 1026 nv_wr32(priv, 0x409c24, 0x000f0000);
1516 nvc0_graph_init_gpc_1(priv); 1027 nv_wr32(priv, 0x404000, 0xc0000000);
1517 nvc0_graph_init_rop(priv); 1028 nv_wr32(priv, 0x404600, 0xc0000000);
1029 nv_wr32(priv, 0x408030, 0xc0000000);
1030 nv_wr32(priv, 0x40601c, 0xc0000000);
1031 nv_wr32(priv, 0x404490, 0xc0000000);
1032 nv_wr32(priv, 0x406018, 0xc0000000);
1033 nv_wr32(priv, 0x405840, 0xc0000000);
1034 nv_wr32(priv, 0x405844, 0x00ffffff);
1035 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
1036 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
1037
1038 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1039 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1040 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1041 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1042 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1043 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
1044 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
1045 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
1046 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
1047 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
1048 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
1049 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
1050 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
1051 }
1052 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
1053 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
1054 }
1055
1056 for (rop = 0; rop < priv->rop_nr; rop++) {
1057 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
1058 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
1059 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
1060 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
1061 }
1518 1062
1519 nv_wr32(priv, 0x400108, 0xffffffff); 1063 nv_wr32(priv, 0x400108, 0xffffffff);
1520 nv_wr32(priv, 0x400138, 0xffffffff); 1064 nv_wr32(priv, 0x400138, 0xffffffff);
@@ -1522,22 +1066,205 @@ nvc0_graph_init(struct nouveau_object *object)
1522 nv_wr32(priv, 0x400130, 0xffffffff); 1066 nv_wr32(priv, 0x400130, 0xffffffff);
1523 nv_wr32(priv, 0x40011c, 0xffffffff); 1067 nv_wr32(priv, 0x40011c, 0xffffffff);
1524 nv_wr32(priv, 0x400134, 0xffffffff); 1068 nv_wr32(priv, 0x400134, 0xffffffff);
1069
1525 nv_wr32(priv, 0x400054, 0x34ce3464); 1070 nv_wr32(priv, 0x400054, 0x34ce3464);
1071 return nvc0_graph_init_ctxctl(priv);
1072}
1073
1074static void
1075nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
1076{
1077 kfree(fuc->data);
1078 fuc->data = NULL;
1079}
1080
1081int
1082nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
1083 struct nvc0_graph_fuc *fuc)
1084{
1085 struct nouveau_device *device = nv_device(priv);
1086 const struct firmware *fw;
1087 char f[32];
1088 int ret;
1089
1090 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1091 ret = request_firmware(&fw, f, &device->pdev->dev);
1092 if (ret) {
1093 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1094 ret = request_firmware(&fw, f, &device->pdev->dev);
1095 if (ret) {
1096 nv_error(priv, "failed to load %s\n", fwname);
1097 return ret;
1098 }
1099 }
1100
1101 fuc->size = fw->size;
1102 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1103 release_firmware(fw);
1104 return (fuc->data != NULL) ? 0 : -ENOMEM;
1105}
1106
1107void
1108nvc0_graph_dtor(struct nouveau_object *object)
1109{
1110 struct nvc0_graph_priv *priv = (void *)object;
1111
1112 kfree(priv->data);
1113
1114 nvc0_graph_dtor_fw(&priv->fuc409c);
1115 nvc0_graph_dtor_fw(&priv->fuc409d);
1116 nvc0_graph_dtor_fw(&priv->fuc41ac);
1117 nvc0_graph_dtor_fw(&priv->fuc41ad);
1118
1119 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
1120 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
1121
1122 nouveau_graph_destroy(&priv->base);
1123}
1124
1125int
1126nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1127 struct nouveau_oclass *bclass, void *data, u32 size,
1128 struct nouveau_object **pobject)
1129{
1130 struct nvc0_graph_oclass *oclass = (void *)bclass;
1131 struct nouveau_device *device = nv_device(parent);
1132 struct nvc0_graph_priv *priv;
1133 int ret, i;
1134
1135 ret = nouveau_graph_create(parent, engine, bclass,
1136 (oclass->fecs.ucode != NULL), &priv);
1137 *pobject = nv_object(priv);
1138 if (ret)
1139 return ret;
1140
1141 nv_subdev(priv)->unit = 0x18001000;
1142 nv_subdev(priv)->intr = nvc0_graph_intr;
1143
1144 priv->base.units = nvc0_graph_units;
1526 1145
1527 ret = nvc0_graph_init_ctxctl(priv); 1146 if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
1147 nv_info(priv, "using external firmware\n");
1148 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
1149 nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
1150 nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
1151 nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
1152 return -EINVAL;
1153 priv->firmware = true;
1154 }
1155
1156 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
1157 &priv->unk4188b4);
1158 if (ret)
1159 return ret;
1160
1161 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
1162 &priv->unk4188b8);
1528 if (ret) 1163 if (ret)
1529 return ret; 1164 return ret;
1530 1165
1166 for (i = 0; i < 0x1000; i += 4) {
1167 nv_wo32(priv->unk4188b4, i, 0x00000010);
1168 nv_wo32(priv->unk4188b8, i, 0x00000010);
1169 }
1170
1171 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
1172 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
1173 for (i = 0; i < priv->gpc_nr; i++) {
1174 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
1175 priv->tpc_total += priv->tpc_nr[i];
1176 }
1177
1178 /*XXX: these need figuring out... though it might not even matter */
1179 switch (nv_device(priv)->chipset) {
1180 case 0xc0:
1181 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
1182 priv->magic_not_rop_nr = 0x07;
1183 } else
1184 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
1185 priv->magic_not_rop_nr = 0x05;
1186 } else
1187 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
1188 priv->magic_not_rop_nr = 0x06;
1189 }
1190 break;
1191 case 0xc3: /* 450, 4/0/0/0, 2 */
1192 priv->magic_not_rop_nr = 0x03;
1193 break;
1194 case 0xc4: /* 460, 3/4/0/0, 4 */
1195 priv->magic_not_rop_nr = 0x01;
1196 break;
1197 case 0xc1: /* 2/0/0/0, 1 */
1198 priv->magic_not_rop_nr = 0x01;
1199 break;
1200 case 0xc8: /* 4/4/3/4, 5 */
1201 priv->magic_not_rop_nr = 0x06;
1202 break;
1203 case 0xce: /* 4/4/0/0, 4 */
1204 priv->magic_not_rop_nr = 0x03;
1205 break;
1206 case 0xcf: /* 4/0/0/0, 3 */
1207 priv->magic_not_rop_nr = 0x03;
1208 break;
1209 case 0xd7:
1210 case 0xd9: /* 1/0/0/0, 1 */
1211 priv->magic_not_rop_nr = 0x01;
1212 break;
1213 }
1214
1215 nv_engine(priv)->cclass = *oclass->cclass;
1216 nv_engine(priv)->sclass = oclass->sclass;
1531 return 0; 1217 return 0;
1532} 1218}
1533 1219
1534struct nouveau_oclass 1220struct nvc0_graph_init *
1535nvc0_graph_oclass = { 1221nvc0_graph_init_mmio[] = {
1536 .handle = NV_ENGINE(GR, 0xc0), 1222 nvc0_graph_init_regs,
1537 .ofuncs = &(struct nouveau_ofuncs) { 1223 nvc0_graph_init_unk40xx,
1224 nvc0_graph_init_unk44xx,
1225 nvc0_graph_init_unk78xx,
1226 nvc0_graph_init_unk60xx,
1227 nvc0_graph_init_unk58xx,
1228 nvc0_graph_init_unk80xx,
1229 nvc0_graph_init_gpc,
1230 nvc0_graph_init_tpc,
1231 nvc0_graph_init_unk88xx,
1232 nvc0_graph_tpc_0,
1233 NULL
1234};
1235
1236#include "fuc/hubnvc0.fuc.h"
1237
1238struct nvc0_graph_ucode
1239nvc0_graph_fecs_ucode = {
1240 .code.data = nvc0_grhub_code,
1241 .code.size = sizeof(nvc0_grhub_code),
1242 .data.data = nvc0_grhub_data,
1243 .data.size = sizeof(nvc0_grhub_data),
1244};
1245
1246#include "fuc/gpcnvc0.fuc.h"
1247
1248struct nvc0_graph_ucode
1249nvc0_graph_gpccs_ucode = {
1250 .code.data = nvc0_grgpc_code,
1251 .code.size = sizeof(nvc0_grgpc_code),
1252 .data.data = nvc0_grgpc_data,
1253 .data.size = sizeof(nvc0_grgpc_data),
1254};
1255
1256struct nouveau_oclass *
1257nvc0_graph_oclass = &(struct nvc0_graph_oclass) {
1258 .base.handle = NV_ENGINE(GR, 0xc0),
1259 .base.ofuncs = &(struct nouveau_ofuncs) {
1538 .ctor = nvc0_graph_ctor, 1260 .ctor = nvc0_graph_ctor,
1539 .dtor = nvc0_graph_dtor, 1261 .dtor = nvc0_graph_dtor,
1540 .init = nvc0_graph_init, 1262 .init = nvc0_graph_init,
1541 .fini = _nouveau_graph_fini, 1263 .fini = _nouveau_graph_fini,
1542 }, 1264 },
1543}; 1265 .cclass = &nvc0_grctx_oclass,
1266 .sclass = nvc0_graph_sclass,
1267 .mmio = nvc0_graph_init_mmio,
1268 .fecs.ucode = &nvc0_graph_fecs_ucode,
1269 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
1270}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index af7212d96f3f..ea17a80ad7fc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -102,76 +102,187 @@ struct nvc0_graph_chan {
102 } data[4]; 102 } data[4];
103}; 103};
104 104
105static inline u32 105int nvc0_grctx_generate(struct nvc0_graph_priv *);
106nvc0_graph_class(void *obj) 106
107{ 107int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
108 struct nouveau_device *device = nv_device(obj); 108 struct nouveau_oclass *, void *, u32,
109 109 struct nouveau_object **);
110 switch (device->chipset) { 110void nvc0_graph_context_dtor(struct nouveau_object *);
111 case 0xc0: 111
112 case 0xc3: 112void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
113 case 0xc4: 113
114 case 0xce: /* guess, mmio trace shows only 0x9097 state */ 114u64 nvc0_graph_units(struct nouveau_graph *);
115 case 0xcf: /* guess, mmio trace shows only 0x9097 state */ 115int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *,
116 return 0x9097; 116 struct nouveau_oclass *, void *data, u32 size,
117 case 0xc1: 117 struct nouveau_object **);
118 return 0x9197; 118void nvc0_graph_dtor(struct nouveau_object *);
119 case 0xc8: 119int nvc0_graph_init(struct nouveau_object *);
120 case 0xd9: 120int nve4_graph_init(struct nouveau_object *);
121 case 0xd7: 121
122 return 0x9297; 122extern struct nouveau_oclass nvc0_graph_sclass[];
123 case 0xe4: 123
124 case 0xe7: 124extern struct nouveau_oclass nvc8_graph_sclass[];
125 case 0xe6: 125
126 return 0xa097; 126struct nvc0_graph_init {
127 case 0xf0: 127 u32 addr;
128 return 0xa197; 128 u8 count;
129 default: 129 u8 pitch;
130 return 0; 130 u32 data;
131 } 131};
132} 132
133 133struct nvc0_graph_mthd {
134void nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data); 134 u16 oclass;
135 135 struct nvc0_graph_init *init;
136static inline void 136};
137nv_mthd(struct nvc0_graph_priv *priv, u32 class, u32 mthd, u32 data)
138{
139 nv_wr32(priv, 0x40448c, data);
140 nv_wr32(priv, 0x404488, 0x80000000 | (mthd << 14) | class);
141}
142 137
143struct nvc0_grctx { 138struct nvc0_grctx {
144 struct nvc0_graph_priv *priv; 139 struct nvc0_graph_priv *priv;
145 struct nvc0_graph_data *data; 140 struct nvc0_graph_data *data;
146 struct nvc0_graph_mmio *mmio; 141 struct nvc0_graph_mmio *mmio;
147 struct nouveau_gpuobj *chan;
148 int buffer_nr; 142 int buffer_nr;
149 u64 buffer[4]; 143 u64 buffer[4];
150 u64 addr; 144 u64 addr;
151}; 145};
152 146
147struct nvc0_grctx_oclass {
148 struct nouveau_oclass base;
149 /* main context generation function */
150 void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
151 /* context-specific modify-on-first-load list generation function */
152 void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
153 void (*unkn)(struct nvc0_graph_priv *);
154 /* mmio context data */
155 struct nvc0_graph_init **hub;
156 struct nvc0_graph_init **gpc;
157 /* indirect context data, generated with icmds/mthds */
158 struct nvc0_graph_init *icmd;
159 struct nvc0_graph_mthd *mthd;
160};
161
162struct nvc0_graph_ucode {
163 struct nvc0_graph_fuc code;
164 struct nvc0_graph_fuc data;
165};
166
167extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode;
168extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode;
169
170struct nvc0_graph_oclass {
171 struct nouveau_oclass base;
172 struct nouveau_oclass **cclass;
173 struct nouveau_oclass *sclass;
174 struct nvc0_graph_init **mmio;
175 struct {
176 struct nvc0_graph_ucode *ucode;
177 } fecs;
178 struct {
179 struct nvc0_graph_ucode *ucode;
180 } gpccs;
181};
182
183void nvc0_graph_mmio(struct nvc0_graph_priv *, struct nvc0_graph_init *);
184void nvc0_graph_icmd(struct nvc0_graph_priv *, struct nvc0_graph_init *);
185void nvc0_graph_mthd(struct nvc0_graph_priv *, struct nvc0_graph_mthd *);
186int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
187
188extern struct nvc0_graph_init nvc0_graph_init_regs[];
189extern struct nvc0_graph_init nvc0_graph_init_unk40xx[];
190extern struct nvc0_graph_init nvc0_graph_init_unk44xx[];
191extern struct nvc0_graph_init nvc0_graph_init_unk78xx[];
192extern struct nvc0_graph_init nvc0_graph_init_unk60xx[];
193extern struct nvc0_graph_init nvc0_graph_init_unk58xx[];
194extern struct nvc0_graph_init nvc0_graph_init_unk80xx[];
195extern struct nvc0_graph_init nvc0_graph_init_gpc[];
196extern struct nvc0_graph_init nvc0_graph_init_unk88xx[];
197extern struct nvc0_graph_init nvc0_graph_tpc_0[];
198
199extern struct nvc0_graph_init nvc3_graph_init_unk58xx[];
200
201extern struct nvc0_graph_init nvd9_graph_init_unk58xx[];
202extern struct nvc0_graph_init nvd9_graph_init_unk64xx[];
203
204extern struct nvc0_graph_init nve4_graph_init_regs[];
205extern struct nvc0_graph_init nve4_graph_init_unk[];
206extern struct nvc0_graph_init nve4_graph_init_unk88xx[];
207
153int nvc0_grctx_generate(struct nvc0_graph_priv *); 208int nvc0_grctx_generate(struct nvc0_graph_priv *);
154int nvc0_grctx_init(struct nvc0_graph_priv *, struct nvc0_grctx *); 209void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
155void nvc0_grctx_data(struct nvc0_grctx *, u32, u32, u32); 210void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
156void nvc0_grctx_mmio(struct nvc0_grctx *, u32, u32, u32, u32); 211void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
157int nvc0_grctx_fini(struct nvc0_grctx *); 212void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
213void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
214void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
215void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
216void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
217void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
158 218
159int nve0_grctx_generate(struct nvc0_graph_priv *); 219extern struct nouveau_oclass *nvc0_grctx_oclass;
220extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
221extern struct nvc0_graph_init nvc0_grctx_init_base[];
222extern struct nvc0_graph_init nvc0_grctx_init_unk40xx[];
223extern struct nvc0_graph_init nvc0_grctx_init_unk44xx[];
224extern struct nvc0_graph_init nvc0_grctx_init_unk46xx[];
225extern struct nvc0_graph_init nvc0_grctx_init_unk47xx[];
226extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[];
227extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[];
228extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[];
229extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[];
230extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[];
231extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
232extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
233extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
234extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
160 235
161#define mmio_data(s,a,p) nvc0_grctx_data(&info, (s), (a), (p)) 236extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
162#define mmio_list(r,d,s,b) nvc0_grctx_mmio(&info, (r), (d), (s), (b)) 237extern struct nvc0_graph_init nvc0_grctx_init_902d[];
238extern struct nvc0_graph_init nvc0_grctx_init_9039[];
239extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
240extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
163 241
164void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); 242void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
165int nvc0_graph_ctor_fw(struct nvc0_graph_priv *, const char *, 243void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
166 struct nvc0_graph_fuc *); 244extern struct nouveau_oclass *nvc1_grctx_oclass;
167void nvc0_graph_dtor(struct nouveau_object *); 245extern struct nvc0_graph_init nvc1_grctx_init_9097[];
168void nvc0_graph_init_fw(struct nvc0_graph_priv *, u32 base, 246
169 struct nvc0_graph_fuc *, struct nvc0_graph_fuc *); 247extern struct nouveau_oclass *nvc3_grctx_oclass;
170int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, 248
171 struct nouveau_oclass *, void *, u32, 249extern struct nouveau_oclass *nvc8_grctx_oclass;
172 struct nouveau_object **); 250extern struct nvc0_graph_init nvc8_grctx_init_9197[];
173void nvc0_graph_context_dtor(struct nouveau_object *); 251extern struct nvc0_graph_init nvc8_grctx_init_9297[];
252
253extern struct nouveau_oclass *nvd7_grctx_oclass;
254
255extern struct nouveau_oclass *nvd9_grctx_oclass;
256extern struct nvc0_graph_init nvd9_grctx_init_rop[];
257extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
258
259void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
260void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
261extern struct nouveau_oclass *nve4_grctx_oclass;
262extern struct nvc0_graph_init nve4_grctx_init_unk46xx[];
263extern struct nvc0_graph_init nve4_grctx_init_unk47xx[];
264extern struct nvc0_graph_init nve4_grctx_init_unk58xx[];
265extern struct nvc0_graph_init nve4_grctx_init_unk80xx[];
266extern struct nvc0_graph_init nve4_grctx_init_unk90xx[];
267
268extern struct nouveau_oclass *nvf0_grctx_oclass;
269
270#define mmio_data(s,a,p) do { \
271 info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \
272 info->addr = info->buffer[info->buffer_nr++] + (s); \
273 info->data->size = (s); \
274 info->data->align = (a); \
275 info->data->access = (p); \
276 info->data++; \
277} while(0)
174 278
175u64 nvc0_graph_units(struct nouveau_graph *); 279#define mmio_list(r,d,s,b) do { \
280 info->mmio->addr = (r); \
281 info->mmio->data = (d); \
282 info->mmio->shift = (s); \
283 info->mmio->buffer = (b); \
284 info->mmio++; \
285 nv_wr32(priv, (r), (d) | ((s) ? (info->buffer[(b)] >> (s)) : 0)); \
286} while(0)
176 287
177#endif 288#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
new file mode 100644
index 000000000000..bc4a469b86cb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31static struct nouveau_oclass
32nvc1_graph_sclass[] = {
33 { 0x902d, &nouveau_object_ofuncs },
34 { 0x9039, &nouveau_object_ofuncs },
35 { 0x9097, &nouveau_object_ofuncs },
36 { 0x90c0, &nouveau_object_ofuncs },
37 { 0x9197, &nouveau_object_ofuncs },
38 {}
39};
40
41/*******************************************************************************
42 * PGRAPH engine/subdev functions
43 ******************************************************************************/
44
45static struct nvc0_graph_init
46nvc1_graph_init_gpc[] = {
47 { 0x4184a0, 1, 0x04, 0x00000000 },
48 { 0x418604, 1, 0x04, 0x00000000 },
49 { 0x418680, 1, 0x04, 0x00000000 },
50 { 0x418714, 1, 0x04, 0x00000000 },
51 { 0x418384, 1, 0x04, 0x00000000 },
52 { 0x418814, 3, 0x04, 0x00000000 },
53 { 0x418b04, 1, 0x04, 0x00000000 },
54 { 0x4188c8, 2, 0x04, 0x00000000 },
55 { 0x4188d0, 1, 0x04, 0x00010000 },
56 { 0x4188d4, 1, 0x04, 0x00000001 },
57 { 0x418910, 1, 0x04, 0x00010001 },
58 { 0x418914, 1, 0x04, 0x00000301 },
59 { 0x418918, 1, 0x04, 0x00800000 },
60 { 0x418980, 1, 0x04, 0x77777770 },
61 { 0x418984, 3, 0x04, 0x77777777 },
62 { 0x418c04, 1, 0x04, 0x00000000 },
63 { 0x418c88, 1, 0x04, 0x00000000 },
64 { 0x418d00, 1, 0x04, 0x00000000 },
65 { 0x418f08, 1, 0x04, 0x00000000 },
66 { 0x418e00, 1, 0x04, 0x00000003 },
67 { 0x418e08, 1, 0x04, 0x00000000 },
68 { 0x41900c, 1, 0x04, 0x00000000 },
69 { 0x419018, 1, 0x04, 0x00000000 },
70 {}
71};
72
73static struct nvc0_graph_init
74nvc1_graph_init_tpc[] = {
75 { 0x419d08, 2, 0x04, 0x00000000 },
76 { 0x419d10, 1, 0x04, 0x00000014 },
77 { 0x419ab0, 1, 0x04, 0x00000000 },
78 { 0x419ac8, 1, 0x04, 0x00000000 },
79 { 0x419ab8, 1, 0x04, 0x000000e7 },
80 { 0x419abc, 2, 0x04, 0x00000000 },
81 { 0x41980c, 2, 0x04, 0x00000000 },
82 { 0x419814, 1, 0x04, 0x00000004 },
83 { 0x419844, 1, 0x04, 0x00000000 },
84 { 0x41984c, 1, 0x04, 0x00005bc5 },
85 { 0x419850, 4, 0x04, 0x00000000 },
86 { 0x419880, 1, 0x04, 0x00000002 },
87 { 0x419c98, 1, 0x04, 0x00000000 },
88 { 0x419ca8, 1, 0x04, 0x80000000 },
89 { 0x419cb4, 1, 0x04, 0x00000000 },
90 { 0x419cb8, 1, 0x04, 0x00008bf4 },
91 { 0x419cbc, 1, 0x04, 0x28137606 },
92 { 0x419cc0, 2, 0x04, 0x00000000 },
93 { 0x419bd4, 1, 0x04, 0x00800000 },
94 { 0x419bdc, 1, 0x04, 0x00000000 },
95 { 0x419d2c, 1, 0x04, 0x00000000 },
96 { 0x419c0c, 1, 0x04, 0x00000000 },
97 { 0x419e00, 1, 0x04, 0x00000000 },
98 { 0x419ea0, 1, 0x04, 0x00000000 },
99 { 0x419ea4, 1, 0x04, 0x00000100 },
100 { 0x419ea8, 1, 0x04, 0x00001100 },
101 { 0x419eac, 1, 0x04, 0x11100702 },
102 { 0x419eb0, 1, 0x04, 0x00000003 },
103 { 0x419eb4, 4, 0x04, 0x00000000 },
104 { 0x419ec8, 1, 0x04, 0x0e063818 },
105 { 0x419ecc, 1, 0x04, 0x0e060e06 },
106 { 0x419ed0, 1, 0x04, 0x00003818 },
107 { 0x419ed4, 1, 0x04, 0x011104f1 },
108 { 0x419edc, 1, 0x04, 0x00000000 },
109 { 0x419f00, 1, 0x04, 0x00000000 },
110 { 0x419f2c, 1, 0x04, 0x00000000 },
111 {}
112};
113
114struct nvc0_graph_init *
115nvc1_graph_init_mmio[] = {
116 nvc0_graph_init_regs,
117 nvc0_graph_init_unk40xx,
118 nvc0_graph_init_unk44xx,
119 nvc0_graph_init_unk78xx,
120 nvc0_graph_init_unk60xx,
121 nvc3_graph_init_unk58xx,
122 nvc0_graph_init_unk80xx,
123 nvc1_graph_init_gpc,
124 nvc1_graph_init_tpc,
125 nvc0_graph_init_unk88xx,
126 nvc0_graph_tpc_0,
127 NULL
128};
129
130struct nouveau_oclass *
131nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
132 .base.handle = NV_ENGINE(GR, 0xc1),
133 .base.ofuncs = &(struct nouveau_ofuncs) {
134 .ctor = nvc0_graph_ctor,
135 .dtor = nvc0_graph_dtor,
136 .init = nvc0_graph_init,
137 .fini = _nouveau_graph_fini,
138 },
139 .cclass = &nvc1_grctx_oclass,
140 .sclass = nvc1_graph_sclass,
141 .mmio = nvc1_graph_init_mmio,
142 .fecs.ucode = &nvc0_graph_fecs_ucode,
143 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
144}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
new file mode 100644
index 000000000000..d44b3b3ee800
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
@@ -0,0 +1,110 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * PGRAPH engine/subdev functions
29 ******************************************************************************/
30
31struct nvc0_graph_init
32nvc3_graph_init_unk58xx[] = {
33 { 0x405844, 1, 0x04, 0x00ffffff },
34 { 0x405850, 1, 0x04, 0x00000000 },
35 { 0x405900, 1, 0x04, 0x00002834 },
36 { 0x405908, 1, 0x04, 0x00000000 },
37 {}
38};
39
40static struct nvc0_graph_init
41nvc3_graph_init_tpc[] = {
42 { 0x419d08, 2, 0x04, 0x00000000 },
43 { 0x419d10, 1, 0x04, 0x00000014 },
44 { 0x419ab0, 1, 0x04, 0x00000000 },
45 { 0x419ac8, 1, 0x04, 0x00000000 },
46 { 0x419ab8, 1, 0x04, 0x000000e7 },
47 { 0x419abc, 2, 0x04, 0x00000000 },
48 { 0x41980c, 3, 0x04, 0x00000000 },
49 { 0x419844, 1, 0x04, 0x00000000 },
50 { 0x41984c, 1, 0x04, 0x00005bc5 },
51 { 0x419850, 4, 0x04, 0x00000000 },
52 { 0x419880, 1, 0x04, 0x00000002 },
53 { 0x419c98, 1, 0x04, 0x00000000 },
54 { 0x419ca8, 1, 0x04, 0x80000000 },
55 { 0x419cb4, 1, 0x04, 0x00000000 },
56 { 0x419cb8, 1, 0x04, 0x00008bf4 },
57 { 0x419cbc, 1, 0x04, 0x28137606 },
58 { 0x419cc0, 2, 0x04, 0x00000000 },
59 { 0x419bd4, 1, 0x04, 0x00800000 },
60 { 0x419bdc, 1, 0x04, 0x00000000 },
61 { 0x419d2c, 1, 0x04, 0x00000000 },
62 { 0x419c0c, 1, 0x04, 0x00000000 },
63 { 0x419e00, 1, 0x04, 0x00000000 },
64 { 0x419ea0, 1, 0x04, 0x00000000 },
65 { 0x419ea4, 1, 0x04, 0x00000100 },
66 { 0x419ea8, 1, 0x04, 0x00001100 },
67 { 0x419eac, 1, 0x04, 0x11100702 },
68 { 0x419eb0, 1, 0x04, 0x00000003 },
69 { 0x419eb4, 4, 0x04, 0x00000000 },
70 { 0x419ec8, 1, 0x04, 0x0e063818 },
71 { 0x419ecc, 1, 0x04, 0x0e060e06 },
72 { 0x419ed0, 1, 0x04, 0x00003818 },
73 { 0x419ed4, 1, 0x04, 0x011104f1 },
74 { 0x419edc, 1, 0x04, 0x00000000 },
75 { 0x419f00, 1, 0x04, 0x00000000 },
76 { 0x419f2c, 1, 0x04, 0x00000000 },
77 {}
78};
79
80static struct nvc0_graph_init *
81nvc3_graph_init_mmio[] = {
82 nvc0_graph_init_regs,
83 nvc0_graph_init_unk40xx,
84 nvc0_graph_init_unk44xx,
85 nvc0_graph_init_unk78xx,
86 nvc0_graph_init_unk60xx,
87 nvc3_graph_init_unk58xx,
88 nvc0_graph_init_unk80xx,
89 nvc0_graph_init_gpc,
90 nvc3_graph_init_tpc,
91 nvc0_graph_init_unk88xx,
92 nvc0_graph_tpc_0,
93 NULL
94};
95
96struct nouveau_oclass *
97nvc3_graph_oclass = &(struct nvc0_graph_oclass) {
98 .base.handle = NV_ENGINE(GR, 0xc3),
99 .base.ofuncs = &(struct nouveau_ofuncs) {
100 .ctor = nvc0_graph_ctor,
101 .dtor = nvc0_graph_dtor,
102 .init = nvc0_graph_init,
103 .fini = _nouveau_graph_fini,
104 },
105 .cclass = &nvc3_grctx_oclass,
106 .sclass = nvc0_graph_sclass,
107 .mmio = nvc3_graph_init_mmio,
108 .fecs.ucode = &nvc0_graph_fecs_ucode,
109 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
110}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
new file mode 100644
index 000000000000..02845e567314
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
@@ -0,0 +1,141 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31struct nouveau_oclass
32nvc8_graph_sclass[] = {
33 { 0x902d, &nouveau_object_ofuncs },
34 { 0x9039, &nouveau_object_ofuncs },
35 { 0x9097, &nouveau_object_ofuncs },
36 { 0x90c0, &nouveau_object_ofuncs },
37 { 0x9197, &nouveau_object_ofuncs },
38 { 0x9297, &nouveau_object_ofuncs },
39 {}
40};
41
42/*******************************************************************************
43 * PGRAPH engine/subdev functions
44 ******************************************************************************/
45
46static struct nvc0_graph_init
47nvc8_graph_init_gpc[] = {
48 { 0x4184a0, 1, 0x04, 0x00000000 },
49 { 0x418604, 1, 0x04, 0x00000000 },
50 { 0x418680, 1, 0x04, 0x00000000 },
51 { 0x418714, 1, 0x04, 0x80000000 },
52 { 0x418384, 1, 0x04, 0x00000000 },
53 { 0x418814, 3, 0x04, 0x00000000 },
54 { 0x418b04, 1, 0x04, 0x00000000 },
55 { 0x4188c8, 2, 0x04, 0x00000000 },
56 { 0x4188d0, 1, 0x04, 0x00010000 },
57 { 0x4188d4, 1, 0x04, 0x00000001 },
58 { 0x418910, 1, 0x04, 0x00010001 },
59 { 0x418914, 1, 0x04, 0x00000301 },
60 { 0x418918, 1, 0x04, 0x00800000 },
61 { 0x418980, 1, 0x04, 0x77777770 },
62 { 0x418984, 3, 0x04, 0x77777777 },
63 { 0x418c04, 1, 0x04, 0x00000000 },
64 { 0x418c88, 1, 0x04, 0x00000000 },
65 { 0x418d00, 1, 0x04, 0x00000000 },
66 { 0x418f08, 1, 0x04, 0x00000000 },
67 { 0x418e00, 1, 0x04, 0x00000050 },
68 { 0x418e08, 1, 0x04, 0x00000000 },
69 { 0x41900c, 1, 0x04, 0x00000000 },
70 { 0x419018, 1, 0x04, 0x00000000 },
71 {}
72};
73
74static struct nvc0_graph_init
75nvc8_graph_init_tpc[] = {
76 { 0x419d08, 2, 0x04, 0x00000000 },
77 { 0x419d10, 1, 0x04, 0x00000014 },
78 { 0x419ab0, 1, 0x04, 0x00000000 },
79 { 0x419ab8, 1, 0x04, 0x000000e7 },
80 { 0x419abc, 2, 0x04, 0x00000000 },
81 { 0x41980c, 3, 0x04, 0x00000000 },
82 { 0x419844, 1, 0x04, 0x00000000 },
83 { 0x41984c, 1, 0x04, 0x00005bc5 },
84 { 0x419850, 4, 0x04, 0x00000000 },
85 { 0x419c98, 1, 0x04, 0x00000000 },
86 { 0x419ca8, 1, 0x04, 0x80000000 },
87 { 0x419cb4, 1, 0x04, 0x00000000 },
88 { 0x419cb8, 1, 0x04, 0x00008bf4 },
89 { 0x419cbc, 1, 0x04, 0x28137606 },
90 { 0x419cc0, 2, 0x04, 0x00000000 },
91 { 0x419bd4, 1, 0x04, 0x00800000 },
92 { 0x419bdc, 1, 0x04, 0x00000000 },
93 { 0x419d2c, 1, 0x04, 0x00000000 },
94 { 0x419c0c, 1, 0x04, 0x00000000 },
95 { 0x419e00, 1, 0x04, 0x00000000 },
96 { 0x419ea0, 1, 0x04, 0x00000000 },
97 { 0x419ea4, 1, 0x04, 0x00000100 },
98 { 0x419ea8, 1, 0x04, 0x00001100 },
99 { 0x419eac, 1, 0x04, 0x11100f02 },
100 { 0x419eb0, 1, 0x04, 0x00000003 },
101 { 0x419eb4, 4, 0x04, 0x00000000 },
102 { 0x419ec8, 1, 0x04, 0x06060618 },
103 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
104 { 0x419ed4, 1, 0x04, 0x011104f1 },
105 { 0x419edc, 1, 0x04, 0x00000000 },
106 { 0x419f00, 1, 0x04, 0x00000000 },
107 { 0x419f2c, 1, 0x04, 0x00000000 },
108 {}
109};
110
111static struct nvc0_graph_init *
112nvc8_graph_init_mmio[] = {
113 nvc0_graph_init_regs,
114 nvc0_graph_init_unk40xx,
115 nvc0_graph_init_unk44xx,
116 nvc0_graph_init_unk78xx,
117 nvc0_graph_init_unk60xx,
118 nvc0_graph_init_unk58xx,
119 nvc0_graph_init_unk80xx,
120 nvc8_graph_init_gpc,
121 nvc8_graph_init_tpc,
122 nvc0_graph_init_unk88xx,
123 nvc0_graph_tpc_0,
124 NULL
125};
126
127struct nouveau_oclass *
128nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
129 .base.handle = NV_ENGINE(GR, 0xc8),
130 .base.ofuncs = &(struct nouveau_ofuncs) {
131 .ctor = nvc0_graph_ctor,
132 .dtor = nvc0_graph_dtor,
133 .init = nvc0_graph_init,
134 .fini = _nouveau_graph_fini,
135 },
136 .cclass = &nvc8_grctx_oclass,
137 .sclass = nvc8_graph_sclass,
138 .mmio = nvc8_graph_init_mmio,
139 .fecs.ucode = &nvc0_graph_fecs_ucode,
140 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
141}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
new file mode 100644
index 000000000000..5052d7ab4d72
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
@@ -0,0 +1,167 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * PGRAPH engine/subdev functions
29 ******************************************************************************/
30
31#include "fuc/hubnvd7.fuc.h"
32
33struct nvc0_graph_ucode
34nvd7_graph_fecs_ucode = {
35 .code.data = nvd7_grhub_code,
36 .code.size = sizeof(nvd7_grhub_code),
37 .data.data = nvd7_grhub_data,
38 .data.size = sizeof(nvd7_grhub_data),
39};
40
41#include "fuc/gpcnvd7.fuc.h"
42
43struct nvc0_graph_ucode
44nvd7_graph_gpccs_ucode = {
45 .code.data = nvd7_grgpc_code,
46 .code.size = sizeof(nvd7_grgpc_code),
47 .data.data = nvd7_grgpc_data,
48 .data.size = sizeof(nvd7_grgpc_data),
49};
50
51static struct nvc0_graph_init
52nvd7_graph_init_gpc[] = {
53 { 0x418408, 1, 0x04, 0x00000000 },
54 { 0x4184a0, 1, 0x04, 0x00000000 },
55 { 0x4184a4, 2, 0x04, 0x00000000 },
56 { 0x418604, 1, 0x04, 0x00000000 },
57 { 0x418680, 1, 0x04, 0x00000000 },
58 { 0x418714, 1, 0x04, 0x00000000 },
59 { 0x418384, 1, 0x04, 0x00000000 },
60 { 0x418814, 3, 0x04, 0x00000000 },
61 { 0x418b04, 1, 0x04, 0x00000000 },
62 { 0x4188c8, 2, 0x04, 0x00000000 },
63 { 0x4188d0, 1, 0x04, 0x00010000 },
64 { 0x4188d4, 1, 0x04, 0x00000001 },
65 { 0x418910, 1, 0x04, 0x00010001 },
66 { 0x418914, 1, 0x04, 0x00000301 },
67 { 0x418918, 1, 0x04, 0x00800000 },
68 { 0x418980, 1, 0x04, 0x77777770 },
69 { 0x418984, 3, 0x04, 0x77777777 },
70 { 0x418c04, 1, 0x04, 0x00000000 },
71 { 0x418c64, 1, 0x04, 0x00000000 },
72 { 0x418c68, 1, 0x04, 0x00000000 },
73 { 0x418c88, 1, 0x04, 0x00000000 },
74 { 0x418cb4, 2, 0x04, 0x00000000 },
75 { 0x418d00, 1, 0x04, 0x00000000 },
76 { 0x418d28, 1, 0x04, 0x00000000 },
77 { 0x418f00, 1, 0x04, 0x00000000 },
78 { 0x418f08, 1, 0x04, 0x00000000 },
79 { 0x418f20, 2, 0x04, 0x00000000 },
80 { 0x418e00, 1, 0x04, 0x00000003 },
81 { 0x418e08, 1, 0x04, 0x00000000 },
82 { 0x418e1c, 1, 0x04, 0x00000000 },
83 { 0x418e20, 1, 0x04, 0x00000000 },
84 { 0x41900c, 1, 0x04, 0x00000000 },
85 { 0x419018, 1, 0x04, 0x00000000 },
86 {}
87};
88
89static struct nvc0_graph_init
90nvd7_graph_init_tpc[] = {
91 { 0x419d08, 2, 0x04, 0x00000000 },
92 { 0x419d10, 1, 0x04, 0x00000014 },
93 { 0x419ab0, 1, 0x04, 0x00000000 },
94 { 0x419ac8, 1, 0x04, 0x00000000 },
95 { 0x419ab8, 1, 0x04, 0x000000e7 },
96 { 0x419abc, 2, 0x04, 0x00000000 },
97 { 0x419ab4, 1, 0x04, 0x00000000 },
98 { 0x41980c, 1, 0x04, 0x00000010 },
99 { 0x419844, 1, 0x04, 0x00000000 },
100 { 0x41984c, 1, 0x04, 0x00005bc8 },
101 { 0x419850, 2, 0x04, 0x00000000 },
102 { 0x419c98, 1, 0x04, 0x00000000 },
103 { 0x419ca8, 1, 0x04, 0x80000000 },
104 { 0x419cb4, 1, 0x04, 0x00000000 },
105 { 0x419cb8, 1, 0x04, 0x00008bf4 },
106 { 0x419cbc, 1, 0x04, 0x28137606 },
107 { 0x419cc0, 2, 0x04, 0x00000000 },
108 { 0x419c0c, 1, 0x04, 0x00000000 },
109 { 0x419e00, 1, 0x04, 0x00000000 },
110 { 0x419ea0, 1, 0x04, 0x00000000 },
111 { 0x419ea4, 1, 0x04, 0x00000100 },
112 { 0x419ea8, 1, 0x04, 0x02001100 },
113 { 0x419eac, 1, 0x04, 0x11100702 },
114 { 0x419eb0, 1, 0x04, 0x00000003 },
115 { 0x419eb4, 4, 0x04, 0x00000000 },
116 { 0x419ec8, 1, 0x04, 0x0e063818 },
117 { 0x419ecc, 1, 0x04, 0x0e060e06 },
118 { 0x419ed0, 1, 0x04, 0x00003818 },
119 { 0x419ed4, 1, 0x04, 0x011104f1 },
120 { 0x419edc, 1, 0x04, 0x00000000 },
121 { 0x419f00, 1, 0x04, 0x00000000 },
122 { 0x419f2c, 1, 0x04, 0x00000000 },
123 {}
124};
125
126static struct nvc0_graph_init
127nvd7_graph_init_tpc_0[] = {
128 { 0x40402c, 1, 0x04, 0x00000000 },
129 { 0x4040f0, 1, 0x04, 0x00000000 },
130 { 0x404174, 1, 0x04, 0x00000000 },
131 { 0x503018, 1, 0x04, 0x00000001 },
132 {}
133};
134
135static struct nvc0_graph_init *
136nvd7_graph_init_mmio[] = {
137 nvc0_graph_init_regs,
138 nvc0_graph_init_unk40xx,
139 nvc0_graph_init_unk44xx,
140 nvc0_graph_init_unk78xx,
141 nvc0_graph_init_unk60xx,
142 nvd9_graph_init_unk64xx,
143 nvd9_graph_init_unk58xx,
144 nvc0_graph_init_unk80xx,
145 nvd7_graph_init_gpc,
146 nvd7_graph_init_tpc,
147 nve4_graph_init_unk,
148 nvc0_graph_init_unk88xx,
149 nvd7_graph_init_tpc_0,
150 NULL
151};
152
153struct nouveau_oclass *
154nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
155 .base.handle = NV_ENGINE(GR, 0xd7),
156 .base.ofuncs = &(struct nouveau_ofuncs) {
157 .ctor = nvc0_graph_ctor,
158 .dtor = nvc0_graph_dtor,
159 .init = nvc0_graph_init,
160 .fini = _nouveau_graph_fini,
161 },
162 .cclass = &nvd7_grctx_oclass,
163 .sclass = nvc8_graph_sclass,
164 .mmio = nvd7_graph_init_mmio,
165 .fecs.ucode = &nvd7_graph_fecs_ucode,
166 .gpccs.ucode = &nvd7_graph_gpccs_ucode,
167}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
new file mode 100644
index 000000000000..652098e0df3f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
@@ -0,0 +1,165 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * PGRAPH engine/subdev functions
29 ******************************************************************************/
30
31struct nvc0_graph_init
32nvd9_graph_init_unk64xx[] = {
33 { 0x4064f0, 3, 0x04, 0x00000000 },
34 {}
35};
36
37struct nvc0_graph_init
38nvd9_graph_init_unk58xx[] = {
39 { 0x405844, 1, 0x04, 0x00ffffff },
40 { 0x405850, 1, 0x04, 0x00000000 },
41 { 0x405900, 1, 0x04, 0x00002834 },
42 { 0x405908, 1, 0x04, 0x00000000 },
43 { 0x405928, 1, 0x04, 0x00000000 },
44 { 0x40592c, 1, 0x04, 0x00000000 },
45 {}
46};
47
48static struct nvc0_graph_init
49nvd9_graph_init_gpc[] = {
50 { 0x418408, 1, 0x04, 0x00000000 },
51 { 0x4184a0, 1, 0x04, 0x00000000 },
52 { 0x4184a4, 2, 0x04, 0x00000000 },
53 { 0x418604, 1, 0x04, 0x00000000 },
54 { 0x418680, 1, 0x04, 0x00000000 },
55 { 0x418714, 1, 0x04, 0x00000000 },
56 { 0x418384, 1, 0x04, 0x00000000 },
57 { 0x418814, 3, 0x04, 0x00000000 },
58 { 0x418b04, 1, 0x04, 0x00000000 },
59 { 0x4188c8, 2, 0x04, 0x00000000 },
60 { 0x4188d0, 1, 0x04, 0x00010000 },
61 { 0x4188d4, 1, 0x04, 0x00000001 },
62 { 0x418910, 1, 0x04, 0x00010001 },
63 { 0x418914, 1, 0x04, 0x00000301 },
64 { 0x418918, 1, 0x04, 0x00800000 },
65 { 0x418980, 1, 0x04, 0x77777770 },
66 { 0x418984, 3, 0x04, 0x77777777 },
67 { 0x418c04, 1, 0x04, 0x00000000 },
68 { 0x418c64, 1, 0x04, 0x00000000 },
69 { 0x418c68, 1, 0x04, 0x00000000 },
70 { 0x418c88, 1, 0x04, 0x00000000 },
71 { 0x418cb4, 2, 0x04, 0x00000000 },
72 { 0x418d00, 1, 0x04, 0x00000000 },
73 { 0x418d28, 1, 0x04, 0x00000000 },
74 { 0x418d2c, 1, 0x04, 0x00000000 },
75 { 0x418f00, 1, 0x04, 0x00000000 },
76 { 0x418f08, 1, 0x04, 0x00000000 },
77 { 0x418f20, 2, 0x04, 0x00000000 },
78 { 0x418e00, 1, 0x04, 0x00000003 },
79 { 0x418e08, 1, 0x04, 0x00000000 },
80 { 0x418e1c, 1, 0x04, 0x00000000 },
81 { 0x418e20, 1, 0x04, 0x00000000 },
82 { 0x41900c, 1, 0x04, 0x00000000 },
83 { 0x419018, 1, 0x04, 0x00000000 },
84 {}
85};
86
87static struct nvc0_graph_init
88nvd9_graph_init_tpc[] = {
89 { 0x419d08, 2, 0x04, 0x00000000 },
90 { 0x419d10, 1, 0x04, 0x00000014 },
91 { 0x419ab0, 1, 0x04, 0x00000000 },
92 { 0x419ac8, 1, 0x04, 0x00000000 },
93 { 0x419ab8, 1, 0x04, 0x000000e7 },
94 { 0x419abc, 2, 0x04, 0x00000000 },
95 { 0x419ab4, 1, 0x04, 0x00000000 },
96 { 0x41980c, 1, 0x04, 0x00000010 },
97 { 0x419810, 1, 0x04, 0x00000000 },
98 { 0x419814, 1, 0x04, 0x00000004 },
99 { 0x419844, 1, 0x04, 0x00000000 },
100 { 0x41984c, 1, 0x04, 0x0000a918 },
101 { 0x419850, 4, 0x04, 0x00000000 },
102 { 0x419880, 1, 0x04, 0x00000002 },
103 { 0x419c98, 1, 0x04, 0x00000000 },
104 { 0x419ca8, 1, 0x04, 0x80000000 },
105 { 0x419cb4, 1, 0x04, 0x00000000 },
106 { 0x419cb8, 1, 0x04, 0x00008bf4 },
107 { 0x419cbc, 1, 0x04, 0x28137606 },
108 { 0x419cc0, 2, 0x04, 0x00000000 },
109 { 0x419bd4, 1, 0x04, 0x00800000 },
110 { 0x419bdc, 1, 0x04, 0x00000000 },
111 { 0x419bf8, 1, 0x04, 0x00000000 },
112 { 0x419bfc, 1, 0x04, 0x00000000 },
113 { 0x419d2c, 1, 0x04, 0x00000000 },
114 { 0x419d48, 1, 0x04, 0x00000000 },
115 { 0x419d4c, 1, 0x04, 0x00000000 },
116 { 0x419c0c, 1, 0x04, 0x00000000 },
117 { 0x419e00, 1, 0x04, 0x00000000 },
118 { 0x419ea0, 1, 0x04, 0x00000000 },
119 { 0x419ea4, 1, 0x04, 0x00000100 },
120 { 0x419ea8, 1, 0x04, 0x02001100 },
121 { 0x419eac, 1, 0x04, 0x11100702 },
122 { 0x419eb0, 1, 0x04, 0x00000003 },
123 { 0x419eb4, 4, 0x04, 0x00000000 },
124 { 0x419ec8, 1, 0x04, 0x0e063818 },
125 { 0x419ecc, 1, 0x04, 0x0e060e06 },
126 { 0x419ed0, 1, 0x04, 0x00003818 },
127 { 0x419ed4, 1, 0x04, 0x011104f1 },
128 { 0x419edc, 1, 0x04, 0x00000000 },
129 { 0x419f00, 1, 0x04, 0x00000000 },
130 { 0x419f2c, 1, 0x04, 0x00000000 },
131 {}
132};
133
134static struct nvc0_graph_init *
135nvd9_graph_init_mmio[] = {
136 nvc0_graph_init_regs,
137 nvc0_graph_init_unk40xx,
138 nvc0_graph_init_unk44xx,
139 nvc0_graph_init_unk78xx,
140 nvc0_graph_init_unk60xx,
141 nvd9_graph_init_unk64xx,
142 nvd9_graph_init_unk58xx,
143 nvc0_graph_init_unk80xx,
144 nvd9_graph_init_gpc,
145 nvd9_graph_init_tpc,
146 nvc0_graph_init_unk88xx,
147 nvc0_graph_tpc_0,
148 NULL
149};
150
151struct nouveau_oclass *
152nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
153 .base.handle = NV_ENGINE(GR, 0xd9),
154 .base.ofuncs = &(struct nouveau_ofuncs) {
155 .ctor = nvc0_graph_ctor,
156 .dtor = nvc0_graph_dtor,
157 .init = nvc0_graph_init,
158 .fini = _nouveau_graph_fini,
159 },
160 .cclass = &nvd9_grctx_oclass,
161 .sclass = nvc8_graph_sclass,
162 .mmio = nvd9_graph_init_mmio,
163 .fecs.ucode = &nvc0_graph_fecs_ucode,
164 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
165}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
deleted file mode 100644
index f4685bb66eb8..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ /dev/null
@@ -1,1105 +0,0 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nvc0.h"
26#include "fuc/hubnve0.fuc.h"
27#include "fuc/gpcnve0.fuc.h"
28
29/*******************************************************************************
30 * Graphics object classes
31 ******************************************************************************/
32
33static struct nouveau_oclass
34nve0_graph_sclass[] = {
35 { 0x902d, &nouveau_object_ofuncs },
36 { 0xa040, &nouveau_object_ofuncs },
37 { 0xa097, &nouveau_object_ofuncs },
38 { 0xa0c0, &nouveau_object_ofuncs },
39 {}
40};
41
42/*******************************************************************************
43 * PGRAPH context
44 ******************************************************************************/
45
46static struct nouveau_oclass
47nve0_graph_cclass = {
48 .handle = NV_ENGCTX(GR, 0xe0),
49 .ofuncs = &(struct nouveau_ofuncs) {
50 .ctor = nvc0_graph_context_ctor,
51 .dtor = nvc0_graph_context_dtor,
52 .init = _nouveau_graph_context_init,
53 .fini = _nouveau_graph_context_fini,
54 .rd32 = _nouveau_graph_context_rd32,
55 .wr32 = _nouveau_graph_context_wr32,
56 },
57};
58
59/*******************************************************************************
60 * PGRAPH engine/subdev functions
61 ******************************************************************************/
62
63static void
64nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
65{
66 u32 ustat = nv_rd32(priv, 0x409c18);
67
68 if (ustat & 0x00000001)
69 nv_error(priv, "CTXCTRL ucode error\n");
70 if (ustat & 0x00080000)
71 nv_error(priv, "CTXCTRL watchdog timeout\n");
72 if (ustat & ~0x00080001)
73 nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
74
75 nvc0_graph_ctxctl_debug(priv);
76 nv_wr32(priv, 0x409c20, ustat);
77}
78
79static const struct nouveau_enum nve0_mp_warp_error[] = {
80 { 0x00, "NO_ERROR" },
81 { 0x01, "STACK_MISMATCH" },
82 { 0x05, "MISALIGNED_PC" },
83 { 0x08, "MISALIGNED_GPR" },
84 { 0x09, "INVALID_OPCODE" },
85 { 0x0d, "GPR_OUT_OF_BOUNDS" },
86 { 0x0e, "MEM_OUT_OF_BOUNDS" },
87 { 0x0f, "UNALIGNED_MEM_ACCESS" },
88 { 0x11, "INVALID_PARAM" },
89 {}
90};
91
92static const struct nouveau_bitfield nve0_mp_global_error[] = {
93 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
94 { 0x00000008, "OUT_OF_STACK_SPACE" },
95 {}
96};
97
98static const struct nouveau_enum nve0_gpc_rop_error[] = {
99 { 1, "RT_PITCH_OVERRUN" },
100 { 4, "RT_WIDTH_OVERRUN" },
101 { 5, "RT_HEIGHT_OVERRUN" },
102 { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
103 { 8, "RT_STORAGE_TYPE_MISMATCH" },
104 { 10, "RT_LINEAR_MISMATCH" },
105 {}
106};
107
108static const struct nouveau_enum nve0_sked_error[] = {
109 { 7, "CONSTANT_BUFFER_SIZE" },
110 { 9, "LOCAL_MEMORY_SIZE_POS" },
111 { 10, "LOCAL_MEMORY_SIZE_NEG" },
112 { 11, "WARP_CSTACK_SIZE" },
113 { 12, "TOTAL_TEMP_SIZE" },
114 { 13, "REGISTER_COUNT" },
115 { 18, "TOTAL_THREADS" },
116 { 20, "PROGRAM_OFFSET" },
117 { 21, "SHARED_MEMORY_SIZE" },
118 { 25, "SHARED_CONFIG_TOO_SMALL" },
119 { 26, "TOTAL_REGISTER_COUNT" },
120 {}
121};
122
123static void
124nve0_graph_mp_trap(struct nvc0_graph_priv *priv, int gpc, int tpc)
125{
126 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
127 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
128
129 nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
130 nouveau_bitfield_print(nve0_mp_global_error, gerr);
131 if (werr) {
132 pr_cont(" ");
133 nouveau_enum_print(nve0_mp_warp_error, werr & 0xffff);
134 }
135 pr_cont("\n");
136
137 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
138 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
139}
140
141static void
142nve0_graph_tpc_trap(struct nvc0_graph_priv *priv, int gpc, int tpc)
143{
144 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x508));
145
146 if (stat & 0x1) {
147 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x224));
148 nv_error(priv, "GPC%i/TPC%i/TEX trap: %08x\n",
149 gpc, tpc, trap);
150
151 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
152 stat &= ~0x1;
153 }
154
155 if (stat & 0x2) {
156 nve0_graph_mp_trap(priv, gpc, tpc);
157 stat &= ~0x2;
158 }
159
160 if (stat & 0x4) {
161 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x084));
162 nv_error(priv, "GPC%i/TPC%i/POLY trap: %08x\n",
163 gpc, tpc, trap);
164
165 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
166 stat &= ~0x4;
167 }
168
169 if (stat & 0x8) {
170 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x48c));
171 nv_error(priv, "GPC%i/TPC%i/L1C trap: %08x\n",
172 gpc, tpc, trap);
173
174 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
175 stat &= ~0x8;
176 }
177
178 if (stat) {
179 nv_error(priv, "GPC%i/TPC%i: unknown stat %08x\n",
180 gpc, tpc, stat);
181 }
182}
183
184static void
185nve0_graph_gpc_trap(struct nvc0_graph_priv *priv)
186{
187 const u32 mask = nv_rd32(priv, 0x400118);
188 int gpc;
189
190 for (gpc = 0; gpc < 4; ++gpc) {
191 u32 stat;
192 int tpc;
193
194 if (!(mask & (1 << gpc)))
195 continue;
196 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
197
198 if (stat & 0x0001) {
199 u32 trap[4];
200 int i;
201
202 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
203 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
204 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
205 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
206
207 nv_error(priv, "GPC%i/PROP trap:", gpc);
208 for (i = 0; i <= 29; ++i) {
209 if (!(trap[0] & (1 << i)))
210 continue;
211 pr_cont(" ");
212 nouveau_enum_print(nve0_gpc_rop_error, i);
213 }
214 pr_cont("\n");
215
216 nv_error(priv, "x = %u, y = %u, "
217 "format = %x, storage type = %x\n",
218 trap[1] & 0xffff,
219 trap[1] >> 16,
220 (trap[2] >> 8) & 0x3f,
221 trap[3] & 0xff);
222
223 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
224 stat &= ~0x0001;
225 }
226
227 if (stat & 0x0002) {
228 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
229 nv_error(priv, "GPC%i/ZCULL trap: %08x\n", gpc,
230 trap);
231 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
232 stat &= ~0x0002;
233 }
234
235 if (stat & 0x0004) {
236 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
237 nv_error(priv, "GPC%i/CCACHE trap: %08x\n", gpc,
238 trap);
239 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
240 stat &= ~0x0004;
241 }
242
243 if (stat & 0x0008) {
244 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
245 nv_error(priv, "GPC%i/ESETUP trap %08x\n", gpc,
246 trap);
247 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
248 stat &= ~0x0008;
249 }
250
251 for (tpc = 0; tpc < 8; ++tpc) {
252 if (stat & (1 << (16 + tpc)))
253 nve0_graph_tpc_trap(priv, gpc, tpc);
254 }
255 stat &= ~0xff0000;
256
257 if (stat) {
258 nv_error(priv, "GPC%i: unknown stat %08x\n",
259 gpc, stat);
260 }
261 }
262}
263
264
265static void
266nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst,
267 struct nouveau_object *engctx)
268{
269 u32 trap = nv_rd32(priv, 0x400108);
270 int i;
271 int rop;
272
273 if (trap & 0x00000001) {
274 u32 stat = nv_rd32(priv, 0x404000);
275 nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
276 chid, inst, nouveau_client_name(engctx), stat);
277 nv_wr32(priv, 0x404000, 0xc0000000);
278 nv_wr32(priv, 0x400108, 0x00000001);
279 trap &= ~0x00000001;
280 }
281
282 if (trap & 0x00000010) {
283 u32 stat = nv_rd32(priv, 0x405840);
284 nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
285 chid, inst, nouveau_client_name(engctx), stat);
286 nv_wr32(priv, 0x405840, 0xc0000000);
287 nv_wr32(priv, 0x400108, 0x00000010);
288 trap &= ~0x00000010;
289 }
290
291 if (trap & 0x00000100) {
292 u32 stat = nv_rd32(priv, 0x407020);
293 nv_error(priv, "SKED ch %d [0x%010llx %s]:",
294 chid, inst, nouveau_client_name(engctx));
295
296 for (i = 0; i <= 29; ++i) {
297 if (!(stat & (1 << i)))
298 continue;
299 pr_cont(" ");
300 nouveau_enum_print(nve0_sked_error, i);
301 }
302 pr_cont("\n");
303
304 if (stat & 0x3fffffff)
305 nv_wr32(priv, 0x407020, 0x40000000);
306 nv_wr32(priv, 0x400108, 0x00000100);
307 trap &= ~0x00000100;
308 }
309
310 if (trap & 0x01000000) {
311 nv_error(priv, "GPC ch %d [0x%010llx %s]:\n",
312 chid, inst, nouveau_client_name(engctx));
313 nve0_graph_gpc_trap(priv);
314 trap &= ~0x01000000;
315 }
316
317 if (trap & 0x02000000) {
318 for (rop = 0; rop < priv->rop_nr; rop++) {
319 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
320 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
321 nv_error(priv,
322 "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
323 rop, chid, inst, nouveau_client_name(engctx),
324 statz, statc);
325 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
326 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
327 }
328 nv_wr32(priv, 0x400108, 0x02000000);
329 trap &= ~0x02000000;
330 }
331
332 if (trap) {
333 nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
334 chid, inst, nouveau_client_name(engctx), trap);
335 nv_wr32(priv, 0x400108, trap);
336 }
337}
338
339static void
340nve0_graph_intr(struct nouveau_subdev *subdev)
341{
342 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
343 struct nouveau_engine *engine = nv_engine(subdev);
344 struct nouveau_object *engctx;
345 struct nouveau_handle *handle;
346 struct nvc0_graph_priv *priv = (void *)subdev;
347 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
348 u32 stat = nv_rd32(priv, 0x400100);
349 u32 addr = nv_rd32(priv, 0x400704);
350 u32 mthd = (addr & 0x00003ffc);
351 u32 subc = (addr & 0x00070000) >> 16;
352 u32 data = nv_rd32(priv, 0x400708);
353 u32 code = nv_rd32(priv, 0x400110);
354 u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
355 int chid;
356
357 engctx = nouveau_engctx_get(engine, inst);
358 chid = pfifo->chid(pfifo, engctx);
359
360 if (stat & 0x00000010) {
361 handle = nouveau_handle_get_class(engctx, class);
362 if (!handle || nv_call(handle->object, mthd, data)) {
363 nv_error(priv,
364 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
365 chid, inst, nouveau_client_name(engctx), subc,
366 class, mthd, data);
367 }
368 nouveau_handle_put(handle);
369 nv_wr32(priv, 0x400100, 0x00000010);
370 stat &= ~0x00000010;
371 }
372
373 if (stat & 0x00000020) {
374 nv_error(priv,
375 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
376 chid, inst, nouveau_client_name(engctx), subc, class,
377 mthd, data);
378 nv_wr32(priv, 0x400100, 0x00000020);
379 stat &= ~0x00000020;
380 }
381
382 if (stat & 0x00100000) {
383 nv_error(priv, "DATA_ERROR [");
384 nouveau_enum_print(nv50_data_error_names, code);
385 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
386 chid, inst, nouveau_client_name(engctx), subc, class,
387 mthd, data);
388 nv_wr32(priv, 0x400100, 0x00100000);
389 stat &= ~0x00100000;
390 }
391
392 if (stat & 0x00200000) {
393 nve0_graph_trap_isr(priv, chid, inst, engctx);
394 nv_wr32(priv, 0x400100, 0x00200000);
395 stat &= ~0x00200000;
396 }
397
398 if (stat & 0x00080000) {
399 nve0_graph_ctxctl_isr(priv);
400 nv_wr32(priv, 0x400100, 0x00080000);
401 stat &= ~0x00080000;
402 }
403
404 if (stat) {
405 nv_error(priv, "unknown stat 0x%08x\n", stat);
406 nv_wr32(priv, 0x400100, stat);
407 }
408
409 nv_wr32(priv, 0x400500, 0x00010001);
410 nouveau_engctx_put(engctx);
411}
412
413static int
414nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
415 struct nouveau_oclass *oclass, void *data, u32 size,
416 struct nouveau_object **pobject)
417{
418 struct nouveau_device *device = nv_device(parent);
419 struct nvc0_graph_priv *priv;
420 int ret, i;
421
422 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
423 *pobject = nv_object(priv);
424 if (ret)
425 return ret;
426
427 nv_subdev(priv)->unit = 0x18001000;
428 nv_subdev(priv)->intr = nve0_graph_intr;
429 nv_engine(priv)->cclass = &nve0_graph_cclass;
430 nv_engine(priv)->sclass = nve0_graph_sclass;
431
432 priv->base.units = nvc0_graph_units;
433
434 if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
435 nv_info(priv, "using external firmware\n");
436 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
437 nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
438 nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
439 nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
440 return -EINVAL;
441 priv->firmware = true;
442 }
443
444 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
445 &priv->unk4188b4);
446 if (ret)
447 return ret;
448
449 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
450 &priv->unk4188b8);
451 if (ret)
452 return ret;
453
454 for (i = 0; i < 0x1000; i += 4) {
455 nv_wo32(priv->unk4188b4, i, 0x00000010);
456 nv_wo32(priv->unk4188b8, i, 0x00000010);
457 }
458
459 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
460 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
461 for (i = 0; i < priv->gpc_nr; i++) {
462 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
463 priv->tpc_total += priv->tpc_nr[i];
464 }
465
466 switch (nv_device(priv)->chipset) {
467 case 0xe4:
468 if (priv->tpc_total == 8)
469 priv->magic_not_rop_nr = 3;
470 else
471 if (priv->tpc_total == 7)
472 priv->magic_not_rop_nr = 1;
473 break;
474 case 0xe7:
475 case 0xe6:
476 priv->magic_not_rop_nr = 1;
477 break;
478 case 0xf0:
479 default:
480 break;
481 }
482
483 return 0;
484}
485
486static void
487nve0_graph_init_obj418880(struct nvc0_graph_priv *priv)
488{
489 int i;
490
491 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
492 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
493 for (i = 0; i < 4; i++)
494 nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
495 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
496 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
497}
498
499static void
500nve0_graph_init_regs(struct nvc0_graph_priv *priv)
501{
502 nv_wr32(priv, 0x400080, 0x003083c2);
503 nv_wr32(priv, 0x400088, 0x0001ffe7);
504 nv_wr32(priv, 0x40008c, 0x00000000);
505 nv_wr32(priv, 0x400090, 0x00000030);
506 nv_wr32(priv, 0x40013c, 0x003901f7);
507 nv_wr32(priv, 0x400140, 0x00000100);
508 nv_wr32(priv, 0x400144, 0x00000000);
509 nv_wr32(priv, 0x400148, 0x00000110);
510 nv_wr32(priv, 0x400138, 0x00000000);
511 nv_wr32(priv, 0x400130, 0x00000000);
512 nv_wr32(priv, 0x400134, 0x00000000);
513 nv_wr32(priv, 0x400124, 0x00000002);
514}
515
516static void
517nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
518{
519 nv_wr32(priv, 0x40415c, 0x00000000);
520 nv_wr32(priv, 0x404170, 0x00000000);
521 switch (nv_device(priv)->chipset) {
522 case 0xf0:
523 nv_wr32(priv, 0x4041b4, 0x00000000);
524 break;
525 default:
526 break;
527 }
528}
529
530static void
531nve0_graph_init_unk44xx(struct nvc0_graph_priv *priv)
532{
533 nv_wr32(priv, 0x404488, 0x00000000);
534 nv_wr32(priv, 0x40448c, 0x00000000);
535}
536
537static void
538nve0_graph_init_unk78xx(struct nvc0_graph_priv *priv)
539{
540 nv_wr32(priv, 0x407808, 0x00000000);
541}
542
543static void
544nve0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
545{
546 nv_wr32(priv, 0x406024, 0x00000000);
547}
548
549static void
550nve0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
551{
552 nv_wr32(priv, 0x4064f0, 0x00000000);
553 nv_wr32(priv, 0x4064f4, 0x00000000);
554 nv_wr32(priv, 0x4064f8, 0x00000000);
555}
556
557static void
558nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
559{
560 nv_wr32(priv, 0x405844, 0x00ffffff);
561 nv_wr32(priv, 0x405850, 0x00000000);
562 switch (nv_device(priv)->chipset) {
563 case 0xf0:
564 nv_wr32(priv, 0x405900, 0x0000ff00);
565 break;
566 default:
567 nv_wr32(priv, 0x405900, 0x0000ff34);
568 break;
569 }
570 nv_wr32(priv, 0x405908, 0x00000000);
571 nv_wr32(priv, 0x405928, 0x00000000);
572 nv_wr32(priv, 0x40592c, 0x00000000);
573}
574
575static void
576nve0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
577{
578 nv_wr32(priv, 0x40803c, 0x00000000);
579}
580
581static void
582nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)
583{
584 nv_wr32(priv, 0x407010, 0x00000000);
585 switch (nv_device(priv)->chipset) {
586 case 0xf0:
587 nv_wr32(priv, 0x407040, 0x80440424);
588 nv_wr32(priv, 0x407048, 0x0000000a);
589 break;
590 default:
591 break;
592 }
593}
594
595static void
596nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)
597{
598 switch (nv_device(priv)->chipset) {
599 case 0xf0:
600 nv_wr32(priv, 0x505b44, 0x00000000);
601 break;
602 default:
603 break;
604 }
605 nv_wr32(priv, 0x405b50, 0x00000000);
606}
607
608static void
609nve0_graph_init_gpc(struct nvc0_graph_priv *priv)
610{
611 nv_wr32(priv, 0x418408, 0x00000000);
612 nv_wr32(priv, 0x4184a0, 0x00000000);
613 nv_wr32(priv, 0x4184a4, 0x00000000);
614 nv_wr32(priv, 0x4184a8, 0x00000000);
615 nv_wr32(priv, 0x418604, 0x00000000);
616 nv_wr32(priv, 0x418680, 0x00000000);
617 nv_wr32(priv, 0x418714, 0x00000000);
618 nv_wr32(priv, 0x418384, 0x00000000);
619 nv_wr32(priv, 0x418814, 0x00000000);
620 nv_wr32(priv, 0x418818, 0x00000000);
621 nv_wr32(priv, 0x41881c, 0x00000000);
622 nv_wr32(priv, 0x418b04, 0x00000000);
623 nv_wr32(priv, 0x4188c8, 0x00000000);
624 nv_wr32(priv, 0x4188cc, 0x00000000);
625 nv_wr32(priv, 0x4188d0, 0x00010000);
626 nv_wr32(priv, 0x4188d4, 0x00000001);
627 nv_wr32(priv, 0x418910, 0x00010001);
628 nv_wr32(priv, 0x418914, 0x00000301);
629 nv_wr32(priv, 0x418918, 0x00800000);
630 nv_wr32(priv, 0x418980, 0x77777770);
631 nv_wr32(priv, 0x418984, 0x77777777);
632 nv_wr32(priv, 0x418988, 0x77777777);
633 nv_wr32(priv, 0x41898c, 0x77777777);
634 nv_wr32(priv, 0x418c04, 0x00000000);
635 nv_wr32(priv, 0x418c64, 0x00000000);
636 nv_wr32(priv, 0x418c68, 0x00000000);
637 nv_wr32(priv, 0x418c88, 0x00000000);
638 nv_wr32(priv, 0x418cb4, 0x00000000);
639 nv_wr32(priv, 0x418cb8, 0x00000000);
640 nv_wr32(priv, 0x418d00, 0x00000000);
641 nv_wr32(priv, 0x418d28, 0x00000000);
642 nv_wr32(priv, 0x418d2c, 0x00000000);
643 switch (nv_device(priv)->chipset) {
644 case 0xf0:
645 nv_wr32(priv, 0x418f00, 0x00000400);
646 break;
647 default:
648 nv_wr32(priv, 0x418f00, 0x00000000);
649 break;
650 }
651 nv_wr32(priv, 0x418f08, 0x00000000);
652 nv_wr32(priv, 0x418f20, 0x00000000);
653 nv_wr32(priv, 0x418f24, 0x00000000);
654 switch (nv_device(priv)->chipset) {
655 case 0xf0:
656 nv_wr32(priv, 0x418e00, 0x00000000);
657 break;
658 default:
659 nv_wr32(priv, 0x418e00, 0x00000060);
660 break;
661 }
662 nv_wr32(priv, 0x418e08, 0x00000000);
663 nv_wr32(priv, 0x418e1c, 0x00000000);
664 nv_wr32(priv, 0x418e20, 0x00000000);
665 nv_wr32(priv, 0x41900c, 0x00000000);
666 nv_wr32(priv, 0x419018, 0x00000000);
667}
668
669static void
670nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
671{
672 nv_wr32(priv, 0x419d0c, 0x00000000);
673 nv_wr32(priv, 0x419d10, 0x00000014);
674 nv_wr32(priv, 0x419ab0, 0x00000000);
675 nv_wr32(priv, 0x419ac8, 0x00000000);
676 nv_wr32(priv, 0x419ab8, 0x000000e7);
677 switch (nv_device(priv)->chipset) {
678 case 0xf0:
679 nv_wr32(priv, 0x419aec, 0x00000000);
680 break;
681 default:
682 break;
683 }
684 nv_wr32(priv, 0x419abc, 0x00000000);
685 nv_wr32(priv, 0x419ac0, 0x00000000);
686 nv_wr32(priv, 0x419ab4, 0x00000000);
687 switch (nv_device(priv)->chipset) {
688 case 0xf0:
689 nv_wr32(priv, 0x419aa8, 0x00000000);
690 nv_wr32(priv, 0x419aac, 0x00000000);
691 break;
692 default:
693 break;
694 }
695 nv_wr32(priv, 0x41980c, 0x00000010);
696 nv_wr32(priv, 0x419844, 0x00000000);
697 nv_wr32(priv, 0x419850, 0x00000004);
698 nv_wr32(priv, 0x419854, 0x00000000);
699 nv_wr32(priv, 0x419858, 0x00000000);
700 nv_wr32(priv, 0x419c98, 0x00000000);
701 nv_wr32(priv, 0x419ca8, 0x00000000);
702 nv_wr32(priv, 0x419cb0, 0x01000000);
703 nv_wr32(priv, 0x419cb4, 0x00000000);
704 nv_wr32(priv, 0x419cb8, 0x00b08bea);
705 nv_wr32(priv, 0x419c84, 0x00010384);
706 switch (nv_device(priv)->chipset) {
707 case 0xf0:
708 nv_wr32(priv, 0x419cbc, 0x281b3646);
709 break;
710 default:
711 nv_wr32(priv, 0x419cbc, 0x28137646);
712 break;
713 }
714 nv_wr32(priv, 0x419cc0, 0x00000000);
715 nv_wr32(priv, 0x419cc4, 0x00000000);
716 switch (nv_device(priv)->chipset) {
717 case 0xf0:
718 nv_wr32(priv, 0x419c80, 0x00020230);
719 nv_wr32(priv, 0x419ccc, 0x00000000);
720 nv_wr32(priv, 0x419cd0, 0x00000000);
721 nv_wr32(priv, 0x419c0c, 0x00000000);
722 nv_wr32(priv, 0x419e00, 0x00000080);
723 break;
724 default:
725 nv_wr32(priv, 0x419c80, 0x00020232);
726 nv_wr32(priv, 0x419c0c, 0x00000000);
727 nv_wr32(priv, 0x419e00, 0x00000000);
728 break;
729 }
730 nv_wr32(priv, 0x419ea0, 0x00000000);
731 nv_wr32(priv, 0x419ee4, 0x00000000);
732 nv_wr32(priv, 0x419ea4, 0x00000100);
733 nv_wr32(priv, 0x419ea8, 0x00000000);
734 nv_wr32(priv, 0x419eb4, 0x00000000);
735 switch (nv_device(priv)->chipset) {
736 case 0xf0:
737 break;
738 default:
739 nv_wr32(priv, 0x419eb8, 0x00000000);
740 break;
741 }
742 nv_wr32(priv, 0x419ebc, 0x00000000);
743 nv_wr32(priv, 0x419ec0, 0x00000000);
744 nv_wr32(priv, 0x419edc, 0x00000000);
745 nv_wr32(priv, 0x419f00, 0x00000000);
746 switch (nv_device(priv)->chipset) {
747 case 0xf0:
748 nv_wr32(priv, 0x419ed0, 0x00003234);
749 nv_wr32(priv, 0x419f74, 0x00015555);
750 nv_wr32(priv, 0x419f80, 0x00000000);
751 nv_wr32(priv, 0x419f84, 0x00000000);
752 nv_wr32(priv, 0x419f88, 0x00000000);
753 nv_wr32(priv, 0x419f8c, 0x00000000);
754 break;
755 default:
756 nv_wr32(priv, 0x419f74, 0x00000555);
757 break;
758 }
759}
760
761static void
762nve0_graph_init_tpcunk(struct nvc0_graph_priv *priv)
763{
764 nv_wr32(priv, 0x41be04, 0x00000000);
765 nv_wr32(priv, 0x41be08, 0x00000004);
766 nv_wr32(priv, 0x41be0c, 0x00000000);
767 nv_wr32(priv, 0x41be10, 0x003b8bc7);
768 nv_wr32(priv, 0x41be14, 0x00000000);
769 nv_wr32(priv, 0x41be18, 0x00000000);
770 nv_wr32(priv, 0x41bfd4, 0x00800000);
771 nv_wr32(priv, 0x41bfdc, 0x00000000);
772 nv_wr32(priv, 0x41bff8, 0x00000000);
773 nv_wr32(priv, 0x41bffc, 0x00000000);
774 nv_wr32(priv, 0x41becc, 0x00000000);
775 nv_wr32(priv, 0x41bee8, 0x00000000);
776 nv_wr32(priv, 0x41beec, 0x00000000);
777}
778
779static void
780nve0_graph_init_unk88xx(struct nvc0_graph_priv *priv)
781{
782 nv_wr32(priv, 0x40880c, 0x00000000);
783 nv_wr32(priv, 0x408850, 0x00000004);
784 nv_wr32(priv, 0x408910, 0x00000000);
785 nv_wr32(priv, 0x408914, 0x00000000);
786 nv_wr32(priv, 0x408918, 0x00000000);
787 nv_wr32(priv, 0x40891c, 0x00000000);
788 nv_wr32(priv, 0x408920, 0x00000000);
789 nv_wr32(priv, 0x408924, 0x00000000);
790 nv_wr32(priv, 0x408928, 0x00000000);
791 nv_wr32(priv, 0x40892c, 0x00000000);
792 nv_wr32(priv, 0x408930, 0x00000000);
793 nv_wr32(priv, 0x408950, 0x00000000);
794 nv_wr32(priv, 0x408954, 0x0000ffff);
795 nv_wr32(priv, 0x408958, 0x00000034);
796 nv_wr32(priv, 0x408984, 0x00000000);
797 nv_wr32(priv, 0x408988, 0x08040201);
798 nv_wr32(priv, 0x40898c, 0x80402010);
799}
800
801static void
802nve0_graph_init_units(struct nvc0_graph_priv *priv)
803{
804 nv_wr32(priv, 0x409ffc, 0x00000000);
805 nv_wr32(priv, 0x409c14, 0x00003e3e);
806 switch (nv_device(priv)->chipset) {
807 case 0xe4:
808 case 0xe7:
809 case 0xe6:
810 nv_wr32(priv, 0x409c24, 0x000f0001);
811 break;
812 case 0xf0:
813 nv_wr32(priv, 0x409c24, 0x000f0000);
814 break;
815 }
816
817 nv_wr32(priv, 0x404000, 0xc0000000);
818 nv_wr32(priv, 0x404600, 0xc0000000);
819 nv_wr32(priv, 0x408030, 0xc0000000);
820 nv_wr32(priv, 0x404490, 0xc0000000);
821 nv_wr32(priv, 0x406018, 0xc0000000);
822 nv_wr32(priv, 0x407020, 0x40000000);
823 nv_wr32(priv, 0x405840, 0xc0000000);
824 nv_wr32(priv, 0x405844, 0x00ffffff);
825
826 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
827 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
828
829}
830
831static void
832nve0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
833{
834 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
835 u32 data[TPC_MAX / 8];
836 u8 tpcnr[GPC_MAX];
837 int i, gpc, tpc;
838
839 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
840
841 memset(data, 0x00, sizeof(data));
842 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
843 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
844 do {
845 gpc = (gpc + 1) % priv->gpc_nr;
846 } while (!tpcnr[gpc]);
847 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
848
849 data[i / 8] |= tpc << ((i % 8) * 4);
850 }
851
852 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
853 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
854 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
855 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
856
857 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
858 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
859 priv->tpc_nr[gpc]);
860 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
861 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
862 }
863
864 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
865 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
866}
867
868static void
869nve0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
870{
871 int gpc, tpc;
872
873 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
874 nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
875 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
876 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
877 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
878 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
879 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
880 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
881 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
882 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
883 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
884 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
885 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
886 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
887 }
888 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
889 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
890 }
891}
892
893static void
894nve0_graph_init_rop(struct nvc0_graph_priv *priv)
895{
896 int rop;
897
898 for (rop = 0; rop < priv->rop_nr; rop++) {
899 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
900 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
901 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
902 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
903 }
904}
905
906static int
907nve0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
908{
909 u32 r000260;
910 int i;
911
912 if (priv->firmware) {
913 /* load fuc microcode */
914 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
915 nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, &priv->fuc409d);
916 nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
917 nv_wr32(priv, 0x000260, r000260);
918
919 /* start both of them running */
920 nv_wr32(priv, 0x409840, 0xffffffff);
921 nv_wr32(priv, 0x41a10c, 0x00000000);
922 nv_wr32(priv, 0x40910c, 0x00000000);
923 nv_wr32(priv, 0x41a100, 0x00000002);
924 nv_wr32(priv, 0x409100, 0x00000002);
925 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
926 nv_error(priv, "0x409800 wait failed\n");
927
928 nv_wr32(priv, 0x409840, 0xffffffff);
929 nv_wr32(priv, 0x409500, 0x7fffffff);
930 nv_wr32(priv, 0x409504, 0x00000021);
931
932 nv_wr32(priv, 0x409840, 0xffffffff);
933 nv_wr32(priv, 0x409500, 0x00000000);
934 nv_wr32(priv, 0x409504, 0x00000010);
935 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
936 nv_error(priv, "fuc09 req 0x10 timeout\n");
937 return -EBUSY;
938 }
939 priv->size = nv_rd32(priv, 0x409800);
940
941 nv_wr32(priv, 0x409840, 0xffffffff);
942 nv_wr32(priv, 0x409500, 0x00000000);
943 nv_wr32(priv, 0x409504, 0x00000016);
944 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
945 nv_error(priv, "fuc09 req 0x16 timeout\n");
946 return -EBUSY;
947 }
948
949 nv_wr32(priv, 0x409840, 0xffffffff);
950 nv_wr32(priv, 0x409500, 0x00000000);
951 nv_wr32(priv, 0x409504, 0x00000025);
952 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
953 nv_error(priv, "fuc09 req 0x25 timeout\n");
954 return -EBUSY;
955 }
956
957 nv_wr32(priv, 0x409800, 0x00000000);
958 nv_wr32(priv, 0x409500, 0x00000001);
959 nv_wr32(priv, 0x409504, 0x00000030);
960 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
961 nv_error(priv, "fuc09 req 0x30 timeout\n");
962 return -EBUSY;
963 }
964
965 nv_wr32(priv, 0x409810, 0xb00095c8);
966 nv_wr32(priv, 0x409800, 0x00000000);
967 nv_wr32(priv, 0x409500, 0x00000001);
968 nv_wr32(priv, 0x409504, 0x00000031);
969 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
970 nv_error(priv, "fuc09 req 0x31 timeout\n");
971 return -EBUSY;
972 }
973
974 nv_wr32(priv, 0x409810, 0x00080420);
975 nv_wr32(priv, 0x409800, 0x00000000);
976 nv_wr32(priv, 0x409500, 0x00000001);
977 nv_wr32(priv, 0x409504, 0x00000032);
978 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
979 nv_error(priv, "fuc09 req 0x32 timeout\n");
980 return -EBUSY;
981 }
982
983 nv_wr32(priv, 0x409614, 0x00000070);
984 nv_wr32(priv, 0x409614, 0x00000770);
985 nv_wr32(priv, 0x40802c, 0x00000001);
986
987 if (priv->data == NULL) {
988 int ret = nve0_grctx_generate(priv);
989 if (ret) {
990 nv_error(priv, "failed to construct context\n");
991 return ret;
992 }
993 }
994
995 return 0;
996 }
997
998 /* load HUB microcode */
999 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
1000 nv_wr32(priv, 0x4091c0, 0x01000000);
1001 for (i = 0; i < sizeof(nve0_grhub_data) / 4; i++)
1002 nv_wr32(priv, 0x4091c4, nve0_grhub_data[i]);
1003
1004 nv_wr32(priv, 0x409180, 0x01000000);
1005 for (i = 0; i < sizeof(nve0_grhub_code) / 4; i++) {
1006 if ((i & 0x3f) == 0)
1007 nv_wr32(priv, 0x409188, i >> 6);
1008 nv_wr32(priv, 0x409184, nve0_grhub_code[i]);
1009 }
1010
1011 /* load GPC microcode */
1012 nv_wr32(priv, 0x41a1c0, 0x01000000);
1013 for (i = 0; i < sizeof(nve0_grgpc_data) / 4; i++)
1014 nv_wr32(priv, 0x41a1c4, nve0_grgpc_data[i]);
1015
1016 nv_wr32(priv, 0x41a180, 0x01000000);
1017 for (i = 0; i < sizeof(nve0_grgpc_code) / 4; i++) {
1018 if ((i & 0x3f) == 0)
1019 nv_wr32(priv, 0x41a188, i >> 6);
1020 nv_wr32(priv, 0x41a184, nve0_grgpc_code[i]);
1021 }
1022 nv_wr32(priv, 0x000260, r000260);
1023
1024 /* start HUB ucode running, it'll init the GPCs */
1025 nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
1026 nv_wr32(priv, 0x40910c, 0x00000000);
1027 nv_wr32(priv, 0x409100, 0x00000002);
1028 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
1029 nv_error(priv, "HUB_INIT timed out\n");
1030 nvc0_graph_ctxctl_debug(priv);
1031 return -EBUSY;
1032 }
1033
1034 priv->size = nv_rd32(priv, 0x409804);
1035 if (priv->data == NULL) {
1036 int ret = nve0_grctx_generate(priv);
1037 if (ret) {
1038 nv_error(priv, "failed to construct context\n");
1039 return ret;
1040 }
1041 }
1042
1043 return 0;
1044}
1045
1046static int
1047nve0_graph_init(struct nouveau_object *object)
1048{
1049 struct nvc0_graph_priv *priv = (void *)object;
1050 int ret;
1051
1052 ret = nouveau_graph_init(&priv->base);
1053 if (ret)
1054 return ret;
1055
1056 nve0_graph_init_obj418880(priv);
1057 nve0_graph_init_regs(priv);
1058 nve0_graph_init_unk40xx(priv);
1059 nve0_graph_init_unk44xx(priv);
1060 nve0_graph_init_unk78xx(priv);
1061 nve0_graph_init_unk60xx(priv);
1062 nve0_graph_init_unk64xx(priv);
1063 nve0_graph_init_unk58xx(priv);
1064 nve0_graph_init_unk80xx(priv);
1065 nve0_graph_init_unk70xx(priv);
1066 nve0_graph_init_unk5bxx(priv);
1067 nve0_graph_init_gpc(priv);
1068 nve0_graph_init_tpc(priv);
1069 nve0_graph_init_tpcunk(priv);
1070 nve0_graph_init_unk88xx(priv);
1071 nve0_graph_init_gpc_0(priv);
1072
1073 nv_wr32(priv, 0x400500, 0x00010001);
1074 nv_wr32(priv, 0x400100, 0xffffffff);
1075 nv_wr32(priv, 0x40013c, 0xffffffff);
1076
1077 nve0_graph_init_units(priv);
1078 nve0_graph_init_gpc_1(priv);
1079 nve0_graph_init_rop(priv);
1080
1081 nv_wr32(priv, 0x400108, 0xffffffff);
1082 nv_wr32(priv, 0x400138, 0xffffffff);
1083 nv_wr32(priv, 0x400118, 0xffffffff);
1084 nv_wr32(priv, 0x400130, 0xffffffff);
1085 nv_wr32(priv, 0x40011c, 0xffffffff);
1086 nv_wr32(priv, 0x400134, 0xffffffff);
1087 nv_wr32(priv, 0x400054, 0x34ce3464);
1088
1089 ret = nve0_graph_init_ctxctl(priv);
1090 if (ret)
1091 return ret;
1092
1093 return 0;
1094}
1095
1096struct nouveau_oclass
1097nve0_graph_oclass = {
1098 .handle = NV_ENGINE(GR, 0xe0),
1099 .ofuncs = &(struct nouveau_ofuncs) {
1100 .ctor = nve0_graph_ctor,
1101 .dtor = nvc0_graph_dtor,
1102 .init = nve0_graph_init,
1103 .fini = _nouveau_graph_fini,
1104 },
1105};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
new file mode 100644
index 000000000000..05ec09c88517
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
@@ -0,0 +1,354 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31static struct nouveau_oclass
32nve4_graph_sclass[] = {
33 { 0x902d, &nouveau_object_ofuncs },
34 { 0xa040, &nouveau_object_ofuncs },
35 { 0xa097, &nouveau_object_ofuncs },
36 { 0xa0c0, &nouveau_object_ofuncs },
37 {}
38};
39
40/*******************************************************************************
41 * PGRAPH engine/subdev functions
42 ******************************************************************************/
43
44struct nvc0_graph_init
45nve4_graph_init_regs[] = {
46 { 0x400080, 1, 0x04, 0x003083c2 },
47 { 0x400088, 1, 0x04, 0x0001ffe7 },
48 { 0x40008c, 1, 0x04, 0x00000000 },
49 { 0x400090, 1, 0x04, 0x00000030 },
50 { 0x40013c, 1, 0x04, 0x003901f7 },
51 { 0x400140, 1, 0x04, 0x00000100 },
52 { 0x400144, 1, 0x04, 0x00000000 },
53 { 0x400148, 1, 0x04, 0x00000110 },
54 { 0x400138, 1, 0x04, 0x00000000 },
55 { 0x400130, 2, 0x04, 0x00000000 },
56 { 0x400124, 1, 0x04, 0x00000002 },
57 {}
58};
59
60static struct nvc0_graph_init
61nve4_graph_init_unk58xx[] = {
62 { 0x405844, 1, 0x04, 0x00ffffff },
63 { 0x405850, 1, 0x04, 0x00000000 },
64 { 0x405900, 1, 0x04, 0x0000ff34 },
65 { 0x405908, 1, 0x04, 0x00000000 },
66 { 0x405928, 1, 0x04, 0x00000000 },
67 { 0x40592c, 1, 0x04, 0x00000000 },
68 {}
69};
70
71static struct nvc0_graph_init
72nve4_graph_init_unk70xx[] = {
73 { 0x407010, 1, 0x04, 0x00000000 },
74 {}
75};
76
77struct nvc0_graph_init
78nve4_graph_init_unk5bxx[] = {
79 { 0x405b50, 1, 0x04, 0x00000000 },
80 {}
81};
82
83static struct nvc0_graph_init
84nve4_graph_init_gpc[] = {
85 { 0x418408, 1, 0x04, 0x00000000 },
86 { 0x4184a0, 1, 0x04, 0x00000000 },
87 { 0x4184a4, 2, 0x04, 0x00000000 },
88 { 0x418604, 1, 0x04, 0x00000000 },
89 { 0x418680, 1, 0x04, 0x00000000 },
90 { 0x418714, 1, 0x04, 0x00000000 },
91 { 0x418384, 1, 0x04, 0x00000000 },
92 { 0x418814, 3, 0x04, 0x00000000 },
93 { 0x418b04, 1, 0x04, 0x00000000 },
94 { 0x4188c8, 2, 0x04, 0x00000000 },
95 { 0x4188d0, 1, 0x04, 0x00010000 },
96 { 0x4188d4, 1, 0x04, 0x00000001 },
97 { 0x418910, 1, 0x04, 0x00010001 },
98 { 0x418914, 1, 0x04, 0x00000301 },
99 { 0x418918, 1, 0x04, 0x00800000 },
100 { 0x418980, 1, 0x04, 0x77777770 },
101 { 0x418984, 3, 0x04, 0x77777777 },
102 { 0x418c04, 1, 0x04, 0x00000000 },
103 { 0x418c64, 1, 0x04, 0x00000000 },
104 { 0x418c68, 1, 0x04, 0x00000000 },
105 { 0x418c88, 1, 0x04, 0x00000000 },
106 { 0x418cb4, 2, 0x04, 0x00000000 },
107 { 0x418d00, 1, 0x04, 0x00000000 },
108 { 0x418d28, 1, 0x04, 0x00000000 },
109 { 0x418d2c, 1, 0x04, 0x00000000 },
110 { 0x418f00, 1, 0x04, 0x00000000 },
111 { 0x418f08, 1, 0x04, 0x00000000 },
112 { 0x418f20, 2, 0x04, 0x00000000 },
113 { 0x418e00, 1, 0x04, 0x00000060 },
114 { 0x418e08, 1, 0x04, 0x00000000 },
115 { 0x418e1c, 1, 0x04, 0x00000000 },
116 { 0x418e20, 1, 0x04, 0x00000000 },
117 { 0x41900c, 1, 0x04, 0x00000000 },
118 { 0x419018, 1, 0x04, 0x00000000 },
119 {}
120};
121
122static struct nvc0_graph_init
123nve4_graph_init_tpc[] = {
124 { 0x419d0c, 1, 0x04, 0x00000000 },
125 { 0x419d10, 1, 0x04, 0x00000014 },
126 { 0x419ab0, 1, 0x04, 0x00000000 },
127 { 0x419ac8, 1, 0x04, 0x00000000 },
128 { 0x419ab8, 1, 0x04, 0x000000e7 },
129 { 0x419abc, 2, 0x04, 0x00000000 },
130 { 0x419ab4, 1, 0x04, 0x00000000 },
131 { 0x41980c, 1, 0x04, 0x00000010 },
132 { 0x419844, 1, 0x04, 0x00000000 },
133 { 0x419850, 1, 0x04, 0x00000004 },
134 { 0x419854, 2, 0x04, 0x00000000 },
135 { 0x419c98, 1, 0x04, 0x00000000 },
136 { 0x419ca8, 1, 0x04, 0x00000000 },
137 { 0x419cb0, 1, 0x04, 0x01000000 },
138 { 0x419cb4, 1, 0x04, 0x00000000 },
139 { 0x419cb8, 1, 0x04, 0x00b08bea },
140 { 0x419c84, 1, 0x04, 0x00010384 },
141 { 0x419cbc, 1, 0x04, 0x28137646 },
142 { 0x419cc0, 2, 0x04, 0x00000000 },
143 { 0x419c80, 1, 0x04, 0x00020232 },
144 { 0x419c0c, 1, 0x04, 0x00000000 },
145 { 0x419e00, 1, 0x04, 0x00000000 },
146 { 0x419ea0, 1, 0x04, 0x00000000 },
147 { 0x419ee4, 1, 0x04, 0x00000000 },
148 { 0x419ea4, 1, 0x04, 0x00000100 },
149 { 0x419ea8, 1, 0x04, 0x00000000 },
150 { 0x419eb4, 1, 0x04, 0x00000000 },
151 { 0x419eb8, 3, 0x04, 0x00000000 },
152 { 0x419edc, 1, 0x04, 0x00000000 },
153 { 0x419f00, 1, 0x04, 0x00000000 },
154 { 0x419f74, 1, 0x04, 0x00000555 },
155 {}
156};
157
158struct nvc0_graph_init
159nve4_graph_init_unk[] = {
160 { 0x41be04, 1, 0x04, 0x00000000 },
161 { 0x41be08, 1, 0x04, 0x00000004 },
162 { 0x41be0c, 1, 0x04, 0x00000000 },
163 { 0x41be10, 1, 0x04, 0x003b8bc7 },
164 { 0x41be14, 2, 0x04, 0x00000000 },
165 { 0x41bfd4, 1, 0x04, 0x00800000 },
166 { 0x41bfdc, 1, 0x04, 0x00000000 },
167 { 0x41bff8, 1, 0x04, 0x00000000 },
168 { 0x41bffc, 1, 0x04, 0x00000000 },
169 { 0x41becc, 1, 0x04, 0x00000000 },
170 { 0x41bee8, 1, 0x04, 0x00000000 },
171 { 0x41beec, 1, 0x04, 0x00000000 },
172 {}
173};
174
175struct nvc0_graph_init
176nve4_graph_init_unk88xx[] = {
177 { 0x40880c, 1, 0x04, 0x00000000 },
178 { 0x408850, 1, 0x04, 0x00000004 },
179 { 0x408910, 9, 0x04, 0x00000000 },
180 { 0x408950, 1, 0x04, 0x00000000 },
181 { 0x408954, 1, 0x04, 0x0000ffff },
182 { 0x408958, 1, 0x04, 0x00000034 },
183 { 0x408984, 1, 0x04, 0x00000000 },
184 { 0x408988, 1, 0x04, 0x08040201 },
185 { 0x40898c, 1, 0x04, 0x80402010 },
186 {}
187};
188
189int
190nve4_graph_init(struct nouveau_object *object)
191{
192 struct nvc0_graph_oclass *oclass = (void *)object->oclass;
193 struct nvc0_graph_priv *priv = (void *)object;
194 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
195 u32 data[TPC_MAX / 8] = {};
196 u8 tpcnr[GPC_MAX];
197 int gpc, tpc, rop;
198 int ret, i;
199
200 ret = nouveau_graph_init(&priv->base);
201 if (ret)
202 return ret;
203
204 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
205 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
206 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
207 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
208 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
209 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
210 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
211 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
212
213 for (i = 0; oclass->mmio[i]; i++)
214 nvc0_graph_mmio(priv, oclass->mmio[i]);
215
216 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
217
218 memset(data, 0x00, sizeof(data));
219 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
220 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
221 do {
222 gpc = (gpc + 1) % priv->gpc_nr;
223 } while (!tpcnr[gpc]);
224 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
225
226 data[i / 8] |= tpc << ((i % 8) * 4);
227 }
228
229 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
230 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
231 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
232 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
233
234 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
235 nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
236 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
237 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
238 priv->tpc_total);
239 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
240 }
241
242 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
243 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
244
245 nv_wr32(priv, 0x400500, 0x00010001);
246
247 nv_wr32(priv, 0x400100, 0xffffffff);
248 nv_wr32(priv, 0x40013c, 0xffffffff);
249
250 nv_wr32(priv, 0x409ffc, 0x00000000);
251 nv_wr32(priv, 0x409c14, 0x00003e3e);
252 nv_wr32(priv, 0x409c24, 0x000f0001);
253 nv_wr32(priv, 0x404000, 0xc0000000);
254 nv_wr32(priv, 0x404600, 0xc0000000);
255 nv_wr32(priv, 0x408030, 0xc0000000);
256 nv_wr32(priv, 0x404490, 0xc0000000);
257 nv_wr32(priv, 0x406018, 0xc0000000);
258 nv_wr32(priv, 0x407020, 0x40000000);
259 nv_wr32(priv, 0x405840, 0xc0000000);
260 nv_wr32(priv, 0x405844, 0x00ffffff);
261 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
262 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
263
264 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
265 nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
266 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
267 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
268 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
269 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
270 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
271 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
272 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
273 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
274 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
275 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
276 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
277 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
278 }
279 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
280 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
281 }
282
283 for (rop = 0; rop < priv->rop_nr; rop++) {
284 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
285 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
286 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
287 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
288 }
289
290 nv_wr32(priv, 0x400108, 0xffffffff);
291 nv_wr32(priv, 0x400138, 0xffffffff);
292 nv_wr32(priv, 0x400118, 0xffffffff);
293 nv_wr32(priv, 0x400130, 0xffffffff);
294 nv_wr32(priv, 0x40011c, 0xffffffff);
295 nv_wr32(priv, 0x400134, 0xffffffff);
296
297 nv_wr32(priv, 0x400054, 0x34ce3464);
298 return nvc0_graph_init_ctxctl(priv);
299}
300
301static struct nvc0_graph_init *
302nve4_graph_init_mmio[] = {
303 nve4_graph_init_regs,
304 nvc0_graph_init_unk40xx,
305 nvc0_graph_init_unk44xx,
306 nvc0_graph_init_unk78xx,
307 nvc0_graph_init_unk60xx,
308 nvd9_graph_init_unk64xx,
309 nve4_graph_init_unk58xx,
310 nvc0_graph_init_unk80xx,
311 nve4_graph_init_unk70xx,
312 nve4_graph_init_unk5bxx,
313 nve4_graph_init_gpc,
314 nve4_graph_init_tpc,
315 nve4_graph_init_unk,
316 nve4_graph_init_unk88xx,
317 NULL
318};
319
320#include "fuc/hubnve0.fuc.h"
321
322static struct nvc0_graph_ucode
323nve4_graph_fecs_ucode = {
324 .code.data = nve0_grhub_code,
325 .code.size = sizeof(nve0_grhub_code),
326 .data.data = nve0_grhub_data,
327 .data.size = sizeof(nve0_grhub_data),
328};
329
330#include "fuc/gpcnve0.fuc.h"
331
332static struct nvc0_graph_ucode
333nve4_graph_gpccs_ucode = {
334 .code.data = nve0_grgpc_code,
335 .code.size = sizeof(nve0_grgpc_code),
336 .data.data = nve0_grgpc_data,
337 .data.size = sizeof(nve0_grgpc_data),
338};
339
340struct nouveau_oclass *
341nve4_graph_oclass = &(struct nvc0_graph_oclass) {
342 .base.handle = NV_ENGINE(GR, 0xe4),
343 .base.ofuncs = &(struct nouveau_ofuncs) {
344 .ctor = nvc0_graph_ctor,
345 .dtor = nvc0_graph_dtor,
346 .init = nve4_graph_init,
347 .fini = _nouveau_graph_fini,
348 },
349 .cclass = &nve4_grctx_oclass,
350 .sclass = nve4_graph_sclass,
351 .mmio = nve4_graph_init_mmio,
352 .fecs.ucode = &nve4_graph_fecs_ucode,
353 .gpccs.ucode = &nve4_graph_gpccs_ucode,
354}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
new file mode 100644
index 000000000000..2f0ac7832234
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
@@ -0,0 +1,248 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25#include "nvc0.h"
26
27/*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31static struct nouveau_oclass
32nvf0_graph_sclass[] = {
33 { 0x902d, &nouveau_object_ofuncs },
34 { 0xa140, &nouveau_object_ofuncs },
35 { 0xa197, &nouveau_object_ofuncs },
36 { 0xa1c0, &nouveau_object_ofuncs },
37 {}
38};
39
40/*******************************************************************************
41 * PGRAPH engine/subdev functions
42 ******************************************************************************/
43
44static struct nvc0_graph_init
45nvf0_graph_init_unk40xx[] = {
46 { 0x40415c, 1, 0x04, 0x00000000 },
47 { 0x404170, 1, 0x04, 0x00000000 },
48 { 0x4041b4, 1, 0x04, 0x00000000 },
49 {}
50};
51
52static struct nvc0_graph_init
53nvf0_graph_init_unk58xx[] = {
54 { 0x405844, 1, 0x04, 0x00ffffff },
55 { 0x405850, 1, 0x04, 0x00000000 },
56 { 0x405900, 1, 0x04, 0x0000ff00 },
57 { 0x405908, 1, 0x04, 0x00000000 },
58 { 0x405928, 1, 0x04, 0x00000000 },
59 { 0x40592c, 1, 0x04, 0x00000000 },
60 {}
61};
62
63static struct nvc0_graph_init
64nvf0_graph_init_unk70xx[] = {
65 { 0x407010, 1, 0x04, 0x00000000 },
66 { 0x407040, 1, 0x04, 0x80440424 },
67 { 0x407048, 1, 0x04, 0x0000000a },
68 {}
69};
70
71static struct nvc0_graph_init
72nvf0_graph_init_unk5bxx[] = {
73 { 0x405b44, 1, 0x04, 0x00000000 },
74 { 0x405b50, 1, 0x04, 0x00000000 },
75 {}
76};
77
78static struct nvc0_graph_init
79nvf0_graph_init_gpc[] = {
80 { 0x418408, 1, 0x04, 0x00000000 },
81 { 0x4184a0, 1, 0x04, 0x00000000 },
82 { 0x4184a4, 2, 0x04, 0x00000000 },
83 { 0x418604, 1, 0x04, 0x00000000 },
84 { 0x418680, 1, 0x04, 0x00000000 },
85 { 0x418714, 1, 0x04, 0x00000000 },
86 { 0x418384, 1, 0x04, 0x00000000 },
87 { 0x418814, 3, 0x04, 0x00000000 },
88 { 0x418b04, 1, 0x04, 0x00000000 },
89 { 0x4188c8, 2, 0x04, 0x00000000 },
90 { 0x4188d0, 1, 0x04, 0x00010000 },
91 { 0x4188d4, 1, 0x04, 0x00000001 },
92 { 0x418910, 1, 0x04, 0x00010001 },
93 { 0x418914, 1, 0x04, 0x00000301 },
94 { 0x418918, 1, 0x04, 0x00800000 },
95 { 0x418980, 1, 0x04, 0x77777770 },
96 { 0x418984, 3, 0x04, 0x77777777 },
97 { 0x418c04, 1, 0x04, 0x00000000 },
98 { 0x418c64, 1, 0x04, 0x00000000 },
99 { 0x418c68, 1, 0x04, 0x00000000 },
100 { 0x418c88, 1, 0x04, 0x00000000 },
101 { 0x418cb4, 2, 0x04, 0x00000000 },
102 { 0x418d00, 1, 0x04, 0x00000000 },
103 { 0x418d28, 1, 0x04, 0x00000000 },
104 { 0x418d2c, 1, 0x04, 0x00000000 },
105 { 0x418f00, 1, 0x04, 0x00000400 },
106 { 0x418f08, 1, 0x04, 0x00000000 },
107 { 0x418f20, 1, 0x04, 0x00000000 },
108 { 0x418f24, 1, 0x04, 0x00000000 },
109 { 0x418e00, 1, 0x04, 0x00000000 },
110 { 0x418e08, 1, 0x04, 0x00000000 },
111 { 0x418e1c, 2, 0x04, 0x00000000 },
112 { 0x41900c, 1, 0x04, 0x00000000 },
113 { 0x419018, 1, 0x04, 0x00000000 },
114 {}
115};
116
117static struct nvc0_graph_init
118nvf0_graph_init_tpc[] = {
119 { 0x419d0c, 1, 0x04, 0x00000000 },
120 { 0x419d10, 1, 0x04, 0x00000014 },
121 { 0x419ab0, 1, 0x04, 0x00000000 },
122 { 0x419ac8, 1, 0x04, 0x00000000 },
123 { 0x419ab8, 1, 0x04, 0x000000e7 },
124 { 0x419aec, 1, 0x04, 0x00000000 },
125 { 0x419abc, 2, 0x04, 0x00000000 },
126 { 0x419ab4, 1, 0x04, 0x00000000 },
127 { 0x419aa8, 2, 0x04, 0x00000000 },
128 { 0x41980c, 1, 0x04, 0x00000010 },
129 { 0x419844, 1, 0x04, 0x00000000 },
130 { 0x419850, 1, 0x04, 0x00000004 },
131 { 0x419854, 2, 0x04, 0x00000000 },
132 { 0x419c98, 1, 0x04, 0x00000000 },
133 { 0x419ca8, 1, 0x04, 0x00000000 },
134 { 0x419cb0, 1, 0x04, 0x01000000 },
135 { 0x419cb4, 1, 0x04, 0x00000000 },
136 { 0x419cb8, 1, 0x04, 0x00b08bea },
137 { 0x419c84, 1, 0x04, 0x00010384 },
138 { 0x419cbc, 1, 0x04, 0x281b3646 },
139 { 0x419cc0, 2, 0x04, 0x00000000 },
140 { 0x419c80, 1, 0x04, 0x00020230 },
141 { 0x419ccc, 2, 0x04, 0x00000000 },
142 { 0x419c0c, 1, 0x04, 0x00000000 },
143 { 0x419e00, 1, 0x04, 0x00000080 },
144 { 0x419ea0, 1, 0x04, 0x00000000 },
145 { 0x419ee4, 1, 0x04, 0x00000000 },
146 { 0x419ea4, 1, 0x04, 0x00000100 },
147 { 0x419ea8, 1, 0x04, 0x00000000 },
148 { 0x419eb4, 1, 0x04, 0x00000000 },
149 { 0x419ebc, 2, 0x04, 0x00000000 },
150 { 0x419edc, 1, 0x04, 0x00000000 },
151 { 0x419f00, 1, 0x04, 0x00000000 },
152 { 0x419ed0, 1, 0x04, 0x00003234 },
153 { 0x419f74, 1, 0x04, 0x00015555 },
154 { 0x419f80, 4, 0x04, 0x00000000 },
155 {}
156};
157
158static int
159nvf0_graph_fini(struct nouveau_object *object, bool suspend)
160{
161 struct nvc0_graph_priv *priv = (void *)object;
162 static const struct {
163 u32 addr;
164 u32 data;
165 } magic[] = {
166 { 0x020520, 0xfffffffc },
167 { 0x020524, 0xfffffffe },
168 { 0x020524, 0xfffffffc },
169 { 0x020524, 0xfffffff8 },
170 { 0x020524, 0xffffffe0 },
171 { 0x020530, 0xfffffffe },
172 { 0x02052c, 0xfffffffa },
173 { 0x02052c, 0xfffffff0 },
174 { 0x02052c, 0xffffffc0 },
175 { 0x02052c, 0xffffff00 },
176 { 0x02052c, 0xfffffc00 },
177 { 0x02052c, 0xfffcfc00 },
178 { 0x02052c, 0xfff0fc00 },
179 { 0x02052c, 0xff80fc00 },
180 { 0x020528, 0xfffffffe },
181 { 0x020528, 0xfffffffc },
182 };
183 int i;
184
185 nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
186 nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
187 for (i = 0; i < ARRAY_SIZE(magic); i++) {
188 nv_wr32(priv, magic[i].addr, magic[i].data);
189 nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
190 }
191
192 return nouveau_graph_fini(&priv->base, suspend);
193}
194
195static struct nvc0_graph_init *
196nvf0_graph_init_mmio[] = {
197 nve4_graph_init_regs,
198 nvf0_graph_init_unk40xx,
199 nvc0_graph_init_unk44xx,
200 nvc0_graph_init_unk78xx,
201 nvc0_graph_init_unk60xx,
202 nvd9_graph_init_unk64xx,
203 nvf0_graph_init_unk58xx,
204 nvc0_graph_init_unk80xx,
205 nvf0_graph_init_unk70xx,
206 nvf0_graph_init_unk5bxx,
207 nvf0_graph_init_gpc,
208 nvf0_graph_init_tpc,
209 nve4_graph_init_unk,
210 nve4_graph_init_unk88xx,
211 NULL
212};
213
214#include "fuc/hubnvf0.fuc.h"
215
216static struct nvc0_graph_ucode
217nvf0_graph_fecs_ucode = {
218 .code.data = nvf0_grhub_code,
219 .code.size = sizeof(nvf0_grhub_code),
220 .data.data = nvf0_grhub_data,
221 .data.size = sizeof(nvf0_grhub_data),
222};
223
224#include "fuc/gpcnvf0.fuc.h"
225
226static struct nvc0_graph_ucode
227nvf0_graph_gpccs_ucode = {
228 .code.data = nvf0_grgpc_code,
229 .code.size = sizeof(nvf0_grgpc_code),
230 .data.data = nvf0_grgpc_data,
231 .data.size = sizeof(nvf0_grgpc_data),
232};
233
234struct nouveau_oclass *
235nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
236 .base.handle = NV_ENGINE(GR, 0xf0),
237 .base.ofuncs = &(struct nouveau_ofuncs) {
238 .ctor = nvc0_graph_ctor,
239 .dtor = nvc0_graph_dtor,
240 .init = nve4_graph_init,
241 .fini = nvf0_graph_fini,
242 },
243 .cclass = &nvf0_grctx_oclass,
244 .sclass = nvf0_graph_sclass,
245 .mmio = nvf0_graph_init_mmio,
246 .fecs.ucode = 0 ? &nvf0_graph_fecs_ucode : NULL,
247 .gpccs.ucode = &nvf0_graph_gpccs_ucode,
248}.base;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
index 5d392439f2ac..8e1b52312ddc 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
@@ -61,8 +61,14 @@ extern struct nouveau_oclass nv34_graph_oclass;
61extern struct nouveau_oclass nv35_graph_oclass; 61extern struct nouveau_oclass nv35_graph_oclass;
62extern struct nouveau_oclass nv40_graph_oclass; 62extern struct nouveau_oclass nv40_graph_oclass;
63extern struct nouveau_oclass nv50_graph_oclass; 63extern struct nouveau_oclass nv50_graph_oclass;
64extern struct nouveau_oclass nvc0_graph_oclass; 64extern struct nouveau_oclass *nvc0_graph_oclass;
65extern struct nouveau_oclass nve0_graph_oclass; 65extern struct nouveau_oclass *nvc1_graph_oclass;
66extern struct nouveau_oclass *nvc3_graph_oclass;
67extern struct nouveau_oclass *nvc8_graph_oclass;
68extern struct nouveau_oclass *nvd7_graph_oclass;
69extern struct nouveau_oclass *nvd9_graph_oclass;
70extern struct nouveau_oclass *nve4_graph_oclass;
71extern struct nouveau_oclass *nvf0_graph_oclass;
66 72
67extern const struct nouveau_bitfield nv04_graph_nsource[]; 73extern const struct nouveau_bitfield nv04_graph_nsource[];
68extern struct nouveau_ofuncs nv04_graph_ofuncs; 74extern struct nouveau_ofuncs nv04_graph_ofuncs;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
index af407a8637c7..19e265bf4574 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
@@ -80,7 +80,7 @@ nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
80 80
81struct nouveau_oclass 81struct nouveau_oclass
82nvc0_devinit_oclass = { 82nvc0_devinit_oclass = {
83 .handle = NV_SUBDEV(DEVINIT, 0xa3), 83 .handle = NV_SUBDEV(DEVINIT, 0xc0),
84 .ofuncs = &(struct nouveau_ofuncs) { 84 .ofuncs = &(struct nouveau_ofuncs) {
85 .ctor = nvc0_devinit_ctor, 85 .ctor = nvc0_devinit_ctor,
86 .dtor = _nouveau_devinit_dtor, 86 .dtor = _nouveau_devinit_dtor,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
index 34d3fbfbd631..67fcb6c852ac 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
@@ -365,7 +365,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
365 vm->fpde = offset >> (vmm->pgt_bits + 12); 365 vm->fpde = offset >> (vmm->pgt_bits + 12);
366 vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); 366 vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
367 367
368 vm->pgt = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); 368 vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
369 if (!vm->pgt) { 369 if (!vm->pgt) {
370 kfree(vm); 370 kfree(vm);
371 return -ENOMEM; 371 return -ENOMEM;
@@ -374,7 +374,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
374 ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, 374 ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
375 block >> 12); 375 block >> 12);
376 if (ret) { 376 if (ret) {
377 kfree(vm->pgt); 377 vfree(vm->pgt);
378 kfree(vm); 378 kfree(vm);
379 return ret; 379 return ret;
380 } 380 }
@@ -450,7 +450,7 @@ nouveau_vm_del(struct nouveau_vm *vm)
450 } 450 }
451 451
452 nouveau_mm_fini(&vm->mm); 452 nouveau_mm_fini(&vm->mm);
453 kfree(vm->pgt); 453 vfree(vm->pgt);
454 kfree(vm); 454 kfree(vm);
455} 455}
456 456
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 22:43:11 -0400