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authorTim Bird <tbird20d@gmail.com>2014-04-28 09:34:20 -0400
committerFelipe Balbi <balbi@ti.com>2014-04-30 12:29:51 -0400
commit30bf8667cef5655ddfaedf043f13d03606844213 (patch)
tree6a1a3b176f6d2078d04b838830fd5b56a2384de0
parent9f27984b9e098ce0a35b210ec0315c76108494e4 (diff)
usb: phy: msm: Select secondary PHY via TCSR
Select the secondary PHY using the TCSR register, if phy-num=1 in the DTS (or phy_number is set in the platform data). The SOC has 2 PHYs which can be used with the OTG port, and this code allows configuring the correct one. Note: This resolves the problem I was seeing where I couldn't get the USB driver working at all on a dragonboard, from cold boot. This patch depends on patch 5/14 from Ivan's msm USB patch set. It does not use DT for the register address, as there's no evidence that this address changes between SoC versions. Signed-off-by: Tim Bird <tim.bird@sonymobile.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
-rw-r--r--drivers/usb/phy/phy-msm-usb.c14
-rw-r--r--include/linux/usb/msm_hsusb_hw.h3
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index db8d96377620..9437bcf8c367 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -1489,6 +1489,7 @@ static int msm_otg_probe(struct platform_device *pdev)
1489 struct resource *res; 1489 struct resource *res;
1490 struct msm_otg *motg; 1490 struct msm_otg *motg;
1491 struct usb_phy *phy; 1491 struct usb_phy *phy;
1492 void __iomem *phy_select;
1492 1493
1493 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); 1494 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1494 if (!motg) { 1495 if (!motg) {
@@ -1553,6 +1554,19 @@ static int msm_otg_probe(struct platform_device *pdev)
1553 if (IS_ERR(motg->regs)) 1554 if (IS_ERR(motg->regs))
1554 return PTR_ERR(motg->regs); 1555 return PTR_ERR(motg->regs);
1555 1556
1557 /*
1558 * NOTE: The PHYs can be multiplexed between the chipidea controller
1559 * and the dwc3 controller, using a single bit. It is important that
1560 * the dwc3 driver does not set this bit in an incompatible way.
1561 */
1562 if (motg->phy_number) {
1563 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1564 if (IS_ERR(phy_select))
1565 return PTR_ERR(phy_select);
1566 /* Enable second PHY with the OTG port */
1567 writel_relaxed(0x1, phy_select);
1568 }
1569
1556 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); 1570 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1557 1571
1558 motg->irq = platform_get_irq(pdev, 0); 1572 motg->irq = platform_get_irq(pdev, 0);
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 98d3dd8976e5..a29f6030afb1 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -16,6 +16,9 @@
16#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__ 16#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__
17#define __LINUX_USB_GADGET_MSM72K_UDC_H__ 17#define __LINUX_USB_GADGET_MSM72K_UDC_H__
18 18
19/* USB phy selector - in TCSR address range */
20#define USB2_PHY_SEL 0xfd4ab000
21
19#define USB_AHBBURST (MSM_USB_BASE + 0x0090) 22#define USB_AHBBURST (MSM_USB_BASE + 0x0090)
20#define USB_AHBMODE (MSM_USB_BASE + 0x0098) 23#define USB_AHBMODE (MSM_USB_BASE + 0x0098)
21#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ 24#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */