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authorGregory CLEMENT <gregory.clement@free-electrons.com>2012-11-17 09:22:25 -0500
committerThomas Petazzoni <thomas.petazzoni@free-electrons.com>2012-11-20 08:46:49 -0500
commit307c2bf467e3682c6df1b8186365224fd2d581d3 (patch)
treee746efe036e9e5bf44599239f3edf5f1106d5b18
parent9d2027830c6306b079d5e888d40ec1f2efebd6ad (diff)
clocksource: convert time-armada-370-xp to clk framework
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
-rw-r--r--Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt1
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts4
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi1
-rw-r--r--drivers/clocksource/time-armada-370-xp.c11
4 files changed, 8 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
index 8b6ea2267c94..64830118b013 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
@@ -5,6 +5,7 @@ Required properties:
5- compatible: Should be "marvell,armada-370-xp-timer" 5- compatible: Should be "marvell,armada-370-xp-timer"
6- interrupts: Should contain the list of Global Timer interrupts 6- interrupts: Should contain the list of Global Timer interrupts
7- reg: Should contain the base address of the Global Timer registers 7- reg: Should contain the base address of the Global Timer registers
8- clocks: clock driving the timer hardware
8 9
9Optional properties: 10Optional properties:
10- marvell,timer-25Mhz: Tells whether the Global timer supports the 25 11- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index fffd5c2a3041..4a31b0396623 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -34,9 +34,5 @@
34 clock-frequency = <200000000>; 34 clock-frequency = <200000000>;
35 status = "okay"; 35 status = "okay";
36 }; 36 };
37 timer@d0020300 {
38 clock-frequency = <600000000>;
39 status = "okay";
40 };
41 }; 37 };
42}; 38};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 16cc82cdaa81..94b4b9e03571 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -62,6 +62,7 @@
62 compatible = "marvell,armada-370-xp-timer"; 62 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>; 63 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>; 64 interrupts = <37>, <38>, <39>, <40>;
65 clocks = <&coreclk 2>;
65 }; 66 };
66 67
67 addr-decoding@d0020000 { 68 addr-decoding@d0020000 {
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 4674f94957cd..a4605fd7e303 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/clk.h>
21#include <linux/timer.h> 22#include <linux/timer.h>
22#include <linux/clockchips.h> 23#include <linux/clockchips.h>
23#include <linux/interrupt.h> 24#include <linux/interrupt.h>
@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)
167 u32 u; 168 u32 u;
168 struct device_node *np; 169 struct device_node *np;
169 unsigned int timer_clk; 170 unsigned int timer_clk;
170 int ret;
171 np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer"); 171 np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
172 timer_base = of_iomap(np, 0); 172 timer_base = of_iomap(np, 0);
173 WARN_ON(!timer_base); 173 WARN_ON(!timer_base);
@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void)
179 timer_base + TIMER_CTRL_OFF); 179 timer_base + TIMER_CTRL_OFF);
180 timer_clk = 25000000; 180 timer_clk = 25000000;
181 } else { 181 } else {
182 u32 clk = 0; 182 unsigned long rate = 0;
183 ret = of_property_read_u32(np, "clock-frequency", &clk); 183 struct clk *clk = of_clk_get(np, 0);
184 WARN_ON(!clk || ret < 0); 184 WARN_ON(IS_ERR(clk));
185 rate = clk_get_rate(clk);
185 u = readl(timer_base + TIMER_CTRL_OFF); 186 u = readl(timer_base + TIMER_CTRL_OFF);
186 writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ), 187 writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
187 timer_base + TIMER_CTRL_OFF); 188 timer_base + TIMER_CTRL_OFF);
188 timer_clk = clk / TIMER_DIVIDER; 189 timer_clk = rate / TIMER_DIVIDER;
189 } 190 }
190 191
191 /* We use timer 0 as clocksource, and timer 1 for 192 /* We use timer 0 as clocksource, and timer 1 for