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authorMichal Kazior <michal.kazior@tieto.com>2014-02-27 11:50:05 -0500
committerKalle Valo <kvalo@qca.qualcomm.com>2014-02-28 05:00:30 -0500
commit2f5280da40222fc2d61aa9425c681f615965c003 (patch)
treecd32933dcc17f2a6d76e0c9dae7cd1e4a3d75db8
parent45967089d2685d2327c9710fe796d499d90ae844 (diff)
ath10k: remove pci completion list
One of the premises was to guarantee serialized completion handling for upper layers (HTC/WMI/HTT). Since quite some time now it is no longer necessary. The other premise was to batch up tx/rx completions to take advantage of hot caches. However frame tx/rx completion indications come in on a single pipe already so they are already batched up. More meaningful batching is done in HTT itself. This means PCI completion is no longer necessary to keep around. It just wastes memory, cycles and SLOC. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
-rw-r--r--drivers/net/wireless/ath/ath10k/pci.c275
-rw-r--r--drivers/net/wireless/ath/ath10k/pci.h28
2 files changed, 24 insertions, 279 deletions
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index 2305d583019b..9d242d801d9d 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -58,7 +58,6 @@ static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
58static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address, 58static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
59 u32 *data); 59 u32 *data);
60 60
61static void ath10k_pci_process_ce(struct ath10k *ar);
62static int ath10k_pci_post_rx(struct ath10k *ar); 61static int ath10k_pci_post_rx(struct ath10k *ar);
63static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info, 62static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
64 int num); 63 int num);
@@ -73,7 +72,6 @@ static void ath10k_pci_free_irq(struct ath10k *ar);
73static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, 72static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
74 struct ath10k_ce_pipe *rx_pipe, 73 struct ath10k_ce_pipe *rx_pipe,
75 struct bmi_xfer *xfer); 74 struct bmi_xfer *xfer);
76static void ath10k_pci_cleanup_ce(struct ath10k *ar);
77 75
78static const struct ce_attr host_ce_config_wlan[] = { 76static const struct ce_attr host_ce_config_wlan[] = {
79 /* CE0: host->target HTC control and raw streams */ 77 /* CE0: host->target HTC control and raw streams */
@@ -678,34 +676,12 @@ void ath10k_do_pci_sleep(struct ath10k *ar)
678 } 676 }
679} 677}
680 678
681/*
682 * FIXME: Handle OOM properly.
683 */
684static inline
685struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
686{
687 struct ath10k_pci_compl *compl = NULL;
688
689 spin_lock_bh(&pipe_info->pipe_lock);
690 if (list_empty(&pipe_info->compl_free)) {
691 ath10k_warn("Completion buffers are full\n");
692 goto exit;
693 }
694 compl = list_first_entry(&pipe_info->compl_free,
695 struct ath10k_pci_compl, list);
696 list_del(&compl->list);
697exit:
698 spin_unlock_bh(&pipe_info->pipe_lock);
699 return compl;
700}
701
702/* Called by lower (CE) layer when a send to Target completes. */ 679/* Called by lower (CE) layer when a send to Target completes. */
703static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state) 680static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
704{ 681{
705 struct ath10k *ar = ce_state->ar; 682 struct ath10k *ar = ce_state->ar;
706 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 683 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
707 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 684 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
708 struct ath10k_pci_compl *compl;
709 void *transfer_context; 685 void *transfer_context;
710 u32 ce_data; 686 u32 ce_data;
711 unsigned int nbytes; 687 unsigned int nbytes;
@@ -718,27 +694,8 @@ static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
718 if (transfer_context == NULL) 694 if (transfer_context == NULL)
719 continue; 695 continue;
720 696
721 compl = get_free_compl(pipe_info); 697 cb->tx_completion(ar, transfer_context, transfer_id);
722 if (!compl)
723 break;
724
725 compl->state = ATH10K_PCI_COMPL_SEND;
726 compl->ce_state = ce_state;
727 compl->pipe_info = pipe_info;
728 compl->skb = transfer_context;
729 compl->nbytes = nbytes;
730 compl->transfer_id = transfer_id;
731 compl->flags = 0;
732
733 /*
734 * Add the completion to the processing queue.
735 */
736 spin_lock_bh(&ar_pci->compl_lock);
737 list_add_tail(&compl->list, &ar_pci->compl_process);
738 spin_unlock_bh(&ar_pci->compl_lock);
739 } 698 }
740
741 ath10k_pci_process_ce(ar);
742} 699}
743 700
744/* Called by lower (CE) layer when data is received from the Target. */ 701/* Called by lower (CE) layer when data is received from the Target. */
@@ -747,42 +704,40 @@ static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
747 struct ath10k *ar = ce_state->ar; 704 struct ath10k *ar = ce_state->ar;
748 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 705 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
749 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 706 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
750 struct ath10k_pci_compl *compl; 707 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
751 struct sk_buff *skb; 708 struct sk_buff *skb;
752 void *transfer_context; 709 void *transfer_context;
753 u32 ce_data; 710 u32 ce_data;
754 unsigned int nbytes; 711 unsigned int nbytes, max_nbytes;
755 unsigned int transfer_id; 712 unsigned int transfer_id;
756 unsigned int flags; 713 unsigned int flags;
714 int err;
757 715
758 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 716 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
759 &ce_data, &nbytes, &transfer_id, 717 &ce_data, &nbytes, &transfer_id,
760 &flags) == 0) { 718 &flags) == 0) {
761 compl = get_free_compl(pipe_info); 719 err = ath10k_pci_post_rx_pipe(pipe_info, 1);
762 if (!compl) 720 if (unlikely(err)) {
763 break; 721 /* FIXME: retry */
764 722 ath10k_warn("failed to replenish CE rx ring %d: %d\n",
765 compl->state = ATH10K_PCI_COMPL_RECV; 723 pipe_info->pipe_num, err);
766 compl->ce_state = ce_state; 724 }
767 compl->pipe_info = pipe_info;
768 compl->skb = transfer_context;
769 compl->nbytes = nbytes;
770 compl->transfer_id = transfer_id;
771 compl->flags = flags;
772 725
773 skb = transfer_context; 726 skb = transfer_context;
727 max_nbytes = skb->len + skb_tailroom(skb);
774 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 728 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
775 skb->len + skb_tailroom(skb), 729 max_nbytes, DMA_FROM_DEVICE);
776 DMA_FROM_DEVICE);
777 /*
778 * Add the completion to the processing queue.
779 */
780 spin_lock_bh(&ar_pci->compl_lock);
781 list_add_tail(&compl->list, &ar_pci->compl_process);
782 spin_unlock_bh(&ar_pci->compl_lock);
783 }
784 730
785 ath10k_pci_process_ce(ar); 731 if (unlikely(max_nbytes < nbytes)) {
732 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
733 nbytes, max_nbytes);
734 dev_kfree_skb_any(skb);
735 continue;
736 }
737
738 skb_put(skb, nbytes);
739 cb->rx_completion(ar, skb, pipe_info->pipe_num);
740 }
786} 741}
787 742
788static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 743static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
@@ -931,52 +886,6 @@ static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
931 sizeof(ar_pci->msg_callbacks_current)); 886 sizeof(ar_pci->msg_callbacks_current));
932} 887}
933 888
934static int ath10k_pci_alloc_compl(struct ath10k *ar)
935{
936 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
937 const struct ce_attr *attr;
938 struct ath10k_pci_pipe *pipe_info;
939 struct ath10k_pci_compl *compl;
940 int i, pipe_num, completions;
941
942 spin_lock_init(&ar_pci->compl_lock);
943 INIT_LIST_HEAD(&ar_pci->compl_process);
944
945 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
946 pipe_info = &ar_pci->pipe_info[pipe_num];
947
948 spin_lock_init(&pipe_info->pipe_lock);
949 INIT_LIST_HEAD(&pipe_info->compl_free);
950
951 /* Handle Diagnostic CE specially */
952 if (pipe_info->ce_hdl == ar_pci->ce_diag)
953 continue;
954
955 attr = &host_ce_config_wlan[pipe_num];
956 completions = 0;
957
958 if (attr->src_nentries)
959 completions += attr->src_nentries;
960
961 if (attr->dest_nentries)
962 completions += attr->dest_nentries;
963
964 for (i = 0; i < completions; i++) {
965 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
966 if (!compl) {
967 ath10k_warn("No memory for completion state\n");
968 ath10k_pci_cleanup_ce(ar);
969 return -ENOMEM;
970 }
971
972 compl->state = ATH10K_PCI_COMPL_FREE;
973 list_add_tail(&compl->list, &pipe_info->compl_free);
974 }
975 }
976
977 return 0;
978}
979
980static int ath10k_pci_setup_ce_irq(struct ath10k *ar) 889static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
981{ 890{
982 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 891 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
@@ -1021,131 +930,6 @@ static void ath10k_pci_kill_tasklet(struct ath10k *ar)
1021 tasklet_kill(&ar_pci->pipe_info[i].intr); 930 tasklet_kill(&ar_pci->pipe_info[i].intr);
1022} 931}
1023 932
1024static void ath10k_pci_cleanup_ce(struct ath10k *ar)
1025{
1026 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1027 struct ath10k_pci_compl *compl, *tmp;
1028 struct ath10k_pci_pipe *pipe_info;
1029 struct sk_buff *netbuf;
1030 int pipe_num;
1031
1032 /* Free pending completions. */
1033 spin_lock_bh(&ar_pci->compl_lock);
1034 if (!list_empty(&ar_pci->compl_process))
1035 ath10k_warn("pending completions still present! possible memory leaks.\n");
1036
1037 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
1038 list_del(&compl->list);
1039 netbuf = compl->skb;
1040 dev_kfree_skb_any(netbuf);
1041 kfree(compl);
1042 }
1043 spin_unlock_bh(&ar_pci->compl_lock);
1044
1045 /* Free unused completions for each pipe. */
1046 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1047 pipe_info = &ar_pci->pipe_info[pipe_num];
1048
1049 spin_lock_bh(&pipe_info->pipe_lock);
1050 list_for_each_entry_safe(compl, tmp,
1051 &pipe_info->compl_free, list) {
1052 list_del(&compl->list);
1053 kfree(compl);
1054 }
1055 spin_unlock_bh(&pipe_info->pipe_lock);
1056 }
1057}
1058
1059static void ath10k_pci_process_ce(struct ath10k *ar)
1060{
1061 struct ath10k_pci *ar_pci = ar->hif.priv;
1062 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
1063 struct ath10k_pci_compl *compl;
1064 struct sk_buff *skb;
1065 unsigned int nbytes;
1066 int ret, send_done = 0;
1067
1068 /* Upper layers aren't ready to handle tx/rx completions in parallel so
1069 * we must serialize all completion processing. */
1070
1071 spin_lock_bh(&ar_pci->compl_lock);
1072 if (ar_pci->compl_processing) {
1073 spin_unlock_bh(&ar_pci->compl_lock);
1074 return;
1075 }
1076 ar_pci->compl_processing = true;
1077 spin_unlock_bh(&ar_pci->compl_lock);
1078
1079 for (;;) {
1080 spin_lock_bh(&ar_pci->compl_lock);
1081 if (list_empty(&ar_pci->compl_process)) {
1082 spin_unlock_bh(&ar_pci->compl_lock);
1083 break;
1084 }
1085 compl = list_first_entry(&ar_pci->compl_process,
1086 struct ath10k_pci_compl, list);
1087 list_del(&compl->list);
1088 spin_unlock_bh(&ar_pci->compl_lock);
1089
1090 switch (compl->state) {
1091 case ATH10K_PCI_COMPL_SEND:
1092 cb->tx_completion(ar,
1093 compl->skb,
1094 compl->transfer_id);
1095 send_done = 1;
1096 break;
1097 case ATH10K_PCI_COMPL_RECV:
1098 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
1099 if (ret) {
1100 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1101 compl->pipe_info->pipe_num, ret);
1102 break;
1103 }
1104
1105 skb = compl->skb;
1106 nbytes = compl->nbytes;
1107
1108 ath10k_dbg(ATH10K_DBG_PCI,
1109 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
1110 skb, nbytes);
1111 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
1112 "ath10k rx: ", skb->data, nbytes);
1113
1114 if (skb->len + skb_tailroom(skb) >= nbytes) {
1115 skb_trim(skb, 0);
1116 skb_put(skb, nbytes);
1117 cb->rx_completion(ar, skb,
1118 compl->pipe_info->pipe_num);
1119 } else {
1120 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
1121 nbytes,
1122 skb->len + skb_tailroom(skb));
1123 }
1124 break;
1125 case ATH10K_PCI_COMPL_FREE:
1126 ath10k_warn("free completion cannot be processed\n");
1127 break;
1128 default:
1129 ath10k_warn("invalid completion state (%d)\n",
1130 compl->state);
1131 break;
1132 }
1133
1134 compl->state = ATH10K_PCI_COMPL_FREE;
1135
1136 /*
1137 * Add completion back to the pipe's free list.
1138 */
1139 spin_lock_bh(&compl->pipe_info->pipe_lock);
1140 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
1141 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1142 }
1143
1144 spin_lock_bh(&ar_pci->compl_lock);
1145 ar_pci->compl_processing = false;
1146 spin_unlock_bh(&ar_pci->compl_lock);
1147}
1148
1149/* TODO - temporary mapping while we have too few CE's */ 933/* TODO - temporary mapping while we have too few CE's */
1150static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, 934static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1151 u16 service_id, u8 *ul_pipe, 935 u16 service_id, u8 *ul_pipe,
@@ -1317,17 +1101,11 @@ static int ath10k_pci_hif_start(struct ath10k *ar)
1317 ath10k_pci_free_early_irq(ar); 1101 ath10k_pci_free_early_irq(ar);
1318 ath10k_pci_kill_tasklet(ar); 1102 ath10k_pci_kill_tasklet(ar);
1319 1103
1320 ret = ath10k_pci_alloc_compl(ar);
1321 if (ret) {
1322 ath10k_warn("failed to allocate CE completions: %d\n", ret);
1323 goto err_early_irq;
1324 }
1325
1326 ret = ath10k_pci_request_irq(ar); 1104 ret = ath10k_pci_request_irq(ar);
1327 if (ret) { 1105 if (ret) {
1328 ath10k_warn("failed to post RX buffers for all pipes: %d\n", 1106 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1329 ret); 1107 ret);
1330 goto err_free_compl; 1108 goto err_early_irq;
1331 } 1109 }
1332 1110
1333 ret = ath10k_pci_setup_ce_irq(ar); 1111 ret = ath10k_pci_setup_ce_irq(ar);
@@ -1351,9 +1129,6 @@ err_stop:
1351 ath10k_ce_disable_interrupts(ar); 1129 ath10k_ce_disable_interrupts(ar);
1352 ath10k_pci_free_irq(ar); 1130 ath10k_pci_free_irq(ar);
1353 ath10k_pci_kill_tasklet(ar); 1131 ath10k_pci_kill_tasklet(ar);
1354 ath10k_pci_process_ce(ar);
1355err_free_compl:
1356 ath10k_pci_cleanup_ce(ar);
1357err_early_irq: 1132err_early_irq:
1358 /* Though there should be no interrupts (device was reset) 1133 /* Though there should be no interrupts (device was reset)
1359 * power_down() expects the early IRQ to be installed as per the 1134 * power_down() expects the early IRQ to be installed as per the
@@ -1494,8 +1269,6 @@ static void ath10k_pci_hif_stop(struct ath10k *ar)
1494 * not DMA nor interrupt. We process the leftovers and then free 1269 * not DMA nor interrupt. We process the leftovers and then free
1495 * everything else up. */ 1270 * everything else up. */
1496 1271
1497 ath10k_pci_process_ce(ar);
1498 ath10k_pci_cleanup_ce(ar);
1499 ath10k_pci_buffer_cleanup(ar); 1272 ath10k_pci_buffer_cleanup(ar);
1500 1273
1501 /* Make the sure the device won't access any structures on the host by 1274 /* Make the sure the device won't access any structures on the host by
diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h
index a4f32038c440..b43fdb4f7319 100644
--- a/drivers/net/wireless/ath/ath10k/pci.h
+++ b/drivers/net/wireless/ath/ath10k/pci.h
@@ -43,23 +43,6 @@ struct bmi_xfer {
43 u32 resp_len; 43 u32 resp_len;
44}; 44};
45 45
46enum ath10k_pci_compl_state {
47 ATH10K_PCI_COMPL_FREE = 0,
48 ATH10K_PCI_COMPL_SEND,
49 ATH10K_PCI_COMPL_RECV,
50};
51
52struct ath10k_pci_compl {
53 struct list_head list;
54 enum ath10k_pci_compl_state state;
55 struct ath10k_ce_pipe *ce_state;
56 struct ath10k_pci_pipe *pipe_info;
57 struct sk_buff *skb;
58 unsigned int nbytes;
59 unsigned int transfer_id;
60 unsigned int flags;
61};
62
63/* 46/*
64 * PCI-specific Target state 47 * PCI-specific Target state
65 * 48 *
@@ -175,9 +158,6 @@ struct ath10k_pci_pipe {
175 /* protects compl_free and num_send_allowed */ 158 /* protects compl_free and num_send_allowed */
176 spinlock_t pipe_lock; 159 spinlock_t pipe_lock;
177 160
178 /* List of free CE completion slots */
179 struct list_head compl_free;
180
181 struct ath10k_pci *ar_pci; 161 struct ath10k_pci *ar_pci;
182 struct tasklet_struct intr; 162 struct tasklet_struct intr;
183}; 163};
@@ -205,14 +185,6 @@ struct ath10k_pci {
205 atomic_t keep_awake_count; 185 atomic_t keep_awake_count;
206 bool verified_awake; 186 bool verified_awake;
207 187
208 /* List of CE completions to be processed */
209 struct list_head compl_process;
210
211 /* protects compl_processing and compl_process */
212 spinlock_t compl_lock;
213
214 bool compl_processing;
215
216 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; 188 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
217 189
218 struct ath10k_hif_cb msg_callbacks_current; 190 struct ath10k_hif_cb msg_callbacks_current;