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authorPankaj Dubey <pankaj.dubey@samsung.com>2014-07-18 14:43:22 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-22 19:20:30 -0400
commit2e94ac42898f84d76e3c21dd91bcd1c51c920dff (patch)
tree099ba810bbcaea5849e6c6d9430549631b66c724
parent20fe6f98fae6968b9d6067d49d9ecae9d9593b37 (diff)
ARM: EXYNOS: Refactored code for using PMU address via DT
Under "arm/mach-exynos" many files are using PMU register offsets. Since we have added support for accessing PMU base address via DT, now we can remove PMU mapping from exynosX_iodesc. Let's convert all these access using iomapped address. This will help us in removing static mapping of PMU base address as well as help in reducing dependency over machine header files. Thus helping for migration of PMU implementation from machine to driver folder which can be reused for ARM64 based SoC. Also as we have removed static mappings from "regs-pmu.h" it does not need map.h anymore. But "platsmp.c" needed this and till now it got included indirectly. So lets move header inclusion of "mach/map.h" from "regs-pmu.h" to "platsmp.c". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos/common.h14
-rw-r--r--arch/arm/mach-exynos/exynos.c12
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c8
-rw-r--r--arch/arm/mach-exynos/platsmp.c4
-rw-r--r--arch/arm/mach-exynos/pm.c76
-rw-r--r--arch/arm/mach-exynos/pmu.c40
-rw-r--r--arch/arm/mach-exynos/regs-pmu.h522
-rw-r--r--arch/arm/plat-samsung/include/plat/map-s5p.h1
9 files changed, 339 insertions, 341 deletions
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9cc5617..47b904b3b973 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
134 134
135/* PMU(Power Management Unit) support */ 135/* PMU(Power Management Unit) support */
136 136
137#define PMU_TABLE_END NULL 137#define PMU_TABLE_END (-1U)
138 138
139enum sys_powerdown { 139enum sys_powerdown {
140 SYS_AFTR, 140 SYS_AFTR,
@@ -144,7 +144,7 @@ enum sys_powerdown {
144}; 144};
145 145
146struct exynos_pmu_conf { 146struct exynos_pmu_conf {
147 void __iomem *reg; 147 unsigned int offset;
148 unsigned int val[NUM_SYS_POWERDOWN]; 148 unsigned int val[NUM_SYS_POWERDOWN];
149}; 149};
150 150
@@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
160extern void s5p_init_cpu(void __iomem *cpuid_addr); 160extern void s5p_init_cpu(void __iomem *cpuid_addr);
161extern unsigned int samsung_rev(void); 161extern unsigned int samsung_rev(void);
162 162
163static inline void pmu_raw_writel(u32 val, u32 offset)
164{
165 __raw_writel(val, pmu_base_addr + offset);
166}
167
168static inline u32 pmu_raw_readl(u32 offset)
169{
170 return __raw_readl(pmu_base_addr + offset);
171}
172
163#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 173#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2a43a1734eca..5eaf878af528 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
61 .length = SZ_4K, 61 .length = SZ_4K,
62 .type = MT_DEVICE, 62 .type = MT_DEVICE,
63 }, { 63 }, {
64 .virtual = (unsigned long)S5P_VA_PMU,
65 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
66 .length = SZ_64K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 64 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
70 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), 65 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
71 .length = SZ_4K, 66 .length = SZ_4K,
@@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
139 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 134 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
140 .length = 144 * SZ_1K, 135 .length = 144 * SZ_1K,
141 .type = MT_DEVICE, 136 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S5P_VA_PMU,
144 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
145 .length = SZ_64K,
146 .type = MT_DEVICE,
147 }, 137 },
148}; 138};
149 139
@@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
151{ 141{
152 struct device_node *np; 142 struct device_node *np;
153 u32 val = 0x1; 143 u32 val = 0x1;
154 void __iomem *addr = EXYNOS_SWRESET; 144 void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
155 145
156 if (of_machine_is_compatible("samsung,exynos5440")) { 146 if (of_machine_is_compatible("samsung,exynos5440")) {
157 u32 status; 147 u32 status;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 963002fb15c3..f0b7e92bad6c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -27,9 +27,6 @@
27#define EXYNOS4_PA_SYSCON 0x10010000 27#define EXYNOS4_PA_SYSCON 0x10010000
28#define EXYNOS5_PA_SYSCON 0x10050100 28#define EXYNOS5_PA_SYSCON 0x10050100
29 29
30#define EXYNOS4_PA_PMU 0x10020000
31#define EXYNOS5_PA_PMU 0x10040000
32
33#define EXYNOS4_PA_CMU 0x10030000 30#define EXYNOS4_PA_CMU 0x10030000
34#define EXYNOS5_PA_CMU 0x10010000 31#define EXYNOS5_PA_CMU 0x10010000
35 32
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 9315ba91c1fb..70e8ccd94668 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -55,7 +55,7 @@
55 "dsb\n\t" \ 55 "dsb\n\t" \
56 "ldmfd sp!, {fp, ip}" \ 56 "ldmfd sp!, {fp, ip}" \
57 : \ 57 : \
58 : "Ir" (S5P_INFORM0) \ 58 : "Ir" (pmu_base_addr + S5P_INFORM0) \
59 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 59 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
60 "r9", "r10", "lr", "memory") 60 "r9", "r10", "lr", "memory")
61 61
@@ -337,7 +337,7 @@ static int __init exynos_mcpm_init(void)
337 * To increase the stability of KFC reset we need to program 337 * To increase the stability of KFC reset we need to program
338 * the PMU SPARE3 register 338 * the PMU SPARE3 register
339 */ 339 */
340 __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); 340 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
341 341
342 exynos_mcpm_usage_count_init(); 342 exynos_mcpm_usage_count_init();
343 343
@@ -366,11 +366,11 @@ static int __init exynos_mcpm_init(void)
366 * turned on before the first man is powered up. 366 * turned on before the first man is powered up.
367 */ 367 */
368 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) { 368 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
369 value = __raw_readl(EXYNOS_COMMON_OPTION(i)); 369 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
370 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN | 370 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
371 EXYNOS5420_USE_ARM_CORE_DOWN_STATE | 371 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
372 EXYNOS5420_USE_L2_COMMON_UP_STATE; 372 EXYNOS5420_USE_L2_COMMON_UP_STATE;
373 __raw_writel(value, EXYNOS_COMMON_OPTION(i)); 373 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
374 } 374 }
375 375
376 /* 376 /*
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a43822698361..7c829989859c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,6 +26,8 @@
26#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
27#include <asm/firmware.h> 27#include <asm/firmware.h>
28 28
29#include <mach/map.h>
30
29#include "common.h" 31#include "common.h"
30#include "regs-pmu.h" 32#include "regs-pmu.h"
31 33
@@ -34,7 +36,7 @@ extern void exynos4_secondary_startup(void);
34static inline void __iomem *cpu_boot_reg_base(void) 36static inline void __iomem *cpu_boot_reg_base(void)
35{ 37{
36 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 38 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
37 return S5P_INFORM5; 39 return pmu_base_addr + S5P_INFORM5;
38 return sysram_base_addr; 40 return sysram_base_addr;
39} 41}
40 42
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f127c0cefbb8..bcb96be1efee 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -111,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
111 */ 111 */
112void exynos_cpu_power_down(int cpu) 112void exynos_cpu_power_down(int cpu)
113{ 113{
114 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 114 pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
115} 115}
116 116
117/** 117/**
@@ -122,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
122 */ 122 */
123void exynos_cpu_power_up(int cpu) 123void exynos_cpu_power_up(int cpu)
124{ 124{
125 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 125 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
126 EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 126 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
127} 127}
128 128
129/** 129/**
@@ -133,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
133 */ 133 */
134int exynos_cpu_power_state(int cpu) 134int exynos_cpu_power_state(int cpu)
135{ 135{
136 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 136 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
137 S5P_CORE_LOCAL_PWR_EN); 137 S5P_CORE_LOCAL_PWR_EN);
138} 138}
139 139
@@ -143,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
143 */ 143 */
144void exynos_cluster_power_down(int cluster) 144void exynos_cluster_power_down(int cluster)
145{ 145{
146 __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 146 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
147} 147}
148 148
149/** 149/**
@@ -152,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
152 */ 152 */
153void exynos_cluster_power_up(int cluster) 153void exynos_cluster_power_up(int cluster)
154{ 154{
155 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 155 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
156 EXYNOS_COMMON_CONFIGURATION(cluster)); 156 EXYNOS_COMMON_CONFIGURATION(cluster));
157} 157}
158 158
159/** 159/**
@@ -163,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
163 */ 163 */
164int exynos_cluster_power_state(int cluster) 164int exynos_cluster_power_state(int cluster)
165{ 165{
166 return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 166 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
167 S5P_CORE_LOCAL_PWR_EN); 167 S5P_CORE_LOCAL_PWR_EN);
168} 168}
169 169
170#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 170#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
171 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 171 pmu_base_addr + S5P_INFORM7 : \
172 (sysram_base_addr + 0x24) : S5P_INFORM0)) 172 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
173 (sysram_base_addr + 0x24) : \
174 pmu_base_addr + S5P_INFORM0))
173#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 175#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
174 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 176 pmu_base_addr + S5P_INFORM6 : \
175 (sysram_base_addr + 0x20) : S5P_INFORM1)) 177 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
178 (sysram_base_addr + 0x20) : \
179 pmu_base_addr + S5P_INFORM1))
176 180
177#define S5P_CHECK_AFTR 0xFCBA0D10 181#define S5P_CHECK_AFTR 0xFCBA0D10
178#define S5P_CHECK_SLEEP 0x00000BAD 182#define S5P_CHECK_SLEEP 0x00000BAD
@@ -180,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
180/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 184/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
181static void exynos_set_wakeupmask(long mask) 185static void exynos_set_wakeupmask(long mask)
182{ 186{
183 __raw_writel(mask, S5P_WAKEUP_MASK); 187 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
184} 188}
185 189
186static void exynos_cpu_set_boot_vector(long flags) 190static void exynos_cpu_set_boot_vector(long flags)
@@ -257,27 +261,27 @@ static void exynos_pm_prepare(void)
257 unsigned int tmp; 261 unsigned int tmp;
258 262
259 /* Set wake-up mask registers */ 263 /* Set wake-up mask registers */
260 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 264 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
261 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 265 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
262 266
263 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 267 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
264 268
265 if (soc_is_exynos5250()) { 269 if (soc_is_exynos5250()) {
266 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 270 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
267 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 271 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
268 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 272 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
269 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 273 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
270 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 274 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
271 } 275 }
272 276
273 /* Set value of power down register for sleep mode */ 277 /* Set value of power down register for sleep mode */
274 278
275 exynos_sys_powerdown_conf(SYS_SLEEP); 279 exynos_sys_powerdown_conf(SYS_SLEEP);
276 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 280 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
277 281
278 /* ensure at least INFORM0 has the resume address */ 282 /* ensure at least INFORM0 has the resume address */
279 283
280 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 284 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
281} 285}
282 286
283static void exynos_pm_central_suspend(void) 287static void exynos_pm_central_suspend(void)
@@ -285,9 +289,9 @@ static void exynos_pm_central_suspend(void)
285 unsigned long tmp; 289 unsigned long tmp;
286 290
287 /* Setting Central Sequence Register for power down mode */ 291 /* Setting Central Sequence Register for power down mode */
288 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 292 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
289 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 293 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
290 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 294 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
291} 295}
292 296
293static int exynos_pm_suspend(void) 297static int exynos_pm_suspend(void)
@@ -299,7 +303,7 @@ static int exynos_pm_suspend(void)
299 /* Setting SEQ_OPTION register */ 303 /* Setting SEQ_OPTION register */
300 304
301 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 305 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
302 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 306 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
303 307
304 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 308 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
305 exynos_cpu_save_register(); 309 exynos_cpu_save_register();
@@ -317,12 +321,12 @@ static int exynos_pm_central_resume(void)
317 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 321 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
318 * in this situation. 322 * in this situation.
319 */ 323 */
320 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 324 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
321 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 325 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
322 tmp |= S5P_CENTRAL_LOWPWR_CFG; 326 tmp |= S5P_CENTRAL_LOWPWR_CFG;
323 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 327 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
324 /* clear the wakeup state register */ 328 /* clear the wakeup state register */
325 __raw_writel(0x0, S5P_WAKEUP_STAT); 329 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
326 /* No need to perform below restore code */ 330 /* No need to perform below restore code */
327 return -1; 331 return -1;
328 } 332 }
@@ -340,13 +344,13 @@ static void exynos_pm_resume(void)
340 344
341 /* For release retention */ 345 /* For release retention */
342 346
343 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 347 pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
344 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 348 pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
345 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 349 pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
346 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 350 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
347 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 351 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
348 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 352 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
349 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 353 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
350 354
351 if (soc_is_exynos5250()) 355 if (soc_is_exynos5250())
352 s3c_pm_do_restore(exynos5_sys_save, 356 s3c_pm_do_restore(exynos5_sys_save,
@@ -360,7 +364,7 @@ static void exynos_pm_resume(void)
360early_wakeup: 364early_wakeup:
361 365
362 /* Clear SLEEP mode set in INFORM1 */ 366 /* Clear SLEEP mode set in INFORM1 */
363 __raw_writel(0x0, S5P_INFORM1); 367 pmu_raw_writel(0x0, S5P_INFORM1);
364 368
365 return; 369 return;
366} 370}
@@ -404,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
404 s3c_pm_restore_uarts(); 408 s3c_pm_restore_uarts();
405 409
406 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 410 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
407 __raw_readl(S5P_WAKEUP_STAT)); 411 pmu_raw_readl(S5P_WAKEUP_STAT));
408 412
409 s3c_pm_check_restore(); 413 s3c_pm_check_restore();
410 414
@@ -475,9 +479,9 @@ void __init exynos_pm_init(void)
475 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 479 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
476 480
477 /* All wakeup disable */ 481 /* All wakeup disable */
478 tmp = __raw_readl(S5P_WAKEUP_MASK); 482 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
479 tmp |= ((0xFF << 8) | (0x1F << 1)); 483 tmp |= ((0xFF << 8) | (0x1F << 1));
480 __raw_writel(tmp, S5P_WAKEUP_MASK); 484 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
481 485
482 register_syscore_ops(&exynos_pm_syscore_ops); 486 register_syscore_ops(&exynos_pm_syscore_ops);
483 suspend_set_ops(&exynos_suspend_ops); 487 suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index dcfcb44c3c55..ff9d23f0a7d9 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -18,7 +18,7 @@
18static const struct exynos_pmu_conf *exynos_pmu_config; 18static const struct exynos_pmu_conf *exynos_pmu_config;
19 19
20static const struct exynos_pmu_conf exynos4210_pmu_config[] = { 20static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
21 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 21 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
212}; 212};
213 213
214static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 214static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
215 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 215 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
315 { PMU_TABLE_END,}, 315 { PMU_TABLE_END,},
316}; 316};
317 317
318static void __iomem * const exynos5_list_both_cnt_feed[] = { 318static unsigned int const exynos5_list_both_cnt_feed[] = {
319 EXYNOS5_ARM_CORE0_OPTION, 319 EXYNOS5_ARM_CORE0_OPTION,
320 EXYNOS5_ARM_CORE1_OPTION, 320 EXYNOS5_ARM_CORE1_OPTION,
321 EXYNOS5_ARM_COMMON_OPTION, 321 EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
329 EXYNOS5_TOP_PWR_SYSMEM_OPTION, 329 EXYNOS5_TOP_PWR_SYSMEM_OPTION,
330}; 330};
331 331
332static void __iomem * const exynos5_list_diable_wfi_wfe[] = { 332static unsigned int const exynos5_list_diable_wfi_wfe[] = {
333 EXYNOS5_ARM_CORE1_OPTION, 333 EXYNOS5_ARM_CORE1_OPTION,
334 EXYNOS5_FSYS_ARM_OPTION, 334 EXYNOS5_FSYS_ARM_OPTION,
335 EXYNOS5_ISP_ARM_OPTION, 335 EXYNOS5_ISP_ARM_OPTION,
@@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
344 * Enable both SC_FEEDBACK and SC_COUNTER 344 * Enable both SC_FEEDBACK and SC_COUNTER
345 */ 345 */
346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) { 346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
347 tmp = __raw_readl(exynos5_list_both_cnt_feed[i]); 347 tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
348 tmp |= (EXYNOS5_USE_SC_FEEDBACK | 348 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
349 EXYNOS5_USE_SC_COUNTER); 349 EXYNOS5_USE_SC_COUNTER);
350 __raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 350 pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
351 } 351 }
352 352
353 /* 353 /*
354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
355 */ 355 */
356 tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); 356 tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
358 __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 358 pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
359 359
360 /* 360 /*
361 * Disable WFI/WFE on XXX_OPTION 361 * Disable WFI/WFE on XXX_OPTION
362 */ 362 */
363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) { 363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
364 tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]); 364 tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
366 EXYNOS5_OPTION_USE_STANDBYWFI); 366 EXYNOS5_OPTION_USE_STANDBYWFI);
367 __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]); 367 pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
368 } 368 }
369} 369}
370 370
@@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
375 if (soc_is_exynos5250()) 375 if (soc_is_exynos5250())
376 exynos5_init_pmu(); 376 exynos5_init_pmu();
377 377
378 for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++) 378 for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
379 __raw_writel(exynos_pmu_config[i].val[mode], 379 pmu_raw_writel(exynos_pmu_config[i].val[mode],
380 exynos_pmu_config[i].reg); 380 exynos_pmu_config[i].offset);
381 381
382 if (soc_is_exynos4412()) { 382 if (soc_is_exynos4412()) {
383 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) 383 for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
384 __raw_writel(exynos4412_pmu_config[i].val[mode], 384 pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
385 exynos4412_pmu_config[i].reg); 385 exynos4412_pmu_config[i].offset);
386 } 386 }
387} 387}
388 388
@@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
403 * When SYS_WDTRESET is set, watchdog timer reset request 403 * When SYS_WDTRESET is set, watchdog timer reset request
404 * is ignored by power management unit. 404 * is ignored by power management unit.
405 */ 405 */
406 value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 406 value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
407 value &= ~EXYNOS5_SYS_WDTRESET; 407 value &= ~EXYNOS5_SYS_WDTRESET;
408 __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 408 pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
409 409
410 value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 410 value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
411 value &= ~EXYNOS5_SYS_WDTRESET; 411 value &= ~EXYNOS5_SYS_WDTRESET;
412 __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 412 pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
413 413
414 exynos_pmu_config = exynos5250_pmu_config; 414 exynos_pmu_config = exynos5250_pmu_config;
415 pr_info("EXYNOS5250 PMU Initialize\n"); 415 pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index e5e298c0fd01..96a1569262b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,106 +12,102 @@
12#ifndef __ASM_ARCH_REGS_PMU_H 12#ifndef __ASM_ARCH_REGS_PMU_H
13#define __ASM_ARCH_REGS_PMU_H __FILE__ 13#define __ASM_ARCH_REGS_PMU_H __FILE__
14 14
15#include <mach/map.h> 15#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
16
17#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
18
19#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
20 16
21#define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 17#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
22 18
23#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) 19#define S5P_CENTRAL_SEQ_OPTION 0x0208
24 20
25#define S5P_USE_STANDBY_WFI0 (1 << 16) 21#define S5P_USE_STANDBY_WFI0 (1 << 16)
26#define S5P_USE_STANDBY_WFE0 (1 << 24) 22#define S5P_USE_STANDBY_WFE0 (1 << 24)
27 23
28#define EXYNOS_SWRESET S5P_PMUREG(0x0400) 24#define EXYNOS_SWRESET 0x0400
29#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) 25#define EXYNOS5440_SWRESET 0x00C4
30 26
31#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 27#define S5P_WAKEUP_STAT 0x0600
32#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 28#define S5P_EINT_WAKEUP_MASK 0x0604
33#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 29#define S5P_WAKEUP_MASK 0x0608
34 30
35#define S5P_INFORM0 S5P_PMUREG(0x0800) 31#define S5P_INFORM0 0x0800
36#define S5P_INFORM1 S5P_PMUREG(0x0804) 32#define S5P_INFORM1 0x0804
37#define S5P_INFORM5 S5P_PMUREG(0x0814) 33#define S5P_INFORM5 0x0814
38#define S5P_INFORM6 S5P_PMUREG(0x0818) 34#define S5P_INFORM6 0x0818
39#define S5P_INFORM7 S5P_PMUREG(0x081C) 35#define S5P_INFORM7 0x081C
40#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C) 36#define S5P_PMU_SPARE3 0x090C
41 37
42#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) 38#define S5P_ARM_CORE0_LOWPWR 0x1000
43#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) 39#define S5P_DIS_IRQ_CORE0 0x1004
44#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) 40#define S5P_DIS_IRQ_CENTRAL0 0x1008
45#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) 41#define S5P_ARM_CORE1_LOWPWR 0x1010
46#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) 42#define S5P_DIS_IRQ_CORE1 0x1014
47#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) 43#define S5P_DIS_IRQ_CENTRAL1 0x1018
48#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) 44#define S5P_ARM_COMMON_LOWPWR 0x1080
49#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) 45#define S5P_L2_0_LOWPWR 0x10C0
50#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) 46#define S5P_L2_1_LOWPWR 0x10C4
51#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) 47#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
52#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) 48#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
53#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) 49#define S5P_CMU_RESET_LOWPWR 0x110C
54#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) 50#define S5P_APLL_SYSCLK_LOWPWR 0x1120
55#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) 51#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
56#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) 52#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
57#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) 53#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
58#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) 54#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
59#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) 55#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
60#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) 56#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
61#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) 57#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
62#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 58#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
63#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 59#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
64#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 60#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
65#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 61#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
66#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 62#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
67#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 63#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
68#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) 64#define S5P_CMU_RESET_TV_LOWPWR 0x1164
69#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 65#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
70#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 66#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
71#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 67#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
72#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 68#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
73#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 69#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
74#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 70#define S5P_TOP_BUS_LOWPWR 0x1180
75#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) 71#define S5P_TOP_RETENTION_LOWPWR 0x1184
76#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 72#define S5P_TOP_PWR_LOWPWR 0x1188
77#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 73#define S5P_LOGIC_RESET_LOWPWR 0x11A0
78#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 74#define S5P_ONENAND_MEM_LOWPWR 0x11C0
79#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 75#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
80#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 76#define S5P_USBOTG_MEM_LOWPWR 0x11CC
81#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 77#define S5P_HSMMC_MEM_LOWPWR 0x11D0
82#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 78#define S5P_CSSYS_MEM_LOWPWR 0x11D4
83#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 79#define S5P_SECSS_MEM_LOWPWR 0x11D8
84#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 80#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
85#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 81#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
86#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 82#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
87#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) 83#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
88#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) 84#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
89#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) 85#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
90#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) 86#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
91#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) 87#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
92#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) 88#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
93#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) 89#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
94#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) 90#define S5P_XUSBXTI_LOWPWR 0x1280
95#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) 91#define S5P_XXTI_LOWPWR 0x1284
96#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) 92#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
97#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) 93#define S5P_GPIO_MODE_LOWPWR 0x1300
98#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) 94#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
99#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) 95#define S5P_CAM_LOWPWR 0x1380
100#define S5P_TV_LOWPWR S5P_PMUREG(0x1384) 96#define S5P_TV_LOWPWR 0x1384
101#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 97#define S5P_MFC_LOWPWR 0x1388
102#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 98#define S5P_G3D_LOWPWR 0x138C
103#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 99#define S5P_LCD0_LOWPWR 0x1390
104#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 100#define S5P_MAUDIO_LOWPWR 0x1398
105#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 101#define S5P_GPS_LOWPWR 0x139C
106#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 102#define S5P_GPS_ALIVE_LOWPWR 0x13A0
107 103
108#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) 104#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
109#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 105#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
110 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 106 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
111#define EXYNOS_ARM_CORE_STATUS(_nr) \ 107#define EXYNOS_ARM_CORE_STATUS(_nr) \
112 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 108 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
113 109
114#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500) 110#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
115#define EXYNOS_COMMON_CONFIGURATION(_nr) \ 111#define EXYNOS_COMMON_CONFIGURATION(_nr) \
116 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 112 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
117#define EXYNOS_COMMON_STATUS(_nr) \ 113#define EXYNOS_COMMON_STATUS(_nr) \
@@ -119,195 +115,195 @@
119#define EXYNOS_COMMON_OPTION(_nr) \ 115#define EXYNOS_COMMON_OPTION(_nr) \
120 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 116 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
121 117
122#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) 118#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
123#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) 119#define S5P_PAD_RET_GPIO_OPTION 0x3108
124#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) 120#define S5P_PAD_RET_UART_OPTION 0x3128
125#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) 121#define S5P_PAD_RET_MMCA_OPTION 0x3148
126#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) 122#define S5P_PAD_RET_MMCB_OPTION 0x3168
127#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) 123#define S5P_PAD_RET_EBIA_OPTION 0x3188
128#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) 124#define S5P_PAD_RET_EBIB_OPTION 0x31A8
129 125
130#define S5P_CORE_LOCAL_PWR_EN 0x3 126#define S5P_CORE_LOCAL_PWR_EN 0x3
131 127
132/* Only for EXYNOS4210 */ 128/* Only for EXYNOS4210 */
133#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) 129#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
134#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) 130#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
135#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) 131#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
136#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) 132#define S5P_PCIE_MEM_LOWPWR 0x11E0
137#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) 133#define S5P_SATA_MEM_LOWPWR 0x11E4
138#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) 134#define S5P_LCD1_LOWPWR 0x1394
139 135
140/* Only for EXYNOS4x12 */ 136/* Only for EXYNOS4x12 */
141#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 137#define S5P_ISP_ARM_LOWPWR 0x1050
142#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 138#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
143#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 139#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
144#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) 140#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
145#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) 141#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
146#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) 142#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
147#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) 143#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
148#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) 144#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
149#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) 145#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
150#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) 146#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
151#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) 147#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
152#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) 148#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
153#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) 149#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
154#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) 150#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
155#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) 151#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
156#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) 152#define S5P_HSI_MEM_LOWPWR 0x11C4
157#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) 153#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
158#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) 154#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
159#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) 155#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
160#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) 156#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
161#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) 157#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
162#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) 158#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
163#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) 159#define S5P_ISP_LOWPWR 0x1394
164#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) 160#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
165#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) 161#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
166#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) 162#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
167#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) 163#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
168#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) 164#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
169 165
170#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) 166#define S5P_ARM_L2_0_OPTION 0x2608
171#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) 167#define S5P_ARM_L2_1_OPTION 0x2628
172#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) 168#define S5P_ONENAND_MEM_OPTION 0x2E08
173#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) 169#define S5P_HSI_MEM_OPTION 0x2E28
174#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) 170#define S5P_G2D_ACP_MEM_OPTION 0x2E48
175#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) 171#define S5P_USBOTG_MEM_OPTION 0x2E68
176#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) 172#define S5P_HSMMC_MEM_OPTION 0x2E88
177#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) 173#define S5P_CSSYS_MEM_OPTION 0x2EA8
178#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 174#define S5P_SECSS_MEM_OPTION 0x2EC8
179#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 175#define S5P_ROTATOR_MEM_OPTION 0x2F48
180 176
181/* Only for EXYNOS4412 */ 177/* Only for EXYNOS4412 */
182#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) 178#define S5P_ARM_CORE2_LOWPWR 0x1020
183#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) 179#define S5P_DIS_IRQ_CORE2 0x1024
184#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) 180#define S5P_DIS_IRQ_CENTRAL2 0x1028
185#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) 181#define S5P_ARM_CORE3_LOWPWR 0x1030
186#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) 182#define S5P_DIS_IRQ_CORE3 0x1034
187#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) 183#define S5P_DIS_IRQ_CENTRAL3 0x1038
188 184
189/* For EXYNOS5 */ 185/* For EXYNOS5 */
190 186
191#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) 187#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
192#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) 188#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
193 189
194#define EXYNOS5_SYS_WDTRESET (1 << 20) 190#define EXYNOS5_SYS_WDTRESET (1 << 20)
195 191
196#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) 192#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
197#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) 193#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
198#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) 194#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
199#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010) 195#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
200#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014) 196#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
201#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018) 197#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
202#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040) 198#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
203#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048) 199#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
204#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050) 200#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
205#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054) 201#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
206#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058) 202#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
207#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080) 203#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
208#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0) 204#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
209#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100) 205#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
210#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104) 206#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
211#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C) 207#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
212#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120) 208#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
213#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124) 209#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
214#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C) 210#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
215#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130) 211#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
216#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134) 212#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
217#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138) 213#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
218#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140) 214#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
219#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144) 215#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
220#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148) 216#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
221#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C) 217#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
222#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150) 218#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
223#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154) 219#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
224#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164) 220#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
225#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170) 221#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
226#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180) 222#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
227#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184) 223#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
228#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188) 224#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
229#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190) 225#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
230#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194) 226#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
231#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198) 227#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
232#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0) 228#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
233#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4) 229#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
234#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0) 230#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
235#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4) 231#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
236#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0) 232#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
237#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8) 233#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
238#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC) 234#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
239#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0) 235#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
240#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4) 236#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
241#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8) 237#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
242#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC) 238#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
243#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0) 239#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
244#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4) 240#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
245#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8) 241#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
246#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC) 242#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
247#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4) 243#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
248#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC) 244#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
249#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200) 245#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
250#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204) 246#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
251#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208) 247#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
252#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) 248#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
253#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224) 249#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
254#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228) 250#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
255#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C) 251#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
256#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230) 252#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
257#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234) 253#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
258#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238) 254#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
259#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C) 255#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
260#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240) 256#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
261#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250) 257#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
262#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260) 258#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
263#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280) 259#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
264#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284) 260#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
265#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0) 261#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
266#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300) 262#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
267#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320) 263#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
268#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340) 264#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
269#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344) 265#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
270#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348) 266#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
271#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400) 267#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
272#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404) 268#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
273#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408) 269#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
274#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C) 270#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
275#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) 271#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
276#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418) 272#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
277#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480) 273#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
278#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484) 274#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
279#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488) 275#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
280#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C) 276#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
281#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494) 277#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
282#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498) 278#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
283#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0) 279#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
284#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4) 280#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
285#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8) 281#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
286#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC) 282#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
287#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4) 283#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
288#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8) 284#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
289#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580) 285#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
290#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584) 286#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
291#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588) 287#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
292#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C) 288#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
293#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594) 289#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
294#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598) 290#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
295 291
296#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008) 292#define EXYNOS5_ARM_CORE0_OPTION 0x2008
297#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088) 293#define EXYNOS5_ARM_CORE1_OPTION 0x2088
298#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) 294#define EXYNOS5_FSYS_ARM_OPTION 0x2208
299#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) 295#define EXYNOS5_ISP_ARM_OPTION 0x2288
300#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) 296#define EXYNOS5_ARM_COMMON_OPTION 0x2408
301#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) 297#define EXYNOS5_ARM_L2_OPTION 0x2608
302#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) 298#define EXYNOS5_TOP_PWR_OPTION 0x2C48
303#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) 299#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
304#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) 300#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
305#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) 301#define EXYNOS5_GSCL_OPTION 0x4008
306#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) 302#define EXYNOS5_ISP_OPTION 0x4028
307#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) 303#define EXYNOS5_MFC_OPTION 0x4048
308#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) 304#define EXYNOS5_G3D_OPTION 0x4068
309#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) 305#define EXYNOS5_DISP1_OPTION 0x40A8
310#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) 306#define EXYNOS5_MAU_OPTION 0x40C8
311 307
312#define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 308#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
313#define EXYNOS5_USE_SC_COUNTER (1 << 0) 309#define EXYNOS5_USE_SC_COUNTER (1 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c18678610bc0..f5b9d3ff9cd4 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,7 +15,6 @@
15 15
16#define S5P_VA_CHIPID S3C_ADDR(0x02000000) 16#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
17#define S5P_VA_CMU S3C_ADDR(0x02100000) 17#define S5P_VA_CMU S3C_ADDR(0x02100000)
18#define S5P_VA_PMU S3C_ADDR(0x02180000)
19#define S5P_VA_GPIO S3C_ADDR(0x02200000) 18#define S5P_VA_GPIO S3C_ADDR(0x02200000)
20#define S5P_VA_GPIO1 S5P_VA_GPIO 19#define S5P_VA_GPIO1 S5P_VA_GPIO
21#define S5P_VA_GPIO2 S3C_ADDR(0x02240000) 20#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 10:44:23 -0500