msm: gpio: Remove chip-specific register definitions

Put an SOC prefix on each GPIO register definition, eliminating the need to have SOC ifdefs around the definitions. Change-Id: I5a01fd328a89ce1be610847934d6e118f5465e42 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
author: David Brown <davidb@codeaurora.org> 2011-05-12 04:16:46 -0400
committer: David Brown <davidb@codeaurora.org> 2011-08-01 07:57:59 -0400
commit: 2e01d2c593d1cc5ed48cab6c07493185e4ac7a68 (patch)
tree: 4f2af96389d70817cff120a67bc099b8d6bb9eb9
parent: 03db0729b7603202f7d3a2bf2ec7e89a1ad44a17 (diff)
2 files changed, 220 insertions, 226 deletions
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index c358cedcda97..335afbd97c1d 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -25,17 +25,17 @@
 #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
-#define MSM_GPIO_BANK(bank, first, last)                                \
+#define MSM_GPIO_BANK(soc, bank, first, last)                           \
        {                                                               \
                .regs = {                                               \
-                        .out =         MSM_GPIO_OUT_##bank,             \
+                        .out =         soc##_GPIO_OUT_##bank,           \
-                        .in =          MSM_GPIO_IN_##bank,              \
+                        .in =          soc##_GPIO_IN_##bank,            \
-                        .int_status =  MSM_GPIO_INT_STATUS_##bank,      \
+                        .int_status =  soc##_GPIO_INT_STATUS_##bank,    \
-                        .int_clear =   MSM_GPIO_INT_CLEAR_##bank,       \
+                        .int_clear =   soc##_GPIO_INT_CLEAR_##bank,     \
-                        .int_en =      MSM_GPIO_INT_EN_##bank,          \
+                        .int_en =      soc##_GPIO_INT_EN_##bank,        \
-                        .int_edge =    MSM_GPIO_INT_EDGE_##bank,        \
+                        .int_edge =    soc##_GPIO_INT_EDGE_##bank,      \
-                        .int_pos =     MSM_GPIO_INT_POS_##bank,         \
+                        .int_pos =     soc##_GPIO_INT_POS_##bank,       \
-                        .oe =          MSM_GPIO_OE_##bank,              \
+                        .oe =          soc##_GPIO_OE_##bank,            \
                },                                                      \
                .chip = {                                               \
                        .base = (first),                                \
@@ -191,30 +191,30 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 struct msm_gpio_chip msm_gpio_chips[] = {
 #if defined(CONFIG_ARCH_MSM7X00A)
-        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(MSM7X00, 0,   0,  15),
-        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(MSM7X00, 1,  16,  42),
-        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(MSM7X00, 2,  43,  67),
-        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(MSM7X00, 3,  68,  94),
-        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(MSM7X00, 4,  95, 106),
-        MSM_GPIO_BANK(5, 107, 121),
+        MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
 #elif defined(CONFIG_ARCH_MSM7X30)
-        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(MSM7X30, 0,   0,  15),
-        MSM_GPIO_BANK(1,  16,  43),
+        MSM_GPIO_BANK(MSM7X30, 1,  16,  43),
-        MSM_GPIO_BANK(2,  44,  67),
+        MSM_GPIO_BANK(MSM7X30, 2,  44,  67),
-        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(MSM7X30, 3,  68,  94),
-        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(MSM7X30, 4,  95, 106),
-        MSM_GPIO_BANK(5, 107, 133),
+        MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
-        MSM_GPIO_BANK(6, 134, 150),
+        MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
-        MSM_GPIO_BANK(7, 151, 181),
+        MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
 #elif defined(CONFIG_ARCH_QSD8X50)
-        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(QSD8X50, 0,   0,  15),
-        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(QSD8X50, 1,  16,  42),
-        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(QSD8X50, 2,  43,  67),
-        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(QSD8X50, 3,  68,  94),
-        MSM_GPIO_BANK(4,  95, 103),
+        MSM_GPIO_BANK(QSD8X50, 4,  95, 103),
-        MSM_GPIO_BANK(5, 104, 121),
+        MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
-        MSM_GPIO_BANK(6, 122, 152),
+        MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
-        MSM_GPIO_BANK(7, 153, 164),
+        MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
 #endif
 };
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
index 6b5066038baa..ba7972ade8c5 100644
--- a/arch/arm/mach-msm/gpio_hw.h
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -31,248 +31,242 @@
 ** macros.
 */
-#if defined(CONFIG_ARCH_MSM7X30)
 #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
 #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
-#else
+#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
-#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
-#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
-#endif
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
-    defined(CONFIG_ARCH_MSM7X27)
+/*
+ * MSM7X00 registers
+ */
 /* output value */
-#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0  */
+#define MSM7X00_GPIO_OUT_0      MSM_GPIO1_SHADOW_REG(0x00)  /* gpio  15-0  */
-#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16 */
+#define MSM7X00_GPIO_OUT_1      MSM_GPIO2_SHADOW_REG(0x00)  /* gpio  42-16 */
-#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43 */
+#define MSM7X00_GPIO_OUT_2      MSM_GPIO1_SHADOW_REG(0x04)  /* gpio  67-43 */
-#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68 */
+#define MSM7X00_GPIO_OUT_3      MSM_GPIO1_SHADOW_REG(0x08)  /* gpio  94-68 */
-#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 106-95 */
+#define MSM7X00_GPIO_OUT_4      MSM_GPIO1_SHADOW_REG(0x0C)  /* gpio 106-95 */
-#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)  /* gpio 107-121 */
+#define MSM7X00_GPIO_OUT_5      MSM_GPIO1_SHADOW_REG(0x50)  /* gpio 107-121 */
 /* same pin map as above, output enable */
-#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)
+#define MSM7X00_GPIO_OE_0       MSM_GPIO1_SHADOW_REG(0x10)
-#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM7X00_GPIO_OE_1       MSM_GPIO2_SHADOW_REG(0x08)
-#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)
+#define MSM7X00_GPIO_OE_2       MSM_GPIO1_SHADOW_REG(0x14)
-#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)
+#define MSM7X00_GPIO_OE_3       MSM_GPIO1_SHADOW_REG(0x18)
-#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)
+#define MSM7X00_GPIO_OE_4       MSM_GPIO1_SHADOW_REG(0x1C)
-#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)
+#define MSM7X00_GPIO_OE_5       MSM_GPIO1_SHADOW_REG(0x54)
 /* same pin map as above, input read */
-#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)
+#define MSM7X00_GPIO_IN_0       MSM_GPIO1_SHADOW_REG(0x34)
-#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM7X00_GPIO_IN_1       MSM_GPIO2_SHADOW_REG(0x20)
-#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)
+#define MSM7X00_GPIO_IN_2       MSM_GPIO1_SHADOW_REG(0x38)
-#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)
+#define MSM7X00_GPIO_IN_3       MSM_GPIO1_SHADOW_REG(0x3C)
-#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)
+#define MSM7X00_GPIO_IN_4       MSM_GPIO1_SHADOW_REG(0x40)
-#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)
+#define MSM7X00_GPIO_IN_5       MSM_GPIO1_SHADOW_REG(0x44)
 /* same pin map as above, 1=edge 0=level interrup */
-#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)
+#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
-#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
-#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)
+#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
-#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)
+#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
-#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)
+#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
-#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)
+#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
 /* same pin map as above, 1=positive 0=negative */
-#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)
+#define MSM7X00_GPIO_INT_POS_0  MSM_GPIO1_SHADOW_REG(0x70)
-#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM7X00_GPIO_INT_POS_1  MSM_GPIO2_SHADOW_REG(0x58)
-#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)
+#define MSM7X00_GPIO_INT_POS_2  MSM_GPIO1_SHADOW_REG(0x74)
-#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)
+#define MSM7X00_GPIO_INT_POS_3  MSM_GPIO1_SHADOW_REG(0x78)
-#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)
+#define MSM7X00_GPIO_INT_POS_4  MSM_GPIO1_SHADOW_REG(0x7C)
-#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)
+#define MSM7X00_GPIO_INT_POS_5  MSM_GPIO1_SHADOW_REG(0xBC)
 /* same pin map as above, interrupt enable */
-#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)
+#define MSM7X00_GPIO_INT_EN_0   MSM_GPIO1_SHADOW_REG(0x80)
-#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM7X00_GPIO_INT_EN_1   MSM_GPIO2_SHADOW_REG(0x60)
-#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)
+#define MSM7X00_GPIO_INT_EN_2   MSM_GPIO1_SHADOW_REG(0x84)
-#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)
+#define MSM7X00_GPIO_INT_EN_3   MSM_GPIO1_SHADOW_REG(0x88)
author	David Brown <davidb@codeaurora.org>	2011-05-12 04:16:46 -0400
committer	David Brown <davidb@codeaurora.org>	2011-08-01 07:57:59 -0400
commit	2e01d2c593d1cc5ed48cab6c07493185e4ac7a68 (patch)
tree	4f2af96389d70817cff120a67bc099b8d6bb9eb9
parent	03db0729b7603202f7d3a2bf2ec7e89a1ad44a17 (diff)

diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index c358cedcda97..335afbd97c1d 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c
@@ -25,17 +25,17 @@
25		25
26	#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)	26	#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
27		27
28	#define MSM_GPIO_BANK(bank, first, last) \	28	#define MSM_GPIO_BANK(soc, bank, first, last) \
29	{ \	29	{ \
30	.regs = { \	30	.regs = { \
31	.out = MSM_GPIO_OUT_##bank, \	31	.out = soc##_GPIO_OUT_##bank, \
32	.in = MSM_GPIO_IN_##bank, \	32	.in = soc##_GPIO_IN_##bank, \
33	.int_status = MSM_GPIO_INT_STATUS_##bank, \	33	.int_status = soc##_GPIO_INT_STATUS_##bank, \
34	.int_clear = MSM_GPIO_INT_CLEAR_##bank, \	34	.int_clear = soc##_GPIO_INT_CLEAR_##bank, \
35	.int_en = MSM_GPIO_INT_EN_##bank, \	35	.int_en = soc##_GPIO_INT_EN_##bank, \
36	.int_edge = MSM_GPIO_INT_EDGE_##bank, \	36	.int_edge = soc##_GPIO_INT_EDGE_##bank, \
37	.int_pos = MSM_GPIO_INT_POS_##bank, \	37	.int_pos = soc##_GPIO_INT_POS_##bank, \
38	.oe = MSM_GPIO_OE_##bank, \	38	.oe = soc##_GPIO_OE_##bank, \
39	}, \	39	}, \
40	.chip = { \	40	.chip = { \
41	.base = (first), \	41	.base = (first), \
@@ -191,30 +191,30 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
191		191
192	struct msm_gpio_chip msm_gpio_chips[] = {	192	struct msm_gpio_chip msm_gpio_chips[] = {
193	#if defined(CONFIG_ARCH_MSM7X00A)	193	#if defined(CONFIG_ARCH_MSM7X00A)
194	MSM_GPIO_BANK(0, 0, 15),	194	MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
195	MSM_GPIO_BANK(1, 16, 42),	195	MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
196	MSM_GPIO_BANK(2, 43, 67),	196	MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
197	MSM_GPIO_BANK(3, 68, 94),	197	MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
198	MSM_GPIO_BANK(4, 95, 106),	198	MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
199	MSM_GPIO_BANK(5, 107, 121),	199	MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
200	#elif defined(CONFIG_ARCH_MSM7X30)	200	#elif defined(CONFIG_ARCH_MSM7X30)
201	MSM_GPIO_BANK(0, 0, 15),	201	MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
202	MSM_GPIO_BANK(1, 16, 43),	202	MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
203	MSM_GPIO_BANK(2, 44, 67),	203	MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
204	MSM_GPIO_BANK(3, 68, 94),	204	MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
205	MSM_GPIO_BANK(4, 95, 106),	205	MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
206	MSM_GPIO_BANK(5, 107, 133),	206	MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
207	MSM_GPIO_BANK(6, 134, 150),	207	MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
208	MSM_GPIO_BANK(7, 151, 181),	208	MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
209	#elif defined(CONFIG_ARCH_QSD8X50)	209	#elif defined(CONFIG_ARCH_QSD8X50)
210	MSM_GPIO_BANK(0, 0, 15),	210	MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
211	MSM_GPIO_BANK(1, 16, 42),	211	MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
212	MSM_GPIO_BANK(2, 43, 67),	212	MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
213	MSM_GPIO_BANK(3, 68, 94),	213	MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
214	MSM_GPIO_BANK(4, 95, 103),	214	MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
215	MSM_GPIO_BANK(5, 104, 121),	215	MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
216	MSM_GPIO_BANK(6, 122, 152),	216	MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
217	MSM_GPIO_BANK(7, 153, 164),	217	MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
218	#endif	218	#endif
219	};	219	};
220		220


diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h index 6b5066038baa..ba7972ade8c5 100644 --- a/arch/arm/mach-msm/gpio_hw.h +++ b/arch/arm/mach-msm/gpio_hw.h
@@ -31,248 +31,242 @@
31	** macros.	31	** macros.
32	*/	32	*/
33		33
34	#if defined(CONFIG_ARCH_MSM7X30)
35	#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))	34	#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
36	#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))	35	#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
37	#else	36	#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
38	#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))	37	#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
39	#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
40	#endif
41
42	#if defined(CONFIG_ARCH_MSM7X00A) \|\| defined(CONFIG_ARCH_MSM7X25) \|\|\
43	defined(CONFIG_ARCH_MSM7X27)
44		38
		39	/*
		40	* MSM7X00 registers
		41	*/
45	/* output value */	42	/* output value */
46	#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */	43	#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
47	#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */	44	#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
48	#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */	45	#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
49	#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */	46	#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
50	#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */	47	#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
51	#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */	48	#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
52		49
53	/* same pin map as above, output enable */	50	/* same pin map as above, output enable */
54	#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)	51	#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
55	#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)	52	#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
56	#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)	53	#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
57	#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)	54	#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
58	#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)	55	#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
59	#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)	56	#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
60		57
61	/* same pin map as above, input read */	58	/* same pin map as above, input read */
62	#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)	59	#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
63	#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)	60	#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
64	#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)	61	#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
65	#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)	62	#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
66	#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)	63	#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
67	#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)	64	#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
68		65
69	/* same pin map as above, 1=edge 0=level interrup */	66	/* same pin map as above, 1=edge 0=level interrup */
70	#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)	67	#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
71	#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)	68	#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
72	#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)	69	#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
73	#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)	70	#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
74	#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)	71	#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
75	#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)	72	#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
76		73
77	/* same pin map as above, 1=positive 0=negative */	74	/* same pin map as above, 1=positive 0=negative */
78	#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)	75	#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
79	#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)	76	#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
80	#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)	77	#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
81	#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)	78	#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
82	#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)	79	#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
83	#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)	80	#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
84		81
85	/* same pin map as above, interrupt enable */	82	/* same pin map as above, interrupt enable */
86	#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)	83	#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
87	#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)	84	#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
88	#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)	85	#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
89	#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)	86	#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)