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authorThomas Abraham <thomas.abraham@linaro.org>2013-03-09 03:18:14 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-03-25 05:18:31 -0400
commit2de6847cfc68c45c54922620dbb41cdd821fbaeb (patch)
tree151edf56f6828549bdcc02180b74d66f857b8492
parent7ad34337bc354732736e9e36cbc1c1db67fdd019 (diff)
ARM: dts: add clock provider information for all controllers in Exynos5250 SoC
For all supported peripheral controllers on Exynos5250, add clock lookup information. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi72
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 0fcabd711ec9..f8c9964f367c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -93,6 +93,8 @@
93 interrupt-parent = <&mct_map>; 93 interrupt-parent = <&mct_map>;
94 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 94 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
95 <4 0>, <5 0>; 95 <4 0>, <5 0>;
96 clocks = <&clock 1>, <&clock 335>;
97 clock-names = "fin_pll", "mct";
96 98
97 mct_map: mct-map { 99 mct_map: mct-map {
98 #interrupt-cells = <2>; 100 #interrupt-cells = <2>;
@@ -111,6 +113,8 @@
111 compatible = "samsung,s3c2410-wdt"; 113 compatible = "samsung,s3c2410-wdt";
112 reg = <0x101D0000 0x100>; 114 reg = <0x101D0000 0x100>;
113 interrupts = <0 42 0>; 115 interrupts = <0 42 0>;
116 clocks = <&clock 336>;
117 clock-names = "watchdog";
114 }; 118 };
115 119
116 codec@11000000 { 120 codec@11000000 {
@@ -124,42 +128,56 @@
124 compatible = "samsung,s3c6410-rtc"; 128 compatible = "samsung,s3c6410-rtc";
125 reg = <0x101E0000 0x100>; 129 reg = <0x101E0000 0x100>;
126 interrupts = <0 43 0>, <0 44 0>; 130 interrupts = <0 43 0>, <0 44 0>;
131 clocks = <&clock 337>;
132 clock-names = "rtc";
127 }; 133 };
128 134
129 tmu@10060000 { 135 tmu@10060000 {
130 compatible = "samsung,exynos5250-tmu"; 136 compatible = "samsung,exynos5250-tmu";
131 reg = <0x10060000 0x100>; 137 reg = <0x10060000 0x100>;
132 interrupts = <0 65 0>; 138 interrupts = <0 65 0>;
139 clocks = <&clock 338>;
140 clock-names = "tmu_apbif";
133 }; 141 };
134 142
135 serial@12C00000 { 143 serial@12C00000 {
136 compatible = "samsung,exynos4210-uart"; 144 compatible = "samsung,exynos4210-uart";
137 reg = <0x12C00000 0x100>; 145 reg = <0x12C00000 0x100>;
138 interrupts = <0 51 0>; 146 interrupts = <0 51 0>;
147 clocks = <&clock 289>, <&clock 146>;
148 clock-names = "uart", "clk_uart_baud0";
139 }; 149 };
140 150
141 serial@12C10000 { 151 serial@12C10000 {
142 compatible = "samsung,exynos4210-uart"; 152 compatible = "samsung,exynos4210-uart";
143 reg = <0x12C10000 0x100>; 153 reg = <0x12C10000 0x100>;
144 interrupts = <0 52 0>; 154 interrupts = <0 52 0>;
155 clocks = <&clock 290>, <&clock 147>;
156 clock-names = "uart", "clk_uart_baud0";
145 }; 157 };
146 158
147 serial@12C20000 { 159 serial@12C20000 {
148 compatible = "samsung,exynos4210-uart"; 160 compatible = "samsung,exynos4210-uart";
149 reg = <0x12C20000 0x100>; 161 reg = <0x12C20000 0x100>;
150 interrupts = <0 53 0>; 162 interrupts = <0 53 0>;
163 clocks = <&clock 291>, <&clock 148>;
164 clock-names = "uart", "clk_uart_baud0";
151 }; 165 };
152 166
153 serial@12C30000 { 167 serial@12C30000 {
154 compatible = "samsung,exynos4210-uart"; 168 compatible = "samsung,exynos4210-uart";
155 reg = <0x12C30000 0x100>; 169 reg = <0x12C30000 0x100>;
156 interrupts = <0 54 0>; 170 interrupts = <0 54 0>;
171 clocks = <&clock 292>, <&clock 149>;
172 clock-names = "uart", "clk_uart_baud0";
157 }; 173 };
158 174
159 sata@122F0000 { 175 sata@122F0000 {
160 compatible = "samsung,exynos5-sata-ahci"; 176 compatible = "samsung,exynos5-sata-ahci";
161 reg = <0x122F0000 0x1ff>; 177 reg = <0x122F0000 0x1ff>;
162 interrupts = <0 115 0>; 178 interrupts = <0 115 0>;
179 clocks = <&clock 277>, <&clock 143>;
180 clock-names = "sata", "sclk_sata";
163 }; 181 };
164 182
165 sata-phy@12170000 { 183 sata-phy@12170000 {
@@ -173,6 +191,8 @@
173 interrupts = <0 56 0>; 191 interrupts = <0 56 0>;
174 #address-cells = <1>; 192 #address-cells = <1>;
175 #size-cells = <0>; 193 #size-cells = <0>;
194 clocks = <&clock 294>;
195 clock-names = "i2c";
176 }; 196 };
177 197
178 i2c_1: i2c@12C70000 { 198 i2c_1: i2c@12C70000 {
@@ -181,6 +201,8 @@
181 interrupts = <0 57 0>; 201 interrupts = <0 57 0>;
182 #address-cells = <1>; 202 #address-cells = <1>;
183 #size-cells = <0>; 203 #size-cells = <0>;
204 clocks = <&clock 295>;
205 clock-names = "i2c";
184 }; 206 };
185 207
186 i2c_2: i2c@12C80000 { 208 i2c_2: i2c@12C80000 {
@@ -189,6 +211,8 @@
189 interrupts = <0 58 0>; 211 interrupts = <0 58 0>;
190 #address-cells = <1>; 212 #address-cells = <1>;
191 #size-cells = <0>; 213 #size-cells = <0>;
214 clocks = <&clock 296>;
215 clock-names = "i2c";
192 }; 216 };
193 217
194 i2c_3: i2c@12C90000 { 218 i2c_3: i2c@12C90000 {
@@ -197,6 +221,8 @@
197 interrupts = <0 59 0>; 221 interrupts = <0 59 0>;
198 #address-cells = <1>; 222 #address-cells = <1>;
199 #size-cells = <0>; 223 #size-cells = <0>;
224 clocks = <&clock 297>;
225 clock-names = "i2c";
200 }; 226 };
201 227
202 i2c_4: i2c@12CA0000 { 228 i2c_4: i2c@12CA0000 {
@@ -205,6 +231,8 @@
205 interrupts = <0 60 0>; 231 interrupts = <0 60 0>;
206 #address-cells = <1>; 232 #address-cells = <1>;
207 #size-cells = <0>; 233 #size-cells = <0>;
234 clocks = <&clock 298>;
235 clock-names = "i2c";
208 }; 236 };
209 237
210 i2c_5: i2c@12CB0000 { 238 i2c_5: i2c@12CB0000 {
@@ -213,6 +241,8 @@
213 interrupts = <0 61 0>; 241 interrupts = <0 61 0>;
214 #address-cells = <1>; 242 #address-cells = <1>;
215 #size-cells = <0>; 243 #size-cells = <0>;
244 clocks = <&clock 299>;
245 clock-names = "i2c";
216 }; 246 };
217 247
218 i2c_6: i2c@12CC0000 { 248 i2c_6: i2c@12CC0000 {
@@ -221,6 +251,8 @@
221 interrupts = <0 62 0>; 251 interrupts = <0 62 0>;
222 #address-cells = <1>; 252 #address-cells = <1>;
223 #size-cells = <0>; 253 #size-cells = <0>;
254 clocks = <&clock 300>;
255 clock-names = "i2c";
224 }; 256 };
225 257
226 i2c_7: i2c@12CD0000 { 258 i2c_7: i2c@12CD0000 {
@@ -229,6 +261,8 @@
229 interrupts = <0 63 0>; 261 interrupts = <0 63 0>;
230 #address-cells = <1>; 262 #address-cells = <1>;
231 #size-cells = <0>; 263 #size-cells = <0>;
264 clocks = <&clock 301>;
265 clock-names = "i2c";
232 }; 266 };
233 267
234 i2c_8: i2c@12CE0000 { 268 i2c_8: i2c@12CE0000 {
@@ -237,6 +271,8 @@
237 interrupts = <0 64 0>; 271 interrupts = <0 64 0>;
238 #address-cells = <1>; 272 #address-cells = <1>;
239 #size-cells = <0>; 273 #size-cells = <0>;
274 clocks = <&clock 302>;
275 clock-names = "i2c";
240 }; 276 };
241 277
242 i2c@121D0000 { 278 i2c@121D0000 {
@@ -244,6 +280,8 @@
244 reg = <0x121D0000 0x100>; 280 reg = <0x121D0000 0x100>;
245 #address-cells = <1>; 281 #address-cells = <1>;
246 #size-cells = <0>; 282 #size-cells = <0>;
283 clocks = <&clock 288>;
284 clock-names = "i2c";
247 }; 285 };
248 286
249 spi_0: spi@12d20000 { 287 spi_0: spi@12d20000 {
@@ -255,6 +293,8 @@
255 dma-names = "tx", "rx"; 293 dma-names = "tx", "rx";
256 #address-cells = <1>; 294 #address-cells = <1>;
257 #size-cells = <0>; 295 #size-cells = <0>;
296 clocks = <&clock 304>, <&clock 154>;
297 clock-names = "spi", "spi_busclk0";
258 }; 298 };
259 299
260 spi_1: spi@12d30000 { 300 spi_1: spi@12d30000 {
@@ -266,6 +306,8 @@
266 dma-names = "tx", "rx"; 306 dma-names = "tx", "rx";
267 #address-cells = <1>; 307 #address-cells = <1>;
268 #size-cells = <0>; 308 #size-cells = <0>;
309 clocks = <&clock 305>, <&clock 155>;
310 clock-names = "spi", "spi_busclk0";
269 }; 311 };
270 312
271 spi_2: spi@12d40000 { 313 spi_2: spi@12d40000 {
@@ -277,6 +319,8 @@
277 dma-names = "tx", "rx"; 319 dma-names = "tx", "rx";
278 #address-cells = <1>; 320 #address-cells = <1>;
279 #size-cells = <0>; 321 #size-cells = <0>;
322 clocks = <&clock 306>, <&clock 156>;
323 clock-names = "spi", "spi_busclk0";
280 }; 324 };
281 325
282 dwmmc_0: dwmmc0@12200000 { 326 dwmmc_0: dwmmc0@12200000 {
@@ -285,6 +329,8 @@
285 interrupts = <0 75 0>; 329 interrupts = <0 75 0>;
286 #address-cells = <1>; 330 #address-cells = <1>;
287 #size-cells = <0>; 331 #size-cells = <0>;
332 clocks = <&clock 280>, <&clock 139>;
333 clock-names = "biu", "ciu";
288 }; 334 };
289 335
290 dwmmc_1: dwmmc1@12210000 { 336 dwmmc_1: dwmmc1@12210000 {
@@ -293,6 +339,8 @@
293 interrupts = <0 76 0>; 339 interrupts = <0 76 0>;
294 #address-cells = <1>; 340 #address-cells = <1>;
295 #size-cells = <0>; 341 #size-cells = <0>;
342 clocks = <&clock 281>, <&clock 140>;
343 clock-names = "biu", "ciu";
296 }; 344 };
297 345
298 dwmmc_2: dwmmc2@12220000 { 346 dwmmc_2: dwmmc2@12220000 {
@@ -301,6 +349,8 @@
301 interrupts = <0 77 0>; 349 interrupts = <0 77 0>;
302 #address-cells = <1>; 350 #address-cells = <1>;
303 #size-cells = <0>; 351 #size-cells = <0>;
352 clocks = <&clock 282>, <&clock 141>;
353 clock-names = "biu", "ciu";
304 }; 354 };
305 355
306 dwmmc_3: dwmmc3@12230000 { 356 dwmmc_3: dwmmc3@12230000 {
@@ -309,6 +359,8 @@
309 interrupts = <0 78 0>; 359 interrupts = <0 78 0>;
310 #address-cells = <1>; 360 #address-cells = <1>;
311 #size-cells = <0>; 361 #size-cells = <0>;
362 clocks = <&clock 283>, <&clock 142>;
363 clock-names = "biu", "ciu";
312 }; 364 };
313 365
314 i2s0: i2s@03830000 { 366 i2s0: i2s@03830000 {
@@ -363,6 +415,8 @@
363 compatible = "arm,pl330", "arm,primecell"; 415 compatible = "arm,pl330", "arm,primecell";
364 reg = <0x121A0000 0x1000>; 416 reg = <0x121A0000 0x1000>;
365 interrupts = <0 34 0>; 417 interrupts = <0 34 0>;
418 clocks = <&clock 275>;
419 clock-names = "apb_pclk";
366 #dma-cells = <1>; 420 #dma-cells = <1>;
367 #dma-channels = <8>; 421 #dma-channels = <8>;
368 #dma-requests = <32>; 422 #dma-requests = <32>;
@@ -372,6 +426,8 @@
372 compatible = "arm,pl330", "arm,primecell"; 426 compatible = "arm,pl330", "arm,primecell";
373 reg = <0x121B0000 0x1000>; 427 reg = <0x121B0000 0x1000>;
374 interrupts = <0 35 0>; 428 interrupts = <0 35 0>;
429 clocks = <&clock 276>;
430 clock-names = "apb_pclk";
375 #dma-cells = <1>; 431 #dma-cells = <1>;
376 #dma-channels = <8>; 432 #dma-channels = <8>;
377 #dma-requests = <32>; 433 #dma-requests = <32>;
@@ -381,6 +437,8 @@
381 compatible = "arm,pl330", "arm,primecell"; 437 compatible = "arm,pl330", "arm,primecell";
382 reg = <0x10800000 0x1000>; 438 reg = <0x10800000 0x1000>;
383 interrupts = <0 33 0>; 439 interrupts = <0 33 0>;
440 clocks = <&clock 271>;
441 clock-names = "apb_pclk";
384 #dma-cells = <1>; 442 #dma-cells = <1>;
385 #dma-channels = <8>; 443 #dma-channels = <8>;
386 #dma-requests = <1>; 444 #dma-requests = <1>;
@@ -390,6 +448,8 @@
390 compatible = "arm,pl330", "arm,primecell"; 448 compatible = "arm,pl330", "arm,primecell";
391 reg = <0x11C10000 0x1000>; 449 reg = <0x11C10000 0x1000>;
392 interrupts = <0 124 0>; 450 interrupts = <0 124 0>;
451 clocks = <&clock 271>;
452 clock-names = "apb_pclk";
393 #dma-cells = <1>; 453 #dma-cells = <1>;
394 #dma-channels = <8>; 454 #dma-channels = <8>;
395 #dma-requests = <1>; 455 #dma-requests = <1>;
@@ -649,6 +709,8 @@
649 reg = <0x13e00000 0x1000>; 709 reg = <0x13e00000 0x1000>;
650 interrupts = <0 85 0>; 710 interrupts = <0 85 0>;
651 samsung,power-domain = <&pd_gsc>; 711 samsung,power-domain = <&pd_gsc>;
712 clocks = <&clock 256>;
713 clock-names = "gscl";
652 }; 714 };
653 715
654 gsc_1: gsc@0x13e10000 { 716 gsc_1: gsc@0x13e10000 {
@@ -656,6 +718,8 @@
656 reg = <0x13e10000 0x1000>; 718 reg = <0x13e10000 0x1000>;
657 interrupts = <0 86 0>; 719 interrupts = <0 86 0>;
658 samsung,power-domain = <&pd_gsc>; 720 samsung,power-domain = <&pd_gsc>;
721 clocks = <&clock 257>;
722 clock-names = "gscl";
659 }; 723 };
660 724
661 gsc_2: gsc@0x13e20000 { 725 gsc_2: gsc@0x13e20000 {
@@ -663,6 +727,8 @@
663 reg = <0x13e20000 0x1000>; 727 reg = <0x13e20000 0x1000>;
664 interrupts = <0 87 0>; 728 interrupts = <0 87 0>;
665 samsung,power-domain = <&pd_gsc>; 729 samsung,power-domain = <&pd_gsc>;
730 clocks = <&clock 258>;
731 clock-names = "gscl";
666 }; 732 };
667 733
668 gsc_3: gsc@0x13e30000 { 734 gsc_3: gsc@0x13e30000 {
@@ -670,12 +736,18 @@
670 reg = <0x13e30000 0x1000>; 736 reg = <0x13e30000 0x1000>;
671 interrupts = <0 88 0>; 737 interrupts = <0 88 0>;
672 samsung,power-domain = <&pd_gsc>; 738 samsung,power-domain = <&pd_gsc>;
739 clocks = <&clock 259>;
740 clock-names = "gscl";
673 }; 741 };
674 742
675 hdmi { 743 hdmi {
676 compatible = "samsung,exynos5-hdmi"; 744 compatible = "samsung,exynos5-hdmi";
677 reg = <0x14530000 0x70000>; 745 reg = <0x14530000 0x70000>;
678 interrupts = <0 95 0>; 746 interrupts = <0 95 0>;
747 clocks = <&clock 333>, <&clock 136>, <&clock 137>,
748 <&clock 333>, <&clock 333>;
749 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
750 "sclk_hdmiphy", "hdmiphy";
679 }; 751 };
680 752
681 mixer { 753 mixer {