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authorKukjin Kim <kgene.kim@samsung.com>2012-05-19 14:04:59 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-05-19 14:04:59 -0400
commit2de05a57467c43f58802cdeaa547aee73396b6f3 (patch)
treee73f96c9954479a6909eb6195631284eac0fa47f
parentab5a4e6381d27a6554e6833383e536773e3a6ec1 (diff)
parent380c3a545f7de096c0f84344ba70ea4cfd1a059f (diff)
Merge branch 'next/devel-exynos5250-1' into next/devel-samsung-2
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt52
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts48
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi60
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c51
-rw-r--r--arch/arm/mach-exynos/common.c178
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h9
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h40
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h4
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h2
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c4
-rw-r--r--arch/arm/mach-exynos/mct.c17
-rw-r--r--arch/arm/mach-exynos/pm.c2
-rw-r--r--arch/arm/plat-s5p/Kconfig132
-rw-r--r--arch/arm/plat-s5p/Makefile27
-rw-r--r--arch/arm/plat-samsung/Kconfig140
-rw-r--r--arch/arm/plat-samsung/Makefile13
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h4
-rw-r--r--arch/arm/plat-samsung/s5p-clock.c (renamed from arch/arm/plat-s5p/clock.c)33
-rw-r--r--arch/arm/plat-samsung/s5p-dev-mfc.c (renamed from arch/arm/plat-s5p/dev-mfc.c)4
-rw-r--r--arch/arm/plat-samsung/s5p-dev-uart.c (renamed from arch/arm/plat-s5p/dev-uart.c)78
-rw-r--r--arch/arm/plat-samsung/s5p-irq-eint.c (renamed from arch/arm/plat-s5p/irq-eint.c)3
-rw-r--r--arch/arm/plat-samsung/s5p-irq-gpioint.c (renamed from arch/arm/plat-s5p/irq-gpioint.c)3
-rw-r--r--arch/arm/plat-samsung/s5p-irq-pm.c (renamed from arch/arm/plat-s5p/irq-pm.c)3
-rw-r--r--arch/arm/plat-samsung/s5p-irq.c (renamed from arch/arm/plat-s5p/irq.c)3
-rw-r--r--arch/arm/plat-samsung/s5p-pm.c (renamed from arch/arm/plat-s5p/pm.c)3
-rw-r--r--arch/arm/plat-samsung/s5p-sleep.S (renamed from arch/arm/plat-s5p/sleep.S)3
-rw-r--r--arch/arm/plat-samsung/s5p-time.c (renamed from arch/arm/plat-s5p/s5p-time.c)3
-rw-r--r--arch/arm/plat-samsung/setup-mipiphy.c (renamed from arch/arm/plat-s5p/setup-mipiphy.c)0
-rw-r--r--drivers/gpio/gpio-samsung.c11
32 files changed, 567 insertions, 368 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
new file mode 100644
index 000000000000..f2f2171e530e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -0,0 +1,52 @@
1* Samsung Exynos Interrupt Combiner Controller
2
3Samsung's Exynos4 architecture includes a interrupt combiner controller which
4can combine interrupt sources as a group and provide a single interrupt request
5for the group. The interrupt request from each group are connected to a parent
6interrupt controller, such as GIC in case of Exynos4210.
7
8The interrupt combiner controller consists of multiple combiners. Upto eight
9interrupt sources can be connected to a combiner. The combiner outputs one
10combined interrupt for its eight interrupt sources. The combined interrupt
11is usually connected to a parent interrupt controller.
12
13A single node in the device tree is used to describe the interrupt combiner
14controller module (which includes multiple combiners). A combiner in the
15interrupt controller module shares config/control registers with other
16combiners. For example, a 32-bit interrupt enable/disable config register
17can accommodate upto 4 interrupt combiners (with each combiner supporting
18upto 8 interrupt sources).
19
20Required properties:
21- compatible: should be "samsung,exynos4210-combiner".
22- interrupt-controller: Identifies the node as an interrupt controller.
23- #interrupt-cells: should be <2>. The meaning of the cells are
24 * First Cell: Combiner Group Number.
25 * Second Cell: Interrupt number within the group.
26- reg: Base address and size of interrupt combiner registers.
27- interrupts: The list of interrupts generated by the combiners which are then
28 connected to a parent interrupt controller. The format of the interrupt
29 specifier depends in the interrupt parent controller.
30
31Optional properties:
32- samsung,combiner-nr: The number of interrupt combiners supported. If this
33 property is not specified, the default number of combiners is assumed
34 to be 16.
35- interrupt-parent: pHandle of the parent interrupt controller, if not
36 inherited from the parent node.
37
38
39Example:
40
41 The following is a an example from the Exynos4210 SoC dtsi file.
42
43 combiner:interrupt-controller@10440000 {
44 compatible = "samsung,exynos4210-combiner";
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 reg = <0x10440000 0x1000>;
48 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
49 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
50 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
51 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
52 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36586dba6fa6..85d8e2e9ae27 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1088,7 +1088,6 @@ source "arch/arm/mach-sa1100/Kconfig"
1088 1088
1089source "arch/arm/plat-samsung/Kconfig" 1089source "arch/arm/plat-samsung/Kconfig"
1090source "arch/arm/plat-s3c24xx/Kconfig" 1090source "arch/arm/plat-s3c24xx/Kconfig"
1091source "arch/arm/plat-s5p/Kconfig"
1092 1091
1093source "arch/arm/plat-spear/Kconfig" 1092source "arch/arm/plat-spear/Kconfig"
1094 1093
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc1..f55b509d35c4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -209,7 +209,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik
209plat-$(CONFIG_PLAT_ORION) := orion 209plat-$(CONFIG_PLAT_ORION) := orion
210plat-$(CONFIG_PLAT_PXA) := pxa 210plat-$(CONFIG_PLAT_PXA) := pxa
211plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung 211plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
212plat-$(CONFIG_PLAT_S5P) := s5p samsung 212plat-$(CONFIG_PLAT_S5P) := samsung
213plat-$(CONFIG_PLAT_SPEAR) := spear 213plat-$(CONFIG_PLAT_SPEAR) := spear
214plat-$(CONFIG_PLAT_VERSATILE) := versatile 214plat-$(CONFIG_PLAT_VERSATILE) := versatile
215 215
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b231d2..49945cc1bc7d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,52 @@
23 chosen { 23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; 24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
25 }; 25 };
26
27 i2c@12C60000 {
28 samsung,i2c-sda-delay = <100>;
29 samsung,i2c-max-bus-freq = <20000>;
30 gpios = <&gpb3 0 2 3 0>,
31 <&gpb3 1 2 3 0>;
32
33 eeprom@50 {
34 compatible = "samsung,s524ad0xd1";
35 reg = <0x50>;
36 };
37 };
38
39 i2c@12C70000 {
40 samsung,i2c-sda-delay = <100>;
41 samsung,i2c-max-bus-freq = <20000>;
42 gpios = <&gpb3 2 2 3 0>,
43 <&gpb3 3 2 3 0>;
44
45 eeprom@51 {
46 compatible = "samsung,s524ad0xd1";
47 reg = <0x51>;
48 };
49 };
50
51 i2c@12C80000 {
52 status = "disabled";
53 };
54
55 i2c@12C90000 {
56 status = "disabled";
57 };
58
59 i2c@12CA0000 {
60 status = "disabled";
61 };
62
63 i2c@12CB0000 {
64 status = "disabled";
65 };
66
67 i2c@12CC0000 {
68 status = "disabled";
69 };
70
71 i2c@12CD0000 {
72 status = "disabled";
73 };
26}; 74};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc433599436..5ca0cdb76413 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
23 compatible = "samsung,exynos5250"; 23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>; 24 interrupt-parent = <&gic>;
25 25
26 gic:interrupt-controller@10490000 { 26 gic:interrupt-controller@10481000 {
27 compatible = "arm,cortex-a9-gic"; 27 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>; 28 #interrupt-cells = <3>;
29 interrupt-controller; 29 interrupt-controller;
30 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 30 reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
31 }; 31 };
32 32
33 watchdog { 33 watchdog {
@@ -42,30 +42,6 @@
42 interrupts = <0 43 0>, <0 44 0>; 42 interrupts = <0 43 0>, <0 44 0>;
43 }; 43 };
44 44
45 sdhci@12200000 {
46 compatible = "samsung,exynos4210-sdhci";
47 reg = <0x12200000 0x100>;
48 interrupts = <0 75 0>;
49 };
50
51 sdhci@12210000 {
52 compatible = "samsung,exynos4210-sdhci";
53 reg = <0x12210000 0x100>;
54 interrupts = <0 76 0>;
55 };
56
57 sdhci@12220000 {
58 compatible = "samsung,exynos4210-sdhci";
59 reg = <0x12220000 0x100>;
60 interrupts = <0 77 0>;
61 };
62
63 sdhci@12230000 {
64 compatible = "samsung,exynos4210-sdhci";
65 reg = <0x12230000 0x100>;
66 interrupts = <0 78 0>;
67 };
68
69 serial@12C00000 { 45 serial@12C00000 {
70 compatible = "samsung,exynos4210-uart"; 46 compatible = "samsung,exynos4210-uart";
71 reg = <0x12C00000 0x100>; 47 reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
94 compatible = "samsung,s3c2440-i2c"; 70 compatible = "samsung,s3c2440-i2c";
95 reg = <0x12C60000 0x100>; 71 reg = <0x12C60000 0x100>;
96 interrupts = <0 56 0>; 72 interrupts = <0 56 0>;
73 #address-cells = <1>;
74 #size-cells = <0>;
97 }; 75 };
98 76
99 i2c@12C70000 { 77 i2c@12C70000 {
100 compatible = "samsung,s3c2440-i2c"; 78 compatible = "samsung,s3c2440-i2c";
101 reg = <0x12C70000 0x100>; 79 reg = <0x12C70000 0x100>;
102 interrupts = <0 57 0>; 80 interrupts = <0 57 0>;
81 #address-cells = <1>;
82 #size-cells = <0>;
103 }; 83 };
104 84
105 i2c@12C80000 { 85 i2c@12C80000 {
106 compatible = "samsung,s3c2440-i2c"; 86 compatible = "samsung,s3c2440-i2c";
107 reg = <0x12C80000 0x100>; 87 reg = <0x12C80000 0x100>;
108 interrupts = <0 58 0>; 88 interrupts = <0 58 0>;
89 #address-cells = <1>;
90 #size-cells = <0>;
109 }; 91 };
110 92
111 i2c@12C90000 { 93 i2c@12C90000 {
112 compatible = "samsung,s3c2440-i2c"; 94 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C90000 0x100>; 95 reg = <0x12C90000 0x100>;
114 interrupts = <0 59 0>; 96 interrupts = <0 59 0>;
97 #address-cells = <1>;
98 #size-cells = <0>;
115 }; 99 };
116 100
117 i2c@12CA0000 { 101 i2c@12CA0000 {
118 compatible = "samsung,s3c2440-i2c"; 102 compatible = "samsung,s3c2440-i2c";
119 reg = <0x12CA0000 0x100>; 103 reg = <0x12CA0000 0x100>;
120 interrupts = <0 60 0>; 104 interrupts = <0 60 0>;
105 #address-cells = <1>;
106 #size-cells = <0>;
121 }; 107 };
122 108
123 i2c@12CB0000 { 109 i2c@12CB0000 {
124 compatible = "samsung,s3c2440-i2c"; 110 compatible = "samsung,s3c2440-i2c";
125 reg = <0x12CB0000 0x100>; 111 reg = <0x12CB0000 0x100>;
126 interrupts = <0 61 0>; 112 interrupts = <0 61 0>;
113 #address-cells = <1>;
114 #size-cells = <0>;
127 }; 115 };
128 116
129 i2c@12CC0000 { 117 i2c@12CC0000 {
130 compatible = "samsung,s3c2440-i2c"; 118 compatible = "samsung,s3c2440-i2c";
131 reg = <0x12CC0000 0x100>; 119 reg = <0x12CC0000 0x100>;
132 interrupts = <0 62 0>; 120 interrupts = <0 62 0>;
121 #address-cells = <1>;
122 #size-cells = <0>;
133 }; 123 };
134 124
135 i2c@12CD0000 { 125 i2c@12CD0000 {
136 compatible = "samsung,s3c2440-i2c"; 126 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CD0000 0x100>; 127 reg = <0x12CD0000 0x100>;
138 interrupts = <0 63 0>; 128 interrupts = <0 63 0>;
129 #address-cells = <1>;
130 #size-cells = <0>;
139 }; 131 };
140 132
141 amba { 133 amba {
@@ -157,13 +149,13 @@
157 interrupts = <0 35 0>; 149 interrupts = <0 35 0>;
158 }; 150 };
159 151
160 mdma0: pdma@10800000 { 152 mdma0: mdma@10800000 {
161 compatible = "arm,pl330", "arm,primecell"; 153 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x10800000 0x1000>; 154 reg = <0x10800000 0x1000>;
163 interrupts = <0 33 0>; 155 interrupts = <0 33 0>;
164 }; 156 };
165 157
166 mdma1: pdma@11C10000 { 158 mdma1: mdma@11C10000 {
167 compatible = "arm,pl330", "arm,primecell"; 159 compatible = "arm,pl330", "arm,primecell";
168 reg = <0x11C10000 0x1000>; 160 reg = <0x11C10000 0x1000>;
169 interrupts = <0 124 0>; 161 interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
242 #gpio-cells = <4>; 234 #gpio-cells = <4>;
243 }; 235 };
244 236
237 gpc4: gpio-controller@114002E0 {
238 compatible = "samsung,exynos4-gpio";
239 reg = <0x114002E0 0x20>;
240 #gpio-cells = <4>;
241 };
242
245 gpd0: gpio-controller@11400160 { 243 gpd0: gpio-controller@11400160 {
246 compatible = "samsung,exynos4-gpio"; 244 compatible = "samsung,exynos4-gpio";
247 reg = <0x11400160 0x20>; 245 reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
388 386
389 gpv2: gpio-controller@10D10040 { 387 gpv2: gpio-controller@10D10040 {
390 compatible = "samsung,exynos4-gpio"; 388 compatible = "samsung,exynos4-gpio";
391 reg = <0x10D10040 0x20>; 389 reg = <0x10D10060 0x20>;
392 #gpio-cells = <4>; 390 #gpio-cells = <4>;
393 }; 391 };
394 392
395 gpv3: gpio-controller@10D10060 { 393 gpv3: gpio-controller@10D10060 {
396 compatible = "samsung,exynos4-gpio"; 394 compatible = "samsung,exynos4-gpio";
397 reg = <0x10D10060 0x20>; 395 reg = <0x10D10080 0x20>;
398 #gpio-cells = <4>; 396 #gpio-cells = <4>;
399 }; 397 };
400 398
401 gpv4: gpio-controller@10D10080 { 399 gpv4: gpio-controller@10D10080 {
402 compatible = "samsung,exynos4-gpio"; 400 compatible = "samsung,exynos4-gpio";
403 reg = <0x10D10080 0x20>; 401 reg = <0x10D100C0 0x20>;
404 #gpio-cells = <4>; 402 #gpio-cells = <4>;
405 }; 403 };
406 404
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, 165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
166}; 166};
167 167
168static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
169 .clk = {
170 .name = "mout_bpll_fout",
171 },
172 .sources = &clk_src_bpll_fout,
173 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
174};
175
176static struct clk *exynos5_clk_src_bpll_list[] = {
177 [0] = &clk_fin_bpll,
178 [1] = &exynos5_clk_mout_bpll_fout.clk,
179};
180
181static struct clksrc_sources exynos5_clk_src_bpll = {
182 .sources = exynos5_clk_src_bpll_list,
183 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
184};
185
168static struct clksrc_clk exynos5_clk_mout_bpll = { 186static struct clksrc_clk exynos5_clk_mout_bpll = {
169 .clk = { 187 .clk = {
170 .name = "mout_bpll", 188 .name = "mout_bpll",
171 }, 189 },
172 .sources = &clk_src_bpll, 190 .sources = &exynos5_clk_src_bpll,
173 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, 191 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
174}; 192};
175 193
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
207 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, 225 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
208}; 226};
209 227
228static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
229 .clk = {
230 .name = "mout_mpll_fout",
231 },
232 .sources = &clk_src_mpll_fout,
233 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
234};
235
236static struct clk *exynos5_clk_src_mpll_list[] = {
237 [0] = &clk_fin_mpll,
238 [1] = &exynos5_clk_mout_mpll_fout.clk,
239};
240
241static struct clksrc_sources exynos5_clk_src_mpll = {
242 .sources = exynos5_clk_src_mpll_list,
243 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
244};
245
210struct clksrc_clk exynos5_clk_mout_mpll = { 246struct clksrc_clk exynos5_clk_mout_mpll = {
211 .clk = { 247 .clk = {
212 .name = "mout_mpll", 248 .name = "mout_mpll",
213 }, 249 },
214 .sources = &clk_src_mpll, 250 .sources = &exynos5_clk_src_mpll,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, 251 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
216}; 252};
217 253
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
474 .enable = exynos5_clk_ip_peris_ctrl, 510 .enable = exynos5_clk_ip_peris_ctrl,
475 .ctrlbit = (1 << 20), 511 .ctrlbit = (1 << 20),
476 }, { 512 }, {
513 .name = "watchdog",
514 .parent = &exynos5_clk_aclk_66.clk,
515 .enable = exynos5_clk_ip_peris_ctrl,
516 .ctrlbit = (1 << 19),
517 }, {
477 .name = "hsmmc", 518 .name = "hsmmc",
478 .devname = "exynos4-sdhci.0", 519 .devname = "exynos4-sdhci.0",
479 .parent = &exynos5_clk_aclk_200.clk, 520 .parent = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
1031 &exynos5_clk_mout_apll, 1072 &exynos5_clk_mout_apll,
1032 &exynos5_clk_sclk_apll, 1073 &exynos5_clk_sclk_apll,
1033 &exynos5_clk_mout_bpll, 1074 &exynos5_clk_mout_bpll,
1075 &exynos5_clk_mout_bpll_fout,
1034 &exynos5_clk_mout_bpll_user, 1076 &exynos5_clk_mout_bpll_user,
1035 &exynos5_clk_mout_cpll, 1077 &exynos5_clk_mout_cpll,
1036 &exynos5_clk_mout_epll, 1078 &exynos5_clk_mout_epll,
1037 &exynos5_clk_mout_mpll, 1079 &exynos5_clk_mout_mpll,
1080 &exynos5_clk_mout_mpll_fout,
1038 &exynos5_clk_mout_mpll_user, 1081 &exynos5_clk_mout_mpll_user,
1039 &exynos5_clk_vpllsrc, 1082 &exynos5_clk_vpllsrc,
1040 &exynos5_clk_sclk_vpll, 1083 &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
1098 &exynos5_clk_sclk_hdmi27m, 1141 &exynos5_clk_sclk_hdmi27m,
1099 &exynos5_clk_sclk_hdmiphy, 1142 &exynos5_clk_sclk_hdmiphy,
1100 &clk_fout_bpll, 1143 &clk_fout_bpll,
1144 &clk_fout_bpll_div2,
1101 &clk_fout_cpll, 1145 &clk_fout_cpll,
1146 &clk_fout_mpll_div2,
1102 &exynos5_clk_armclk, 1147 &exynos5_clk_armclk,
1103}; 1148};
1104 1149
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
1263 1308
1264 clk_fout_apll.ops = &exynos5_fout_apll_ops; 1309 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1265 clk_fout_bpll.rate = bpll; 1310 clk_fout_bpll.rate = bpll;
1311 clk_fout_bpll_div2.rate = bpll >> 1;
1266 clk_fout_cpll.rate = cpll; 1312 clk_fout_cpll.rate = cpll;
1267 clk_fout_mpll.rate = mpll; 1313 clk_fout_mpll.rate = mpll;
1314 clk_fout_mpll_div2.rate = mpll >> 1;
1268 clk_fout_epll.rate = epll; 1315 clk_fout_epll.rate = epll;
1269 clk_fout_vpll.rate = vpll; 1316 clk_fout_vpll.rate = vpll;
1270 1317
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e80a607..9900158f026a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,9 @@
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_irq.h> 21#include <linux/of_irq.h>
22#include <linux/export.h>
23#include <linux/irqdomain.h>
24#include <linux/of_address.h>
22 25
23#include <asm/proc-fns.h> 26#include <asm/proc-fns.h>
24#include <asm/exception.h> 27#include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
265 }, { 268 }, {
266 .virtual = (unsigned long)S5P_VA_GIC_CPU, 269 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU), 270 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
268 .length = SZ_64K, 271 .length = SZ_8K,
269 .type = MT_DEVICE, 272 .type = MT_DEVICE,
270 }, { 273 }, {
271 .virtual = (unsigned long)S5P_VA_GIC_DIST, 274 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST), 275 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
273 .length = SZ_64K, 276 .length = SZ_4K,
274 .type = MT_DEVICE, 277 .type = MT_DEVICE,
275 }, 278 },
276}; 279};
@@ -399,6 +402,7 @@ struct combiner_chip_data {
399 void __iomem *base; 402 void __iomem *base;
400}; 403};
401 404
405static struct irq_domain *combiner_irq_domain;
402static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 406static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
403 407
404static inline void __iomem *combiner_base(struct irq_data *data) 408static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
411 415
412static void combiner_mask_irq(struct irq_data *data) 416static void combiner_mask_irq(struct irq_data *data)
413{ 417{
414 u32 mask = 1 << (data->irq % 32); 418 u32 mask = 1 << (data->hwirq % 32);
415 419
416 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); 420 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
417} 421}
418 422
419static void combiner_unmask_irq(struct irq_data *data) 423static void combiner_unmask_irq(struct irq_data *data)
420{ 424{
421 u32 mask = 1 << (data->irq % 32); 425 u32 mask = 1 << (data->hwirq % 32);
422 426
423 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); 427 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
424} 428}
@@ -474,49 +478,127 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
474 irq_set_chained_handler(irq, combiner_handle_cascade_irq); 478 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
475} 479}
476 480
477static void __init combiner_init(unsigned int combiner_nr, void __iomem *base, 481static void __init combiner_init_one(unsigned int combiner_nr,
478 unsigned int irq_start) 482 void __iomem *base)
479{ 483{
480 unsigned int i;
481 unsigned int max_nr;
482
483 if (soc_is_exynos5250())
484 max_nr = EXYNOS5_MAX_COMBINER_NR;
485 else
486 max_nr = EXYNOS4_MAX_COMBINER_NR;
487
488 if (combiner_nr >= max_nr)
489 BUG();
490
491 combiner_data[combiner_nr].base = base; 484 combiner_data[combiner_nr].base = base;
492 combiner_data[combiner_nr].irq_offset = irq_start; 485 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
486 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
493 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); 487 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
494 488
495 /* Disable all interrupts */ 489 /* Disable all interrupts */
496
497 __raw_writel(combiner_data[combiner_nr].irq_mask, 490 __raw_writel(combiner_data[combiner_nr].irq_mask,
498 base + COMBINER_ENABLE_CLEAR); 491 base + COMBINER_ENABLE_CLEAR);
492}
499 493
500 /* Setup the Linux IRQ subsystem */ 494#ifdef CONFIG_OF
495static int combiner_irq_domain_xlate(struct irq_domain *d,
496 struct device_node *controller,
497 const u32 *intspec, unsigned int intsize,
498 unsigned long *out_hwirq,
499 unsigned int *out_type)
500{
501 if (d->of_node != controller)
502 return -EINVAL;
503
504 if (intsize < 2)
505 return -EINVAL;
501 506
502 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset 507 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
503 + MAX_IRQ_IN_COMBINER; i++) { 508 *out_type = 0;
504 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); 509
505 irq_set_chip_data(i, &combiner_data[combiner_nr]); 510 return 0;
506 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 511}
512#else
513static int combiner_irq_domain_xlate(struct irq_domain *d,
514 struct device_node *controller,
515 const u32 *intspec, unsigned int intsize,
516 unsigned long *out_hwirq,
517 unsigned int *out_type)
518{
519 return -EINVAL;
520}
521#endif
522
523static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hw)
525{
526 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
527 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
528 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
529
530 return 0;
531}
532
533static struct irq_domain_ops combiner_irq_domain_ops = {
534 .xlate = combiner_irq_domain_xlate,
535 .map = combiner_irq_domain_map,
536};
537
538void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
539{
540 int i, irq, irq_base;
541 unsigned int max_nr, nr_irq;
542
543 if (np) {
544 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
545 pr_warning("%s: number of combiners not specified, "
546 "setting default as %d.\n",
547 __func__, EXYNOS4_MAX_COMBINER_NR);
548 max_nr = EXYNOS4_MAX_COMBINER_NR;
549 }
550 } else {
551 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
552 EXYNOS4_MAX_COMBINER_NR;
553 }
554 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
555
556 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
557 if (IS_ERR_VALUE(irq_base)) {
558 irq_base = COMBINER_IRQ(0, 0);
559 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
560 }
561
562 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
563 &combiner_irq_domain_ops, &combiner_data);
564 if (WARN_ON(!combiner_irq_domain)) {
565 pr_warning("%s: irq domain init failed\n", __func__);
566 return;
567 }
568
569 for (i = 0; i < max_nr; i++) {
570 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
571 irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
572 combiner_cascade_irq(i, irq);
507 } 573 }
508} 574}
509 575
510#ifdef CONFIG_OF 576#ifdef CONFIG_OF
577int __init combiner_of_init(struct device_node *np, struct device_node *parent)
578{
579 void __iomem *combiner_base;
580
581 combiner_base = of_iomap(np, 0);
582 if (!combiner_base) {
583 pr_err("%s: failed to map combiner registers\n", __func__);
584 return -ENXIO;
585 }
586
587 combiner_init(combiner_base, np);
588
589 return 0;
590}
591
511static const struct of_device_id exynos4_dt_irq_match[] = { 592static const struct of_device_id exynos4_dt_irq_match[] = {
512 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 593 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
594 { .compatible = "samsung,exynos4210-combiner",
595 .data = combiner_of_init, },
513 {}, 596 {},
514}; 597};
515#endif 598#endif
516 599
517void __init exynos4_init_irq(void) 600void __init exynos4_init_irq(void)
518{ 601{
519 int irq;
520 unsigned int gic_bank_offset; 602 unsigned int gic_bank_offset;
521 603
522 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 604 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +610,8 @@ void __init exynos4_init_irq(void)
528 of_irq_init(exynos4_dt_irq_match); 610 of_irq_init(exynos4_dt_irq_match);
529#endif 611#endif
530 612
531 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) { 613 if (!of_have_populated_dt())
532 614 combiner_init(S5P_VA_COMBINER_BASE, NULL);
533 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
534 COMBINER_IRQ(irq, 0));
535 combiner_cascade_irq(irq, IRQ_SPI(irq));
536 }
537 615
538 /* 616 /*
539 * The parameters of s5p_init_irq() are for VIC init. 617 * The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +623,9 @@ void __init exynos4_init_irq(void)
545 623
546void __init exynos5_init_irq(void) 624void __init exynos5_init_irq(void)
547{ 625{
548 int irq;
549
550#ifdef CONFIG_OF 626#ifdef CONFIG_OF
551 of_irq_init(exynos4_dt_irq_match); 627 of_irq_init(exynos4_dt_irq_match);
552#endif 628#endif
553
554 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
555 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
556 COMBINER_IRQ(irq, 0));
557 combiner_cascade_irq(irq, IRQ_SPI(irq));
558 }
559
560 /* 629 /*
561 * The parameters of s5p_init_irq() are for VIC init. 630 * The parameters of s5p_init_irq() are for VIC init.
562 * Theses parameters should be NULL and 0 because EXYNOS4 631 * Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +634,18 @@ void __init exynos5_init_irq(void)
565 s5p_init_irq(NULL, 0); 634 s5p_init_irq(NULL, 0);
566} 635}
567 636
568struct bus_type exynos4_subsys = { 637struct bus_type exynos_subsys = {
569 .name = "exynos4-core", 638 .name = "exynos-core",
570 .dev_name = "exynos4-core", 639 .dev_name = "exynos-core",
571};
572
573struct bus_type exynos5_subsys = {
574 .name = "exynos5-core",
575 .dev_name = "exynos5-core",
576}; 640};
577 641
578static struct device exynos4_dev = { 642static struct device exynos4_dev = {
579 .bus = &exynos4_subsys, 643 .bus = &exynos_subsys,
580};
581
582static struct device exynos5_dev = {
583 .bus = &exynos5_subsys,
584}; 644};
585 645
586static int __init exynos_core_init(void) 646static int __init exynos_core_init(void)
587{ 647{
588 if (soc_is_exynos5250()) 648 return subsys_system_register(&exynos_subsys, NULL);
589 return subsys_system_register(&exynos5_subsys, NULL);
590 else
591 return subsys_system_register(&exynos4_subsys, NULL);
592} 649}
593core_initcall(exynos_core_init); 650core_initcall(exynos_core_init);
594 651
@@ -675,10 +732,7 @@ static int __init exynos_init(void)
675{ 732{
676 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 733 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
677 734
678 if (soc_is_exynos5250()) 735 return device_register(&exynos4_dev);
679 return device_register(&exynos5_dev);
680 else
681 return device_register(&exynos4_dev);
682} 736}
683 737
684/* uart registration process */ 738/* uart registration process */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498afe036a..eb24f1eb8e3b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
153#define EXYNOS5_GPIO_B2_NR (4) 153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4) 154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7) 155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (7) 156#define EXYNOS5_GPIO_C1_NR (4)
157#define EXYNOS5_GPIO_C2_NR (7) 157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7) 158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_D0_NR (8) 159#define EXYNOS5_GPIO_C4_NR (7)
160#define EXYNOS5_GPIO_D0_NR (4)
160#define EXYNOS5_GPIO_D1_NR (8) 161#define EXYNOS5_GPIO_D1_NR (8)
161#define EXYNOS5_GPIO_Y0_NR (6) 162#define EXYNOS5_GPIO_Y0_NR (6)
162#define EXYNOS5_GPIO_Y1_NR (4) 163#define EXYNOS5_GPIO_Y1_NR (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
199 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), 200 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
200 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), 201 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
201 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), 202 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
202 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), 203 EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
204 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
203 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), 205 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
204 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), 206 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
205 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), 207 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
242#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) 244#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
243#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) 245#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
244#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) 246#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
247#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
245#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) 248#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
246#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) 249#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
247#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) 250#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 116167524051..561553a96f4b 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -286,6 +286,7 @@
286#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) 286#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
287#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) 287#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
288#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) 288#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
289#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
289#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) 290#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
290#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) 291#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
291#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) 292#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
@@ -294,8 +295,8 @@
294#define EXYNOS5_IRQ_JPEG IRQ_SPI(89) 295#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
295#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) 296#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
296#define EXYNOS5_IRQ_2D IRQ_SPI(91) 297#define EXYNOS5_IRQ_2D IRQ_SPI(91)
297#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92) 298#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
298#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93) 299#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
299#define EXYNOS5_IRQ_MIXER IRQ_SPI(94) 300#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
300#define EXYNOS5_IRQ_HDMI IRQ_SPI(95) 301#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
301#define EXYNOS5_IRQ_MFC IRQ_SPI(96) 302#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
@@ -309,7 +310,7 @@
309#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) 310#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
310#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) 311#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
311#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) 312#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
312 313#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
313#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) 314#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
314#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) 315#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
315#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) 316#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
@@ -318,8 +319,9 @@
318#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) 319#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
319#define EXYNOS5_IRQ_CEC IRQ_SPI(114) 320#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
320#define EXYNOS5_IRQ_SATA IRQ_SPI(115) 321#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
321#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
322 322
323#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
324#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
323#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) 325#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
324#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) 326#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
325#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) 327#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -327,7 +329,6 @@
327#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) 329#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
328 330
329#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) 331#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
330#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
331 332
332#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) 333#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
333#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) 334#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
@@ -338,6 +339,8 @@
338#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) 339#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
339#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) 340#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
340 341
342#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
343#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
341#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) 344#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
342#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) 345#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
343#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) 346#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
@@ -361,8 +364,8 @@
361 364
362#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) 365#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
363#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) 366#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
364#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2) 367#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
365#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3) 368#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
366#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) 369#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
367#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) 370#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
368#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) 371#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
@@ -374,11 +377,9 @@
374#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) 377#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
375#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) 378#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
376#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) 379#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
377#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
378#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
379 380
380#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5) 381#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
381#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6) 382#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
382 383
383#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) 384#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
384#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) 385#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
@@ -394,17 +395,24 @@
394#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) 395#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
395#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) 396#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
396 397
398#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
399
400#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
401
397#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) 402#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
398#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) 403#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
399#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) 404#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
400 405
406#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
407#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
408#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
409#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
410
411#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
412
401#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) 413#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
402#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
403#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
404#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) 414#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
405#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) 415#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
406#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
407#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
408 416
409#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) 417#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
410#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) 418#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
@@ -435,7 +443,7 @@
435 443
436#define EXYNOS5_MAX_COMBINER_NR 32 444#define EXYNOS5_MAX_COMBINER_NR 32
437 445
438#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13 446#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
439#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 447#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
440#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 448#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
441#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 449#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index d30643ba2739..c72f8088d93d 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -81,8 +81,8 @@
81 81
82#define EXYNOS4_PA_GIC_CPU 0x10480000 82#define EXYNOS4_PA_GIC_CPU 0x10480000
83#define EXYNOS4_PA_GIC_DIST 0x10490000 83#define EXYNOS4_PA_GIC_DIST 0x10490000
84#define EXYNOS5_PA_GIC_CPU 0x10480000 84#define EXYNOS5_PA_GIC_CPU 0x10482000
85#define EXYNOS5_PA_GIC_DIST 0x10490000 85#define EXYNOS5_PA_GIC_DIST 0x10481000
86 86
87#define EXYNOS4_PA_COREPERI 0x10500000 87#define EXYNOS4_PA_COREPERI 0x10500000
88#define EXYNOS4_PA_TWD 0x10500600 88#define EXYNOS4_PA_TWD 0x10500600
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
322#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) 322#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
323#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) 323#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
324 324
325#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
326
325#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) 327#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
326 328
327#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) 329#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c8920e37..cf5d2228e998 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
43 "exynos4210-uart.2", NULL), 43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3, 44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
45 "exynos4210-uart.3", NULL), 45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
47 "s3c2440-i2c.0", NULL),
48 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
49 "s3c2440-i2c.1", NULL),
46 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), 50 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
47 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), 51 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
48 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), 52 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9cf226..b601fb8a408b 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
388{ 388{
389 struct mct_clock_event_device *mevt; 389 struct mct_clock_event_device *mevt;
390 unsigned int cpu = smp_processor_id(); 390 unsigned int cpu = smp_processor_id();
391 int mct_lx_irq;
391 392
392 mevt = this_cpu_ptr(&percpu_mct_tick); 393 mevt = this_cpu_ptr(&percpu_mct_tick);
393 mevt->evt = evt; 394 mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
414 415
415 if (mct_int_type == MCT_INT_SPI) { 416 if (mct_int_type == MCT_INT_SPI) {
416 if (cpu == 0) { 417 if (cpu == 0) {
418 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
419 EXYNOS5_IRQ_MCT_L0;
417 mct_tick0_event_irq.dev_id = mevt; 420 mct_tick0_event_irq.dev_id = mevt;
418 evt->irq = EXYNOS4_IRQ_MCT_L0; 421 evt->irq = mct_lx_irq;
419 setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq); 422 setup_irq(mct_lx_irq, &mct_tick0_event_irq);
420 } else { 423 } else {
424 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
425 EXYNOS5_IRQ_MCT_L1;
421 mct_tick1_event_irq.dev_id = mevt; 426 mct_tick1_event_irq.dev_id = mevt;
422 evt->irq = EXYNOS4_IRQ_MCT_L1; 427 evt->irq = mct_lx_irq;
423 setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq); 428 setup_irq(mct_lx_irq, &mct_tick1_event_irq);
424 irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1)); 429 irq_set_affinity(mct_lx_irq, cpumask_of(1));
425 } 430 }
426 } else { 431 } else {
427 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); 432 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
473 478
474static void __init exynos4_timer_init(void) 479static void __init exynos4_timer_init(void)
475{ 480{
476 if (soc_is_exynos4210()) 481 if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
477 mct_int_type = MCT_INT_SPI; 482 mct_int_type = MCT_INT_SPI;
478 else 483 else
479 mct_int_type = MCT_INT_PPI; 484 mct_int_type = MCT_INT_PPI;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f0bb4677eb11..563dea9a6dbb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
275 275
276static struct subsys_interface exynos4_pm_interface = { 276static struct subsys_interface exynos4_pm_interface = {
277 .name = "exynos4_pm", 277 .name = "exynos4_pm",
278 .subsys = &exynos4_subsys, 278 .subsys = &exynos_subsys,
279 .add_dev = exynos4_pm_add, 279 .add_dev = exynos4_pm_add,
280}; 280};
281 281
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
deleted file mode 100644
index 2c1193c59928..000000000000
--- a/arch/arm/plat-s5p/Kconfig
+++ /dev/null
@@ -1,132 +0,0 @@
1# arch/arm/plat-s5p/Kconfig
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8config PLAT_S5P
9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
11 default y
12 select ARM_VIC if !ARCH_EXYNOS
13 select ARM_GIC if ARCH_EXYNOS
14 select GIC_NON_BANKED if ARCH_EXYNOS4
15 select NO_IOPORT
16 select ARCH_REQUIRE_GPIOLIB
17 select S3C_GPIO_TRACK
18 select S5P_GPIO_DRVSTR
19 select SAMSUNG_GPIOLIB_4BIT
20 select PLAT_SAMSUNG
21 select SAMSUNG_CLKSRC
22 select SAMSUNG_IRQ_VIC_TIMER
23 help
24 Base platform code for Samsung's S5P series SoC.
25
26config S5P_EXT_INT
27 bool
28 help
29 Use the external interrupts (other than GPIO interrupts.)
30 Note: Do not choose this for S5P6440 and S5P6450.
31
32config S5P_GPIO_INT
33 bool
34 help
35 Common code for the GPIO interrupts (other than external interrupts.)
36
37config S5P_HRT
38 bool
39 select SAMSUNG_DEV_PWM
40 help
41 Use the High Resolution timer support
42
43config S5P_DEV_UART
44 def_bool y
45 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
46
47config S5P_PM
48 bool
49 help
50 Common code for power management support on S5P and newer SoCs
51 Note: Do not select this for S5P6440 and S5P6450.
52
53config S5P_SLEEP
54 bool
55 help
56 Internal config node to apply common S5P sleep management code.
57 Can be selected by S5P and newer SoCs with similar sleep procedure.
58
59config S5P_DEV_FIMC0
60 bool
61 help
62 Compile in platform device definitions for FIMC controller 0
63
64config S5P_DEV_FIMC1
65 bool
66 help
67 Compile in platform device definitions for FIMC controller 1
68
69config S5P_DEV_FIMC2
70 bool
71 help
72 Compile in platform device definitions for FIMC controller 2
73
74config S5P_DEV_FIMC3
75 bool
76 help
77 Compile in platform device definitions for FIMC controller 3
78
79config S5P_DEV_JPEG
80 bool
81 help
82 Compile in platform device definitions for JPEG codec
83
84config S5P_DEV_G2D
85 bool
86 help
87 Compile in platform device definitions for G2D device
88
89config S5P_DEV_FIMD0
90 bool
91 help
92 Compile in platform device definitions for FIMD controller 0
93
94config S5P_DEV_I2C_HDMIPHY
95 bool
96 help
97 Compile in platform device definitions for I2C HDMIPHY controller
98
99config S5P_DEV_MFC
100 bool
101 help
102 Compile in platform device definitions for MFC
103
104config S5P_DEV_ONENAND
105 bool
106 help
107 Compile in platform device definition for OneNAND controller
108
109config S5P_DEV_CSIS0
110 bool
111 help
112 Compile in platform device definitions for MIPI-CSIS channel 0
113
114config S5P_DEV_CSIS1
115 bool
116 help
117 Compile in platform device definitions for MIPI-CSIS channel 1
118
119config S5P_DEV_TV
120 bool
121 help
122 Compile in platform device definition for TV interface
123
124config S5P_DEV_USB_EHCI
125 bool
126 help
127 Compile in platform device definition for USB EHCI
128
129config S5P_SETUP_MIPIPHY
130 bool
131 help
132 Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
deleted file mode 100644
index 4953d50707be..000000000000
--- a/arch/arm/plat-s5p/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
1# arch/arm/plat-s5p/Makefile
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n := dummy.o
11obj- :=
12
13# Core files
14
15obj-y += clock.o
16obj-y += irq.o
17obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
18obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
19obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o
20obj-$(CONFIG_S5P_SLEEP) += sleep.o
21obj-$(CONFIG_S5P_HRT) += s5p-time.o
22
23# devices
24
25obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o
26obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
27obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 77e65b483f90..a2fae4ea0936 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -13,6 +13,24 @@ config PLAT_SAMSUNG
13 help 13 help
14 Base platform code for all Samsung SoC based systems 14 Base platform code for all Samsung SoC based systems
15 15
16config PLAT_S5P
17 bool
18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
19 default y
20 select ARM_VIC if !ARCH_EXYNOS
21 select ARM_GIC if ARCH_EXYNOS
22 select GIC_NON_BANKED if ARCH_EXYNOS4
23 select NO_IOPORT
24 select ARCH_REQUIRE_GPIOLIB
25 select S3C_GPIO_TRACK
26 select S5P_GPIO_DRVSTR
27 select SAMSUNG_GPIOLIB_4BIT
28 select PLAT_SAMSUNG
29 select SAMSUNG_CLKSRC
30 select SAMSUNG_IRQ_VIC_TIMER
31 help
32 Base platform code for Samsung's S5P series SoC.
33
16if PLAT_SAMSUNG 34if PLAT_SAMSUNG
17 35
18# boot configurations 36# boot configurations
@@ -50,6 +68,14 @@ config S3C_LOWLEVEL_UART_PORT
50 this configuration should be between zero and two. The port 68 this configuration should be between zero and two. The port
51 must have been initialised by the boot-loader before use. 69 must have been initialised by the boot-loader before use.
52 70
71# timer options
72
73config S5P_HRT
74 bool
75 select SAMSUNG_DEV_PWM
76 help
77 Use the High Resolution timer support
78
53# clock options 79# clock options
54 80
55config SAMSUNG_CLKSRC 81config SAMSUNG_CLKSRC
@@ -58,6 +84,11 @@ config SAMSUNG_CLKSRC
58 Select the clock code for the clksrc implementation 84 Select the clock code for the clksrc implementation
59 used by newer systems such as the S3C64XX. 85 used by newer systems such as the S3C64XX.
60 86
87config S5P_CLOCK
88 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
89 help
90 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
91
61# options for IRQ support 92# options for IRQ support
62 93
63config SAMSUNG_IRQ_VIC_TIMER 94config SAMSUNG_IRQ_VIC_TIMER
@@ -65,6 +96,22 @@ config SAMSUNG_IRQ_VIC_TIMER
65 help 96 help
66 Internal configuration to build the VIC timer interrupt code. 97 Internal configuration to build the VIC timer interrupt code.
67 98
99config S5P_IRQ
100 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
101 help
102 Support common interrup part for ARCH_S5P and ARCH_EXYNOS SoCs
103
104config S5P_EXT_INT
105 bool
106 help
107 Use the external interrupts (other than GPIO interrupts.)
108 Note: Do not choose this for S5P6440 and S5P6450.
109
110config S5P_GPIO_INT
111 bool
112 help
113 Common code for the GPIO interrupts (other than external interrupts.)
114
68# options for gpio configuration support 115# options for gpio configuration support
69 116
70config SAMSUNG_GPIOLIB_4BIT 117config SAMSUNG_GPIOLIB_4BIT
@@ -117,6 +164,12 @@ config S3C_GPIO_TRACK
117 Internal configuration option to enable the s3c specific gpio 164 Internal configuration option to enable the s3c specific gpio
118 chip tracking if the platform requires it. 165 chip tracking if the platform requires it.
119 166
167# uart options
168
169config S5P_DEV_UART
170 def_bool y
171 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
172
120# ADC driver 173# ADC driver
121 174
122config S3C_ADC 175config S3C_ADC
@@ -274,6 +327,76 @@ config SAMSUNG_DEV_BACKLIGHT
274 help 327 help
275 Compile in platform device definition LCD backlight with PWM Timer 328 Compile in platform device definition LCD backlight with PWM Timer
276 329
330config S5P_DEV_CSIS0
331 bool
332 help
333 Compile in platform device definitions for MIPI-CSIS channel 0
334
335config S5P_DEV_CSIS1
336 bool
337 help
338 Compile in platform device definitions for MIPI-CSIS channel 1
339
340config S5P_DEV_FIMC0
341 bool
342 help
343 Compile in platform device definitions for FIMC controller 0
344
345config S5P_DEV_FIMC1
346 bool
347 help
348 Compile in platform device definitions for FIMC controller 1
349
350config S5P_DEV_FIMC2
351 bool
352 help
353 Compile in platform device definitions for FIMC controller 2
354
355config S5P_DEV_FIMC3
356 bool
357 help
358 Compile in platform device definitions for FIMC controller 3
359
360config S5P_DEV_FIMD0
361 bool
362 help
363 Compile in platform device definitions for FIMD controller 0
364
365config S5P_DEV_G2D
366 bool
367 help
368 Compile in platform device definitions for G2D device
369
370config S5P_DEV_I2C_HDMIPHY
371 bool
372 help
373 Compile in platform device definitions for I2C HDMIPHY controller
374
375config S5P_DEV_JPEG
376 bool
377 help
378 Compile in platform device definitions for JPEG codec
379
380config S5P_DEV_MFC
381 bool
382 help
383 Compile in setup memory (init) code for MFC
384
385config S5P_DEV_ONENAND
386 bool
387 help
388 Compile in platform device definition for OneNAND controller
389
390config S5P_DEV_TV
391 bool
392 help
393 Compile in platform device definition for TV interface
394
395config S5P_DEV_USB_EHCI
396 bool
397 help
398 Compile in platform device definition for USB EHCI
399
277config S3C24XX_PWM 400config S3C24XX_PWM
278 bool "PWM device support" 401 bool "PWM device support"
279 select HAVE_PWM 402 select HAVE_PWM
@@ -281,6 +404,11 @@ config S3C24XX_PWM
281 Support for exporting the PWM timer blocks via the pwm device 404 Support for exporting the PWM timer blocks via the pwm device
282 system 405 system
283 406
407config S5P_SETUP_MIPIPHY
408 bool
409 help
410 Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
411
284# DMA 412# DMA
285 413
286config S3C_DMA 414config S3C_DMA
@@ -351,6 +479,18 @@ config SAMSUNG_WAKEMASK
351 and above. This code allows a set of interrupt to wakeup-mask 479 and above. This code allows a set of interrupt to wakeup-mask
352 mappings. See <plat/wakeup-mask.h> 480 mappings. See <plat/wakeup-mask.h>
353 481
482config S5P_PM
483 bool
484 help
485 Common code for power management support on S5P and newer SoCs
486 Note: Do not select this for S5P6440 and S5P6450.
487
488config S5P_SLEEP
489 bool
490 help
491 Internal config node to apply common S5P sleep management code.
492 Can be selected by S5P and newer SoCs with similar sleep procedure.
493
354comment "Power Domain" 494comment "Power Domain"
355 495
356config SAMSUNG_PD 496config SAMSUNG_PD
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 6012366f33cb..860b2db4db15 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -13,12 +13,18 @@ obj- :=
13 13
14obj-y += init.o cpu.o 14obj-y += init.o cpu.o
15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o 15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
16obj-$(CONFIG_S5P_HRT) += s5p-time.o
17
16obj-y += clock.o 18obj-y += clock.o
17obj-y += pwm-clock.o 19obj-y += pwm-clock.o
18 20
19obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 21obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
22obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
20 23
21obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o 24obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
25obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
26obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
27obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
22 28
23# ADC 29# ADC
24 30
@@ -30,9 +36,13 @@ obj-y += platformdata.o
30 36
31obj-y += devs.o 37obj-y += devs.o
32obj-y += dev-uart.o 38obj-y += dev-uart.o
39obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
40obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
33 41
34obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o 42obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
35 43
44obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
45
36# DMA support 46# DMA support
37 47
38obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o 48obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o
@@ -47,6 +57,9 @@ obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
47 57
48obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o 58obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
49 59
60obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o
61obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
62
50# PD support 63# PD support
51 64
52obj-$(CONFIG_SAMSUNG_PD) += pd.o 65obj-$(CONFIG_SAMSUNG_PD) += pd.o
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceaca0be8..0721293fad63 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
202extern struct bus_type s3c6410_subsys; 202extern struct bus_type s3c6410_subsys;
203extern struct bus_type s5p64x0_subsys; 203extern struct bus_type s5p64x0_subsys;
204extern struct bus_type s5pv210_subsys; 204extern struct bus_type s5pv210_subsys;
205extern struct bus_type exynos4_subsys; 205extern struct bus_type exynos_subsys;
206 206
207extern void (*s5pc1xx_idle)(void); 207extern void (*s5pc1xx_idle)(void);
208 208
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 1de4b32f98e9..8364b4bea8b8 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -32,8 +32,10 @@ extern struct clk clk_48m;
32extern struct clk s5p_clk_27m; 32extern struct clk s5p_clk_27m;
33extern struct clk clk_fout_apll; 33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll; 34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_bpll_div2;
35extern struct clk clk_fout_cpll; 36extern struct clk clk_fout_cpll;
36extern struct clk clk_fout_mpll; 37extern struct clk clk_fout_mpll;
38extern struct clk clk_fout_mpll_div2;
37extern struct clk clk_fout_epll; 39extern struct clk clk_fout_epll;
38extern struct clk clk_fout_dpll; 40extern struct clk clk_fout_dpll;
39extern struct clk clk_fout_vpll; 41extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
42 44
43extern struct clksrc_sources clk_src_apll; 45extern struct clksrc_sources clk_src_apll;
44extern struct clksrc_sources clk_src_bpll; 46extern struct clksrc_sources clk_src_bpll;
47extern struct clksrc_sources clk_src_bpll_fout;
45extern struct clksrc_sources clk_src_cpll; 48extern struct clksrc_sources clk_src_cpll;
46extern struct clksrc_sources clk_src_mpll; 49extern struct clksrc_sources clk_src_mpll;
50extern struct clksrc_sources clk_src_mpll_fout;
47extern struct clksrc_sources clk_src_epll; 51extern struct clksrc_sources clk_src_epll;
48extern struct clksrc_sources clk_src_dpll; 52extern struct clksrc_sources clk_src_dpll;
49 53
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-samsung/s5p-clock.c
index f68a9bb11948..031a61899bef 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/clock.c 1/*
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 2 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
@@ -68,6 +67,11 @@ struct clk clk_fout_bpll = {
68 .id = -1, 67 .id = -1,
69}; 68};
70 69
70struct clk clk_fout_bpll_div2 = {
71 .name = "fout_bpll_div2",
72 .id = -1,
73};
74
71/* CPLL clock output */ 75/* CPLL clock output */
72 76
73struct clk clk_fout_cpll = { 77struct clk clk_fout_cpll = {
@@ -83,6 +87,11 @@ struct clk clk_fout_mpll = {
83 .id = -1, 87 .id = -1,
84}; 88};
85 89
90struct clk clk_fout_mpll_div2 = {
91 .name = "fout_mpll_div2",
92 .id = -1,
93};
94
86/* EPLL clock output */ 95/* EPLL clock output */
87struct clk clk_fout_epll = { 96struct clk clk_fout_epll = {
88 .name = "fout_epll", 97 .name = "fout_epll",
@@ -126,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
126 .nr_sources = ARRAY_SIZE(clk_src_bpll_list), 135 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
127}; 136};
128 137
138static struct clk *clk_src_bpll_fout_list[] = {
139 [0] = &clk_fout_bpll_div2,
140 [1] = &clk_fout_bpll,
141};
142
143struct clksrc_sources clk_src_bpll_fout = {
144 .sources = clk_src_bpll_fout_list,
145 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
146};
147
129/* Possible clock sources for CPLL Mux */ 148/* Possible clock sources for CPLL Mux */
130static struct clk *clk_src_cpll_list[] = { 149static struct clk *clk_src_cpll_list[] = {
131 [0] = &clk_fin_cpll, 150 [0] = &clk_fin_cpll,
@@ -148,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
148 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 167 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
149}; 168};
150 169
170static struct clk *clk_src_mpll_fout_list[] = {
171 [0] = &clk_fout_mpll_div2,
172 [1] = &clk_fout_mpll,
173};
174
175struct clksrc_sources clk_src_mpll_fout = {
176 .sources = clk_src_mpll_fout_list,
177 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
178};
179
151/* Possible clock sources for EPLL Mux */ 180/* Possible clock sources for EPLL Mux */
152static struct clk *clk_src_epll_list[] = { 181static struct clk *clk_src_epll_list[] = {
153 [0] = &clk_fin_epll, 182 [0] = &clk_fin_epll,
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index a30d36b7f61b..ad6089465e2a 100644
--- a/arch/arm/plat-s5p/dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/dev-mfc.c 1/*
2 *
3 * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd 2 * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
4 * 3 *
5 * Base S5P MFC resource and device definitions 4 * Base S5P MFC resource and device definitions
@@ -9,7 +8,6 @@
9 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
10 */ 9 */
11 10
12
13#include <linux/kernel.h> 11#include <linux/kernel.h>
14#include <linux/interrupt.h> 12#include <linux/interrupt.h>
15#include <linux/platform_device.h> 13#include <linux/platform_device.h>
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
index c9308db36183..cafa3deddcc1 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-samsung/s5p-dev-uart.c
@@ -1,6 +1,5 @@
1/* linux/arch/arm/plat-s5p/dev-uart.c 1/*
2 * 2 * Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
6 * Base S5P UART resource and device definitions 5 * Base S5P UART resource and device definitions
@@ -14,6 +13,7 @@
14#include <linux/types.h> 13#include <linux/types.h>
15#include <linux/interrupt.h> 14#include <linux/interrupt.h>
16#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18 18
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
@@ -26,86 +26,38 @@
26 /* Serial port registrations */ 26 /* Serial port registrations */
27 27
28static struct resource s5p_uart0_resource[] = { 28static struct resource s5p_uart0_resource[] = {
29 [0] = { 29 [0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
30 .start = S5P_PA_UART0, 30 [1] = DEFINE_RES_IRQ(IRQ_UART0),
31 .end = S5P_PA_UART0 + S5P_SZ_UART - 1,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = IRQ_UART0,
36 .end = IRQ_UART0,
37 .flags = IORESOURCE_IRQ,
38 },
39}; 31};
40 32
41static struct resource s5p_uart1_resource[] = { 33static struct resource s5p_uart1_resource[] = {
42 [0] = { 34 [0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
43 .start = S5P_PA_UART1, 35 [1] = DEFINE_RES_IRQ(IRQ_UART1),
44 .end = S5P_PA_UART1 + S5P_SZ_UART - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = IRQ_UART1,
49 .end = IRQ_UART1,
50 .flags = IORESOURCE_IRQ,
51 },
52}; 36};
53 37
54static struct resource s5p_uart2_resource[] = { 38static struct resource s5p_uart2_resource[] = {
55 [0] = { 39 [0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
56 .start = S5P_PA_UART2, 40 [1] = DEFINE_RES_IRQ(IRQ_UART2),
57 .end = S5P_PA_UART2 + S5P_SZ_UART - 1,
58 .flags = IORESOURCE_MEM,
59 },
60 [1] = {
61 .start = IRQ_UART2,
62 .end = IRQ_UART2,
63 .flags = IORESOURCE_IRQ,
64 },
65}; 41};
66 42
67static struct resource s5p_uart3_resource[] = { 43static struct resource s5p_uart3_resource[] = {
68#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 44#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
69 [0] = { 45 [0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
70 .start = S5P_PA_UART3, 46 [1] = DEFINE_RES_IRQ(IRQ_UART3),
71 .end = S5P_PA_UART3 + S5P_SZ_UART - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 [1] = {
75 .start = IRQ_UART3,
76 .end = IRQ_UART3,
77 .flags = IORESOURCE_IRQ,
78 },
79#endif 47#endif
80}; 48};
81 49
82static struct resource s5p_uart4_resource[] = { 50static struct resource s5p_uart4_resource[] = {
83#if CONFIG_SERIAL_SAMSUNG_UARTS > 4 51#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
84 [0] = { 52 [0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
85 .start = S5P_PA_UART4, 53 [1] = DEFINE_RES_IRQ(IRQ_UART4),
86 .end = S5P_PA_UART4 + S5P_SZ_UART - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = IRQ_UART4,
91 .end = IRQ_UART4,
92 .flags = IORESOURCE_IRQ,
93 },
94#endif 54#endif
95}; 55};
96 56
97static struct resource s5p_uart5_resource[] = { 57static struct resource s5p_uart5_resource[] = {
98#if CONFIG_SERIAL_SAMSUNG_UARTS > 5 58#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
99 [0] = { 59 [0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
100 .start = S5P_PA_UART5, 60 [1] = DEFINE_RES_IRQ(IRQ_UART5),
101 .end = S5P_PA_UART5 + S5P_SZ_UART - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = IRQ_UART5,
106 .end = IRQ_UART5,
107 .flags = IORESOURCE_IRQ,
108 },
109#endif 61#endif
110}; 62};
111 63
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
index 139c050918c5..33bd3f3d20f5 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-samsung/s5p-irq-eint.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/irq-eint.c 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index 82c7311017a2..f9431fe5b06e 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/irq-gpioint.c 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * Author: Kyungmin Park <kyungmin.park@samsung.com> 3 * Author: Kyungmin Park <kyungmin.park@samsung.com>
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com> 4 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
index d1bfecae6c9f..7c1e3b7072fc 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-samsung/s5p-irq-pm.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/irq-pm.c 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-samsung/s5p-irq.c
index afdaa1082b9f..dfb47d638f03 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -1,5 +1,4 @@
1/* arch/arm/plat-s5p/irq.c 1/*
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-samsung/s5p-pm.c
index d15dc47b0e3d..0747468f0936 100644
--- a/arch/arm/plat-s5p/pm.c
+++ b/arch/arm/plat-samsung/s5p-pm.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/pm.c 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index 006bd01eda02..bdf6dadf8790 100644
--- a/arch/arm/plat-s5p/sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/sleep.S 1/*
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c
index 17c0a2c58dfd..028b6e877eb9 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-samsung/s5p-time.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s5p/s5p-time.c 1/*
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
diff --git a/arch/arm/plat-s5p/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c
index 683c466c0e6a..683c466c0e6a 100644
--- a/arch/arm/plat-s5p/setup-mipiphy.c
+++ b/arch/arm/plat-samsung/setup-mipiphy.c
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index e991d9171961..f88bb9f919a8 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2454,6 +2454,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
2454 }, 2454 },
2455 }, { 2455 }, {
2456 .chip = { 2456 .chip = {
2457 .base = EXYNOS5_GPC4(0),
2458 .ngpio = EXYNOS5_GPIO_C4_NR,
2459 .label = "GPC4",
2460 },
2461 }, {
2462 .chip = {
2457 .base = EXYNOS5_GPD0(0), 2463 .base = EXYNOS5_GPD0(0),
2458 .ngpio = EXYNOS5_GPIO_D0_NR, 2464 .ngpio = EXYNOS5_GPIO_D0_NR,
2459 .label = "GPD0", 2465 .label = "GPD0",
@@ -2878,8 +2884,11 @@ static __init int samsung_gpiolib_init(void)
2878 goto err_ioremap1; 2884 goto err_ioremap1;
2879 } 2885 }
2880 2886
2887 /* need to set base address for gpc4 */
2888 exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
2889
2881 /* need to set base address for gpx */ 2890 /* need to set base address for gpx */
2882 chip = &exynos5_gpios_1[20]; 2891 chip = &exynos5_gpios_1[21];
2883 gpx_base = gpio_base1 + 0xC00; 2892 gpx_base = gpio_base1 + 0xC00;
2884 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) 2893 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2885 chip->base = gpx_base; 2894 chip->base = gpx_base;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 13:56:52 -0400