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authorPaul Mundt <lethal@linux-sh.org>2009-04-20 08:42:59 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-04-20 08:42:59 -0400
commit2d5efc190eb415dbff79ffab4f8ea731ab0288a9 (patch)
tree3c086544eece0de283755ee14181bbcaa3a4eb1c
parent951a681bda844491de8699b3bdc6c3899cbd4c9f (diff)
sh: pci: Move the se7751 fixups in to arch/sh/drivers/pci/.
The se7751 was still doing the PCI fixups in its own board directory, so we move it over to arch/sh/drivers/pci/ with the rest of the board fixups. It has bitrotted significantly over the years, so will still likely need a bit of work to bring back up to date. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/boards/mach-se/7751/Makefile2
-rw-r--r--arch/sh/boards/mach-se/7751/pci.c150
-rw-r--r--arch/sh/drivers/pci/Makefile1
-rw-r--r--arch/sh/drivers/pci/fixups-se7751.c111
4 files changed, 112 insertions, 152 deletions
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index dbc29f3a9de5..e6f4341bfe6e 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := setup.o io.o irq.o 5obj-y := setup.o io.o irq.o
6
7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/sh/boards/mach-se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c
deleted file mode 100644
index 9ec64a416b30..000000000000
--- a/arch/sh/boards/mach-se/7751/pci.c
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * linux/arch/sh/boards/se/7751/pci.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19
20#include <asm/io.h>
21#include "../../../drivers/pci/pci-sh7751.h"
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33#define xPCIBIOS_MIN_IO board_pci_channels->io_resource->start
34#define xPCIBIOS_MIN_MEM board_pci_channels->mem_resource->start
35
36/*
37 * Description: This function sets up and initializes the pcic, sets
38 * up the BARS, maps the DRAM into the address space etc, etc.
39 */
40int __init pcibios_init_platform(void)
41{
42 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
43 unsigned short bcr2;
44
45 /*
46 * Initialize the slave bus controller on the pcic. The values used
47 * here should not be hardcoded, but they should be taken from the bsc
48 * on the processor, to make this function as generic as possible.
49 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
50 * for the pcic to work, its settings need to be exactly the same.)
51 */
52 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
53 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
54 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
55 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
56 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
57 mcr = (*(volatile unsigned long*)(SH7751_MCR));
58
59 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
60 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
61
62 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
63 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
64 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
65 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
66 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
67 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
68 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
69 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
70
71
72 /* Enable all interrupts, so we know what to fix */
73 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
74 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
75
76 /* Set up standard PCI config registers */
77 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
78 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
79 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
80 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
81 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
82 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
83 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
84 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
85 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
86 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
87
88 /* Now turn it on... */
89 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
90
91 /*
92 * Set PCIMBR and PCIIOBR here, assuming a single window
93 * (16M MEM, 256K IO) is enough. If a larger space is
94 * needed, the readx/writex and inx/outx functions will
95 * have to do more (e.g. setting registers for each call).
96 */
97
98 /*
99 * Set the MBR so PCI address is one-to-one with window,
100 * meaning all calls go straight through... use BUG_ON to
101 * catch erroneous assumption.
102 */
103 BUG_ON(xPCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
104
105 PCIC_WRITE(SH7751_PCIMBR, xPCIBIOS_MIN_MEM);
106
107 /* Set IOBR for window containing area specified in pci.h */
108 PCIC_WRITE(SH7751_PCIIOBR, (xPCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
109
110 /* All done, may as well say so... */
111 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
112
113 return 1;
114}
115
116int __init pcibios_map_platform_irq(u8 slot, u8 pin)
117{
118 switch (slot) {
119 case 0: return 13;
120 case 1: return 13; /* AMD Ethernet controller */
121 case 2: return -1;
122 case 3: return -1;
123 case 4: return -1;
124 default:
125 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
126 return -1;
127 }
128}
129
130static struct resource sh7751_io_resource = {
131 .name = "SH7751 IO",
132 .start = SH7751_PCI_IO_BASE,
133 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
134 .flags = IORESOURCE_IO
135};
136
137static struct resource sh7751_mem_resource = {
138 .name = "SH7751 mem",
139 .start = SH7751_PCI_MEMORY_BASE,
140 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
141 .flags = IORESOURCE_MEM
142};
143
144extern struct pci_ops sh7751_pci_ops;
145
146struct pci_channel board_pci_channels[] = {
147 { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
148 { NULL, NULL, NULL, 0, 0 },
149};
150
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index fbebd73b22f6..e388a70d1463 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
15obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ 15obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
16 pci-dreamcast.o 16 pci-dreamcast.o
17obj-$(CONFIG_SH_SECUREEDGE5410) += fixups-snapgear.o 17obj-$(CONFIG_SH_SECUREEDGE5410) += fixups-snapgear.o
18obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += fixups-se7751.o
18obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o 19obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o
19obj-$(CONFIG_SH_SH03) += fixups-sh03.o 20obj-$(CONFIG_SH_SH03) += fixups-sh03.o
20obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o 21obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
new file mode 100644
index 000000000000..475fa9f0fe2c
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -0,0 +1,111 @@
1#include <linux/kernel.h>
2#include <linux/types.h>
3#include <linux/init.h>
4#include <linux/delay.h>
5#include <linux/pci.h>
6#include <linux/io.h>
7#include "pci-sh4.h"
8
9int __init pcibios_map_platform_irq(u8 slot, u8 pin)
10{
11 switch (slot) {
12 case 0: return 13;
13 case 1: return 13; /* AMD Ethernet controller */
14 case 2: return -1;
15 case 3: return -1;
16 case 4: return -1;
17 default:
18 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
19 return -1;
20 }
21}
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int pci_fixup_pcic(struct pci_channel *chan)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
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