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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-24 15:48:47 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-24 15:48:47 -0400
commit2cc91884b6b3f7328680b8ea7563016d3aee3d19 (patch)
tree954cdb444e6bfe92a8622d19c10a96367017e180
parentcdc63a059508b96cad1de793437ad2296d80ffe6 (diff)
parent4846f1181635e1f68aed0725f71700c15c2fb449 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: "This is the first round of fixes and tying up loose ends for MIPS. - plenty of fixes for build errors in specific obscure configurations - remove redundant code on the Lantiq platform - removal of a useless SEAD I2C driver that was causing a build issue - fix an earlier TLB exeption handler fix to also work on Octeon. - fix ISA level dependencies in FPU emulator's instruction decoding. - don't hardcode kernel command line in Octeon software emulator. - fix an earlier fix for the Loondson 2 clock setting" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: SEAD3: Fix I2C device registration. MIPS: SEAD3: Nuke PIC32 I2C driver. MIPS: ftrace: Fix a microMIPS build problem MIPS: MSP71xx: Fix build error MIPS: Malta: Do not build the malta-amon.c file if CMP is not enabled MIPS: Prevent compiler warning from cop2_{save,restore} MIPS: Kconfig: Add missing MIPS_CPS dependencies to PM and cpuidle MIPS: idle: Remove leftover __pastwait symbol and its references MIPS: Sibyte: Include the swarm subdir to the sb1250 LittleSur builds MIPS: ptrace.h: Add a missing include MIPS: ath79: Fix compilation error when CONFIG_PCI is disabled MIPS: MSP71xx: Remove compilation error when CONFIG_MIPS_MT is present MIPS: Octeon: Remove special case for simulator command line. MIPS: tlbex: Properly fix HUGE TLB Refill exception handler MIPS: loongson2_cpufreq: Fix CPU clock rate setting mismerge pci: pci-lantiq: remove duplicate check on resource MIPS: Lasat: Add missing CONFIG_PROC_FS dependency to PICVUE_PROC MIPS: cp1emu: Fix ISA restrictions for cop1x_op instructions
Diffstat
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/ath79/mach-db120.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c9
-rw-r--r--arch/mips/include/asm/cop2.h8
-rw-r--r--arch/mips/include/asm/ftrace.h4
-rw-r--r--arch/mips/include/asm/idle.h7
-rw-r--r--arch/mips/include/uapi/asm/ptrace.h2
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/lasat/Kconfig2
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c5
-rw-r--r--arch/mips/math-emu/cp1emu.c4
-rw-r--r--arch/mips/mm/tlbex.c6
-rw-r--r--arch/mips/mti-malta/Makefile3
-rw-r--r--arch/mips/mti-sead3/Makefile1
-rw-r--r--arch/mips/mti-sead3/sead3-i2c.c8
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-bus.c102
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-i2c-drv.c423
-rw-r--r--arch/mips/pci/pci-lantiq.c7
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq.c1
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq_cic.c4
-rw-r--r--arch/mips/sibyte/Makefile1
-rw-r--r--drivers/cpuidle/Kconfig.mips2
22 files changed, 30 insertions, 575 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ad6badb6be71..f43aa536c517 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2066,6 +2066,7 @@ config MIPS_CPS
2066 support is unavailable. 2066 support is unavailable.
2067 2067
2068config MIPS_CPS_PM 2068config MIPS_CPS_PM
2069 depends on MIPS_CPS
2069 select MIPS_CPC 2070 select MIPS_CPC
2070 bool 2071 bool
2071 2072
diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c
index 4d661a1d2dae..9423f5aed287 100644
--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
@@ -113,7 +113,7 @@ static void __init db120_pci_init(u8 *eeprom)
113 ath79_register_pci(); 113 ath79_register_pci();
114} 114}
115#else 115#else
116static inline void db120_pci_init(void) {} 116static inline void db120_pci_init(u8 *eeprom) {}
117#endif /* CONFIG_PCI */ 117#endif /* CONFIG_PCI */
118 118
119static void __init db120_setup(void) 119static void __init db120_setup(void)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 38f4c32e2816..5ebdb32d9a2b 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -806,15 +806,6 @@ void __init prom_init(void)
806#endif 806#endif
807 } 807 }
808 808
809 if (octeon_is_simulation()) {
810 /*
811 * The simulator uses a mtdram device pre filled with
812 * the filesystem. Also specify the calibration delay
813 * to avoid calculating it every time.
814 */
815 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
816 }
817
818 mips_hpt_frequency = octeon_get_clock_rate(); 809 mips_hpt_frequency = octeon_get_clock_rate();
819 810
820 octeon_init_cvmcount(); 811 octeon_init_cvmcount();
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 51f80bd36fcc..63b3468ede4c 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -37,15 +37,15 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
37 37
38#define cop2_present 1 38#define cop2_present 1
39#define cop2_lazy_restore 1 39#define cop2_lazy_restore 1
40#define cop2_save(r) do { (r); } while (0) 40#define cop2_save(r) do { (void)(r); } while (0)
41#define cop2_restore(r) do { (r); } while (0) 41#define cop2_restore(r) do { (void)(r); } while (0)
42 42
43#else 43#else
44 44
45#define cop2_present 0 45#define cop2_present 0
46#define cop2_lazy_restore 0 46#define cop2_lazy_restore 0
47#define cop2_save(r) do { (r); } while (0) 47#define cop2_save(r) do { (void)(r); } while (0)
48#define cop2_restore(r) do { (r); } while (0) 48#define cop2_restore(r) do { (void)(r); } while (0)
49#endif 49#endif
50 50
51enum cu2_ops { 51enum cu2_ops {
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 992aaba603b5..b463f2aa5a61 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -24,7 +24,7 @@ do { \
24 asm volatile ( \ 24 asm volatile ( \
25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \ 25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26 " li %[tmp_err], 0\n" \ 26 " li %[tmp_err], 0\n" \
27 "2:\n" \ 27 "2: .insn\n" \
28 \ 28 \
29 ".section .fixup, \"ax\"\n" \ 29 ".section .fixup, \"ax\"\n" \
30 "3: li %[tmp_err], 1\n" \ 30 "3: li %[tmp_err], 1\n" \
@@ -46,7 +46,7 @@ do { \
46 asm volatile ( \ 46 asm volatile ( \
47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\ 47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48 " li %[tmp_err], 0\n" \ 48 " li %[tmp_err], 0\n" \
49 "2:\n" \ 49 "2: .insn\n" \
50 \ 50 \
51 ".section .fixup, \"ax\"\n" \ 51 ".section .fixup, \"ax\"\n" \
52 "3: li %[tmp_err], 1\n" \ 52 "3: li %[tmp_err], 1\n" \
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
index d9f932de80e9..1c967abd545c 100644
--- a/arch/mips/include/asm/idle.h
+++ b/arch/mips/include/asm/idle.h
@@ -8,19 +8,12 @@ extern void (*cpu_wait)(void);
8extern void r4k_wait(void); 8extern void r4k_wait(void);
9extern asmlinkage void __r4k_wait(void); 9extern asmlinkage void __r4k_wait(void);
10extern void r4k_wait_irqoff(void); 10extern void r4k_wait_irqoff(void);
11extern void __pastwait(void);
12 11
13static inline int using_rollback_handler(void) 12static inline int using_rollback_handler(void)
14{ 13{
15 return cpu_wait == r4k_wait; 14 return cpu_wait == r4k_wait;
16} 15}
17 16
18static inline int address_is_in_r4k_wait_irqoff(unsigned long addr)
19{
20 return addr >= (unsigned long)r4k_wait_irqoff &&
21 addr < (unsigned long)__pastwait;
22}
23
24extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev, 17extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
25 struct cpuidle_driver *drv, int index); 18 struct cpuidle_driver *drv, int index);
26 19
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index bbcfb8ba8106..91a3d197ede3 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -9,6 +9,8 @@
9#ifndef _UAPI_ASM_PTRACE_H 9#ifndef _UAPI_ASM_PTRACE_H
10#define _UAPI_ASM_PTRACE_H 10#define _UAPI_ASM_PTRACE_H
11 11
12#include <linux/types.h>
13
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ 14/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32 15#define FPR_BASE 32
14#define PC 64 16#define PC 64
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 09ce45980758..0b9082b6b683 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -68,9 +68,6 @@ void r4k_wait_irqoff(void)
68 " wait \n" 68 " wait \n"
69 " .set pop \n"); 69 " .set pop \n");
70 local_irq_enable(); 70 local_irq_enable();
71 __asm__(
72 " .globl __pastwait \n"
73 "__pastwait: \n");
74} 71}
75 72
76/* 73/*
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
index 1d2ee8a9be13..8776d0a34274 100644
--- a/arch/mips/lasat/Kconfig
+++ b/arch/mips/lasat/Kconfig
@@ -4,7 +4,7 @@ config PICVUE
4 4
5config PICVUE_PROC 5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface" 6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE 7 depends on PICVUE && PROC_FS
8 8
9config DS1603 9config DS1603
10 bool "DS1603 RTC driver" 10 bool "DS1603 RTC driver"
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index a217061beee3..462e34d46b4a 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
91 91
92int clk_set_rate(struct clk *clk, unsigned long rate) 92int clk_set_rate(struct clk *clk, unsigned long rate)
93{ 93{
94 unsigned int rate_khz = rate / 1000;
94 struct cpufreq_frequency_table *pos; 95 struct cpufreq_frequency_table *pos;
95 int ret = 0; 96 int ret = 0;
96 int regval; 97 int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
107 propagate_rate(clk); 108 propagate_rate(clk);
108 109
109 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table) 110 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
110 if (rate == pos->frequency) 111 if (rate_khz == pos->frequency)
111 break; 112 break;
112 if (rate != pos->frequency) 113 if (rate_khz != pos->frequency)
113 return -ENOTSUPP; 114 return -ENOTSUPP;
114 115
115 clk->rate = rate; 116 clk->rate = rate;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7a4727795a70..51a0fde4bec1 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1023,7 +1023,7 @@ emul:
1023 goto emul; 1023 goto emul;
1024 1024
1025 case cop1x_op: 1025 case cop1x_op:
1026 if (cpu_has_mips_4_5 || cpu_has_mips64) 1026 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1027 /* its one of ours */ 1027 /* its one of ours */
1028 goto emul; 1028 goto emul;
1029 1029
@@ -1068,7 +1068,7 @@ emul:
1068 break; 1068 break;
1069 1069
1070 case cop1x_op: 1070 case cop1x_op:
1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64) 1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1072 return SIGILL; 1072 return SIGILL;
1073 1073
1074 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1074 sig = fpux_emu(xcp, ctx, ir, fault_addr);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a08dd53a1cc5..b5f228e7eae6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1062,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1062struct mips_huge_tlb_info { 1062struct mips_huge_tlb_info {
1063 int huge_pte; 1063 int huge_pte;
1064 int restore_scratch; 1064 int restore_scratch;
1065 bool need_reload_pte;
1065}; 1066};
1066 1067
1067static struct mips_huge_tlb_info 1068static struct mips_huge_tlb_info
@@ -1076,6 +1077,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1076 1077
1077 rv.huge_pte = scratch; 1078 rv.huge_pte = scratch;
1078 rv.restore_scratch = 0; 1079 rv.restore_scratch = 0;
1080 rv.need_reload_pte = false;
1079 1081
1080 if (check_for_high_segbits) { 1082 if (check_for_high_segbits) {
1081 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1083 UASM_i_MFC0(p, tmp, C0_BADVADDR);
@@ -1264,6 +1266,7 @@ static void build_r4000_tlb_refill_handler(void)
1264 } else { 1266 } else {
1265 htlb_info.huge_pte = K0; 1267 htlb_info.huge_pte = K0;
1266 htlb_info.restore_scratch = 0; 1268 htlb_info.restore_scratch = 0;
1269 htlb_info.need_reload_pte = true;
1267 vmalloc_mode = refill_noscratch; 1270 vmalloc_mode = refill_noscratch;
1268 /* 1271 /*
1269 * create the plain linear handler 1272 * create the plain linear handler
@@ -1300,7 +1303,8 @@ static void build_r4000_tlb_refill_handler(void)
1300 } 1303 }
1301#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1304#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1302 uasm_l_tlb_huge_update(&l, p); 1305 uasm_l_tlb_huge_update(&l, p);
1303 UASM_i_LW(&p, K0, 0, K1); 1306 if (htlb_info.need_reload_pte)
1307 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1304 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1308 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1309 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1306 htlb_info.restore_scratch); 1310 htlb_info.restore_scratch);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index b9510ea8db56..6510ace272d4 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -5,8 +5,9 @@
5# Copyright (C) 2008 Wind River Systems, Inc. 5# Copyright (C) 2008 Wind River Systems, Inc.
6# written by Ralf Baechle <ralf@linux-mips.org> 6# written by Ralf Baechle <ralf@linux-mips.org>
7# 7#
8obj-y := malta-amon.o malta-display.o malta-init.o \ 8obj-y := malta-display.o malta-init.o \
9 malta-int.o malta-memory.o malta-platform.o \ 9 malta-int.o malta-memory.o malta-platform.o \
10 malta-reset.o malta-setup.o malta-time.o 10 malta-reset.o malta-setup.o malta-time.o
11 11
12obj-$(CONFIG_MIPS_CMP) += malta-amon.o
12obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o 13obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index febf4334545e..2ae49e99eb67 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -14,7 +14,6 @@ obj-y := sead3-lcd.o sead3-display.o sead3-init.o \
14 sead3-setup.o sead3-time.o 14 sead3-setup.o sead3-time.o
15 15
16obj-y += sead3-i2c-dev.o sead3-i2c.o \ 16obj-y += sead3-i2c-dev.o sead3-i2c.o \
17 sead3-pic32-i2c-drv.o sead3-pic32-bus.o \
18 leds-sead3.o sead3-leds.o 17 leds-sead3.o sead3-leds.o
19 18
20obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o 19obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c
index f70d5fc58ef5..795ae83894e0 100644
--- a/arch/mips/mti-sead3/sead3-i2c.c
+++ b/arch/mips/mti-sead3/sead3-i2c.c
@@ -5,10 +5,8 @@
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/module.h>
9#include <linux/init.h> 8#include <linux/init.h>
10#include <linux/platform_device.h> 9#include <linux/platform_device.h>
11#include <irq.h>
12 10
13struct resource sead3_i2c_resources[] = { 11struct resource sead3_i2c_resources[] = {
14 { 12 {
@@ -30,8 +28,4 @@ static int __init sead3_i2c_init(void)
30 return platform_device_register(&sead3_i2c_device); 28 return platform_device_register(&sead3_i2c_device);
31} 29}
32 30
33module_init(sead3_i2c_init); 31device_initcall(sead3_i2c_init);
34
35MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
36MODULE_LICENSE("GPL");
37MODULE_DESCRIPTION("I2C probe driver for SEAD3");
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
deleted file mode 100644
index 3b12aa5a7c88..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/spinlock.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13
14#define PIC32_NULL 0x00
15#define PIC32_RD 0x01
16#define PIC32_SYSRD 0x02
17#define PIC32_WR 0x10
18#define PIC32_SYSWR 0x20
19#define PIC32_IRQ_CLR 0x40
20#define PIC32_STATUS 0x80
21
22#define DELAY() udelay(100) /* FIXME: needed? */
23
24/* spinlock to ensure atomic access to PIC32 */
25static DEFINE_SPINLOCK(pic32_bus_lock);
26
27/* FIXME: io_remap these */
28static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
29static void __iomem *bus_status = (void __iomem *)0xbf000060;
30
31static inline unsigned int ioready(void)
32{
33 return readl(bus_status) & 1;
34}
35
36static inline void wait_ioready(void)
37{
38 do { } while (!ioready());
39}
40
41static inline void wait_ioclear(void)
42{
43 do { } while (ioready());
44}
45
46static inline void check_ioclear(void)
47{
48 if (ioready()) {
49 pr_debug("ioclear: initially busy\n");
50 do {
51 (void) readl(bus_xfer);
52 DELAY();
53 } while (ioready());
54 pr_debug("ioclear: cleared busy\n");
55 }
56}
57
58u32 pic32_bus_readl(u32 reg)
59{
60 unsigned long flags;
61 u32 status, val;
62
63 spin_lock_irqsave(&pic32_bus_lock, flags);
64
65 check_ioclear();
66
67 writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer);
68 DELAY();
69 wait_ioready();
70 status = readl(bus_xfer);
71 DELAY();
72 val = readl(bus_xfer);
73 wait_ioclear();
74
75 pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status);
76
77 spin_unlock_irqrestore(&pic32_bus_lock, flags);
78
79 return val;
80}
81
82void pic32_bus_writel(u32 val, u32 reg)
83{
84 unsigned long flags;
85 u32 status;
86
87 spin_lock_irqsave(&pic32_bus_lock, flags);
88
89 check_ioclear();
90
91 writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer);
92 DELAY();
93 writel(val, bus_xfer);
94 DELAY();
95 wait_ioready();
96 status = readl(bus_xfer);
97 wait_ioclear();
98
99 pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status);
100
101 spin_unlock_irqrestore(&pic32_bus_lock, flags);
102}
diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
deleted file mode 100644
index 80fe194cfa53..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
+++ /dev/null
@@ -1,423 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17
18#define PIC32_I2CxCON 0x0000
19#define PIC32_I2CxCONCLR 0x0004
20#define PIC32_I2CxCONSET 0x0008
21#define PIC32_I2CxCONINV 0x000C
22#define I2CCON_ON (1<<15)
23#define I2CCON_FRZ (1<<14)
24#define I2CCON_SIDL (1<<13)
25#define I2CCON_SCLREL (1<<12)
26#define I2CCON_STRICT (1<<11)
27#define I2CCON_A10M (1<<10)
28#define I2CCON_DISSLW (1<<9)
29#define I2CCON_SMEN (1<<8)
30#define I2CCON_GCEN (1<<7)
31#define I2CCON_STREN (1<<6)
32#define I2CCON_ACKDT (1<<5)
33#define I2CCON_ACKEN (1<<4)
34#define I2CCON_RCEN (1<<3)
35#define I2CCON_PEN (1<<2)
36#define I2CCON_RSEN (1<<1)
37#define I2CCON_SEN (1<<0)
38
39#define PIC32_I2CxSTAT 0x0010
40#define PIC32_I2CxSTATCLR 0x0014
41#define PIC32_I2CxSTATSET 0x0018
42#define PIC32_I2CxSTATINV 0x001C
43#define I2CSTAT_ACKSTAT (1<<15)
44#define I2CSTAT_TRSTAT (1<<14)
45#define I2CSTAT_BCL (1<<10)
46#define I2CSTAT_GCSTAT (1<<9)
47#define I2CSTAT_ADD10 (1<<8)
48#define I2CSTAT_IWCOL (1<<7)
49#define I2CSTAT_I2COV (1<<6)
50#define I2CSTAT_DA (1<<5)
51#define I2CSTAT_P (1<<4)
52#define I2CSTAT_S (1<<3)
53#define I2CSTAT_RW (1<<2)
54#define I2CSTAT_RBF (1<<1)
55#define I2CSTAT_TBF (1<<0)
56
57#define PIC32_I2CxADD 0x0020
58#define PIC32_I2CxADDCLR 0x0024
59#define PIC32_I2CxADDSET 0x0028
60#define PIC32_I2CxADDINV 0x002C
61#define PIC32_I2CxMSK 0x0030
62#define PIC32_I2CxMSKCLR 0x0034
63#define PIC32_I2CxMSKSET 0x0038
64#define PIC32_I2CxMSKINV 0x003C
65#define PIC32_I2CxBRG 0x0040
66#define PIC32_I2CxBRGCLR 0x0044
67#define PIC32_I2CxBRGSET 0x0048
68#define PIC32_I2CxBRGINV 0x004C
69#define PIC32_I2CxTRN 0x0050
70#define PIC32_I2CxTRNCLR 0x0054
71#define PIC32_I2CxTRNSET 0x0058
72#define PIC32_I2CxTRNINV 0x005C
73#define PIC32_I2CxRCV 0x0060
74
75struct i2c_platform_data {
76 u32 base;
77 struct i2c_adapter adap;
78 u32 xfer_timeout;
79 u32 ack_timeout;
80 u32 ctl_timeout;
81};
82
83extern u32 pic32_bus_readl(u32 reg);
84extern void pic32_bus_writel(u32 val, u32 reg);
85
86static inline void
87StartI2C(struct i2c_platform_data *adap)
88{
89 pr_debug("StartI2C\n");
90 pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET);
91}
92
93static inline void
94StopI2C(struct i2c_platform_data *adap)
95{
96 pr_debug("StopI2C\n");
97 pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET);
98}
99
100static inline void
101AckI2C(struct i2c_platform_data *adap)
102{
103 pr_debug("AckI2C\n");
104 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR);
105 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
106}
107
108static inline void
109NotAckI2C(struct i2c_platform_data *adap)
110{
111 pr_debug("NakI2C\n");
112 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET);
113 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
114}
115
116static inline int
117IdleI2C(struct i2c_platform_data *adap)
118{
119 int i;
120
121 pr_debug("IdleI2C\n");
122 for (i = 0; i < adap->ctl_timeout; i++) {
123 if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) &
124 (I2CCON_ACKEN | I2CCON_RCEN | I2CCON_PEN | I2CCON_RSEN |
125 I2CCON_SEN)) == 0) &&
126 ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
127 (I2CSTAT_TRSTAT)) == 0))
128 return 0;
129 udelay(1);
130 }
131 return -ETIMEDOUT;
132}
133
134static inline u32
135MasterWriteI2C(struct i2c_platform_data *adap, u32 byte)
136{
137 pr_debug("MasterWriteI2C\n");
138
139 pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN);
140
141 return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL;
142}
143
144static inline u32
145MasterReadI2C(struct i2c_platform_data *adap)
146{
147 pr_debug("MasterReadI2C\n");
148
149 pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET);
150
151 while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN)
152 ;
153
154 pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR);
155
156 return pic32_bus_readl(adap->base + PIC32_I2CxRCV);
157}
158
159static int
160do_address(struct i2c_platform_data *adap, unsigned int addr, int rd)
161{
162 pr_debug("doaddress\n");
163
164 IdleI2C(adap);
165 StartI2C(adap);
166 IdleI2C(adap);
167
168 addr <<= 1;
169 if (rd)
170 addr |= 1;
171
172 if (MasterWriteI2C(adap, addr))
173 return -EIO;
174 IdleI2C(adap);
175 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT)
176 return -EIO;
177 return 0;
178}
179
180static int
181i2c_read(struct i2c_platform_data *adap, unsigned char *buf,
182 unsigned int len)
183{
184 int i;
185 u32 data;
186
187 pr_debug("i2c_read\n");
188
189 i = 0;
190 while (i < len) {
191 data = MasterReadI2C(adap);
192 buf[i++] = data;
193 if (i < len)
194 AckI2C(adap);
195 else
196 NotAckI2C(adap);
197 }
198
199 StopI2C(adap);
200 IdleI2C(adap);
201 return 0;
202}
203
204static int
205i2c_write(struct i2c_platform_data *adap, unsigned char *buf,
206 unsigned int len)
207{
208 int i;
209 u32 data;
210
211 pr_debug("i2c_write\n");
212
213 i = 0;
214 while (i < len) {
215 data = buf[i];
216 if (MasterWriteI2C(adap, data))
217 return -EIO;
218 IdleI2C(adap);
219 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
220 I2CSTAT_ACKSTAT)
221 return -EIO;
222 i++;
223 }
224
225 StopI2C(adap);
226 IdleI2C(adap);
227 return 0;
228}
229
230static int
231platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
232{
233 struct i2c_platform_data *adap = i2c_adap->algo_data;
234 struct i2c_msg *p;
235 int i, err = 0;
236
237 pr_debug("platform_xfer\n");
238 for (i = 0; i < num; i++) {
239#define __BUFSIZE 80
240 int ii;
241 static char buf[__BUFSIZE];
242 char *b = buf;
243
244 p = &msgs[i];
245 b += sprintf(buf, " [%d bytes]", p->len);
246 if ((p->flags & I2C_M_RD) == 0) {
247 for (ii = 0; ii < p->len; ii++) {
248 if (b < &buf[__BUFSIZE-4]) {
249 b += sprintf(b, " %02x", p->buf[ii]);
250 } else {
251 strcat(b, "...");
252 break;
253 }
254 }
255 }
256 pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr,
257 (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf);
258 }
259
260
261 for (i = 0; !err && i < num; i++) {
262 p = &msgs[i];
263 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
264 if (err || !p->len)
265 continue;
266 if (p->flags & I2C_M_RD)
267 err = i2c_read(adap, p->buf, p->len);
268 else
269 err = i2c_write(adap, p->buf, p->len);
270 }
271
272 /* Return the number of messages processed, or the error code. */
273 if (err == 0)
274 err = num;
275
276 return err;
277}
278
279static u32
280platform_func(struct i2c_adapter *adap)
281{
282 pr_debug("platform_algo\n");
283 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
284}
285
286static const struct i2c_algorithm platform_algo = {
287 .master_xfer = platform_xfer,
288 .functionality = platform_func,
289};
290
291static void i2c_platform_setup(struct i2c_platform_data *priv)
292{
293 pr_debug("i2c_platform_setup\n");
294
295 pic32_bus_writel(500, priv->base + PIC32_I2CxBRG);
296 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR);
297 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET);
298 pic32_bus_writel((I2CSTAT_BCL | I2CSTAT_IWCOL),
299 (priv->base + PIC32_I2CxSTATCLR));
300}
301
302static void i2c_platform_disable(struct i2c_platform_data *priv)
303{
304 pr_debug("i2c_platform_disable\n");
305}
306
307static int i2c_platform_probe(struct platform_device *pdev)
308{
309 struct i2c_platform_data *priv;
310 struct resource *r;
311 int ret;
312
313 pr_debug("i2c_platform_probe\n");
314 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 if (!r)
316 return -ENODEV;
317
318 priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_platform_data),
319 GFP_KERNEL);
320 if (!priv)
321 return -ENOMEM;
322
323 /* FIXME: need to allocate resource in PIC32 space */
324#if 0
325 priv->base = bus_request_region(r->start, resource_size(r),
326 pdev->name);
327#else
328 priv->base = r->start;
329#endif
330 if (!priv->base)
331 return -EBUSY;
332
333 priv->xfer_timeout = 200;
334 priv->ack_timeout = 200;
335 priv->ctl_timeout = 200;
336
337 priv->adap.nr = pdev->id;
338 priv->adap.algo = &platform_algo;
339 priv->adap.algo_data = priv;
340 priv->adap.dev.parent = &pdev->dev;
341 strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name));
342
343 i2c_platform_setup(priv);
344
345 ret = i2c_add_numbered_adapter(&priv->adap);
346 if (ret) {
347 i2c_platform_disable(priv);
348 return ret;
349 }
350
351 platform_set_drvdata(pdev, priv);
352 return 0;
353}
354
355static int i2c_platform_remove(struct platform_device *pdev)
356{
357 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
358
359 pr_debug("i2c_platform_remove\n");
360 platform_set_drvdata(pdev, NULL);
361 i2c_del_adapter(&priv->adap);
362 i2c_platform_disable(priv);
363 return 0;
364}
365
366#ifdef CONFIG_PM
367static int
368i2c_platform_suspend(struct platform_device *pdev, pm_message_t state)
369{
370 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
371
372 dev_dbg(&pdev->dev, "i2c_platform_disable\n");
373 i2c_platform_disable(priv);
374
375 return 0;
376}
377
378static int
379i2c_platform_resume(struct platform_device *pdev)
380{
381 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
382
383 dev_dbg(&pdev->dev, "i2c_platform_setup\n");
384 i2c_platform_setup(priv);
385
386 return 0;
387}
388#else
389#define i2c_platform_suspend NULL
390#define i2c_platform_resume NULL
391#endif
392
393static struct platform_driver i2c_platform_driver = {
394 .driver = {
395 .name = "i2c_pic32",
396 .owner = THIS_MODULE,
397 },
398 .probe = i2c_platform_probe,
399 .remove = i2c_platform_remove,
400 .suspend = i2c_platform_suspend,
401 .resume = i2c_platform_resume,
402};
403
404static int __init
405i2c_platform_init(void)
406{
407 pr_debug("i2c_platform_init\n");
408 return platform_driver_register(&i2c_platform_driver);
409}
410
411static void __exit
412i2c_platform_exit(void)
413{
414 pr_debug("i2c_platform_exit\n");
415 platform_driver_unregister(&i2c_platform_driver);
416}
417
418MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC.");
419MODULE_DESCRIPTION("PIC32 I2C driver");
420MODULE_LICENSE("GPL");
421
422module_init(i2c_platform_init);
423module_exit(i2c_platform_exit);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 37fe8e7887e2..d3ed15b2b2d1 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -215,17 +215,12 @@ static int ltq_pci_probe(struct platform_device *pdev)
215 215
216 pci_clear_flags(PCI_PROBE_ONLY); 216 pci_clear_flags(PCI_PROBE_ONLY);
217 217
218 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); 218 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
220 if (!res_cfg || !res_bridge) {
221 dev_err(&pdev->dev, "missing memory resources\n");
222 return -EINVAL;
223 }
224
225 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); 219 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
226 if (IS_ERR(ltq_pci_membase)) 220 if (IS_ERR(ltq_pci_membase))
227 return PTR_ERR(ltq_pci_membase); 221 return PTR_ERR(ltq_pci_membase);
228 222
223 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); 224 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
230 if (IS_ERR(ltq_pci_mapped_cfg)) 225 if (IS_ERR(ltq_pci_mapped_cfg))
231 return PTR_ERR(ltq_pci_mapped_cfg); 226 return PTR_ERR(ltq_pci_mapped_cfg);
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c
index f914c753de21..8d53d7a2ed45 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq.c
@@ -16,6 +16,7 @@
16#include <linux/time.h> 16#include <linux/time.h>
17 17
18#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
19#include <asm/setup.h>
19 20
20#include <msp_int.h> 21#include <msp_int.h>
21 22
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
index b8df2f7b3328..1207ec4dfb77 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_data *d,
131 int cpu; 131 int cpu;
132 unsigned long flags; 132 unsigned long flags;
133 unsigned int mtflags; 133 unsigned int mtflags;
134 unsigned long imask = (1 << (irq - MSP_CIC_INTBASE)); 134 unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));
135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG; 135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
136 136
137 /* timer balancing should be disabled in kernel code */ 137 /* timer balancing should be disabled in kernel code */
138 BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER); 138 BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);
139 139
140 LOCK_CORE(flags, mtflags); 140 LOCK_CORE(flags, mtflags);
141 /* enable if any of each VPE's TCs require this IRQ */ 141 /* enable if any of each VPE's TCs require this IRQ */
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
index c8ed2c807e69..455c40d6d625 100644
--- a/arch/mips/sibyte/Makefile
+++ b/arch/mips/sibyte/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_SIBYTE_RHONE) += swarm/
25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/ 25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/
26obj-$(CONFIG_SIBYTE_SWARM) += swarm/ 26obj-$(CONFIG_SIBYTE_SWARM) += swarm/
27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/ 27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/
28obj-$(CONFIG_SIBYTE_LITTLESUR) += swarm/
diff --git a/drivers/cpuidle/Kconfig.mips b/drivers/cpuidle/Kconfig.mips
index 0e70ee28a5ca..4102be01d06a 100644
--- a/drivers/cpuidle/Kconfig.mips
+++ b/drivers/cpuidle/Kconfig.mips
@@ -3,7 +3,7 @@
3# 3#
4config MIPS_CPS_CPUIDLE 4config MIPS_CPS_CPUIDLE
5 bool "CPU Idle driver for MIPS CPS platforms" 5 bool "CPU Idle driver for MIPS CPS platforms"
6 depends on CPU_IDLE 6 depends on CPU_IDLE && MIPS_CPS
7 depends on SYS_SUPPORTS_MIPS_CPS 7 depends on SYS_SUPPORTS_MIPS_CPS
8 select ARCH_NEEDS_CPU_IDLE_COUPLED if MIPS_MT 8 select ARCH_NEEDS_CPU_IDLE_COUPLED if MIPS_MT
9 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 9 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-02 01:14:42 -0500