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authorMichael Hennerich <michael.hennerich@analog.com>2008-02-08 15:11:14 -0500
committerBryan Wu <bryan.wu@analog.com>2008-02-08 15:11:14 -0500
commit2c4f829b0ce3d2fb447acca823e141094a50daa5 (patch)
tree4f0b36956425896d0f8db28022ddc45372014a4b
parent856783b37a958086c83ea44544d366affd0c2c4b (diff)
[Blackfin] arch: Merge BF561 support into ints-priority
Merge single core ints-priority-sc.c and dual core ints-priority-dc.c into one common code ints-priority.c Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat
-rw-r--r--arch/blackfin/mach-common/Makefile4
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c484
-rw-r--r--arch/blackfin/mach-common/ints-priority.c (renamed from arch/blackfin/mach-common/ints-priority-sc.c)129
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h20
4 files changed, 117 insertions, 520 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 8636d4284bdb..15e33ca1ce80 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,8 +4,6 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o entry.o \ 6 cache.o cacheinit.o entry.o \
7 interrupt.o lock.o irqpanic.o arch_checks.o 7 interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
8 8
9obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
10obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
11obj-$(CONFIG_PM) += pm.o dpmc.o 9obj-$(CONFIG_PM) += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
deleted file mode 100644
index 8d18d6b163bb..000000000000
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ /dev/null
@@ -1,484 +0,0 @@
1/*
2 * File: arch/blackfin/mach-common/ints-priority-dc.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2006 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48/*
49 * NOTES:
50 * - we have separated the physical Hardware interrupt from the
51 * levels that the LINUX kernel sees (see the description in irq.h)
52 * -
53 */
54
55/* Initialize this to an actual value to force it into the .data
56 * section so that we know it is properly initialized at entry into
57 * the kernel but before bss is initialized to zero (which is where
58 * it would live otherwise). The 0x1f magic represents the IRQs we
59 * cannot actually mask out in hardware.
60 */
61unsigned long irq_flags = 0x1f;
62
63/* The number of spurious interrupts */
64atomic_t num_spurious;
65
66struct ivgx {
67 /* irq number for request_irq, available in mach-bf561/irq.h */
68 int irqno;
69 /* corresponding bit in the SICA_ISR0 register */
70 int isrflag0;
71 /* corresponding bit in the SICA_ISR1 register */
72 int isrflag1;
73} ivg_table[NR_PERI_INTS];
74
75struct ivg_slice {
76 /* position of first irq in ivg_table for given ivg */
77 struct ivgx *ifirst;
78 struct ivgx *istop;
79} ivg7_13[IVG13 - IVG7 + 1];
80
81static void search_IAR(void);
82
83/*
84 * Search SIC_IAR and fill tables with the irqvalues
85 * and their positions in the SIC_ISR register.
86 */
87static void __init search_IAR(void)
88{
89 unsigned ivg, irq_pos = 0;
90 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
91 int irqn;
92
93 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
94
95 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
96 int iar_shift = (irqn & 7) * 4;
97 if (ivg ==
98 (0xf &
99 bfin_read32((unsigned long *)SICA_IAR0 +
100 (irqn >> 3)) >> iar_shift)) {
101 ivg_table[irq_pos].irqno = IVG7 + irqn;
102 ivg_table[irq_pos].isrflag0 =
103 (irqn < 32 ? (1 << irqn) : 0);
104 ivg_table[irq_pos].isrflag1 =
105 (irqn < 32 ? 0 : (1 << (irqn - 32)));
106 ivg7_13[ivg].istop++;
107 irq_pos++;
108 }
109 }
110 }
111}
112
113/*
114 * This is for BF561 internal IRQs
115 */
116
117static void ack_noop(unsigned int irq)
118{
119 /* Dummy function. */
120}
121
122static void bf561_core_mask_irq(unsigned int irq)
123{
124 irq_flags &= ~(1 << irq);
125 if (!irqs_disabled())
126 local_irq_enable();
127}
128
129static void bf561_core_unmask_irq(unsigned int irq)
130{
131 irq_flags |= 1 << irq;
132 /*
133 * If interrupts are enabled, IMASK must contain the same value
134 * as irq_flags. Make sure that invariant holds. If interrupts
135 * are currently disabled we need not do anything; one of the
136 * callers will take care of setting IMASK to the proper value
137 * when reenabling interrupts.
138 * local_irq_enable just does "STI irq_flags", so it's exactly
139 * what we need.
140 */
141 if (!irqs_disabled())
142 local_irq_enable();
143 return;
144}
145
146static void bf561_internal_mask_irq(unsigned int irq)
147{
148 unsigned long irq_mask;
149 if ((irq - (IRQ_CORETMR + 1)) < 32) {
150 irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
151 bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() & ~irq_mask);
152 } else {
153 irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
154 bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() & ~irq_mask);
155 }
156}
157
158static void bf561_internal_unmask_irq(unsigned int irq)
159{
160 unsigned long irq_mask;
161
162 if ((irq - (IRQ_CORETMR + 1)) < 32) {
163 irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
164 bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() | irq_mask);
165 } else {
166 irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
167 bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() | irq_mask);
168 }
169 SSYNC();
170}
171
172static struct irq_chip bf561_core_irqchip = {
173 .ack = ack_noop,
174 .mask = bf561_core_mask_irq,
175 .unmask = bf561_core_unmask_irq,
176};
177
178static struct irq_chip bf561_internal_irqchip = {
179 .ack = ack_noop,
180 .mask = bf561_internal_mask_irq,
181 .unmask = bf561_internal_unmask_irq,
182};
183
184static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
185static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
186
187static void bf561_gpio_ack_irq(unsigned int irq)
188{
189 u16 gpionr = irq - IRQ_PF0;
190
191 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
192 set_gpio_data(gpionr, 0);
193 SSYNC();
194 }
195}
196
197static void bf561_gpio_mask_ack_irq(unsigned int irq)
198{
199 u16 gpionr = irq - IRQ_PF0;
200
201 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
202 set_gpio_data(gpionr, 0);
203 SSYNC();
204 }
205
206 set_gpio_maska(gpionr, 0);
207 SSYNC();
208}
209
210static void bf561_gpio_mask_irq(unsigned int irq)
211{
212 set_gpio_maska(irq - IRQ_PF0, 0);
213 SSYNC();
214}
215
216static void bf561_gpio_unmask_irq(unsigned int irq)
217{
218 set_gpio_maska(irq - IRQ_PF0, 1);
219 SSYNC();
220}
221
222static unsigned int bf561_gpio_irq_startup(unsigned int irq)
223{
224 unsigned int ret;
225 char buf[8];
226 u16 gpionr = irq - IRQ_PF0;
227
228 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
229 snprintf(buf, sizeof buf, "IRQ %d", irq);
230 ret = gpio_request(gpionr, buf);
231 if (ret)
232 return ret;
233
234 }
235
236 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
237 bf561_gpio_unmask_irq(irq);
238
239 return ret;
240
241}
242
243static void bf561_gpio_irq_shutdown(unsigned int irq)
244{
245 bf561_gpio_mask_irq(irq);
246 gpio_free(irq - IRQ_PF0);
247 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
248}
249
250static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
251{
252
253 unsigned int ret;
254 char buf[8];
255 u16 gpionr = irq - IRQ_PF0;
256
257
258 if (type == IRQ_TYPE_PROBE) {
259 /* only probe unenabled GPIO interrupt lines */
260 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
261 return 0;
262 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
263
264 }
265
266 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
267 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
268
269 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
270 snprintf(buf, sizeof buf, "IRQ %d", irq);
271 ret = gpio_request(gpionr, buf);
272 if (ret)
273 return ret;
274
275 }
276
277 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
278 } else {
279 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
280 return 0;
281 }
282
283
284 set_gpio_dir(gpionr, 0);
285 set_gpio_inen(gpionr, 1);
286
287
288 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
289 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
290 set_gpio_edge(gpionr, 1);
291 } else {
292 set_gpio_edge(gpionr, 0);
293 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
294 }
295
296 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
297 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
298 set_gpio_both(gpionr, 1);
299 else
300 set_gpio_both(gpionr, 0);
301
302 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
303 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
304 else
305 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
306
307 SSYNC();
308
309 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
310 set_irq_handler(irq, handle_edge_irq);
311 else
312 set_irq_handler(irq, handle_level_irq);
313
314 return 0;
315}
316
317static struct irq_chip bf561_gpio_irqchip = {
318 .ack = bf561_gpio_ack_irq,
319 .mask = bf561_gpio_mask_irq,
320 .mask_ack = bf561_gpio_mask_ack_irq,
321 .unmask = bf561_gpio_unmask_irq,
322 .set_type = bf561_gpio_irq_type,
323 .startup = bf561_gpio_irq_startup,
324 .shutdown = bf561_gpio_irq_shutdown
325};
326
327static void bf561_demux_gpio_irq(unsigned int inta_irq,
328 struct irq_desc *intb_desc)
329{
330 int irq, flag_d, mask;
331 u16 gpio;
332
333 switch (inta_irq) {
334 case IRQ_PROG0_INTA:
335 irq = IRQ_PF0;
336 break;
337 case IRQ_PROG1_INTA:
338 irq = IRQ_PF16;
339 break;
340 case IRQ_PROG2_INTA:
341 irq = IRQ_PF32;
342 break;
343 default:
344 dump_stack();
345 return;
346 }
347
348 gpio = irq - IRQ_PF0;
349
350 flag_d = get_gpiop_data(gpio);
351 mask = flag_d & (gpio_enabled[gpio_bank(gpio)] &
352 get_gpiop_maska(gpio));
353
354 do {
355 if (mask & 1) {
356 struct irq_desc *desc = irq_desc + irq;
357 desc->handle_irq(irq, desc);
358 }
359 irq++;
360 mask >>= 1;
361 } while (mask);
362
363
364}
365
366void __init init_exception_vectors(void)
367{
368 SSYNC();
369
370 /* cannot program in software:
371 * evt0 - emulation (jtag)
372 * evt1 - reset
373 */
374 bfin_write_EVT2(evt_nmi);
375 bfin_write_EVT3(trap);
376 bfin_write_EVT5(evt_ivhw);
377 bfin_write_EVT6(evt_timer);
378 bfin_write_EVT7(evt_evt7);
379 bfin_write_EVT8(evt_evt8);
380 bfin_write_EVT9(evt_evt9);
381 bfin_write_EVT10(evt_evt10);
382 bfin_write_EVT11(evt_evt11);
383 bfin_write_EVT12(evt_evt12);
384 bfin_write_EVT13(evt_evt13);
385 bfin_write_EVT14(evt14_softirq);
386 bfin_write_EVT15(evt_system_call);
387 CSYNC();
388}
389
390/*
391 * This function should be called during kernel startup to initialize
392 * the BFin IRQ handling routines.
393 */
394int __init init_arch_irq(void)
395{
396 int irq;
397 unsigned long ilat = 0;
398 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
399 bfin_write_SICA_IMASK0(SIC_UNMASK_ALL);
400 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
401 SSYNC();
402
403 bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
404 bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
405
406 local_irq_disable();
407
408 init_exception_buff();
409
410 for (irq = 0; irq <= SYS_IRQS; irq++) {
411 if (irq <= IRQ_CORETMR)
412 set_irq_chip(irq, &bf561_core_irqchip);
413 else
414 set_irq_chip(irq, &bf561_internal_irqchip);
415
416 if ((irq != IRQ_PROG0_INTA) &&
417 (irq != IRQ_PROG1_INTA) &&
418 (irq != IRQ_PROG2_INTA))
419 set_irq_handler(irq, handle_simple_irq);
420 else
421 set_irq_chained_handler(irq, bf561_demux_gpio_irq);
422 }
423
424 for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
425 set_irq_chip(irq, &bf561_gpio_irqchip);
426 /* if configured as edge, then will be changed to do_edge_IRQ */
427 set_irq_handler(irq, handle_level_irq);
428 }
429
430 bfin_write_IMASK(0);
431 CSYNC();
432 ilat = bfin_read_ILAT();
433 CSYNC();
434 bfin_write_ILAT(ilat);
435 CSYNC();
436
437 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
438 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
439 * local_irq_enable()
440 */
441 program_IAR();
442 /* Therefore it's better to setup IARs before interrupts enabled */
443 search_IAR();
444
445 /* Enable interrupts IVG7-15 */
446 irq_flags = irq_flags | IMASK_IVG15 |
447 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
448 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
449
450 return 0;
451}
452
453#ifdef CONFIG_DO_IRQ_L1
454__attribute__((l1_text))
455#endif
456void do_irq(int vec, struct pt_regs *fp)
457{
458 if (vec == EVT_IVTMR_P) {
459 vec = IRQ_CORETMR;
460 } else {
461 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
462 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
463 unsigned long sic_status0, sic_status1;
464
465 SSYNC();
466 sic_status0 = bfin_read_SICA_IMASK0() & bfin_read_SICA_ISR0();
467 sic_status1 = bfin_read_SICA_IMASK1() & bfin_read_SICA_ISR1();
468
469 for (;; ivg++) {
470 if (ivg >= ivg_stop) {
471 atomic_inc(&num_spurious);
472 return;
473 } else if ((sic_status0 & ivg->isrflag0) ||
474 (sic_status1 & ivg->isrflag1))
475 break;
476 }
477 vec = ivg->irqno;
478 }
479 asm_do_IRQ(vec, fp);
480
481#ifdef CONFIG_KGDB
482 kgdb_process_breakpoint();
483#endif
484}
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority.c
index dec42acb5de0..166dbba0c396 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -98,8 +98,7 @@ static void __init search_IAR(void)
98 98
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100 int iar_shift = (irqn & 7) * 4; 100 int iar_shift = (irqn & 7) * 4;
101 if (ivg == 101 if (ivg == (0xf &
102 (0xf &
103#ifndef CONFIG_BF52x 102#ifndef CONFIG_BF52x
104 bfin_read32((unsigned long *)SIC_IAR0 + 103 bfin_read32((unsigned long *)SIC_IAR0 +
105 (irqn >> 3)) >> iar_shift)) { 104 (irqn >> 3)) >> iar_shift)) {
@@ -206,8 +205,7 @@ static void bfin_generic_error_mask_irq(unsigned int irq)
206 if (!error_int_mask) { 205 if (!error_int_mask) {
207 local_irq_disable(); 206 local_irq_disable();
208 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 207 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
209 ~(1 << 208 ~(1 << (IRQ_GENERIC_ERROR -
210 (IRQ_GENERIC_ERROR -
211 (IRQ_CORETMR + 1)))); 209 (IRQ_CORETMR + 1))));
212 SSYNC(); 210 SSYNC();
213 local_irq_enable(); 211 local_irq_enable();
@@ -232,7 +230,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
232}; 230};
233 231
234static void bfin_demux_error_irq(unsigned int int_err_irq, 232static void bfin_demux_error_irq(unsigned int int_err_irq,
235 struct irq_desc *intb_desc) 233 struct irq_desc *inta_desc)
236{ 234{
237 int irq = 0; 235 int irq = 0;
238 236
@@ -446,27 +444,81 @@ static struct irq_chip bfin_gpio_irqchip = {
446 .shutdown = bfin_gpio_irq_shutdown 444 .shutdown = bfin_gpio_irq_shutdown
447}; 445};
448 446
449static void bfin_demux_gpio_irq(unsigned int intb_irq, 447static void bfin_demux_gpio_irq(unsigned int inta_irq,
450 struct irq_desc *intb_desc) 448 struct irq_desc *desc)
451{ 449{
452 u16 i; 450 unsigned int i, gpio, mask, irq, search = 0;
453 struct irq_desc *desc; 451
454 452 switch (inta_irq) {
455 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { 453#if defined(CONFIG_BF53x)
456 int irq = IRQ_PF0 + i; 454 case IRQ_PROG_INTA:
457 int flag_d = get_gpiop_data(i); 455 irq = IRQ_PF0;
458 int mask = 456 search = 1;
459 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i)); 457 break;
460 458# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
461 while (mask) { 459 case IRQ_MAC_RX:
462 if (mask & 1) { 460 irq = IRQ_PH0;
463 desc = irq_desc + irq; 461 break;
464 desc->handle_irq(irq, desc); 462# endif
463#elif defined(CONFIG_BF52x)
464 case IRQ_PORTF_INTA:
465 irq = IRQ_PF0;
466 break;
467 case IRQ_PORTG_INTA:
468 irq = IRQ_PG0;
469 break;
470 case IRQ_PORTH_INTA:
471 irq = IRQ_PH0;
472 break;
473#elif defined(CONFIG_BF561)
474 case IRQ_PROG0_INTA:
475 irq = IRQ_PF0;
476 break;
477 case IRQ_PROG1_INTA:
478 irq = IRQ_PF16;
479 break;
480 case IRQ_PROG2_INTA:
481 irq = IRQ_PF32;
482 break;
483#endif
484 default:
485 BUG();
486 return;
487 }
488
489 if (search) {
490 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
491 irq += i;
492
493 mask = get_gpiop_data(i) &
494 (gpio_enabled[gpio_bank(i)] &
495 get_gpiop_maska(i));
496
497 while (mask) {
498 if (mask & 1) {
499 desc = irq_desc + irq;
500 desc->handle_irq(irq, desc);
501 }
502 irq++;
503 mask >>= 1;
465 } 504 }
466 irq++;
467 mask >>= 1;
468 } 505 }
506 } else {
507 gpio = irq_to_gpio(irq);
508 mask = get_gpiop_data(gpio) &
509 (gpio_enabled[gpio_bank(gpio)] &
510 get_gpiop_maska(gpio));
511
512 do {
513 if (mask & 1) {
514 desc = irq_desc + irq;
515 desc->handle_irq(irq, desc);
516 }
517 irq++;
518 mask >>= 1;
519 } while (mask);
469 } 520 }
521
470} 522}
471 523
472#else /* CONFIG_BF54x */ 524#else /* CONFIG_BF54x */
@@ -721,14 +773,13 @@ static struct irq_chip bfin_gpio_irqchip = {
721 .shutdown = bfin_gpio_irq_shutdown 773 .shutdown = bfin_gpio_irq_shutdown
722}; 774};
723 775
724static void bfin_demux_gpio_irq(unsigned int intb_irq, 776static void bfin_demux_gpio_irq(unsigned int inta_irq,
725 struct irq_desc *intb_desc) 777 struct irq_desc *desc)
726{ 778{
727 u8 bank, pint_val; 779 u8 bank, pint_val;
728 u32 request, irq; 780 u32 request, irq;
729 struct irq_desc *desc;
730 781
731 switch (intb_irq) { 782 switch (inta_irq) {
732 case IRQ_PINT0: 783 case IRQ_PINT0:
733 bank = 0; 784 bank = 0;
734 break; 785 break;
@@ -795,7 +846,7 @@ int __init init_arch_irq(void)
795 int irq; 846 int irq;
796 unsigned long ilat = 0; 847 unsigned long ilat = 0;
797 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 848 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
798#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) 849#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
799 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 850 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
800 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 851 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
801 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 852 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
@@ -812,6 +863,8 @@ int __init init_arch_irq(void)
812 863
813 local_irq_disable(); 864 local_irq_disable();
814 865
866 init_exception_buff();
867
815#ifdef CONFIG_BF54x 868#ifdef CONFIG_BF54x
816# ifdef CONFIG_PINTx_REASSIGN 869# ifdef CONFIG_PINTx_REASSIGN
817 pint[0]->assign = CONFIG_PINT0_ASSIGN; 870 pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -874,6 +927,19 @@ int __init init_arch_irq(void)
874 set_irq_chained_handler(irq, 927 set_irq_chained_handler(irq,
875 bfin_demux_gpio_irq); 928 bfin_demux_gpio_irq);
876 break; 929 break;
930#elif defined(CONFIG_BF561)
931 case IRQ_PROG0_INTA:
932 set_irq_chained_handler(irq,
933 bfin_demux_gpio_irq);
934 break;
935 case IRQ_PROG1_INTA:
936 set_irq_chained_handler(irq,
937 bfin_demux_gpio_irq);
938 break;
939 case IRQ_PROG2_INTA:
940 set_irq_chained_handler(irq,
941 bfin_demux_gpio_irq);
942 break;
877#endif 943#endif
878 default: 944 default:
879 set_irq_handler(irq, handle_simple_irq); 945 set_irq_handler(irq, handle_simple_irq);
@@ -893,11 +959,8 @@ int __init init_arch_irq(void)
893 } 959 }
894#endif 960#endif
895 961
896#ifndef CONFIG_BF54x 962 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
897 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { 963
898#else
899 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
900#endif
901 set_irq_chip(irq, &bfin_gpio_irqchip); 964 set_irq_chip(irq, &bfin_gpio_irqchip);
902 /* if configured as edge, then will be changed to do_edge_IRQ */ 965 /* if configured as edge, then will be changed to do_edge_IRQ */
903 set_irq_handler(irq, handle_level_irq); 966 set_irq_handler(irq, handle_level_irq);
@@ -936,7 +999,7 @@ void do_irq(int vec, struct pt_regs *fp)
936 } else { 999 } else {
937 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1000 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
938 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1001 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
939#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) 1002#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
940 unsigned long sic_status[3]; 1003 unsigned long sic_status[3];
941 1004
942 SSYNC(); 1005 SSYNC();
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 562aee39895c..362617f93845 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -49,4 +49,24 @@
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51 51
52
53#define SIC_IAR0 SICA_IAR0
54#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
55#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
56#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
57#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
58
59#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
60#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
61#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
62#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
63#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
64#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
65
66#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
67#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
68#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
69#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
70
71
52#endif /* _MACH_BLACKFIN_H_ */ 72#endif /* _MACH_BLACKFIN_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 09:50:54 -0500