arm: sunxi: Add clock definitions for the new clock driver

This introduces proper clock definitions on sunxi.dtsi, to be used
with the new clock driver for sunxi.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

1 files changed, 80 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 8b36abea9f2e..acf7777cf61f 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -24,13 +24,90 @@
 
         clocks {
                 #address-cells = <1>;
-                #size-cells = <0>;
+                #size-cells = <1>;
+                ranges;
 
-                osc: oscillator {
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M_fixed: osc24M_fixed {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <24000000>;
                 };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clocks = <&osc24M_fixed>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sunxi-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
         };
 
         soc {
@@ -44,7 +121,7 @@
                         compatible = "allwinner,sunxi-timer";
                         reg = <0x01c20c00 0x90>;
                         interrupts = <22>;
-                        clocks = <&osc>;
+                        clocks = <&osc24M>;
                 };
 
                 wdt: watchdog@01c20c90 {