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authorHeiko Stübner <heiko@sntech.de>2014-07-02 20:01:14 -0400
committerMike Turquette <mturquette@linaro.org>2014-07-13 15:17:09 -0400
commit2c14736c75dba10d9da4c8337e1baee11577691c (patch)
treec99a6e5f1adfea7a4b721e4013e80617c345d5a3
parent43aea81778e280a4e1d7ef144b3511bbc4aace11 (diff)
clk: rockchip: add clock driver for rk3188 and rk3066 clocks
This adds a clock driver that handles the specific muxes, dividers and gates of rk3188 and rk3066 SoCs. The structure of the clock list resembles the arrangement of their counterparts in the clock architecture diagrams found in the SoC documentation. Clocks exported to the clock provider are currently limited to well known or measured ones. So additional clock exports may be necessary in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c672
-rw-r--r--include/dt-bindings/clock/rk3066a-cru.h35
-rw-r--r--include/dt-bindings/clock/rk3188-cru-common.h249
-rw-r--r--include/dt-bindings/clock/rk3188-cru.h51
5 files changed, 1009 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 85f8a551fc1a..3eebf72fe91f 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,3 +6,5 @@ obj-y += clk-rockchip.o
6obj-y += clk.o 6obj-y += clk.o
7obj-y += clk-pll.o 7obj-y += clk-pll.o
8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
9
10obj-y += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
new file mode 100644
index 000000000000..a83a6d8d0fb6
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -0,0 +1,672 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3188-cru-common.h>
20#include "clk.h"
21
22#define RK3188_GRF_SOC_STATUS 0xac
23
24enum rk3188_plls {
25 apll, cpll, dpll, gpll,
26};
27
28struct rockchip_pll_rate_table rk3188_pll_rates[] = {
29 RK3066_PLL_RATE(2208000000, 1, 92, 1),
30 RK3066_PLL_RATE(2184000000, 1, 91, 1),
31 RK3066_PLL_RATE(2160000000, 1, 90, 1),
32 RK3066_PLL_RATE(2136000000, 1, 89, 1),
33 RK3066_PLL_RATE(2112000000, 1, 88, 1),
34 RK3066_PLL_RATE(2088000000, 1, 87, 1),
35 RK3066_PLL_RATE(2064000000, 1, 86, 1),
36 RK3066_PLL_RATE(2040000000, 1, 85, 1),
37 RK3066_PLL_RATE(2016000000, 1, 84, 1),
38 RK3066_PLL_RATE(1992000000, 1, 83, 1),
39 RK3066_PLL_RATE(1968000000, 1, 82, 1),
40 RK3066_PLL_RATE(1944000000, 1, 81, 1),
41 RK3066_PLL_RATE(1920000000, 1, 80, 1),
42 RK3066_PLL_RATE(1896000000, 1, 79, 1),
43 RK3066_PLL_RATE(1872000000, 1, 78, 1),
44 RK3066_PLL_RATE(1848000000, 1, 77, 1),
45 RK3066_PLL_RATE(1824000000, 1, 76, 1),
46 RK3066_PLL_RATE(1800000000, 1, 75, 1),
47 RK3066_PLL_RATE(1776000000, 1, 74, 1),
48 RK3066_PLL_RATE(1752000000, 1, 73, 1),
49 RK3066_PLL_RATE(1728000000, 1, 72, 1),
50 RK3066_PLL_RATE(1704000000, 1, 71, 1),
51 RK3066_PLL_RATE(1680000000, 1, 70, 1),
52 RK3066_PLL_RATE(1656000000, 1, 69, 1),
53 RK3066_PLL_RATE(1632000000, 1, 68, 1),
54 RK3066_PLL_RATE(1608000000, 1, 67, 1),
55 RK3066_PLL_RATE(1560000000, 1, 65, 1),
56 RK3066_PLL_RATE(1512000000, 1, 63, 1),
57 RK3066_PLL_RATE(1488000000, 1, 62, 1),
58 RK3066_PLL_RATE(1464000000, 1, 61, 1),
59 RK3066_PLL_RATE(1440000000, 1, 60, 1),
60 RK3066_PLL_RATE(1416000000, 1, 59, 1),
61 RK3066_PLL_RATE(1392000000, 1, 58, 1),
62 RK3066_PLL_RATE(1368000000, 1, 57, 1),
63 RK3066_PLL_RATE(1344000000, 1, 56, 1),
64 RK3066_PLL_RATE(1320000000, 1, 55, 1),
65 RK3066_PLL_RATE(1296000000, 1, 54, 1),
66 RK3066_PLL_RATE(1272000000, 1, 53, 1),
67 RK3066_PLL_RATE(1248000000, 1, 52, 1),
68 RK3066_PLL_RATE(1224000000, 1, 51, 1),
69 RK3066_PLL_RATE(1200000000, 1, 50, 1),
70 RK3066_PLL_RATE(1188000000, 2, 99, 1),
71 RK3066_PLL_RATE(1176000000, 1, 49, 1),
72 RK3066_PLL_RATE(1128000000, 1, 47, 1),
73 RK3066_PLL_RATE(1104000000, 1, 46, 1),
74 RK3066_PLL_RATE(1008000000, 1, 84, 2),
75 RK3066_PLL_RATE( 912000000, 1, 76, 2),
76 RK3066_PLL_RATE( 891000000, 8, 594, 2),
77 RK3066_PLL_RATE( 888000000, 1, 74, 2),
78 RK3066_PLL_RATE( 816000000, 1, 68, 2),
79 RK3066_PLL_RATE( 798000000, 2, 133, 2),
80 RK3066_PLL_RATE( 792000000, 1, 66, 2),
81 RK3066_PLL_RATE( 768000000, 1, 64, 2),
82 RK3066_PLL_RATE( 742500000, 8, 495, 2),
83 RK3066_PLL_RATE( 696000000, 1, 58, 2),
84 RK3066_PLL_RATE( 600000000, 1, 50, 2),
85 RK3066_PLL_RATE( 594000000, 2, 198, 4),
86 RK3066_PLL_RATE( 552000000, 1, 46, 2),
87 RK3066_PLL_RATE( 504000000, 1, 84, 4),
88 RK3066_PLL_RATE( 456000000, 1, 76, 4),
89 RK3066_PLL_RATE( 408000000, 1, 68, 4),
90 RK3066_PLL_RATE( 384000000, 2, 128, 4),
91 RK3066_PLL_RATE( 360000000, 1, 60, 4),
92 RK3066_PLL_RATE( 312000000, 1, 52, 4),
93 RK3066_PLL_RATE( 300000000, 1, 50, 4),
94 RK3066_PLL_RATE( 297000000, 2, 198, 8),
95 RK3066_PLL_RATE( 252000000, 1, 84, 8),
96 RK3066_PLL_RATE( 216000000, 1, 72, 8),
97 RK3066_PLL_RATE( 148500000, 2, 99, 8),
98 RK3066_PLL_RATE( 126000000, 1, 84, 16),
99 RK3066_PLL_RATE( 48000000, 1, 64, 32),
100 { /* sentinel */ },
101};
102
103PNAME(mux_pll_p) = { "xin24m", "xin32k" };
104PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
105PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
106PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
107PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
108PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
109PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
110PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
111PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
112PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
113PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
114PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
115PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
116PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
117PNAME(mux_mac_p) = { "gpll", "dpll" };
118PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
119
120static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
121 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
122 RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
123 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
124 RK2928_MODE_CON, 4, 5, NULL),
125 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
126 RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
127 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
128 RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
129};
130
131#define MFLAGS CLK_MUX_HIWORD_MASK
132#define DFLAGS CLK_DIVIDER_HIWORD_MASK
133#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
134
135/* 2 ^ (val + 1) */
136static struct clk_div_table div_core_peri_t[] = {
137 { .val = 0, .div = 2 },
138 { .val = 1, .div = 4 },
139 { .val = 2, .div = 8 },
140 { .val = 3, .div = 16 },
141 { /* sentinel */ },
142};
143
144static struct rockchip_clk_branch common_clk_branches[] __initdata = {
145 /*
146 * Clock-Architecture Diagram 2
147 */
148
149 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
150
151 /* these two are set by the cpuclk and should not be changed */
152 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
153 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
154 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
155
156 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
157 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
158 RK2928_CLKGATE_CON(3), 9, GFLAGS),
159 GATE(0, "hclk_vepu", "aclk_vepu", 0,
160 RK2928_CLKGATE_CON(3), 10, GFLAGS),
161 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
162 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
163 RK2928_CLKGATE_CON(3), 11, GFLAGS),
164 GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
165 RK2928_CLKGATE_CON(3), 12, GFLAGS),
166
167 GATE(0, "gpll_ddr", "gpll", 0,
168 RK2928_CLKGATE_CON(1), 7, GFLAGS),
169 COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,