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authorAaro Koskinen <aaro.koskinen@iki.fi>2011-03-08 15:16:19 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-03-09 19:02:55 -0500
commit2b9edd38230ba99f7faeebf69400cfa612642695 (patch)
tree4f470d59fa3e24d7140624f9299bc6eaad47ca35
parent81018f0038269d6957b6cfd0f5d454b48f5369f2 (diff)
staging: xgifb: vb_init: delete unused functions
Delete unused functions. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/xgifb/vb_init.c1014
1 files changed, 0 insertions, 1014 deletions
diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index 24dc00c2c3e0..2cf50ddc5b5b 100644
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -17,27 +17,6 @@
17 17
18static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth; 18static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19 19
20static unsigned short XGINew_SDRDRAM_TYPE[13][5] = {
21 { 2, 12, 9, 64, 0x35},
22 { 1, 13, 9, 64, 0x44},
23 { 2, 12, 8, 32, 0x31},
24 { 2, 11, 9, 32, 0x25},
25 { 1, 12, 9, 32, 0x34},
26 { 1, 13, 8, 32, 0x40},
27 { 2, 11, 8, 16, 0x21},
28 { 1, 12, 8, 16, 0x30},
29 { 1, 11, 9, 16, 0x24},
30 { 1, 11, 8, 8, 0x20},
31 { 2, 9, 8, 4, 0x01},
32 { 1, 10, 8, 4, 0x10},
33 { 1, 9, 8, 2, 0x00} };
34
35static unsigned short XGINew_DDRDRAM_TYPE[4][5] = {
36 { 2, 12, 9, 64, 0x35},
37 { 2, 12, 8, 32, 0x31},
38 { 2, 11, 8, 16, 0x21},
39 { 2, 9, 8, 4, 0x01} };
40
41static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = { 20static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
42 { 2, 13, 9, 64, 0x45}, 21 { 2, 13, 9, 64, 0x45},
43 { 2, 12, 9, 32, 0x35}, 22 { 2, 12, 9, 32, 0x35},
@@ -59,23 +38,14 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
59 { 2, 12, 8, 4, 0x31} }; 38 { 2, 12, 8, 4, 0x31} };
60 39
61void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *); 40void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *);
62void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *, struct vb_device_info *);
63void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *); 41void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
64void XGINew_SetDRAMModeRegister(struct vb_device_info *);
65void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension, 42void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
66 unsigned long, struct vb_device_info *); 43 unsigned long, struct vb_device_info *);
67unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, 44unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
68 struct vb_device_info *pVBInfo); 45 struct vb_device_info *pVBInfo);
69 46
70int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *); 47int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
71void XGINew_DisableRefresh(struct xgi_hw_device_info *, struct vb_device_info *) ;
72void XGINew_CheckBusWidth_310(struct vb_device_info *) ;
73int XGINew_SDRSizing(struct vb_device_info *);
74int XGINew_DDRSizing(struct vb_device_info *);
75void XGINew_EnableRefresh(struct xgi_hw_device_info *, struct vb_device_info *);
76static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/ 48static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
77void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
78 unsigned long XGI_P3d4Port);
79void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo); 49void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
80void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo); 50void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
81void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ; 51void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
@@ -502,40 +472,6 @@ unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtensio
502 } 472 }
503} 473}
504 474
505static unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo)
506{
507 unsigned char data;
508
509 /* index = XGINew_GetReg1(pVBInfo->P3c4, 0x1A); */
510 /* index &= 07; */
511
512 if (*pVBInfo->pSoftSetting & SoftDRAMType)
513 data = *pVBInfo->pSoftSetting & 0x03;
514 else
515 data = XGINew_GetReg1(pVBInfo->P3c4, 0x3a) & 0x03;
516
517 return data;
518}
519
520/*
521void XGINew_Delay15us(unsigned long ulMicrsoSec)
522{
523}
524*/
525
526static void XGINew_SDR_MRS(struct vb_device_info *pVBInfo)
527{
528 unsigned short data;
529
530 data = XGINew_GetReg1(pVBInfo->P3c4, 0x16);
531 data &= 0x3F; /* SR16 D7=0,D6=0 */
532 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data); /* enable mode register set(MRS) low */
533 /* XGINew_Delay15us(0x100); */
534 data |= 0x80; /* SR16 D7=1,D6=0 */
535 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data); /* enable mode register set(MRS) high */
536 /* XGINew_Delay15us(0x100); */
537}
538
539static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo) 475static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
540{ 476{
541 XGINew_SetReg1(P3c4, 0x18, 0x01); 477 XGINew_SetReg1(P3c4, 0x18, 0x01);
@@ -566,29 +502,6 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBI
566 XGINew_SetReg1(P3c4, 0x1B, 0x00); 502 XGINew_SetReg1(P3c4, 0x1B, 0x00);
567} 503}
568 504
569static void XGINew_DDR2x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
570{
571 XGINew_SetReg1(P3c4, 0x18, 0x00);
572 XGINew_SetReg1(P3c4, 0x19, 0x20);
573 XGINew_SetReg1(P3c4, 0x16, 0x00);
574 XGINew_SetReg1(P3c4, 0x16, 0x80);
575 DelayUS(60);
576 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
577 /* XGINew_SetReg1(P3c4 ,0x18 ,0x31); */
578 XGINew_SetReg1(P3c4, 0x19, 0x01);
579 XGINew_SetReg1(P3c4, 0x16, 0x05);
580 XGINew_SetReg1(P3c4, 0x16, 0x85);
581 DelayUS(1000);
582 XGINew_SetReg1(P3c4, 0x1B, 0x03);
583 DelayUS(500);
584 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
585 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
586 XGINew_SetReg1(P3c4, 0x19, 0x00);
587 XGINew_SetReg1(P3c4, 0x16, 0x05);
588 XGINew_SetReg1(P3c4, 0x16, 0x85);
589 XGINew_SetReg1(P3c4, 0x1B, 0x00);
590}
591
592static void XGINew_DDRII_Bootup_XG27( 505static void XGINew_DDRII_Bootup_XG27(
593 struct xgi_hw_device_info *HwDeviceExtension, 506 struct xgi_hw_device_info *HwDeviceExtension,
594 unsigned long P3c4, struct vb_device_info *pVBInfo) 507 unsigned long P3c4, struct vb_device_info *pVBInfo)
@@ -710,79 +623,6 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
710 DelayUS(200); 623 DelayUS(200);
711} 624}
712 625
713#if 0
714static void XGINew_DDR2_MRS_XG27(struct xgi_hw_device_info *HwDeviceExtension,
715 unsigned long P3c4, struct vb_device_info *pVBInfo)
716{
717 unsigned long P3d4 = P3c4 + 0x10;
718
719 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
720 XGINew_SetMemoryClock(HwDeviceExtension , pVBInfo);
721
722 XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
723 DelayUS(200);
724 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
725 XGINew_SetReg1(P3c4, 0x19, 0x80);
726
727 XGINew_SetReg1(P3c4, 0x16, 0x10);
728 DelayUS(15); /* 06/11/23 XG27 A0 for CKE enable */
729 XGINew_SetReg1(P3c4, 0x16, 0x90);
730
731 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
732 XGINew_SetReg1(P3c4, 0x19, 0xC0);
733
734 XGINew_SetReg1(P3c4, 0x16, 0x00);
735 DelayUS(15); /* 06/11/22 XG27 A0 */
736 XGINew_SetReg1(P3c4, 0x16, 0x80);
737
738 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
739 XGINew_SetReg1(P3c4, 0x19, 0x40);
740
741 XGINew_SetReg1(P3c4, 0x16, 0x00);
742 DelayUS(15); /* 06/11/22 XG27 A0 */
743 XGINew_SetReg1(P3c4, 0x16, 0x80);
744
745 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
746 XGINew_SetReg1(P3c4, 0x19, 0x06); /* [Billy]06/11/22 DLL Reset for XG27 Hynix DRAM */
747
748 XGINew_SetReg1(P3c4, 0x16, 0x00);
749 DelayUS(15); /* 06/11/23 XG27 A0 */
750 XGINew_SetReg1(P3c4, 0x16, 0x80);
751
752 DelayUS(30); /* 06/11/23 XG27 A0 Start Auto-PreCharge */
753 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
754 DelayUS(60);
755 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
756
757 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
758 XGINew_SetReg1(P3c4, 0x19, 0x04); /* DLL without Reset for XG27 Hynix DRAM */
759
760 XGINew_SetReg1(P3c4, 0x16, 0x00);
761 DelayUS(30);
762 XGINew_SetReg1(P3c4, 0x16, 0x80);
763
764 XGINew_SetReg1(P3c4, 0x18, 0x80); /* XG27 OCD ON */
765 XGINew_SetReg1(P3c4, 0x19, 0x46);
766
767 XGINew_SetReg1(P3c4, 0x16, 0x00);
768 DelayUS(30);
769 XGINew_SetReg1(P3c4, 0x16, 0x80);
770
771 XGINew_SetReg1(P3c4, 0x18, 0x00);
772 XGINew_SetReg1(P3c4, 0x19, 0x40);
773
774 XGINew_SetReg1(P3c4, 0x16, 0x00);
775 DelayUS(30);
776 XGINew_SetReg1(P3c4, 0x16, 0x80);
777
778 DelayUS(15); /* Start Auto-PreCharge */
779 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
780 DelayUS(200);
781 XGINew_SetReg1(P3c4, 0x1B, 0x03); /* SR1B */
782
783}
784#endif
785
786static void XGINew_DDR1x_DefaultRegister( 626static void XGINew_DDR1x_DefaultRegister(
787 struct xgi_hw_device_info *HwDeviceExtension, 627 struct xgi_hw_device_info *HwDeviceExtension,
788 unsigned long Port, struct vb_device_info *pVBInfo) 628 unsigned long Port, struct vb_device_info *pVBInfo)
@@ -833,51 +673,6 @@ static void XGINew_DDR1x_DefaultRegister(
833 } 673 }
834} 674}
835 675
836#if 0
837
838static void XGINew_DDR2x_DefaultRegister(
839 struct xgi_hw_device_info *HwDeviceExtension,
840 unsigned long Port, struct vb_device_info *pVBInfo)
841{
842 unsigned long P3d4 = Port ,
843 P3c4 = Port - 0x10;
844
845 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
846
847 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
848 switch (HwDeviceExtension->jChipType) {
849 case XG41:
850 case XG42:
851 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
852 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
853 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
854 break;
855 default:
856 /* keep following setting sequence, each setting in the same reg insert idle */
857 XGINew_SetReg1(P3d4, 0x82, 0x88);
858 XGINew_SetReg1(P3d4, 0x86, 0x00);
859 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
860 XGINew_SetReg1(P3d4, 0x86, 0x88);
861 XGINew_SetReg1(P3d4, 0x82, 0x77);
862 XGINew_SetReg1(P3d4, 0x85, 0x00);
863 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
864 XGINew_SetReg1(P3d4, 0x85, 0x88);
865 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
866 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
867 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
868 }
869 XGINew_SetReg1(P3d4, 0x97, 0x11);
870 if (HwDeviceExtension->jChipType == XG42)
871 XGINew_SetReg1(P3d4, 0x98, 0x01);
872 else
873 XGINew_SetReg1(P3d4, 0x98, 0x03);
874
875 XGINew_SetReg1(P3d4, 0x9A, 0x02);
876
877 XGINew_DDR2x_MRS_340(P3c4, pVBInfo);
878}
879#endif
880
881static void XGINew_DDR2_DefaultRegister( 676static void XGINew_DDR2_DefaultRegister(
882 struct xgi_hw_device_info *HwDeviceExtension, 677 struct xgi_hw_device_info *HwDeviceExtension,
883 unsigned long Port, struct vb_device_info *pVBInfo) 678 unsigned long Port, struct vb_device_info *pVBInfo)
@@ -1039,95 +834,6 @@ void XGINew_SetDRAMDefaultRegister340(
1039 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */ 834 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
1040} 835}
1041 836
1042static void XGINew_DDR_MRS(struct vb_device_info *pVBInfo)
1043{
1044 unsigned short data;
1045
1046 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1047
1048 /* SR16 <- 1F,DF,2F,AF */
1049 /* yriver modified SR16 <- 0F,DF,0F,AF */
1050 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1051 data = pVideoMemory[0xFB];
1052 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x16); */
1053
1054 data &= 0x0F;
1055 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1056 data |= 0xC0;
1057 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1058 data &= 0x0F;
1059 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1060 data |= 0x80;
1061 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1062 data &= 0x0F;
1063 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1064 data |= 0xD0;
1065 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1066 data &= 0x0F;
1067 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1068 data |= 0xA0;
1069 XGINew_SetReg1(pVBInfo->P3c4, 0x16, data);
1070 /*
1071 else {
1072 data &= 0x0F;
1073 data |= 0x10;
1074 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1075
1076 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) {
1077 data &= 0x0F;
1078 }
1079
1080 data |= 0xC0;
1081 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1082
1083 data &= 0x0F;
1084 data |= 0x20;
1085 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1086 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) {
1087 data &= 0x0F;
1088 }
1089
1090 data |= 0x80;
1091 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1092 }
1093 */
1094}
1095
1096/* check if read cache pointer is correct */
1097
1098static void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension,
1099 struct vb_device_info *pVBInfo)
1100{
1101 unsigned char *pVideoMemory = pVBInfo->FBAddr;
1102 unsigned char i, j;
1103 unsigned short Temp, SR21;
1104
1105 pVideoMemory[0] = 0xaa; /* alan */
1106 pVideoMemory[16] = 0x55; /* note: PCI read cache is off */
1107
1108 if ((pVideoMemory[0] != 0xaa) || (pVideoMemory[16] != 0x55)) {
1109 for (i = 0, j = 16; i < 2; i++, j += 16) {
1110 SR21 = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1111 Temp = SR21 & 0xFB; /* disable PCI post write buffer empty gating */
1112 XGINew_SetReg1(pVBInfo->P3c4, 0x21, Temp);
1113
1114 Temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3C);
1115 Temp |= 0x01; /* MCLK reset */
1116
1117 Temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3C);
1118 Temp &= 0xFE; /* MCLK normal operation */
1119
1120 XGINew_SetReg1(pVBInfo->P3c4, 0x21, SR21);
1121
1122 pVideoMemory[16 + j] = j;
1123 if (pVideoMemory[16 + j] == j) {
1124 pVideoMemory[j] = j;
1125 break;
1126 }
1127 }
1128 }
1129}
1130
1131void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension, 837void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1132 struct vb_device_info *pVBInfo) 838 struct vb_device_info *pVBInfo)
1133{ 839{
@@ -1150,155 +856,6 @@ void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1150 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */ 856 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
1151} 857}
1152 858
1153void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension,
1154 struct vb_device_info *pVBInfo)
1155{
1156 unsigned short data;
1157 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase, pVBInfo->FBAddr
1158 = HwDeviceExtension->pjVideoMemoryAddress;
1159#ifdef XGI301
1160 /* XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x40); */
1161#endif
1162
1163#ifdef XGI302 /* alan,should change value */
1164 XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x4D);
1165 XGINew_SetReg1(pVBInfo->P3d4, 0x31, 0xc0);
1166 XGINew_SetReg1(pVBInfo->P3d4, 0x34, 0x3F);
1167#endif
1168
1169 XGISetModeNew(HwDeviceExtension, 0x2e);
1170
1171 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1172 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
1173
1174 data = XGINew_GetReg1(pVBInfo->P3c4, 0x1);
1175 data |= 0x20;
1176 XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); /* Turn OFF Display */
1177
1178 data = XGINew_GetReg1(pVBInfo->P3c4, 0x16);
1179
1180 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short) (data | 0x0F)); /* assume lowest speed DRAM */
1181
1182 XGINew_SetDRAMModeRegister(pVBInfo);
1183 XGINew_DisableRefresh(HwDeviceExtension, pVBInfo);
1184 XGINew_CheckBusWidth_310(pVBInfo);
1185 XGINew_VerifyMclk(HwDeviceExtension, pVBInfo); /* alan 2000/7/3 */
1186
1187 if (XGINew_Get310DRAMType(pVBInfo) < 2)
1188 XGINew_SDRSizing(pVBInfo);
1189 else
1190 XGINew_DDRSizing(pVBInfo);
1191
1192 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
1193
1194 XGINew_EnableRefresh(HwDeviceExtension, pVBInfo);
1195 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1196 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
1197}
1198
1199void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension)
1200{
1201 unsigned char data;
1202 struct vb_device_info VBINF;
1203 struct vb_device_info *pVBInfo = &VBINF;
1204 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1205 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1206 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1207 pVBInfo->ISXPDOS = 0;
1208
1209 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1210 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1211 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1212 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1213 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1214 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1215 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1216 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1217 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1218 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1219 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1220 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1221 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1222 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1223 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1224 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1225 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1226 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1227 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1228
1229 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1230
1231 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1232
1233 if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0) {
1234 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02) >> 1;
1235 if (data == 0x01)
1236 XGINew_DDR2x_MRS_340(pVBInfo->P3c4, pVBInfo);
1237 else
1238 XGINew_DDR1x_MRS_340(pVBInfo->P3c4, pVBInfo);
1239 } else {
1240 XGINew_DDR2_MRS_XG20(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1241 }
1242 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
1243}
1244
1245void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo)
1246{
1247 if (XGINew_Get310DRAMType(pVBInfo) < 2) {
1248 XGINew_SDR_MRS(pVBInfo);
1249 } else {
1250 /* SR16 <- 0F,CF,0F,8F */
1251 XGINew_DDR_MRS(pVBInfo);
1252 }
1253}
1254
1255void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension,
1256 struct vb_device_info *pVBInfo)
1257{
1258 unsigned short data;
1259
1260 data = XGINew_GetReg1(pVBInfo->P3c4, 0x1B);
1261 data &= 0xF8;
1262 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, data);
1263
1264}
1265
1266void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension,
1267 struct vb_device_info *pVBInfo)
1268{
1269
1270 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
1271
1272}
1273
1274static void XGINew_DisableChannelInterleaving(int index,
1275 unsigned short XGINew_DDRDRAM_TYPE[][5],
1276 struct vb_device_info *pVBInfo)
1277{
1278 unsigned short data;
1279
1280 data = XGINew_GetReg1(pVBInfo->P3c4, 0x15);
1281 data &= 0x1F;
1282
1283 switch (XGINew_DDRDRAM_TYPE[index][3]) {
1284 case 64:
1285 data |= 0;
1286 break;
1287 case 32:
1288 data |= 0x20;
1289 break;
1290 case 16:
1291 data |= 0x40;
1292 break;
1293 case 4:
1294 data |= 0x60;
1295 break;
1296 default:
1297 break;
1298 }
1299 XGINew_SetReg1(pVBInfo->P3c4, 0x15, data);
1300}
1301
1302static void XGINew_SetDRAMSizingType(int index, 859static void XGINew_SetDRAMSizingType(int index,
1303 unsigned short DRAMTYPE_TABLE[][5], 860 unsigned short DRAMTYPE_TABLE[][5],
1304 struct vb_device_info *pVBInfo) 861 struct vb_device_info *pVBInfo)
@@ -1311,349 +868,6 @@ static void XGINew_SetDRAMSizingType(int index,
1311 /* should delay 50 ns */ 868 /* should delay 50 ns */
1312} 869}
1313 870
1314void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo)
1315{
1316 unsigned short data;
1317 volatile unsigned long *pVideoMemory;
1318
1319 pVideoMemory = (unsigned long *) pVBInfo->FBAddr;
1320
1321 if (XGINew_Get310DRAMType(pVBInfo) < 2) {
1322 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x00);
1323 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x12);
1324 /* should delay */
1325 XGINew_SDR_MRS(pVBInfo);
1326
1327 XGINew_ChannelAB = 0;
1328 XGINew_DataBusWidth = 128;
1329 pVideoMemory[0] = 0x01234567L;
1330 pVideoMemory[1] = 0x456789ABL;
1331 pVideoMemory[2] = 0x89ABCDEFL;
1332 pVideoMemory[3] = 0xCDEF0123L;
1333 pVideoMemory[4] = 0x55555555L;
1334 pVideoMemory[5] = 0x55555555L;
1335 pVideoMemory[6] = 0xFFFFFFFFL;
1336 pVideoMemory[7] = 0xFFFFFFFFL;
1337
1338 if ((pVideoMemory[3] != 0xCDEF0123L) || (pVideoMemory[2]
1339 != 0x89ABCDEFL)) {
1340 /* ChannelA64Bit */
1341 XGINew_DataBusWidth = 64;
1342 XGINew_ChannelAB = 0;
1343 data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1344 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1345 (unsigned short) (data & 0xFD));
1346 }
1347
1348 if ((pVideoMemory[1] != 0x456789ABL) || (pVideoMemory[0]
1349 != 0x01234567L)) {
1350 /* ChannelB64Bit */
1351 XGINew_DataBusWidth = 64;
1352 XGINew_ChannelAB = 1;
1353 data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1354 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1355 (unsigned short) ((data & 0xFD) | 0x01));
1356 }
1357
1358 return;
1359 } else {
1360 /* DDR Dual channel */
1361 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x00);
1362 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x02); /* Channel A, 64bit */
1363 /* should delay */
1364 XGINew_DDR_MRS(pVBInfo);
1365
1366 XGINew_ChannelAB = 0;
1367 XGINew_DataBusWidth = 64;
1368 pVideoMemory[0] = 0x01234567L;
1369 pVideoMemory[1] = 0x456789ABL;
1370 pVideoMemory[2] = 0x89ABCDEFL;
1371 pVideoMemory[3] = 0xCDEF0123L;
1372 pVideoMemory[4] = 0x55555555L;
1373 pVideoMemory[5] = 0x55555555L;
1374 pVideoMemory[6] = 0xAAAAAAAAL;
1375 pVideoMemory[7] = 0xAAAAAAAAL;
1376
1377 if (pVideoMemory[1] == 0x456789ABL) {
1378 if (pVideoMemory[0] == 0x01234567L) {
1379 /* Channel A 64bit */
1380 return;
1381 }
1382 } else {
1383 if (pVideoMemory[0] == 0x01234567L) {
1384 /* Channel A 32bit */
1385 XGINew_DataBusWidth = 32;
1386 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x00);
1387 return;
1388 }
1389 }
1390
1391 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x03); /* Channel B, 64bit */
1392 XGINew_DDR_MRS(pVBInfo);
1393
1394 XGINew_ChannelAB = 1;
1395 XGINew_DataBusWidth = 64;
1396 pVideoMemory[0] = 0x01234567L;
1397 pVideoMemory[1] = 0x456789ABL;
1398 pVideoMemory[2] = 0x89ABCDEFL;
1399 pVideoMemory[3] = 0xCDEF0123L;
1400 pVideoMemory[4] = 0x55555555L;
1401 pVideoMemory[5] = 0x55555555L;
1402 pVideoMemory[6] = 0xAAAAAAAAL;
1403 pVideoMemory[7] = 0xAAAAAAAAL;
1404
1405 if (pVideoMemory[1] == 0x456789ABL) {
1406 /* Channel B 64 */
1407 if (pVideoMemory[0] == 0x01234567L) {
1408 /* Channel B 64bit */
1409 return;
1410 } else {
1411 /* error */
1412 }
1413 } else {
1414 if (pVideoMemory[0] == 0x01234567L) {
1415 /* Channel B 32 */
1416 XGINew_DataBusWidth = 32;
1417 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x01);
1418 } else {
1419 /* error */
1420 }
1421 }
1422 }
1423}
1424
1425static int XGINew_SetRank(int index, unsigned char RankNo,
1426 unsigned char XGINew_ChannelAB,
1427 unsigned short DRAMTYPE_TABLE[][5],
1428 struct vb_device_info *pVBInfo)
1429{
1430 unsigned short data;
1431 int RankSize;
1432
1433 if ((RankNo == 2) && (DRAMTYPE_TABLE[index][0] == 2))
1434 return 0;
1435
1436 RankSize = DRAMTYPE_TABLE[index][3] / 2 * XGINew_DataBusWidth / 32;
1437
1438 if ((RankNo * RankSize) <= 128) {
1439 data = 0;
1440
1441 while ((RankSize >>= 1) > 0)
1442 data += 0x10;
1443
1444 data |= (RankNo - 1) << 2;
1445 data |= (XGINew_DataBusWidth / 64) & 2;
1446 data |= XGINew_ChannelAB;
1447 XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1448 /* should delay */
1449 XGINew_SDR_MRS(pVBInfo);
1450 return 1;
1451 } else {
1452 return 0;
1453 }
1454}
1455
1456static int XGINew_SetDDRChannel(int index, unsigned char ChannelNo,
1457 unsigned char XGINew_ChannelAB,
1458 unsigned short DRAMTYPE_TABLE[][5],
1459 struct vb_device_info *pVBInfo)
1460{
1461 unsigned short data;
1462 int RankSize;
1463
1464 RankSize = DRAMTYPE_TABLE[index][3] / 2 * XGINew_DataBusWidth / 32;
1465 /* RankSize = DRAMTYPE_TABLE[index][3]; */
1466 if (ChannelNo * RankSize <= 128) {
1467 data = 0;
1468 while ((RankSize >>= 1) > 0)
1469 data += 0x10;
1470
1471 if (ChannelNo == 2)
1472 data |= 0x0C;
1473
1474 data |= (XGINew_DataBusWidth / 32) & 2;
1475 data |= XGINew_ChannelAB;
1476 XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1477 /* should delay */
1478 XGINew_DDR_MRS(pVBInfo);
1479 return 1;
1480 } else {
1481 return 0;
1482 }
1483}
1484
1485static int XGINew_CheckColumn(int index, unsigned short DRAMTYPE_TABLE[][5],
1486 struct vb_device_info *pVBInfo)
1487{
1488 int i;
1489 unsigned long Increment, Position;
1490
1491 /* Increment = 1 << (DRAMTYPE_TABLE[index][2] + XGINew_DataBusWidth / 64 + 1); */
1492 Increment = 1 << (10 + XGINew_DataBusWidth / 64);
1493
1494 for (i = 0, Position = 0; i < 2; i++) {
1495 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1496 Position += Increment;
1497 }
1498
1499 for (i = 0, Position = 0; i < 2; i++) {
1500 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1501 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1502 return 0;
1503 Position += Increment;
1504 }
1505 return 1;
1506}
1507
1508static int XGINew_CheckBanks(int index, unsigned short DRAMTYPE_TABLE[][5],
1509 struct vb_device_info *pVBInfo)
1510{
1511 int i;
1512 unsigned long Increment, Position;
1513
1514 Increment = 1 << (DRAMTYPE_TABLE[index][2] + XGINew_DataBusWidth / 64 + 2);
1515
1516 for (i = 0, Position = 0; i < 4; i++) {
1517 /* pVBInfo->FBAddr[Position] = Position; */
1518 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1519 Position += Increment;
1520 }
1521
1522 for (i = 0, Position = 0; i < 4; i++) {
1523 /* if (pVBInfo->FBAddr[Position] != Position) */
1524 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1525 return 0;
1526 Position += Increment;
1527 }
1528 return 1;
1529}
1530
1531static int XGINew_CheckRank(int RankNo, int index,
1532 unsigned short DRAMTYPE_TABLE[][5],
1533 struct vb_device_info *pVBInfo)
1534{
1535 int i;
1536 unsigned long Increment, Position;
1537
1538 Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1]
1539 + DRAMTYPE_TABLE[index][0] + XGINew_DataBusWidth / 64
1540 + RankNo);
1541
1542 for (i = 0, Position = 0; i < 2; i++) {
1543 /* pVBInfo->FBAddr[Position] = Position; */
1544 /* *((unsigned long *)(pVBInfo->FBAddr)) = Position; */
1545 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
1546 Position += Increment;
1547 }
1548
1549 for (i = 0, Position = 0; i < 2; i++) {
1550 /* if (pVBInfo->FBAddr[Position] != Position) */
1551 /* if ((*(unsigned long *)(pVBInfo->FBAddr)) != Position) */
1552 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
1553 return 0;
1554 Position += Increment;
1555 }
1556 return 1;
1557}
1558
1559static int XGINew_CheckDDRRank(int RankNo, int index,
1560 unsigned short DRAMTYPE_TABLE[][5],
1561 struct vb_device_info *pVBInfo)
1562{
1563 unsigned long Increment, Position;
1564 unsigned short data;
1565
1566 Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1]
1567 + DRAMTYPE_TABLE[index][0] + XGINew_DataBusWidth / 64
1568 + RankNo);
1569
1570 Increment += Increment / 2;
1571
1572 Position = 0;
1573 *((unsigned long *) (pVBInfo->FBAddr + Position + 0)) = 0x01234567;
1574 *((unsigned long *) (pVBInfo->FBAddr + Position + 1)) = 0x456789AB;
1575 *((unsigned long *) (pVBInfo->FBAddr + Position + 2)) = 0x55555555;
1576 *((unsigned long *) (pVBInfo->FBAddr + Position + 3)) = 0x55555555;
1577 *((unsigned long *) (pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA;
1578 *((unsigned long *) (pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA;
1579
1580 if ((*(unsigned long *) (pVBInfo->FBAddr + 1)) == 0x456789AB)
1581 return 1;
1582
1583 if ((*(unsigned long *) (pVBInfo->FBAddr + 0)) == 0x01234567)
1584 return 0;
1585
1586 data = XGINew_GetReg1(pVBInfo->P3c4, 0x14);
1587 data &= 0xF3;
1588 data |= 0x0E;
1589 XGINew_SetReg1(pVBInfo->P3c4, 0x14, data);
1590 data = XGINew_GetReg1(pVBInfo->P3c4, 0x15);
1591 data += 0x20;
1592 XGINew_SetReg1(pVBInfo->P3c4, 0x15, data);
1593
1594 return 1;
1595}
1596
1597static int XGINew_CheckRanks(int RankNo, int index,
1598 unsigned short DRAMTYPE_TABLE[][5],
1599 struct vb_device_info *pVBInfo)
1600{
1601 int r;
1602
1603 for (r = RankNo; r >= 1; r--) {
1604 if (!XGINew_CheckRank(r, index, DRAMTYPE_TABLE, pVBInfo))
1605 return 0;
1606 }
1607
1608 if (!XGINew_CheckBanks(index, DRAMTYPE_TABLE, pVBInfo))
1609 return 0;
1610
1611 if (!XGINew_CheckColumn(index, DRAMTYPE_TABLE, pVBInfo))
1612 return 0;
1613
1614 return 1;
1615}
1616
1617static int XGINew_CheckDDRRanks(int RankNo, int index,
1618 unsigned short DRAMTYPE_TABLE[][5],
1619 struct vb_device_info *pVBInfo)
1620{
1621 int r;
1622
1623 for (r = RankNo; r >= 1; r--) {
1624 if (!XGINew_CheckDDRRank(r, index, DRAMTYPE_TABLE, pVBInfo))
1625 return 0;
1626 }
1627
1628 if (!XGINew_CheckBanks(index, DRAMTYPE_TABLE, pVBInfo))
1629 return 0;
1630
1631 if (!XGINew_CheckColumn(index, DRAMTYPE_TABLE, pVBInfo))
1632 return 0;
1633
1634 return 1;
1635}
1636
1637int XGINew_SDRSizing(struct vb_device_info *pVBInfo)
1638{
1639 int i;
1640 unsigned char j;
1641
1642 for (i = 0; i < 13; i++) {
1643 XGINew_SetDRAMSizingType(i, XGINew_SDRDRAM_TYPE, pVBInfo);
1644
1645 for (j = 2; j > 0; j--) {
1646 if (!XGINew_SetRank(i, (unsigned char) j, XGINew_ChannelAB, XGINew_SDRDRAM_TYPE, pVBInfo)) {
1647 continue;
1648 } else {
1649 if (XGINew_CheckRanks(j, i, XGINew_SDRDRAM_TYPE, pVBInfo))
1650 return 1;
1651 }
1652 }
1653 }
1654 return 0;
1655}
1656
1657static unsigned short XGINew_SetDRAMSizeReg(int index, 871static unsigned short XGINew_SetDRAMSizeReg(int index,
1658 unsigned short DRAMTYPE_TABLE[][5], 872 unsigned short DRAMTYPE_TABLE[][5],
1659 struct vb_device_info *pVBInfo) 873 struct vb_device_info *pVBInfo)
@@ -2075,27 +1289,6 @@ int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
2075 return 0; 1289 return 0;
2076} 1290}
2077 1291
2078int XGINew_DDRSizing(struct vb_device_info *pVBInfo)
2079{
2080 int i;
2081 unsigned char j;
2082
2083 for (i = 0; i < 4; i++) {
2084 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE, pVBInfo);
2085 XGINew_DisableChannelInterleaving(i, XGINew_DDRDRAM_TYPE, pVBInfo);
2086 for (j = 2; j > 0; j--) {
2087 XGINew_SetDDRChannel(i, j, XGINew_ChannelAB, XGINew_DDRDRAM_TYPE, pVBInfo);
2088 if (!XGINew_SetRank(i, (unsigned char) j, XGINew_ChannelAB, XGINew_DDRDRAM_TYPE, pVBInfo)) {
2089 continue;
2090 } else {
2091 if (XGINew_CheckDDRRanks(j, i, XGINew_DDRDRAM_TYPE, pVBInfo))
2092 return 1;
2093 }
2094 }
2095 }
2096 return 0;
2097}
2098
2099void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, 1292void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
2100 struct vb_device_info *pVBInfo) 1293 struct vb_device_info *pVBInfo)
2101{ 1294{
@@ -2121,89 +1314,6 @@ void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
2121 } 1314 }
2122} 1315}
2123 1316
2124unsigned char ChkLFB(struct vb_device_info *pVBInfo)
2125{
2126 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4, 0x78))
2127 return 1;
2128 else
2129 return 0;
2130}
2131
2132/* --------------------------------------------------------------------- */
2133/* input : dx ,valid value : CR or second chip's CR */
2134/* */
2135/* SetPowerConsume : */
2136/* Description: reduce 40/43 power consumption in first chip or */
2137/* in second chip, assume CR A1 D[6]="1" in this case */
2138/* output : none */
2139/* --------------------------------------------------------------------- */
2140void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
2141 unsigned long XGI_P3d4Port)
2142{
2143 unsigned long lTemp;
2144 unsigned char bTemp;
2145
2146 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x08, 0, &lTemp); /* Get */
2147 if ((lTemp & 0xFF) == 0) {
2148 /* set CR58 D[5]=0 D[3]=0 */
2149 XGINew_SetRegAND(XGI_P3d4Port, 0x58, 0xD7);
2150 bTemp = (unsigned char) XGINew_GetReg1(XGI_P3d4Port, 0xCB);
2151 if (bTemp & 0x20) {
2152 if (!(bTemp & 0x10))
2153 XGINew_SetRegANDOR(XGI_P3d4Port, 0x58, 0xD7, 0x20); /* CR58 D[5]=1 D[3]=0 */
2154 else
2155 XGINew_SetRegANDOR(XGI_P3d4Port, 0x58, 0xD7, 0x08); /* CR58 D[5]=0 D[3]=1 */
2156
2157 }
2158
2159 }
2160}
2161
2162#if 0
2163static void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension,
2164 struct vb_device_info *pVBInfo)
2165{
2166
2167 /* unsigned long ROMAddr = (unsigned long) HwDeviceExtension->pjVirtualRomBase; */
2168 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2169 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2170 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2171 pVBInfo->ISXPDOS = 0;
2172
2173 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2174 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2175 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2176 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2177 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2178 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2179 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2180 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2181 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2182 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2183 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2184 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2185 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2186 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2187 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2188 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2189 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2190 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
2191 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
2192
2193 switch (HwDeviceExtension->jChipType) {
2194 case XG40:
2195 case XG41:
2196 case XG42:
2197 case XG20:
2198 case XG21:
2199 default:
2200 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2201 return;
2202 }
2203
2204}
2205#endif
2206
2207void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo) 1317void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
2208{ 1318{
2209 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr; 1319 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
@@ -2324,130 +1434,6 @@ void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
2324 XGINew_SetReg1(P3c4, 0x1B, 0x00); 1434 XGINew_SetReg1(P3c4, 0x1B, 0x00);
2325} 1435}
2326 1436
2327void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension)
2328{
2329 struct vb_device_info VBINF;
2330 struct vb_device_info *pVBInfo = &VBINF;
2331 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2332 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2333 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2334 pVBInfo->ISXPDOS = 0;
2335
2336 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2337 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2338 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2339 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2340 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2341 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2342 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2343 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2344 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2345 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2346 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2347 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2348 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2349 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2350 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2351 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2352 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2353
2354 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2355
2356 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
2357
2358 if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2359 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2360 else
2361 XGINew_DDR2_MRS_XG20(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2362
2363 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
2364}
2365
2366void XGINew_SetDRAMModeRegister_XG27(
2367 struct xgi_hw_device_info *HwDeviceExtension)
2368{
2369 struct vb_device_info VBINF;
2370 struct vb_device_info *pVBInfo = &VBINF;
2371 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2372 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2373 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
2374 pVBInfo->ISXPDOS = 0;
2375
2376 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2377 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2378 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2379 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2380 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2381 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2382 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2383 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2384 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2385 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2386 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2387 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2388 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2389 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2390 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2391 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2392 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2393
2394 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
2395
2396 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
2397
2398 if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2399 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2400 else
2401 /* XGINew_DDR2_MRS_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo); */
2402 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2403
2404 /* XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03); */
2405 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
2406
2407}
2408
2409/*
2410void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
2411{
2412 unsigned char data;
2413 struct vb_device_info VBINF;
2414 struct vb_device_info *pVBInfo = &VBINF;
2415 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
2416 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
2417 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress;
2418 pVBInfo->ISXPDOS = 0;
2419
2420 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
2421 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
2422 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
2423 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
2424 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
2425 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
2426 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
2427 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
2428 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
2429 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
2430 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
2431 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
2432 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
2433 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
2434 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
2435 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
2436 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
2437
2438 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2439
2440 ReadVBIOSTablData(HwDeviceExtension->jChipType , pVBInfo);
2441
2442 if (XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) == 0)
2443 XGINew_DDR1x_MRS_XG20(pVBInfo->P3c4, pVBInfo);
2444 else
2445 XGINew_DDR2_MRS_XG27(HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
2446
2447 XGINew_SetReg1(pVBInfo->P3c4, 0x1B, 0x03);
2448}
2449*/
2450
2451void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, 1437void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
2452 struct vb_device_info *pVBInfo) 1438 struct vb_device_info *pVBInfo)
2453{ 1439{
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 03:40:30 -0400