diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-03 15:07:28 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-03 17:37:30 -0400 |
commit | 2b90eddcd7091dd631ead1d79e28e79ad589bb8d (patch) | |
tree | be3caf45a587f65844650fb792f3a09267f656a2 | |
parent | 0124853eb1eda5e193e4753bd5d5ac77085027b2 (diff) |
drm/radeon/sumo: disable PG when changing UVD clocks
Causes hangs for some people.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/sumo_dpm.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index bf187a5b3d58..b13448f13ee8 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c | |||
@@ -811,6 +811,23 @@ static void sumo_program_bootup_state(struct radeon_device *rdev) | |||
811 | sumo_power_level_enable(rdev, i, false); | 811 | sumo_power_level_enable(rdev, i, false); |
812 | } | 812 | } |
813 | 813 | ||
814 | static void sumo_setup_uvd_clocks(struct radeon_device *rdev, | ||
815 | struct radeon_ps *new_rps, | ||
816 | struct radeon_ps *old_rps) | ||
817 | { | ||
818 | struct sumo_power_info *pi = sumo_get_pi(rdev); | ||
819 | |||
820 | if (pi->enable_gfx_power_gating) { | ||
821 | sumo_gfx_powergating_enable(rdev, false); | ||
822 | } | ||
823 | |||
824 | radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); | ||
825 | |||
826 | if (pi->enable_gfx_power_gating) { | ||
827 | sumo_gfx_powergating_enable(rdev, true); | ||
828 | } | ||
829 | } | ||
830 | |||
814 | static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, | 831 | static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, |
815 | struct radeon_ps *new_rps, | 832 | struct radeon_ps *new_rps, |
816 | struct radeon_ps *old_rps) | 833 | struct radeon_ps *old_rps) |
@@ -826,7 +843,7 @@ static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, | |||
826 | current_ps->levels[current_ps->num_levels - 1].sclk) | 843 | current_ps->levels[current_ps->num_levels - 1].sclk) |
827 | return; | 844 | return; |
828 | 845 | ||
829 | radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); | 846 | sumo_setup_uvd_clocks(rdev, new_rps, old_rps); |
830 | } | 847 | } |
831 | 848 | ||
832 | static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, | 849 | static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, |
@@ -844,7 +861,7 @@ static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, | |||
844 | current_ps->levels[current_ps->num_levels - 1].sclk) | 861 | current_ps->levels[current_ps->num_levels - 1].sclk) |
845 | return; | 862 | return; |
846 | 863 | ||
847 | radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); | 864 | sumo_setup_uvd_clocks(rdev, new_rps, old_rps); |
848 | } | 865 | } |
849 | 866 | ||
850 | void sumo_take_smu_control(struct radeon_device *rdev, bool enable) | 867 | void sumo_take_smu_control(struct radeon_device *rdev, bool enable) |