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authorArnd Bergmann <arnd@arndb.de>2013-04-09 11:10:31 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-09 11:10:31 -0400
commit2b07910131b7935d9c532e0a769a0875560e18d1 (patch)
tree6c7feab9eb5a03ccee8f07cbeec13d1a40d34c06
parent5790c58b133913f92fd737c03efce9db7a1d2d4d (diff)
parent964ea47572b89589b61b553e44bbe9907d4f12a6 (diff)
Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: clock driver development This branch contains most fixes and enhancements to the Tegra common clock driver. The main new feature is a driver for Tegra114, which coupled with later device tree changes enables many devices on that chip, such as MMC, I2C, etc. This branch depends on a patch in: git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 Mike has stated that this branch is stable, and is aware of this dependency and merge. Mike's branch is based on v3.9-rc3, which includes a USB change which causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence, this branch pulls in v3.9-rc4 to ensure bisectability as much as possible. This branch is based on v3.9-rc4, followed by a merge of previous Tegra "soc" pull request, followed by a merge of clk-for-3.10. * tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: fix enum tegra114_clk to match binding clk: tegra: Remove forced clk_enable of uartd ARM: dt: Add references to tegra_car clocks clk: tegra: devicetree match for nvidia,tegra114-car clk: tegra: Implement clocks for Tegra114 ARM: tegra: Define Tegra114 CAR binding clk: tegra: Workaround for Tegra114 MSENC problem clk: tegra: Add flags to tegra_clk_periph() clk: tegra: Add new fields and PLL types for Tegra114 clk: tegra: move from a lock bit idx to a lock mask clk: tegra: Add PLL post divider table clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE clk: tegra: Add TEGRA_PLL_BYPASS flag clk: tegra: Refactor PLL programming code clk: tegra: provide dummy cpu car ops clk: tegra: defer application of init table clk: tegra: Fix cdev1 and cdev2 IDs clk: tegra: Make gr2d and gr3d clocks children of pll_c clk: tegra: Export peripheral reset functions clk: tegra: Fix periph_clk_to_bit macro Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt303
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt4
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts1
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts1
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi8
-rw-r--r--arch/arm/mach-tegra/tegra.c3
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c11
-rw-r--r--drivers/clk/tegra/clk-periph.c14
-rw-r--r--drivers/clk/tegra/clk-pll.c1144
-rw-r--r--drivers/clk/tegra/clk-tegra114.c2085
-rw-r--r--drivers/clk/tegra/clk-tegra20.c184
-rw-r--r--drivers/clk/tegra/clk-tegra30.c276
-rw-r--r--drivers/clk/tegra/clk.c14
-rw-r--r--drivers/clk/tegra/clk.h98
-rw-r--r--include/linux/clk/tegra.h1
16 files changed, 3807 insertions, 341 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
new file mode 100644
index 000000000000..d6cb083b90a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -0,0 +1,303 @@
1NVIDIA Tegra114 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra114-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
27
28 0 unassigned
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 unassigned
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 unassigned
60
61 32 unassigned
62 33 unassigned
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 unassigned
67 38 unassigned
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned
79 50 mipi
80 51 hdmi
81 52 csi
82 53 unassigned
83 54 i2c2
84 55 uartc
85 56 mipi-cal
86 57 emc
87 58 usb2
88 59 usb3
89 60 msenc
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 unassigned
95 65 uartd
96 66 unassigned
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 unassigned
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 unassigned
106 76 la
107 77 trace
108 78 soc_therm
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 tsec
114 84 unassigned
115 85 unassigned
116 86 unassigned
117 87 unassigned
118 88 unassigned
119 89 xusb_host
120 90 unassigned
121 91 msenc
122 92 csus
123 93 unassigned
124 94 unassigned
125 95 unassigned (bit affects xusb_dev and xusb_dev_src)
126
127 96 unassigned
128 97 unassigned
129 98 unassigned
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 unassigned
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 spdif_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 unassigned
155 124 unassigned
156 125 hda
157 126 unassigned
158 127 se
159
160 128 hda2hdmi
161 129 unassigned
162 130 unassigned
163 131 unassigned
164 132 unassigned
165 133 unassigned
166 134 unassigned
167 135 unassigned
168 136 unassigned
169 137 unassigned
170 138 unassigned
171 139 unassigned
172 140 unassigned
173 141 unassigned
174 142 unassigned
175 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
176 xusb_host_src and xusb_ss_src)
177 144 cilab
178 145 cilcd
179 146 cile
180 147 dsialp
181 148 dsiblp
182 149 unassigned
183 150 dds
184 151 unassigned
185 152 dp2
186 153 amx
187 154 adx
188 155 unassigned (bit affects dfll_ref and dfll_soc)
189 156 xusb_ss
190
191 192 uartb
192 193 vfir
193 194 spdif_in
194 195 spdif_out
195 196 vi
196 197 vi_sensor
197 198 fuse
198 199 fuse_burn
199 200 clk_32k
200 201 clk_m
201 202 clk_m_div2
202 203 clk_m_div4
203 204 pll_ref
204 205 pll_c
205 206 pll_c_out1
206 207 pll_c2
207 208 pll_c3
208 209 pll_m
209 210 pll_m_out1
210 211 pll_p
211 212 pll_p_out1
212 213 pll_p_out2
213 214 pll_p_out3
214 215 pll_p_out4
215 216 pll_a
216 217 pll_a_out0
217 218 pll_d
218 219 pll_d_out0
219 220 pll_d2
220 221 pll_d2_out0
221 222 pll_u
222 223 pll_u_480M
223 224 pll_u_60M
224 225 pll_u_48M
225 226 pll_u_12M
226 227 pll_x
227 228 pll_x_out0
228 229 pll_re_vco
229 230 pll_re_out
230 231 pll_e_out0
231 232 spdif_in_sync
232 233 i2s0_sync
233 234 i2s1_sync
234 235 i2s2_sync
235 236 i2s3_sync
236 237 i2s4_sync
237 238 vimclk_sync
238 239 audio0
239 240 audio1
240 241 audio2
241 242 audio3
242 243 audio4
243 244 spdif
244 245 clk_out_1
245 246 clk_out_2
246 247 clk_out_3
247 248 blink
248 252 xusb_host_src
249 253 xusb_falcon_src
250 254 xusb_fs_src
251 255 xusb_ss_src
252 256 xusb_dev_src
253 257 xusb_dev
254 258 xusb_hs_src
255 259 sclk
256 260 hclk
257 261 pclk
258 262 cclk_g
259 263 cclk_lp
260 264 dfll_ref
261 265 dfll_soc
262
263Example SoC include file:
264
265/ {
266 tegra_car: clock {
267 compatible = "nvidia,tegra114-car";
268 reg = <0x60006000 0x1000>;
269 #clock-cells = <1>;
270 };
271
272 usb@c5004000 {
273 clocks = <&tegra_car 58>; /* usb2 */
274 };
275};
276
277Example board file:
278
279/ {
280 clocks {
281 compatible = "simple-bus";
282 #address-cells = <1>;
283 #size-cells = <0>;
284
285 osc: clock@0 {
286 compatible = "fixed-clock";
287 reg = <0>;
288 #clock-cells = <0>;
289 clock-frequency = <12000000>;
290 };
291
292 clk_32k: clock@1 {
293 compatible = "fixed-clock";
294 reg = <1>;
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 };
298 };
299
300 &tegra_car {
301 clocks = <&clk_32k> <&osc>;
302 };
303};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac73528..e885680f6b45 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
120 90 clk_d 120 90 clk_d
121 91 unassigned 121 91 unassigned
122 92 sus 122 92 sus
123 93 cdev1 123 93 cdev2
124 94 cdev2 124 94 cdev1
125 95 unassigned 125 95 unassigned
126 126
127 96 uart2 127 96 uart2
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 6ebc1b704190..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,7 +12,6 @@
12 12
13 serial@70006300 { 13 serial@70006300 {
14 status = "okay"; 14 status = "okay";
15 clock-frequency = <408000000>;
16 }; 15 };
17 16
18 pmc { 17 pmc {
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 5deb8692b350..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,7 +12,6 @@
12 12
13 serial@70006300 { 13 serial@70006300 {
14 status = "okay"; 14 status = "okay";
15 clock-frequency = <408000000>;
16 }; 15 };
17 16
18 pmc { 17 pmc {
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c0b527d15fda..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
24 0 42 0x04 24 0 42 0x04
25 0 121 0x04 25 0 121 0x04
26 0 122 0x04>; 26 0 122 0x04>;
27 clocks = <&tegra_car 5>;
27 }; 28 };
28 29
29 tegra_car: clock { 30 tegra_car: clock {
30 compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; 31 compatible = "nvidia,tegra114-car";
31 reg = <0x60006000 0x1000>; 32 reg = <0x60006000 0x1000>;
32 #clock-cells = <1>; 33 #clock-cells = <1>;
33 }; 34 };
@@ -66,6 +67,7 @@
66 reg-shift = <2>; 67 reg-shift = <2>;
67 interrupts = <0 36 0x04>; 68 interrupts = <0 36 0x04>;
68 status = "disabled"; 69 status = "disabled";
70 clocks = <&tegra_car 6>;
69 }; 71 };
70 72
71 serial@70006040 { 73 serial@70006040 {
@@ -74,6 +76,7 @@
74 reg-shift = <2>; 76 reg-shift = <2>;
75 interrupts = <0 37 0x04>; 77 interrupts = <0 37 0x04>;
76 status = "disabled"; 78 status = "disabled";
79 clocks = <&tegra_car 192>;
77 }; 80 };
78 81
79 serial@70006200 { 82 serial@70006200 {
@@ -82,6 +85,7 @@
82 reg-shift = <2>; 85 reg-shift = <2>;
83 interrupts = <0 46 0x04>; 86 interrupts = <0 46 0x04>;
84 status = "disabled"; 87 status = "disabled";
88 clocks = <&tegra_car 55>;
85 }; 89 };
86 90
87 serial@70006300 { 91 serial@70006300 {
@@ -90,12 +94,14 @@
90 reg-shift = <2>; 94 reg-shift = <2>;
91 interrupts = <0 90 0x04>; 95 interrupts = <0 90 0x04>;
92 status = "disabled"; 96 status = "disabled";
97 clocks = <&tegra_car 65>;
93 }; 98 };
94 99
95 rtc { 100 rtc {
96 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 101 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
97 reg = <0x7000e000 0x100>; 102 reg = <0x7000e000 0x100>;
98 interrupts = <0 2 0x04>; 103 interrupts = <0 2 0x04>;
104 clocks = <&tegra_car 4>;
99 }; 105 };
100 106
101 pmc { 107 pmc {
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 84deeab23ee7..61749e2d8111 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -36,6 +36,7 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/sys_soc.h> 37#include <linux/sys_soc.h>
38#include <linux/usb/tegra_usb_phy.h> 38#include <linux/usb/tegra_usb_phy.h>
39#include <linux/clk/tegra.h>
39 40
40#include <asm/mach-types.h> 41#include <asm/mach-types.h>
41#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
@@ -87,6 +88,8 @@ static void __init tegra_dt_init(void)
87 struct soc_device *soc_dev; 88 struct soc_device *soc_dev;
88 struct device *parent = NULL; 89 struct device *parent = NULL;
89 90
91 tegra_clocks_apply_init_table();
92
90 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 93 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
91 if (!soc_dev_attr) 94 if (!soc_dev_attr)
92 goto out; 95 goto out;
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f4f731..f49fac2d193a 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y += clk-super.o
9 9
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
12obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7b..bafee9895a24 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
41#define write_rst_clr(val, gate) \ 41#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) 42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43 43
44#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32)) 44#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
45
46#define LVL2_CLK_GATE_OVRE 0x554
45 47
46/* Peripheral gate clock ops */ 48/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw) 49static int clk_periph_is_enabled(struct clk_hw *hw)
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
83 } 85 }
84 } 86 }
85 87
88 if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
89 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
90 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
91 udelay(1);
92 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
93 }
94
86 spin_unlock_irqrestore(&periph_ref_lock, flags); 95 spin_unlock_irqrestore(&periph_ref_lock, flags);
87 96
88 return 0; 97 return 0;
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e6331a..b2309d37a963 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/export.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20#include <linux/err.h> 21#include <linux/err.h>
21 22
@@ -128,6 +129,7 @@ void tegra_periph_reset_deassert(struct clk *c)
128 129
129 tegra_periph_reset(gate, 0); 130 tegra_periph_reset(gate, 0);
130} 131}
132EXPORT_SYMBOL(tegra_periph_reset_deassert);
131 133
132void tegra_periph_reset_assert(struct clk *c) 134void tegra_periph_reset_assert(struct clk *c)
133{ 135{
@@ -147,6 +149,7 @@ void tegra_periph_reset_assert(struct clk *c)
147 149
148 tegra_periph_reset(gate, 1); 150 tegra_periph_reset(gate, 1);
149} 151}
152EXPORT_SYMBOL(tegra_periph_reset_assert);
150 153
151const struct clk_ops tegra_clk_periph_ops = { 154const struct clk_ops tegra_clk_periph_ops = {
152 .get_parent = clk_periph_get_parent, 155 .get_parent = clk_periph_get_parent,
@@ -170,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
170static struct clk *_tegra_clk_register_periph(const char *name, 173static struct clk *_tegra_clk_register_periph(const char *name,
171 const char **parent_names, int num_parents, 174 const char **parent_names, int num_parents,
172 struct tegra_clk_periph *periph, 175 struct tegra_clk_periph *periph,
173 void __iomem *clk_base, u32 offset, bool div) 176 void __iomem *clk_base, u32 offset, bool div,
177 unsigned long flags)
174{ 178{
175 struct clk *clk; 179 struct clk *clk;
176 struct clk_init_data init; 180 struct clk_init_data init;
177 181
178 init.name = name; 182 init.name = name;
179 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops; 183 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
180 init.flags = div ? 0 : CLK_SET_RATE_PARENT; 184 init.flags = flags;
181 init.parent_names = parent_names; 185 init.parent_names = parent_names;
182 init.num_parents = num_parents; 186 init.num_parents = num_parents;
183 187
@@ -202,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
202struct clk *tegra_clk_register_periph(const char *name, 206struct clk *tegra_clk_register_periph(const char *name,
203 const char **parent_names, int num_parents, 207 const char **parent_names, int num_parents,
204 struct tegra_clk_periph *periph, void __iomem *clk_base, 208 struct tegra_clk_periph *periph, void __iomem *clk_base,
205 u32 offset) 209 u32 offset, unsigned long flags)
206{ 210{
207 return _tegra_clk_register_periph(name, parent_names, num_parents, 211 return _tegra_clk_register_periph(name, parent_names, num_parents,
208 periph, clk_base, offset, true); 212 periph, clk_base, offset, true, flags);
209} 213}
210 214
211struct clk *tegra_clk_register_periph_nodiv(const char *name, 215struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -214,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
214 u32 offset) 218 u32 offset)
215{ 219{
216 return _tegra_clk_register_periph(name, parent_names, num_parents, 220 return _tegra_clk_register_periph(name, parent_names, num_parents,
217 periph, clk_base, offset, false); 221 periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
218} 222}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f24734c1b..17c2cc086eb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -79,6 +79,48 @@
79#define PLLE_SS_CTRL 0x68 79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10) 80#define PLLE_SS_DISABLE (7 << 10)
81 81
82#define PLLE_AUX_PLLP_SEL BIT(2)
83#define PLLE_AUX_ENABLE_SWCTL BIT(4)
84#define PLLE_AUX_SEQ_ENABLE BIT(24)
85#define PLLE_AUX_PLLRE_SEL BIT(28)
86
87#define PLLE_MISC_PLLE_PTS BIT(8)
88#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
89#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
90#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
91#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
92#define PLLE_MISC_VREG_CTRL_SHIFT 2
93#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
94
95#define PLLCX_MISC_STROBE BIT(31)
96#define PLLCX_MISC_RESET BIT(30)
97#define PLLCX_MISC_SDM_DIV_SHIFT 28
98#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
99#define PLLCX_MISC_FILT_DIV_SHIFT 26
100#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
101#define PLLCX_MISC_ALPHA_SHIFT 18
102#define PLLCX_MISC_DIV_LOW_RANGE \
103 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
104 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
105#define PLLCX_MISC_DIV_HIGH_RANGE \
106 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
107 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
108#define PLLCX_MISC_COEF_LOW_RANGE \
109 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
110#define PLLCX_MISC_KA_SHIFT 2
111#define PLLCX_MISC_KB_SHIFT 9
112#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
113 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
114 PLLCX_MISC_DIV_LOW_RANGE | \
115 PLLCX_MISC_RESET)
116#define PLLCX_MISC1_DEFAULT 0x000d2308
117#define PLLCX_MISC2_DEFAULT 0x30211200
118#define PLLCX_MISC3_DEFAULT 0x200
119
120#define PMC_PLLM_WB0_OVERRIDE 0x1dc
121#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
122#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
123
82#define PMC_SATA_PWRGT 0x1ac 124#define PMC_SATA_PWRGT 0x1ac
83#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 125#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
84#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 126#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
@@ -101,6 +143,24 @@
101#define divn_max(p) (divn_mask(p)) 143#define divn_max(p) (divn_mask(p))
102#define divp_max(p) (1 << (divp_mask(p))) 144#define divp_max(p) (1 << (divp_mask(p)))
103 145
146
147#ifdef CONFIG_ARCH_TEGRA_114_SOC
148/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
149#define PLLXC_PDIV_MAX 14
150
151/* non-monotonic mapping below is not a typo */
152static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
153 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
154 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
155};
156
157#define PLLCX_PDIV_MAX 7
158static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
159 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
160 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
161};
162#endif
163
104static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 164static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
105{ 165{
106 u32 val; 166 u32 val;
@@ -108,25 +168,36 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
108 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) 168 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
109 return; 169 return;
110 170
171 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
172 return;
173
111 val = pll_readl_misc(pll); 174 val = pll_readl_misc(pll);
112 val |= BIT(pll->params->lock_enable_bit_idx); 175 val |= BIT(pll->params->lock_enable_bit_idx);
113 pll_writel_misc(val, pll); 176 pll_writel_misc(val, pll);
114} 177}
115 178
116static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll, 179static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
117 void __iomem *lock_addr, u32 lock_bit_idx)
118{ 180{
119 int i; 181 int i;
120 u32 val; 182 u32 val, lock_mask;
183 void __iomem *lock_addr;
121 184
122 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { 185 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
123 udelay(pll->params->lock_delay); 186 udelay(pll->params->lock_delay);
124 return 0; 187 return 0;
125 } 188 }
126 189
190 lock_addr = pll->clk_base;
191 if (pll->flags & TEGRA_PLL_LOCK_MISC)
192 lock_addr += pll->params->misc_reg;
193 else
194 lock_addr += pll->params->base_reg;
195
196 lock_mask = pll->params->lock_mask;
197
127 for (i = 0; i < pll->params->lock_delay; i++) { 198 for (i = 0; i < pll->params->lock_delay; i++) {
128 val = readl_relaxed(lock_addr); 199 val = readl_relaxed(lock_addr);
129 if (val & BIT(lock_bit_idx)) { 200 if ((val & lock_mask) == lock_mask) {
130 udelay(PLL_POST_LOCK_DELAY); 201 udelay(PLL_POST_LOCK_DELAY);
131 return 0; 202 return 0;
132 } 203 }
@@ -155,7 +226,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
155 return val & PLL_BASE_ENABLE ? 1 : 0; 226 return val & PLL_BASE_ENABLE ? 1 : 0;
156} 227}
157 228
158static int _clk_pll_enable(struct clk_hw *hw) 229static void _clk_pll_enable(struct clk_hw *hw)
159{ 230{
160 struct tegra_clk_pll *pll = to_clk_pll(hw); 231 struct tegra_clk_pll *pll = to_clk_pll(hw);
161 u32 val; 232 u32 val;
@@ -163,7 +234,8 @@ static int _clk_pll_enable(struct clk_hw *hw)
163 clk_pll_enable_lock(pll); 234 clk_pll_enable_lock(pll);
164 235
165 val = pll_readl_base(pll); 236 val = pll_readl_base(pll);
166 val &= ~PLL_BASE_BYPASS; 237 if (pll->flags & TEGRA_PLL_BYPASS)
238 val &= ~PLL_BASE_BYPASS;
167 val |= PLL_BASE_ENABLE; 239 val |= PLL_BASE_ENABLE;
168 pll_writel_base(val, pll); 240 pll_writel_base(val, pll);
169 241
@@ -172,11 +244,6 @@ static int _clk_pll_enable(struct clk_hw *hw)
172 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 244 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
173 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 245 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
174 } 246 }
175
176 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
177 pll->params->lock_bit_idx);
178
179 return 0;
180} 247}
181 248
182static void _clk_pll_disable(struct clk_hw *hw) 249static void _clk_pll_disable(struct clk_hw *hw)
@@ -185,7 +252,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
185 u32 val; 252 u32 val;
186 253
187 val = pll_readl_base(pll); 254 val = pll_readl_base(pll);
188 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 255 if (pll->flags & TEGRA_PLL_BYPASS)
256 val &= ~PLL_BASE_BYPASS;
257 val &= ~PLL_BASE_ENABLE;
189 pll_writel_base(val, pll); 258 pll_writel_base(val, pll);
190 259
191 if (pll->flags & TEGRA_PLLM) { 260 if (pll->flags & TEGRA_PLLM) {
@@ -204,7 +273,9 @@ static int clk_pll_enable(struct clk_hw *hw)
204 if (pll->lock) 273 if (pll->lock)
205 spin_lock_irqsave(pll->lock, flags); 274 spin_lock_irqsave(pll->lock, flags);
206 275
207 ret = _clk_pll_enable(hw); 276 _clk_pll_enable(hw);
277
278 ret = clk_pll_wait_for_lock(pll);
208 279
209 if (pll->lock) 280 if (pll->lock)
210 spin_unlock_irqrestore(pll->lock, flags); 281 spin_unlock_irqrestore(pll->lock, flags);
@@ -241,8 +312,6 @@ static int _get_table_rate(struct clk_hw *hw,
241 if (sel->input_rate == 0) 312 if (sel->input_rate == 0)
242 return -EINVAL; 313 return -EINVAL;
243 314
244 BUG_ON(sel->p < 1);
245
246 cfg->input_rate = sel->input_rate; 315 cfg->input_rate = sel->input_rate;
247 cfg->output_rate = sel->output_rate; 316 cfg->output_rate = sel->output_rate;
248 cfg->m = sel->m; 317 cfg->m = sel->m;
@@ -257,6 +326,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
257 unsigned long rate, unsigned long parent_rate) 326 unsigned long rate, unsigned long parent_rate)
258{ 327{
259 struct tegra_clk_pll *pll = to_clk_pll(hw); 328 struct tegra_clk_pll *pll = to_clk_pll(hw);
329 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
260 unsigned long cfreq; 330 unsigned long cfreq;
261 u32 p_div = 0; 331 u32 p_div = 0;
262 332
@@ -290,88 +360,119 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
290 cfg->output_rate <<= 1) 360 cfg->output_rate <<= 1)
291 p_div++; 361 p_div++;
292 362
293 cfg->p = 1 << p_div;
294 cfg->m = parent_rate / cfreq; 363 cfg->m = parent_rate / cfreq;
295 cfg->n = cfg->output_rate / cfreq; 364 cfg->n = cfg->output_rate / cfreq;
296 cfg->cpcon = OUT_OF_TABLE_CPCON; 365 cfg->cpcon = OUT_OF_TABLE_CPCON;
297 366
298 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 367 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
299 cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) { 368 (1 << p_div) > divp_max(pll)
369 || cfg->output_rate > pll->params->vco_max) {
300 pr_err("%s: Failed to set %s rate %lu\n", 370 pr_err("%s: Failed to set %s rate %lu\n",
301 __func__, __clk_get_name(hw->clk), rate); 371 __func__, __clk_get_name(hw->clk), rate);
302 return -EINVAL; 372 return -EINVAL;
303 } 373 }
304 374
375 if (p_tohw) {
376 p_div = 1 << p_div;
377 while (p_tohw->pdiv) {
378 if (p_div <= p_tohw->pdiv) {
379 cfg->p = p_tohw->hw_val;
380 break;
381 }
382 p_tohw++;
383 }
384 if (!p_tohw->pdiv)
385 return -EINVAL;
386 } else
387 cfg->p = p_div;
388
305 return 0; 389 return 0;
306} 390}
307 391
308static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 392static void _update_pll_mnp(struct tegra_clk_pll *pll,
309 unsigned long rate) 393 struct tegra_clk_pll_freq_table *cfg)
310{ 394{
311 struct tegra_clk_pll *pll = to_clk_pll(hw); 395 u32 val;
312 unsigned long flags = 0;
313 u32 divp, val, old_base;
314 int state;
315
316 divp = __ffs(cfg->p);
317
318 if (pll->flags & TEGRA_PLLU)
319 divp ^= 1;
320 396
321 if (pll->lock) 397 val = pll_readl_base(pll);
322 spin_lock_irqsave(pll->lock, flags);
323 398
324 old_base = val = pll_readl_base(pll);
325 val &= ~((divm_mask(pll) << pll->divm_shift) | 399 val &= ~((divm_mask(pll) << pll->divm_shift) |
326 (divn_mask(pll) << pll->divn_shift) | 400 (divn_mask(pll) << pll->divn_shift) |
327 (divp_mask(pll) << pll->divp_shift)); 401 (divp_mask(pll) << pll->divp_shift));
328 val |= ((cfg->m << pll->divm_shift) | 402 val |= ((cfg->m << pll->divm_shift) |
329 (cfg->n << pll->divn_shift) | 403 (cfg->n << pll->divn_shift) |
330 (divp << pll->divp_shift)); 404 (cfg->p << pll->divp_shift));
331 if (val == old_base) { 405
332 if (pll->lock) 406 pll_writel_base(val, pll);
333 spin_unlock_irqrestore(pll->lock, flags); 407}
334 return 0; 408
409static void _get_pll_mnp(struct tegra_clk_pll *pll,
410 struct tegra_clk_pll_freq_table *cfg)
411{
412 u32 val;
413
414 val = pll_readl_base(pll);
415
416 cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
417 cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
418 cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
419}
420
421static void _update_pll_cpcon(struct tegra_clk_pll *pll,
422 struct tegra_clk_pll_freq_table *cfg,
423 unsigned long rate)
424{
425 u32 val;
426
427 val = pll_readl_misc(pll);
428
429 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
430 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
431
432 if (pll->flags & TEGRA_PLL_SET_LFCON) {
433 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
434 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
435 val |= 1 << PLL_MISC_LFCON_SHIFT;
436 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
437 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
438 if (rate >= (pll->params->vco_max >> 1))
439 val |= 1 << PLL_MISC_DCCON_SHIFT;
335 } 440 }
336 441
442 pll_writel_misc(val, pll);
443}
444
445static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
446 unsigned long rate)
447{
448 struct tegra_clk_pll *pll = to_clk_pll(hw);
449 int state, ret = 0;
450
337 state = clk_pll_is_enabled(hw); 451 state = clk_pll_is_enabled(hw);
338 452
339 if (state) { 453 if (state)
340 _clk_pll_disable(hw); 454 _clk_pll_disable(hw);
341 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
342 }
343 pll_writel_base(val, pll);
344 455
345 if (pll->flags & TEGRA_PLL_HAS_CPCON) { 456 _update_pll_mnp(pll, cfg);
346 val = pll_readl_misc(pll);
347 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
348 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
349 if (pll->flags & TEGRA_PLL_SET_LFCON) {
350 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
351 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
352 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
353 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
354 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
355 if (rate >= (pll->params->vco_max >> 1))
356 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
357 }
358 pll_writel_misc(val, pll);
359 }
360 457
361 if (pll->lock) 458 if (pll->flags & TEGRA_PLL_HAS_CPCON)
362 spin_unlock_irqrestore(pll->lock, flags); 459 _update_pll_cpcon(pll, cfg, rate);
363 460
364 if (state) 461 if (state) {
365 clk_pll_enable(hw); 462 _clk_pll_enable(hw);
463 ret = clk_pll_wait_for_lock(pll);
464 }
366 465
367 return 0; 466 return ret;
368} 467}
369 468
370static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 469static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate) 470 unsigned long parent_rate)
372{ 471{
373 struct tegra_clk_pll *pll = to_clk_pll(hw); 472 struct tegra_clk_pll *pll = to_clk_pll(hw);
374 struct tegra_clk_pll_freq_table cfg; 473 struct tegra_clk_pll_freq_table cfg, old_cfg;
474 unsigned long flags = 0;
475 int ret = 0;
375 476
376 if (pll->flags & TEGRA_PLL_FIXED) { 477 if (pll->flags & TEGRA_PLL_FIXED) {
377 if (rate != pll->fixed_rate) { 478 if (rate != pll->fixed_rate) {
@@ -387,7 +488,18 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
387 _calc_rate(hw, &cfg, rate, parent_rate)) 488 _calc_rate(hw, &cfg, rate, parent_rate))
388 return -EINVAL; 489 return -EINVAL;
389 490
390 return _program_pll(hw, &cfg, rate); 491 if (pll->lock)
492 spin_lock_irqsave(pll->lock, flags);
493
494 _get_pll_mnp(pll, &old_cfg);
495
496 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
497 ret = _program_pll(hw, &cfg, rate);
498
499 if (pll->lock)
500 spin_unlock_irqrestore(pll->lock, flags);
501
502 return ret;
391} 503}
392 504
393static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 505static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -409,7 +521,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
409 return -EINVAL; 521 return -EINVAL;
410 522
411 output_rate *= cfg.n; 523 output_rate *= cfg.n;
412 do_div(output_rate, cfg.m * cfg.p); 524 do_div(output_rate, cfg.m * (1 << cfg.p));
413 525
414 return output_rate; 526 return output_rate;
415} 527}
@@ -418,11 +530,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
418 unsigned long parent_rate) 530 unsigned long parent_rate)
419{ 531{
420 struct tegra_clk_pll *pll = to_clk_pll(hw); 532 struct tegra_clk_pll *pll = to_clk_pll(hw);
421 u32 val = pll_readl_base(pll); 533 struct tegra_clk_pll_freq_table cfg;
422 u32 divn = 0, divm = 0, divp = 0; 534 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
535 u32 val;
423 u64 rate = parent_rate; 536 u64 rate = parent_rate;
537 int pdiv;
538
539 val = pll_readl_base(pll);
424 540
425 if (val & PLL_BASE_BYPASS) 541 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
426 return parent_rate; 542 return parent_rate;
427 543
428 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { 544 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -435,16 +551,29 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
435 return pll->fixed_rate; 551 return pll->fixed_rate;
436 } 552 }
437 553
438 divp = (val >> pll->divp_shift) & (divp_mask(pll)); 554 _get_pll_mnp(pll, &cfg);
439 if (pll->flags & TEGRA_PLLU)
440 divp ^= 1;
441 555
442 divn = (val >> pll->divn_shift) & (divn_mask(pll)); 556 if (p_tohw) {
443 divm = (val >> pll->divm_shift) & (divm_mask(pll)); 557 while (p_tohw->pdiv) {
444 divm *= (1 << divp); 558 if (cfg.p == p_tohw->hw_val) {
559 pdiv = p_tohw->pdiv;
560 break;
561 }
562 p_tohw++;
563 }
564
565 if (!p_tohw->pdiv) {
566 WARN_ON(1);
567 pdiv = 1;
568 }
569 } else
570 pdiv = 1 << cfg.p;
571
572 cfg.m *= pdiv;
573
574 rate *= cfg.n;
575 do_div(rate, cfg.m);
445 576
446 rate *= divn;
447 do_div(rate, divm);
448 return rate; 577 return rate;
449} 578}
450 579
@@ -538,8 +667,8 @@ static int clk_plle_enable(struct clk_hw *hw)
538 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 667 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
539 pll_writel_base(val, pll); 668 pll_writel_base(val, pll);
540 669
541 clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg, 670 clk_pll_wait_for_lock(pll);
542 pll->params->lock_bit_idx); 671
543 return 0; 672 return 0;
544} 673}
545 674
@@ -577,28 +706,531 @@ const struct clk_ops tegra_clk_plle_ops = {
577 .enable = clk_plle_enable, 706 .enable = clk_plle_enable,
578}; 707};
579 708
580static struct clk *_tegra_clk_register_pll(const char *name, 709#ifdef CONFIG_ARCH_TEGRA_114_SOC
581 const char *parent_name, void __iomem *clk_base, 710
582 void __iomem *pmc, unsigned long flags, 711static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
583 unsigned long fixed_rate, 712 unsigned long parent_rate)
584 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 713{
585 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock, 714 if (parent_rate > pll_params->cf_max)
586 const struct clk_ops *ops) 715 return 2;
716 else
717 return 1;
718}
719
720static int clk_pll_iddq_enable(struct clk_hw *hw)
721{
722 struct tegra_clk_pll *pll = to_clk_pll(hw);
723 unsigned long flags = 0;
724
725 u32 val;
726 int ret;
727
728 if (pll->lock)
729 spin_lock_irqsave(pll->lock, flags);
730
731 val = pll_readl(pll->params->iddq_reg, pll);
732 val &= ~BIT(pll->params->iddq_bit_idx);
733 pll_writel(val, pll->params->iddq_reg, pll);
734 udelay(2);
735
736 _clk_pll_enable(hw);
737
738 ret = clk_pll_wait_for_lock(pll);
739
740 if (pll->lock)
741 spin_unlock_irqrestore(pll->lock, flags);
742
743 return 0;
744}
745
746static void clk_pll_iddq_disable(struct clk_hw *hw)
747{
748 struct tegra_clk_pll *pll = to_clk_pll(hw);
749 unsigned long flags = 0;
750 u32 val;
751
752 if (pll->lock)
753 spin_lock_irqsave(pll->lock, flags);
754
755 _clk_pll_disable(hw);
756
757 val = pll_readl(pll->params->iddq_reg, pll);
758 val |= BIT(pll->params->iddq_bit_idx);
759 pll_writel(val, pll->params->iddq_reg, pll);
760 udelay(2);
761
762 if (pll->lock)
763 spin_unlock_irqrestore(pll->lock, flags);
764}
765
766static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
767 struct tegra_clk_pll_freq_table *cfg,
768 unsigned long rate, unsigned long parent_rate)
769{
770 struct tegra_clk_pll *pll = to_clk_pll(hw);
771 unsigned int p;
772
773 if (!rate)
774 return -EINVAL;
775
776 p = DIV_ROUND_UP(pll->params->vco_min, rate);
777 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
778 cfg->p = p;
779 cfg->output_rate = rate * cfg->p;
780 cfg->n = cfg->output_rate * cfg->m / parent_rate;
781
782 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
783 return -EINVAL;
784
785 return 0;
786}
787
788static int _pll_ramp_calc_pll(struct clk_hw *hw,
789 struct tegra_clk_pll_freq_table *cfg,
790 unsigned long rate, unsigned long parent_rate)
791{
792 struct tegra_clk_pll *pll = to_clk_pll(hw);
793 int err = 0;
794
795 err = _get_table_rate(hw, cfg, rate, parent_rate);
796 if (err < 0)
797 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
798 else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
799 WARN_ON(1);
800 err = -EINVAL;
801 goto out;
802 }
803
804 if (!cfg->p || (cfg->p > pll->params->max_p))
805 err = -EINVAL;
806
807out:
808 return err;
809}
810
811static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
812 unsigned long parent_rate)
813{
814 struct tegra_clk_pll *pll = to_clk_pll(hw);
815 struct tegra_clk_pll_freq_table cfg, old_cfg;
816 unsigned long flags = 0;
817 int ret = 0;
818 u8 old_p;
819
820 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
821 if (ret < 0)
822 return ret;
823
824 if (pll->lock)
825 spin_lock_irqsave(pll->lock, flags);
826
827 _get_pll_mnp(pll, &old_cfg);
828
829 old_p = pllxc_p[old_cfg.p];
830 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
831 cfg.p -= 1;
832 ret = _program_pll(hw, &cfg, rate);
833 }
834
835 if (pll->lock)
836 spin_unlock_irqrestore(pll->lock, flags);
837
838 return ret;
839}
840
841static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
842 unsigned long *prate)
843{
844 struct tegra_clk_pll_freq_table cfg;
845 int ret = 0;
846 u64 output_rate = *prate;
847
848 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
849 if (ret < 0)
850 return ret;
851
852 output_rate *= cfg.n;
853 do_div(output_rate, cfg.m * cfg.p);
854
855 return output_rate;
856}
857
858static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
859 unsigned long parent_rate)
860{
861 struct tegra_clk_pll_freq_table cfg;
862 struct tegra_clk_pll *pll = to_clk_pll(hw);
863 unsigned long flags = 0;
864 int state, ret = 0;
865 u32 val;
866
867 if (pll->lock)
868 spin_lock_irqsave(pll->lock, flags);
869
870 state = clk_pll_is_enabled(hw);
871 if (state) {
872 if (rate != clk_get_rate(hw->clk)) {
873 pr_err("%s: Cannot change active PLLM\n", __func__);
874 ret = -EINVAL;
875 goto out;
876 }
877 goto out;
878 }
879
880 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
881 if (ret < 0)
882 goto out;
883
884 cfg.p -= 1;
885
886 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
887 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
888 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
889 val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
890 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
891 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
892
893 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
894 val &= ~(divn_mask(pll) | divm_mask(pll));
895 val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
896 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
897 } else
898 _update_pll_mnp(pll, &cfg);
899
900
901out:
902 if (pll->lock)
903 spin_unlock_irqrestore(pll->lock, flags);
904
905 return ret;
906}
907
908static void _pllcx_strobe(struct tegra_clk_pll *pll)
909{
910 u32 val;
911
912 val = pll_readl_misc(pll);
913 val |= PLLCX_MISC_STROBE;
914 pll_writel_misc(val, pll);
915 udelay(2);
916
917 val &= ~PLLCX_MISC_STROBE;
918 pll_writel_misc(val, pll);
919}
920
921static int clk_pllc_enable(struct clk_hw *hw)
922{
923 struct tegra_clk_pll *pll = to_clk_pll(hw);
924 u32 val;
925 int ret = 0;
926 unsigned long flags = 0;
927
928 if (pll->lock)
929 spin_lock_irqsave(pll->lock, flags);
930
931 _clk_pll_enable(hw);
932 udelay(2);
933
934 val = pll_readl_misc(pll);
935 val &= ~PLLCX_MISC_RESET;
936 pll_writel_misc(val, pll);
937 udelay(2);
938
939 _pllcx_strobe(pll);
940
941 ret = clk_pll_wait_for_lock(pll);
942
943 if (pll->lock)
944 spin_unlock_irqrestore(pll->lock, flags);
945
946 return ret;
947}
948
949static void _clk_pllc_disable(struct clk_hw *hw)
950{
951 struct tegra_clk_pll *pll = to_clk_pll(hw);
952 u32 val;
953
954 _clk_pll_disable(hw);
955
956 val = pll_readl_misc(pll);
957 val |= PLLCX_MISC_RESET;
958 pll_writel_misc(val, pll);
959 udelay(2);
960}
961
962static void clk_pllc_disable(struct clk_hw *hw)
963{
964 struct tegra_clk_pll *pll = to_clk_pll(hw);
965 unsigned long flags = 0;
966
967 if (pll->lock)
968 spin_lock_irqsave(pll->lock, flags);
969
970 _clk_pllc_disable(hw);
971
972 if (pll->lock)
973 spin_unlock_irqrestore(pll->lock, flags);
974}
975
976static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
977 unsigned long input_rate, u32 n)
978{
979 u32 val, n_threshold;
980
981 switch (input_rate) {
982 case 12000000:
983 n_threshold = 70;
984 break;
985 case 13000000:
986 case 26000000:
987 n_threshold = 71;
988 break;
989 case 16800000:
990 n_threshold = 55;
991 break;
992 case 19200000:
993 n_threshold = 48;
994 break;
995 default:
996 pr_err("%s: Unexpected reference rate %lu\n",
997 __func__, input_rate);
998 return -EINVAL;
999 }
1000
1001 val = pll_readl_misc(pll);
1002 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1003 val |= n <= n_threshold ?
1004 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1005 pll_writel_misc(val, pll);
1006
1007 return 0;
1008}
1009
1010static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1011 unsigned long parent_rate)
1012{
1013 struct tegra_clk_pll_freq_table cfg;
1014 struct tegra_clk_pll *pll = to_clk_pll(hw);
1015 unsigned long flags = 0;
1016 int state, ret = 0;
1017 u32 val;
1018 u16 old_m, old_n;
1019 u8 old_p;
1020
1021 if (pll->lock)
1022 spin_lock_irqsave(pll->lock, flags);
1023
1024 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1025 if (ret < 0)
1026 goto out;
1027
1028 val = pll_readl_base(pll);
1029 old_m = (val >> pll->divm_shift) & (divm_mask(pll));
1030 old_n = (val >> pll->divn_shift) & (divn_mask(pll));
1031 old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
1032
1033 if (cfg.m != old_m) {
1034 WARN_ON(1);
1035 goto out;
1036 }
1037
1038 if (old_n == cfg.n && old_p == cfg.p)
1039 goto out;
1040
1041 cfg.p -= 1;
1042
1043 state = clk_pll_is_enabled(hw);
1044 if (state)
1045 _clk_pllc_disable(hw);
1046
1047 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1048 if (ret < 0)
1049 goto out;
1050
1051 _update_pll_mnp(pll, &cfg);
1052
1053 if (state)
1054 ret = clk_pllc_enable(hw);
1055
1056out:
1057 if (pll->lock)
1058 spin_unlock_irqrestore(pll->lock, flags);
1059
1060 return ret;
1061}
1062
1063static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1064 struct tegra_clk_pll_freq_table *cfg,
1065 unsigned long rate, unsigned long parent_rate)
1066{
1067 u16 m, n;
1068 u64 output_rate = parent_rate;
1069
1070 m = _pll_fixed_mdiv(pll->params, parent_rate);
1071 n = rate * m / parent_rate;
1072
1073 output_rate *= n;
1074 do_div(output_rate, m);
1075
1076 if (cfg) {
1077 cfg->m = m;
1078 cfg->n = n;
1079 }
1080
1081 return output_rate;
1082}
1083static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1084 unsigned long parent_rate)
1085{
1086 struct tegra_clk_pll_freq_table cfg, old_cfg;
1087 struct tegra_clk_pll *pll = to_clk_pll(hw);
1088 unsigned long flags = 0;
1089 int state, ret = 0;
1090
1091 if (pll->lock)
1092 spin_lock_irqsave(pll->lock, flags);
1093
1094 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1095 _get_pll_mnp(pll, &old_cfg);
1096 cfg.p = old_cfg.p;
1097
1098 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1099 state = clk_pll_is_enabled(hw);
1100 if (state)
1101 _clk_pll_disable(hw);
1102
1103 _update_pll_mnp(pll, &cfg);
1104
1105 if (state) {
1106 _clk_pll_enable(hw);
1107 ret = clk_pll_wait_for_lock(pll);
1108 }
1109 }
1110
1111 if (pll->lock)
1112 spin_unlock_irqrestore(pll->lock, flags);
1113
1114 return ret;
1115}
1116
1117static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1118 unsigned long parent_rate)
1119{
1120 struct tegra_clk_pll_freq_table cfg;
1121 struct tegra_clk_pll *pll = to_clk_pll(hw);
1122 u64 rate = parent_rate;
1123
1124 _get_pll_mnp(pll, &cfg);
1125
1126 rate *= cfg.n;
1127 do_div(rate, cfg.m);
1128
1129 return rate;
1130}
1131
1132static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1133 unsigned long *prate)
1134{
1135 struct tegra_clk_pll *pll = to_clk_pll(hw);
1136
1137 return _pllre_calc_rate(pll, NULL, rate, *prate);
1138}
1139
1140static int clk_plle_tegra114_enable(struct clk_hw *hw)
1141{
1142 struct tegra_clk_pll *pll = to_clk_pll(hw);
1143 struct tegra_clk_pll_freq_table sel;
1144 u32 val;
1145 int ret;
1146 unsigned long flags = 0;
1147 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1148
1149 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1150 return -EINVAL;
1151
1152 if (pll->lock)
1153 spin_lock_irqsave(pll->lock, flags);
1154
1155 val = pll_readl_base(pll);
1156 val &= ~BIT(29); /* Disable lock override */
1157 pll_writel_base(val, pll);
1158
1159 val = pll_readl(pll->params->aux_reg, pll);
1160 val |= PLLE_AUX_ENABLE_SWCTL;
1161 val &= ~PLLE_AUX_SEQ_ENABLE;
1162 pll_writel(val, pll->params->aux_reg, pll);
1163 udelay(1);
1164
1165 val = pll_readl_misc(pll);
1166 val |= PLLE_MISC_LOCK_ENABLE;
1167 val |= PLLE_MISC_IDDQ_SW_CTRL;
1168 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1169 val |= PLLE_MISC_PLLE_PTS;
1170 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1171 pll_writel_misc(val, pll);
1172 udelay(5);
1173
1174 val = pll_readl(PLLE_SS_CTRL, pll);
1175 val |= PLLE_SS_DISABLE;
1176 pll_writel(val, PLLE_SS_CTRL, pll);
1177
1178 val = pll_readl_base(pll);
1179 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1180 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1181 val |= sel.m << pll->divm_shift;
1182 val |= sel.n << pll->divn_shift;
1183 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1184 pll_writel_base(val, pll);
1185 udelay(1);
1186
1187 _clk_pll_enable(hw);
1188 ret = clk_pll_wait_for_lock(pll);
1189
1190 if (ret < 0)
1191 goto out;
1192
1193 /* TODO: enable hw control of xusb brick pll */
1194
1195out:
1196 if (pll->lock)
1197 spin_unlock_irqrestore(pll->lock, flags);
1198
1199 return ret;
1200}
1201
1202static void clk_plle_tegra114_disable(struct clk_hw *hw)
1203{
1204 struct tegra_clk_pll *pll = to_clk_pll(hw);
1205 unsigned long flags = 0;
1206 u32 val;
1207
1208 if (pll->lock)
1209 spin_lock_irqsave(pll->lock, flags);
1210
1211 _clk_pll_disable(hw);
1212
1213 val = pll_readl_misc(pll);
1214 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1215 pll_writel_misc(val, pll);
1216 udelay(1);
1217
1218 if (pll->lock)
1219 spin_unlock_irqrestore(pll->lock, flags);
1220}
1221#endif
1222
1223static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1224 void __iomem *pmc, unsigned long fixed_rate,
1225 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1226 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
587{ 1227{
588 struct tegra_clk_pll *pll; 1228 struct tegra_clk_pll *pll;
589 struct clk *clk;
590 struct clk_init_data init;
591 1229
592 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1230 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
593 if (!pll) 1231 if (!pll)
594 return ERR_PTR(-ENOMEM); 1232 return ERR_PTR(-ENOMEM);
595 1233
596 init.name = name;
597 init.ops = ops;
598 init.flags = flags;
599 init.parent_names = (parent_name ? &parent_name : NULL);
600 init.num_parents = (parent_name ? 1 : 0);
601
602 pll->clk_base = clk_base; 1234 pll->clk_base = clk_base;
603 pll->pmc = pmc; 1235 pll->pmc = pmc;
604 1236
@@ -615,34 +1247,336 @@ static struct clk *_tegra_clk_register_pll(const char *name,
615 pll->divm_shift = PLL_BASE_DIVM_SHIFT; 1247 pll->divm_shift = PLL_BASE_DIVM_SHIFT;
616 pll->divm_width = PLL_BASE_DIVM_WIDTH; 1248 pll->divm_width = PLL_BASE_DIVM_WIDTH;
617 1249
1250 return pll;
1251}
1252
1253static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1254 const char *name, const char *parent_name, unsigned long flags,
1255 const struct clk_ops *ops)
1256{
1257 struct clk_init_data init;
1258
1259 init.name = name;
1260 init.ops = ops;
1261 init.flags = flags;
1262 init.parent_names = (parent_name ? &parent_name : NULL);
1263 init.num_parents = (parent_name ? 1 : 0);
1264
618 /* Data in .init is copied by clk_register(), so stack variable OK */ 1265 /* Data in .init is copied by clk_register(), so stack variable OK */
619 pll->hw.init = &init; 1266 pll->hw.init = &init;
620 1267
621 clk = clk_register(NULL, &pll->hw); 1268 return clk_register(NULL, &pll->hw);
622 if (IS_ERR(clk))
623 kfree(pll);
624
625 return clk;
626} 1269}
627 1270
628struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1271struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
629 void __iomem *clk_base, void __iomem *pmc, 1272 void __iomem *clk_base, void __iomem *pmc,
630 unsigned long flags, unsigned long fixed_rate, 1273 unsigned long flags, unsigned long fixed_rate,
631 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 1274 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
632 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1275 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
633{ 1276{
634 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc, 1277 struct tegra_clk_pll *pll;
635 flags, fixed_rate, pll_params, pll_flags, freq_table, 1278 struct clk *clk;
636 lock, &tegra_clk_pll_ops); 1279
1280 pll_flags |= TEGRA_PLL_BYPASS;
1281 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1282 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1283 freq_table, lock);
1284 if (IS_ERR(pll))
1285 return ERR_CAST(pll);
1286
1287 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1288 &tegra_clk_pll_ops);
1289 if (IS_ERR(clk))
1290 kfree(pll);
1291
1292 return clk;
637} 1293}
638 1294
639struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1295struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
640 void __iomem *clk_base, void __iomem *pmc, 1296 void __iomem *clk_base, void __iomem *pmc,
641 unsigned long flags, unsigned long fixed_rate, 1297 unsigned long flags, unsigned long fixed_rate,
642 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 1298 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
643 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1299 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
644{ 1300{
645 return _tegra_clk_register_pll(name, parent_name, clk_base, pmc, 1301 struct tegra_clk_pll *pll;
646 flags, fixed_rate, pll_params, pll_flags, freq_table, 1302 struct clk *clk;
647 lock, &tegra_clk_plle_ops); 1303
1304 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1305 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1306 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1307 freq_table, lock);
1308 if (IS_ERR(pll))
1309 return ERR_CAST(pll);
1310
1311 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1312 &tegra_clk_plle_ops);
1313 if (IS_ERR(clk))
1314 kfree(pll);
1315
1316 return clk;
1317}
1318
1319#ifdef CONFIG_ARCH_TEGRA_114_SOC
1320const struct clk_ops tegra_clk_pllxc_ops = {
1321 .is_enabled = clk_pll_is_enabled,
1322 .enable = clk_pll_iddq_enable,
1323 .disable = clk_pll_iddq_disable,
1324 .recalc_rate = clk_pll_recalc_rate,
1325 .round_rate = clk_pll_ramp_round_rate,
1326 .set_rate = clk_pllxc_set_rate,
1327};
1328
1329const struct clk_ops tegra_clk_pllm_ops = {
1330 .is_enabled = clk_pll_is_enabled,
1331 .enable = clk_pll_iddq_enable,
1332 .disable = clk_pll_iddq_disable,
1333 .recalc_rate = clk_pll_recalc_rate,
1334 .round_rate = clk_pll_ramp_round_rate,
1335 .set_rate = clk_pllm_set_rate,
1336};
1337
1338const struct clk_ops tegra_clk_pllc_ops = {
1339 .is_enabled = clk_pll_is_enabled,
1340 .enable = clk_pllc_enable,
1341 .disable = clk_pllc_disable,
1342 .recalc_rate = clk_pll_recalc_rate,
1343 .round_rate = clk_pll_ramp_round_rate,
1344 .set_rate = clk_pllc_set_rate,
1345};
1346
1347const struct clk_ops tegra_clk_pllre_ops = {
1348 .is_enabled = clk_pll_is_enabled,
1349 .enable = clk_pll_iddq_enable,
1350 .disable = clk_pll_iddq_disable,
1351 .recalc_rate = clk_pllre_recalc_rate,
1352 .round_rate = clk_pllre_round_rate,
1353 .set_rate = clk_pllre_set_rate,
1354};
1355
1356const struct clk_ops tegra_clk_plle_tegra114_ops = {
1357 .is_enabled = clk_pll_is_enabled,
1358 .enable = clk_plle_tegra114_enable,
1359 .disable = clk_plle_tegra114_disable,
1360 .recalc_rate = clk_pll_recalc_rate,
1361};
1362
1363
1364struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1365 void __iomem *clk_base, void __iomem *pmc,
1366 unsigned long flags, unsigned long fixed_rate,
1367 struct tegra_clk_pll_params *pll_params,
1368 u32 pll_flags,
1369 struct tegra_clk_pll_freq_table *freq_table,
1370 spinlock_t *lock)
1371{
1372 struct tegra_clk_pll *pll;
1373 struct clk *clk;
1374
1375 if (!pll_params->pdiv_tohw)
1376 return ERR_PTR(-EINVAL);
1377
1378 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1379 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1380 freq_table, lock);
1381 if (IS_ERR(pll))
1382 return ERR_CAST(pll);
1383
1384 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1385 &tegra_clk_pllxc_ops);
1386 if (IS_ERR(clk))
1387 kfree(pll);
1388
1389 return clk;
1390}
1391
1392struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1393 void __iomem *clk_base, void __iomem *pmc,
1394 unsigned long flags, unsigned long fixed_rate,
1395 struct tegra_clk_pll_params *pll_params,
1396 u32 pll_flags,
1397 struct tegra_clk_pll_freq_table *freq_table,
1398 spinlock_t *lock, unsigned long parent_rate)
1399{
1400 u32 val;
1401 struct tegra_clk_pll *pll;
1402 struct clk *clk;
1403
1404 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1405 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1406 freq_table, lock);
1407 if (IS_ERR(pll))
1408 return ERR_CAST(pll);
1409
1410 /* program minimum rate by default */
1411
1412 val = pll_readl_base(pll);
1413 if (val & PLL_BASE_ENABLE)
1414 WARN_ON(val & pll_params->iddq_bit_idx);
1415 else {
1416 int m;
1417
1418 m = _pll_fixed_mdiv(pll_params, parent_rate);
1419 val = m << PLL_BASE_DIVM_SHIFT;
1420 val |= (pll_params->vco_min / parent_rate)
1421 << PLL_BASE_DIVN_SHIFT;
1422 pll_writel_base(val, pll);
1423 }
1424
1425 /* disable lock override */
1426
1427 val = pll_readl_misc(pll);
1428 val &= ~BIT(29);
1429 pll_writel_misc(val, pll);
1430
1431 pll_flags |= TEGRA_PLL_LOCK_MISC;
1432 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1433 &tegra_clk_pllre_ops);
1434 if (IS_ERR(clk))
1435 kfree(pll);
1436
1437 return clk;
1438}
1439
1440struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1441 void __iomem *clk_base, void __iomem *pmc,
1442 unsigned long flags, unsigned long fixed_rate,
1443 struct tegra_clk_pll_params *pll_params,
1444 u32 pll_flags,
1445 struct tegra_clk_pll_freq_table *freq_table,
1446 spinlock_t *lock)
1447{
1448 struct tegra_clk_pll *pll;
1449 struct clk *clk;
1450
1451 if (!pll_params->pdiv_tohw)
1452 return ERR_PTR(-EINVAL);
1453
1454 pll_flags |= TEGRA_PLL_BYPASS;
1455 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1456 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1457 freq_table, lock);
1458 if (IS_ERR(pll))
1459 return ERR_CAST(pll);
1460
1461 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1462 &tegra_clk_pllm_ops);
1463 if (IS_ERR(clk))
1464 kfree(pll);
1465
1466 return clk;
1467}
1468
1469struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1470 void __iomem *clk_base, void __iomem *pmc,
1471 unsigned long flags, unsigned long fixed_rate,
1472 struct tegra_clk_pll_params *pll_params,
1473 u32 pll_flags,
1474 struct tegra_clk_pll_freq_table *freq_table,
1475 spinlock_t *lock)
1476{
1477 struct clk *parent, *clk;
1478 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1479 struct tegra_clk_pll *pll;
1480 struct tegra_clk_pll_freq_table cfg;
1481 unsigned long parent_rate;
1482
1483 if (!p_tohw)
1484 return ERR_PTR(-EINVAL);
1485
1486 parent = __clk_lookup(parent_name);
1487 if (IS_ERR(parent)) {
1488 WARN(1, "parent clk %s of %s must be registered first\n",
1489 name, parent_name);
1490 return ERR_PTR(-EINVAL);
1491 }
1492
1493 pll_flags |= TEGRA_PLL_BYPASS;
1494 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1495 freq_table, lock);
1496 if (IS_ERR(pll))
1497 return ERR_CAST(pll);
1498
1499 parent_rate = __clk_get_rate(parent);
1500
1501 /*
1502 * Most of PLLC register fields are shadowed, and can not be read
1503 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1504 * Initialize PLL to default state: disabled, reset; shadow registers
1505 * loaded with default parameters; dividers are preset for half of
1506 * minimum VCO rate (the latter assured that shadowed divider settings
1507 * are within supported range).
1508 */
1509
1510 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1511 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1512
1513 while (p_tohw->pdiv) {
1514 if (p_tohw->pdiv == 2) {
1515 cfg.p = p_tohw->hw_val;
1516 break;
1517 }
1518 p_tohw++;
1519 }
1520
1521 if (!p_tohw->pdiv) {
1522 WARN_ON(1);
1523 return ERR_PTR(-EINVAL);
1524 }
1525
1526 pll_writel_base(0, pll);
1527 _update_pll_mnp(pll, &cfg);
1528
1529 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1530 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1531 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1532 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1533
1534 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1535
1536 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1537 &tegra_clk_pllc_ops);
1538 if (IS_ERR(clk))
1539 kfree(pll);
1540
1541 return clk;
1542}
1543
1544struct clk *tegra_clk_register_plle_tegra114(const char *name,
1545 const char *parent_name,
1546 void __iomem *clk_base, unsigned long flags,
1547 unsigned long fixed_rate,
1548 struct tegra_clk_pll_params *pll_params,
1549 struct tegra_clk_pll_freq_table *freq_table,
1550 spinlock_t *lock)
1551{
1552 struct tegra_clk_pll *pll;
1553 struct clk *clk;
1554 u32 val, val_aux;
1555
1556 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1557 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1558 if (IS_ERR(pll))
1559 return ERR_CAST(pll);
1560
1561 /* ensure parent is set to pll_re_vco */
1562
1563 val = pll_readl_base(pll);
1564 val_aux = pll_readl(pll_params->aux_reg, pll);
1565
1566 if (val & PLL_BASE_ENABLE) {
1567 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1568 WARN(1, "pll_e enabled with unsupported parent %s\n",
1569 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1570 } else {
1571 val_aux |= PLLE_AUX_PLLRE_SEL;
1572 pll_writel(val, pll_params->aux_reg, pll);
1573 }
1574
1575 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1576 &tegra_clk_plle_tegra114_ops);
1577 if (IS_ERR(clk))
1578 kfree(pll);
1579
1580 return clk;
648} 1581}
1582#endif
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000000000000..d78e16ee161c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2085 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00C
31#define RST_DEVICES_V 0x358
32#define RST_DEVICES_W 0x35C
33#define RST_DEVICES_X 0x28C
34#define RST_DEVICES_SET_L 0x300
35#define RST_DEVICES_CLR_L 0x304
36#define RST_DEVICES_SET_H 0x308
37#define RST_DEVICES_CLR_H 0x30c
38#define RST_DEVICES_SET_U 0x310
39#define RST_DEVICES_CLR_U 0x314
40#define RST_DEVICES_SET_V 0x430
41#define RST_DEVICES_CLR_V 0x434
42#define RST_DEVICES_SET_W 0x438
43#define RST_DEVICES_CLR_W 0x43c
44#define RST_DEVICES_NUM 5
45
46#define CLK_OUT_ENB_L 0x010
47#define CLK_OUT_ENB_H 0x014
48#define CLK_OUT_ENB_U 0x018
49#define CLK_OUT_ENB_V 0x360
50#define CLK_OUT_ENB_W 0x364
51#define CLK_OUT_ENB_X 0x280
52#define CLK_OUT_ENB_SET_L 0x320
53#define CLK_OUT_ENB_CLR_L 0x324
54#define CLK_OUT_ENB_SET_H 0x328
55#define CLK_OUT_ENB_CLR_H 0x32c
56#define CLK_OUT_ENB_SET_U 0x330
57#define CLK_OUT_ENB_CLR_U 0x334
58#define CLK_OUT_ENB_SET_V 0x440
59#define CLK_OUT_ENB_CLR_V 0x444
60#define CLK_OUT_ENB_SET_W 0x448
61#define CLK_OUT_ENB_CLR_W 0x44c
62#define CLK_OUT_ENB_SET_X 0x284
63#define CLK_OUT_ENB_CLR_X 0x288
64#define CLK_OUT_ENB_NUM 6
65
66#define PLLC_BASE 0x80
67#define PLLC_MISC2 0x88
68#define PLLC_MISC 0x8c
69#define PLLC2_BASE 0x4e8
70#define PLLC2_MISC 0x4ec
71#define PLLC3_BASE 0x4fc
72#define PLLC3_MISC 0x500
73#define PLLM_BASE 0x90
74#define PLLM_MISC 0x9c
75#define PLLP_BASE 0xa0
76#define PLLP_MISC 0xac
77#define PLLX_BASE 0xe0
78#define PLLX_MISC 0xe4
79#define PLLX_MISC2 0x514
80#define PLLX_MISC3 0x518
81#define PLLD_BASE 0xd0
82#define PLLD_MISC 0xdc
83#define PLLD2_BASE 0x4b8
84#define PLLD2_MISC 0x4bc
85#define PLLE_BASE 0xe8
86#define PLLE_MISC 0xec
87#define PLLA_BASE 0xb0
88#define PLLA_MISC 0xbc
89#define PLLU_BASE 0xc0
90#define PLLU_MISC 0xcc
91#define PLLRE_BASE 0x4c4
92#define PLLRE_MISC 0x4c8
93
94#define PLL_MISC_LOCK_ENABLE 18
95#define PLLC_MISC_LOCK_ENABLE 24
96#define PLLDU_MISC_LOCK_ENABLE 22
97#define PLLE_MISC_LOCK_ENABLE 9
98#define PLLRE_MISC_LOCK_ENABLE 30
99
100#define PLLC_IDDQ_BIT 26
101#define PLLX_IDDQ_BIT 3
102#define PLLRE_IDDQ_BIT 16
103
104#define PLL_BASE_LOCK BIT(27)
105#define PLLE_MISC_LOCK BIT(11)
106#define PLLRE_MISC_LOCK BIT(24)
107#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
108
109#define PLLE_AUX 0x48c
110#define PLLC_OUT 0x84
111#define PLLM_OUT 0x94
112#define PLLP_OUTA 0xa4
113#define PLLP_OUTB 0xa8
114#define PLLA_OUT 0xb4
115
116#define AUDIO_SYNC_CLK_I2S0 0x4a0
117#define AUDIO_SYNC_CLK_I2S1 0x4a4
118#define AUDIO_SYNC_CLK_I2S2 0x4a8
119#define AUDIO_SYNC_CLK_I2S3 0x4ac
120#define AUDIO_SYNC_CLK_I2S4 0x4b0
121#define AUDIO_SYNC_CLK_SPDIF 0x4b4
122
123#define AUDIO_SYNC_DOUBLER 0x49c
124
125#define PMC_CLK_OUT_CNTRL 0x1a8
126#define PMC_DPD_PADS_ORIDE 0x1c
127#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
128#define PMC_CTRL 0
129#define PMC_CTRL_BLINK_ENB 7
130
131#define OSC_CTRL 0x50
132#define OSC_CTRL_OSC_FREQ_SHIFT 28
133#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
134
135#define PLLXC_SW_MAX_P 6
136
137#define CCLKG_BURST_POLICY 0x368
138#define CCLKLP_BURST_POLICY 0x370
139#define SCLK_BURST_POLICY 0x028
140#define SYSTEM_CLK_RATE 0x030
141
142#define UTMIP_PLL_CFG2 0x488
143#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
144#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
145#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
146#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
147#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
148
149#define UTMIP_PLL_CFG1 0x484
150#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
151#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
152#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
153#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
154#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
155#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
156#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
157
158#define UTMIPLL_HW_PWRDN_CFG0 0x52c
159#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
160#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
161#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
162#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
163#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
164#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
165#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
166#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
167
168#define CLK_SOURCE_I2S0 0x1d8
169#define CLK_SOURCE_I2S1 0x100
170#define CLK_SOURCE_I2S2 0x104
171#define CLK_SOURCE_NDFLASH 0x160
172#define CLK_SOURCE_I2S3 0x3bc
173#define CLK_SOURCE_I2S4 0x3c0
174#define CLK_SOURCE_SPDIF_OUT 0x108
175#define CLK_SOURCE_SPDIF_IN 0x10c
176#define CLK_SOURCE_PWM 0x110
177#define CLK_SOURCE_ADX 0x638
178#define CLK_SOURCE_AMX 0x63c
179#define CLK_SOURCE_HDA 0x428
180#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
181#define CLK_SOURCE_SBC1 0x134
182#define CLK_SOURCE_SBC2 0x118
183#define CLK_SOURCE_SBC3 0x11c
184#define CLK_SOURCE_SBC4 0x1b4
185#define CLK_SOURCE_SBC5 0x3c8
186#define CLK_SOURCE_SBC6 0x3cc
187#define CLK_SOURCE_SATA_OOB 0x420
188#define CLK_SOURCE_SATA 0x424
189#define CLK_SOURCE_NDSPEED 0x3f8
190#define CLK_SOURCE_VFIR 0x168
191#define CLK_SOURCE_SDMMC1 0x150
192#define CLK_SOURCE_SDMMC2 0x154
193#define CLK_SOURCE_SDMMC3 0x1bc
194#define CLK_SOURCE_SDMMC4 0x164
195#define CLK_SOURCE_VDE 0x1c8
196#define CLK_SOURCE_CSITE 0x1d4
197#define CLK_SOURCE_LA 0x1f8
198#define CLK_SOURCE_TRACE 0x634
199#define CLK_SOURCE_OWR 0x1cc
200#define CLK_SOURCE_NOR 0x1d0
201#define CLK_SOURCE_MIPI 0x174
202#define CLK_SOURCE_I2C1 0x124
203#define CLK_SOURCE_I2C2 0x198
204#define CLK_SOURCE_I2C3 0x1b8
205#define CLK_SOURCE_I2C4 0x3c4
206#define CLK_SOURCE_I2C5 0x128
207#define CLK_SOURCE_UARTA 0x178
208#define CLK_SOURCE_UARTB 0x17c
209#define CLK_SOURCE_UARTC 0x1a0
210#define CLK_SOURCE_UARTD 0x1c0
211#define CLK_SOURCE_UARTE 0x1c4
212#define CLK_SOURCE_UARTA_DBG 0x178
213#define CLK_SOURCE_UARTB_DBG 0x17c
214#define CLK_SOURCE_UARTC_DBG 0x1a0
215#define CLK_SOURCE_UARTD_DBG 0x1c0
216#define CLK_SOURCE_UARTE_DBG 0x1c4
217#define CLK_SOURCE_3D 0x158
218#define CLK_SOURCE_2D 0x15c
219#define CLK_SOURCE_VI_SENSOR 0x1a8
220#define CLK_SOURCE_VI 0x148
221#define CLK_SOURCE_EPP 0x16c
222#define CLK_SOURCE_MSENC 0x1f0
223#define CLK_SOURCE_TSEC 0x1f4
224#define CLK_SOURCE_HOST1X 0x180
225#define CLK_SOURCE_HDMI 0x18c
226#define CLK_SOURCE_DISP1 0x138
227#define CLK_SOURCE_DISP2 0x13c
228#define CLK_SOURCE_CILAB 0x614
229#define CLK_SOURCE_CILCD 0x618
230#define CLK_SOURCE_CILE 0x61c
231#define CLK_SOURCE_DSIALP 0x620
232#define CLK_SOURCE_DSIBLP 0x624
233#define CLK_SOURCE_TSENSOR 0x3b8
234#define CLK_SOURCE_D_AUDIO 0x3d0
235#define CLK_SOURCE_DAM0 0x3d8
236#define CLK_SOURCE_DAM1 0x3dc
237#define CLK_SOURCE_DAM2 0x3e0
238#define CLK_SOURCE_ACTMON 0x3e8
239#define CLK_SOURCE_EXTERN1 0x3ec
240#define CLK_SOURCE_EXTERN2 0x3f0
241#define CLK_SOURCE_EXTERN3 0x3f4
242#define CLK_SOURCE_I2CSLOW 0x3fc
243#define CLK_SOURCE_SE 0x42c
244#define CLK_SOURCE_MSELECT 0x3b4
245#define CLK_SOURCE_SOC_THERM 0x644
246#define CLK_SOURCE_XUSB_HOST_SRC 0x600
247#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
248#define CLK_SOURCE_XUSB_FS_SRC 0x608
249#define CLK_SOURCE_XUSB_SS_SRC 0x610
250#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
251#define CLK_SOURCE_EMC 0x19c
252
253static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
254
255static void __iomem *clk_base;
256static void __iomem *pmc_base;
257
258static DEFINE_SPINLOCK(pll_d_lock);
259static DEFINE_SPINLOCK(pll_d2_lock);
260static DEFINE_SPINLOCK(pll_u_lock);
261static DEFINE_SPINLOCK(pll_div_lock);
262static DEFINE_SPINLOCK(pll_re_lock);
263static DEFINE_SPINLOCK(clk_doubler_lock);
264static DEFINE_SPINLOCK(clk_out_lock);
265static DEFINE_SPINLOCK(sysrate_lock);
266
267static struct pdiv_map pllxc_p[] = {
268 { .pdiv = 1, .hw_val = 0 },
269 { .pdiv = 2, .hw_val = 1 },
270 { .pdiv = 3, .hw_val = 2 },
271 { .pdiv = 4, .hw_val = 3 },
272 { .pdiv = 5, .hw_val = 4 },
273 { .pdiv = 6, .hw_val = 5 },
274 { .pdiv = 8, .hw_val = 6 },
275 { .pdiv = 10, .hw_val = 7 },
276 { .pdiv = 12, .hw_val = 8 },
277 { .pdiv = 16, .hw_val = 9 },
278 { .pdiv = 12, .hw_val = 10 },
279 { .pdiv = 16, .hw_val = 11 },
280 { .pdiv = 20, .hw_val = 12 },
281 { .pdiv = 24, .hw_val = 13 },
282 { .pdiv = 32, .hw_val = 14 },
283 { .pdiv = 0, .hw_val = 0 },
284};
285
286static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
287 { 12000000, 624000000, 104, 0, 2},
288 { 12000000, 600000000, 100, 0, 2},
289 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
290 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
291 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
292 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
293 { 0, 0, 0, 0, 0, 0 },
294};
295
296static struct tegra_clk_pll_params pll_c_params = {
297 .input_min = 12000000,
298 .input_max = 800000000,
299 .cf_min = 12000000,
300 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
301 .vco_min = 600000000,
302 .vco_max = 1400000000,
303 .base_reg = PLLC_BASE,
304 .misc_reg = PLLC_MISC,
305 .lock_mask = PLL_BASE_LOCK,
306 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
307 .lock_delay = 300,
308 .iddq_reg = PLLC_MISC,
309 .iddq_bit_idx = PLLC_IDDQ_BIT,
310 .max_p = PLLXC_SW_MAX_P,
311 .dyn_ramp_reg = PLLC_MISC2,
312 .stepa_shift = 17,
313 .stepb_shift = 9,
314 .pdiv_tohw = pllxc_p,
315};
316
317static struct pdiv_map pllc_p[] = {
318 { .pdiv = 1, .hw_val = 0 },
319 { .pdiv = 2, .hw_val = 1 },
320 { .pdiv = 4, .hw_val = 3 },
321 { .pdiv = 8, .hw_val = 5 },
322 { .pdiv = 16, .hw_val = 7 },
323 { .pdiv = 0, .hw_val = 0 },
324};
325
326static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
327 {12000000, 600000000, 100, 0, 2},
328 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
329 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
330 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
331 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
332 {0, 0, 0, 0, 0, 0},
333};
334
335static struct tegra_clk_pll_params pll_c2_params = {
336 .input_min = 12000000,
337 .input_max = 48000000,
338 .cf_min = 12000000,
339 .cf_max = 19200000,
340 .vco_min = 600000000,
341 .vco_max = 1200000000,
342 .base_reg = PLLC2_BASE,
343 .misc_reg = PLLC2_MISC,
344 .lock_mask = PLL_BASE_LOCK,
345 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
346 .lock_delay = 300,
347 .pdiv_tohw = pllc_p,
348 .ext_misc_reg[0] = 0x4f0,
349 .ext_misc_reg[1] = 0x4f4,
350 .ext_misc_reg[2] = 0x4f8,
351};
352
353static struct tegra_clk_pll_params pll_c3_params = {
354 .input_min = 12000000,
355 .input_max = 48000000,
356 .cf_min = 12000000,
357 .cf_max = 19200000,
358 .vco_min = 600000000,
359 .vco_max = 1200000000,
360 .base_reg = PLLC3_BASE,
361 .misc_reg = PLLC3_MISC,
362 .lock_mask = PLL_BASE_LOCK,
363 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
364 .lock_delay = 300,
365 .pdiv_tohw = pllc_p,
366 .ext_misc_reg[0] = 0x504,
367 .ext_misc_reg[1] = 0x508,
368 .ext_misc_reg[2] = 0x50c,
369};
370
371static struct pdiv_map pllm_p[] = {
372 { .pdiv = 1, .hw_val = 0 },
373 { .pdiv = 2, .hw_val = 1 },
374 { .pdiv = 0, .hw_val = 0 },
375};
376
377static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
378 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
379 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
380 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
381 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
382 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
383 {0, 0, 0, 0, 0, 0},
384};
385
386static struct tegra_clk_pll_params pll_m_params = {
387 .input_min = 12000000,
388 .input_max = 500000000,
389 .cf_min = 12000000,
390 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
391 .vco_min = 400000000,
392 .vco_max = 1066000000,
393 .base_reg = PLLM_BASE,
394 .misc_reg = PLLM_MISC,
395 .lock_mask = PLL_BASE_LOCK,
396 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
397 .lock_delay = 300,
398 .max_p = 2,
399 .pdiv_tohw = pllm_p,
400};
401
402static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
403 {12000000, 216000000, 432, 12, 1, 8},
404 {13000000, 216000000, 432, 13, 1, 8},
405 {16800000, 216000000, 360, 14, 1, 8},
406 {19200000, 216000000, 360, 16, 1, 8},
407 {26000000, 216000000, 432, 26, 1, 8},
408 {0, 0, 0, 0, 0, 0},
409};
410
411static struct tegra_clk_pll_params pll_p_params = {
412 .input_min = 2000000,
413 .input_max = 31000000,
414 .cf_min = 1000000,
415 .cf_max = 6000000,
416 .vco_min = 200000000,
417 .vco_max = 700000000,
418 .base_reg = PLLP_BASE,
419 .misc_reg = PLLP_MISC,
420 .lock_mask = PLL_BASE_LOCK,
421 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
422 .lock_delay = 300,
423};
424
425static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
426 {9600000, 282240000, 147, 5, 0, 4},
427 {9600000, 368640000, 192, 5, 0, 4},
428 {9600000, 240000000, 200, 8, 0, 8},
429
430 {28800000, 282240000, 245, 25, 0, 8},
431 {28800000, 368640000, 320, 25, 0, 8},
432 {28800000, 240000000, 200, 24, 0, 8},
433 {0, 0, 0, 0, 0, 0},
434};
435
436
437static struct tegra_clk_pll_params pll_a_params = {
438 .input_min = 2000000,
439 .input_max = 31000000,
440 .cf_min = 1000000,
441 .cf_max = 6000000,
442 .vco_min = 200000000,
443 .vco_max = 700000000,
444 .base_reg = PLLA_BASE,
445 .misc_reg = PLLA_MISC,
446 .lock_mask = PLL_BASE_LOCK,
447 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
448 .lock_delay = 300,
449};
450
451static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
452 {12000000, 216000000, 864, 12, 2, 12},
453 {13000000, 216000000, 864, 13, 2, 12},
454 {16800000, 216000000, 720, 14, 2, 12},
455 {19200000, 216000000, 720, 16, 2, 12},
456 {26000000, 216000000, 864, 26, 2, 12},
457
458 {12000000, 594000000, 594, 12, 0, 12},
459 {13000000, 594000000, 594, 13, 0, 12},
460 {16800000, 594000000, 495, 14, 0, 12},
461 {19200000, 594000000, 495, 16, 0, 12},
462 {26000000, 594000000, 594, 26, 0, 12},
463
464 {12000000, 1000000000, 1000, 12, 0, 12},
465 {13000000, 1000000000, 1000, 13, 0, 12},
466 {19200000, 1000000000, 625, 12, 0, 12},
467 {26000000, 1000000000, 1000, 26, 0, 12},
468
469 {0, 0, 0, 0, 0, 0},
470};
471
472static struct tegra_clk_pll_params pll_d_params = {
473 .input_min = 2000000,
474 .input_max = 40000000,
475 .cf_min = 1000000,
476 .cf_max = 6000000,
477 .vco_min = 500000000,
478 .vco_max = 1000000000,
479 .base_reg = PLLD_BASE,
480 .misc_reg = PLLD_MISC,
481 .lock_mask = PLL_BASE_LOCK,
482 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
483 .lock_delay = 1000,
484};
485
486static struct tegra_clk_pll_params pll_d2_params = {
487 .input_min = 2000000,
488 .input_max = 40000000,
489 .cf_min = 1000000,
490 .cf_max = 6000000,
491 .vco_min = 500000000,
492 .vco_max = 1000000000,
493 .base_reg = PLLD2_BASE,
494 .misc_reg = PLLD2_MISC,
495 .lock_mask = PLL_BASE_LOCK,
496 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
497 .lock_delay = 1000,
498};
499
500static struct pdiv_map pllu_p[] = {
501 { .pdiv = 1, .hw_val = 1 },
502 { .pdiv = 2, .hw_val = 0 },
503 { .pdiv = 0, .hw_val = 0 },
504};
505
506static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
507 {12000000, 480000000, 960, 12, 0, 12},
508 {13000000, 480000000, 960, 13, 0, 12},
509 {16800000, 480000000, 400, 7, 0, 5},
510 {19200000, 480000000, 200, 4, 0, 3},
511 {26000000, 480000000, 960, 26, 0, 12},
512 {0, 0, 0, 0, 0, 0},
513};
514
515static struct tegra_clk_pll_params pll_u_params = {
516 .input_min = 2000000,
517 .input_max = 40000000,
518 .cf_min = 1000000,
519 .cf_max = 6000000,
520 .vco_min = 480000000,
521 .vco_max = 960000000,
522 .base_reg = PLLU_BASE,
523 .misc_reg = PLLU_MISC,
524 .lock_mask = PLL_BASE_LOCK,
525 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
526 .lock_delay = 1000,
527 .pdiv_tohw = pllu_p,
528};
529
530static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
531 /* 1 GHz */
532 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
533 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
534 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
535 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
536 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
537
538 {0, 0, 0, 0, 0, 0},
539};
540
541static struct tegra_clk_pll_params pll_x_params = {
542 .input_min = 12000000,
543 .input_max = 800000000,
544 .cf_min = 12000000,
545 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
546 .vco_min = 700000000,
547 .vco_max = 2400000000U,
548 .base_reg = PLLX_BASE,
549 .misc_reg = PLLX_MISC,
550 .lock_mask = PLL_BASE_LOCK,
551 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
552 .lock_delay = 300,
553 .iddq_reg = PLLX_MISC3,
554 .iddq_bit_idx = PLLX_IDDQ_BIT,
555 .max_p = PLLXC_SW_MAX_P,
556 .dyn_ramp_reg = PLLX_MISC2,
557 .stepa_shift = 16,
558 .stepb_shift = 24,
559 .pdiv_tohw = pllxc_p,
560};
561
562static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
563 /* PLLE special case: use cpcon field to store cml divider value */
564 {336000000, 100000000, 100, 21, 16, 11},
565 {312000000, 100000000, 200, 26, 24, 13},
566 {0, 0, 0, 0, 0, 0},
567};
568
569static struct tegra_clk_pll_params pll_e_params = {
570 .input_min = 12000000,
571 .input_max = 1000000000,
572 .cf_min = 12000000,
573 .cf_max = 75000000,
574 .vco_min = 1600000000,
575 .vco_max = 2400000000U,
576 .base_reg = PLLE_BASE,
577 .misc_reg = PLLE_MISC,
578 .aux_reg = PLLE_AUX,
579 .lock_mask = PLLE_MISC_LOCK,
580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
581 .lock_delay = 300,
582};
583
584static struct tegra_clk_pll_params pll_re_vco_params = {
585 .input_min = 12000000,
586 .input_max = 1000000000,
587 .cf_min = 12000000,
588 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
589 .vco_min = 300000000,
590 .vco_max = 600000000,
591 .base_reg = PLLRE_BASE,
592 .misc_reg = PLLRE_MISC,
593 .lock_mask = PLLRE_MISC_LOCK,
594 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
595 .lock_delay = 300,
596 .iddq_reg = PLLRE_MISC,
597 .iddq_bit_idx = PLLRE_IDDQ_BIT,
598};
599
600/* Peripheral clock registers */
601
602static struct tegra_clk_periph_regs periph_l_regs = {
603 .enb_reg = CLK_OUT_ENB_L,
604 .enb_set_reg = CLK_OUT_ENB_SET_L,
605 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
606 .rst_reg = RST_DEVICES_L,
607 .rst_set_reg = RST_DEVICES_SET_L,
608 .rst_clr_reg = RST_DEVICES_CLR_L,
609};
610
611static struct tegra_clk_periph_regs periph_h_regs = {
612 .enb_reg = CLK_OUT_ENB_H,
613 .enb_set_reg = CLK_OUT_ENB_SET_H,
614 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
615 .rst_reg = RST_DEVICES_H,
616 .rst_set_reg = RST_DEVICES_SET_H,
617 .rst_clr_reg = RST_DEVICES_CLR_H,
618};
619
620static struct tegra_clk_periph_regs periph_u_regs = {
621 .enb_reg = CLK_OUT_ENB_U,
622 .enb_set_reg = CLK_OUT_ENB_SET_U,
623 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
624 .rst_reg = RST_DEVICES_U,
625 .rst_set_reg = RST_DEVICES_SET_U,
626 .rst_clr_reg = RST_DEVICES_CLR_U,
627};
628
629static struct tegra_clk_periph_regs periph_v_regs = {
630 .enb_reg = CLK_OUT_ENB_V,
631 .enb_set_reg = CLK_OUT_ENB_SET_V,
632 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
633 .rst_reg = RST_DEVICES_V,
634 .rst_set_reg = RST_DEVICES_SET_V,
635 .rst_clr_reg = RST_DEVICES_CLR_V,
636};
637
638static struct tegra_clk_periph_regs periph_w_regs = {
639 .enb_reg = CLK_OUT_ENB_W,
640 .enb_set_reg = CLK_OUT_ENB_SET_W,
641 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
642 .rst_reg = RST_DEVICES_W,
643 .rst_set_reg = RST_DEVICES_SET_W,
644 .rst_clr_reg = RST_DEVICES_CLR_W,
645};
646
647/* possible OSC frequencies in Hz */
648static unsigned long tegra114_input_freq[] = {
649 [0] = 13000000,
650 [1] = 16800000,
651 [4] = 19200000,
652 [5] = 38400000,
653 [8] = 12000000,
654 [9] = 48000000,
655 [12] = 260000000,
656};
657
658#define MASK(x) (BIT(x) - 1)
659
660#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
661 _clk_num, _regs, _gate_flags, _clk_id) \
662 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
663 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
664 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
665 _parents##_idx, 0)
666
667#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
668 _clk_num, _regs, _gate_flags, _clk_id, flags)\
669 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
670 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
671 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
672 _parents##_idx, flags)
673
674#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
675 _clk_num, _regs, _gate_flags, _clk_id) \
676 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
677 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
678 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
679 _parents##_idx, 0)
680
681#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
682 _clk_num, _regs, _gate_flags, _clk_id) \
683 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
684 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
685 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
686 _clk_id, _parents##_idx, 0)
687
688#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
689 _clk_num, _regs, _gate_flags, _clk_id, flags)\
690 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
691 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
692 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
693 _clk_id, _parents##_idx, flags)
694
695#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
696 _clk_num, _regs, _gate_flags, _clk_id) \
697 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
698 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
699 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
700 _clk_id, _parents##_idx, 0)
701
702#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
703 _clk_num, _regs, _clk_id) \
704 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
705 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
706 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
707 _parents##_idx, 0)
708
709#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
710 _clk_num, _regs, _clk_id) \
711 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
712 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
713 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
714
715#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
716 _mux_shift, _mux_mask, _clk_num, _regs, \
717 _gate_flags, _clk_id) \
718 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
719 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \
720 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
721 _clk_id, _parents##_idx, 0)
722
723#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
724 _clk_num, _regs, _gate_flags, _clk_id) \
725 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
726 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
727 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
728 _clk_id, _parents##_idx, 0)
729
730#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
731 _regs, _gate_flags, _clk_id) \
732 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
733 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
734 periph_clk_enb_refcnt, _gate_flags , _clk_id, \
735 mux_d_audio_clk_idx, 0)
736
737enum tegra114_clk {
738 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
739 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
740 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
741 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
742 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
743 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
744 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
745 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
746 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
747 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
748 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
749 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
750 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
751 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
752 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
753 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
754 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
755 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
756 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
757 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
758 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
759 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
760 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
761 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
762 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
763 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
764 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
765
766 /* Mux clocks */
767
768 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
769 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
770 dsib_mux, clk_max,
771};
772
773struct utmi_clk_param {
774 /* Oscillator Frequency in KHz */
775 u32 osc_frequency;
776 /* UTMIP PLL Enable Delay Count */
777 u8 enable_delay_count;
778 /* UTMIP PLL Stable count */
779 u8 stable_count;
780 /* UTMIP PLL Active delay count */
781 u8 active_delay_count;
782 /* UTMIP PLL Xtal frequency count */
783 u8 xtal_freq_count;
784};
785
786static const struct utmi_clk_param utmi_parameters[] = {
787 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
788 .stable_count = 0x33, .active_delay_count = 0x05,
789 .xtal_freq_count = 0x7F},
790 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
791 .stable_count = 0x4B, .active_delay_count = 0x06,
792 .xtal_freq_count = 0xBB},
793 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
794 .stable_count = 0x2F, .active_delay_count = 0x04,
795 .xtal_freq_count = 0x76},
796 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
797 .stable_count = 0x66, .active_delay_count = 0x09,
798 .xtal_freq_count = 0xFE},
799 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
800 .stable_count = 0x41, .active_delay_count = 0x0A,
801 .xtal_freq_count = 0xA4},
802};
803
804/* peripheral mux definitions */
805
806#define MUX_I2S_SPDIF(_id) \
807static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
808 #_id, "pll_p",\
809 "clk_m"};
810MUX_I2S_SPDIF(audio0)
811MUX_I2S_SPDIF(audio1)
812MUX_I2S_SPDIF(audio2)
813MUX_I2S_SPDIF(audio3)
814MUX_I2S_SPDIF(audio4)
815MUX_I2S_SPDIF(audio)
816
817#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
818#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
819#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
820#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
821#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
822#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
823
824static const char *mux_pllp_pllc_pllm_clkm[] = {
825 "pll_p", "pll_c", "pll_m", "clk_m"
826};
827#define mux_pllp_pllc_pllm_clkm_idx NULL
828
829static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
830#define mux_pllp_pllc_pllm_idx NULL
831
832static const char *mux_pllp_pllc_clk32_clkm[] = {
833 "pll_p", "pll_c", "clk_32k", "clk_m"
834};
835#define mux_pllp_pllc_clk32_clkm_idx NULL
836
837static const char *mux_plla_pllc_pllp_clkm[] = {
838 "pll_a_out0", "pll_c", "pll_p", "clk_m"
839};
840#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
841
842static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
843 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
844};
845static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
846 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
847};
848
849static const char *mux_pllp_clkm[] = {
850 "pll_p", "clk_m"
851};
852static u32 mux_pllp_clkm_idx[] = {
853 [0] = 0, [1] = 3,
854};
855
856static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
857 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
858};
859#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
860
861static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
862 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
863 "pll_d2_out0", "clk_m"
864};
865#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
866
867static const char *mux_pllm_pllc_pllp_plla[] = {
868 "pll_m", "pll_c", "pll_p", "pll_a_out0"
869};
870#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
871
872static const char *mux_pllp_pllc_clkm[] = {
873 "pll_p", "pll_c", "pll_m"
874};
875static u32 mux_pllp_pllc_clkm_idx[] = {
876 [0] = 0, [1] = 1, [2] = 3,
877};
878
879static const char *mux_pllp_pllc_clkm_clk32[] = {
880 "pll_p", "pll_c", "clk_m", "clk_32k"
881};
882#define mux_pllp_pllc_clkm_clk32_idx NULL
883
884static const char *mux_plla_clk32_pllp_clkm_plle[] = {
885 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
886};
887#define mux_plla_clk32_pllp_clkm_plle_idx NULL
888
889static const char *mux_clkm_pllp_pllc_pllre[] = {
890 "clk_m", "pll_p", "pll_c", "pll_re_out"
891};
892static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
893 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
894};
895
896static const char *mux_clkm_48M_pllp_480M[] = {
897 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
898};
899#define mux_clkm_48M_pllp_480M_idx NULL
900
901static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
902 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
903};
904static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
905 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
906};
907
908static const char *mux_plld_out0_plld2_out0[] = {
909 "pll_d_out0", "pll_d2_out0",
910};
911#define mux_plld_out0_plld2_out0_idx NULL
912
913static const char *mux_d_audio_clk[] = {
914 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
915 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
916};
917static u32 mux_d_audio_clk_idx[] = {
918 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
919 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
920};
921
922static const char *mux_pllmcp_clkm[] = {
923 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
924};
925
926static const struct clk_div_table pll_re_div_table[] = {
927 { .val = 0, .div = 1 },
928 { .val = 1, .div = 2 },
929 { .val = 2, .div = 3 },
930 { .val = 3, .div = 4 },
931 { .val = 4, .div = 5 },
932 { .val = 5, .div = 6 },
933 { .val = 0, .div = 0 },
934};
935
936static struct clk *clks[clk_max];
937static struct clk_onecell_data clk_data;
938
939static unsigned long osc_freq;
940static unsigned long pll_ref_freq;
941
942static int __init tegra114_osc_clk_init(void __iomem *clk_base)
943{
944 struct clk *clk;
945 u32 val, pll_ref_div;
946
947 val = readl_relaxed(clk_base + OSC_CTRL);
948
949 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
950 if (!osc_freq) {
951 WARN_ON(1);
952 return -EINVAL;
953 }
954
955 /* clk_m */
956 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
957 osc_freq);
958 clk_register_clkdev(clk, "clk_m", NULL);
959 clks[clk_m] = clk;
960
961 /* pll_ref */
962 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
963 pll_ref_div = 1 << val;
964 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
965 CLK_SET_RATE_PARENT, 1, pll_ref_div);
966 clk_register_clkdev(clk, "pll_ref", NULL);
967 clks[pll_ref] = clk;
968
969 pll_ref_freq = osc_freq / pll_ref_div;
970
971 return 0;
972}
973
974static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
975{
976 struct clk *clk;
977
978 /* clk_32k */
979 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
980 32768);
981 clk_register_clkdev(clk, "clk_32k", NULL);
982 clks[clk_32k] = clk;
983
984 /* clk_m_div2 */
985 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
986 CLK_SET_RATE_PARENT, 1, 2);
987 clk_register_clkdev(clk, "clk_m_div2", NULL);
988 clks[clk_m_div2] = clk;
989
990 /* clk_m_div4 */
991 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
992 CLK_SET_RATE_PARENT, 1, 4);
993 clk_register_clkdev(clk, "clk_m_div4", NULL);
994 clks[clk_m_div4] = clk;
995
996}
997
998static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
999{
1000 u32 reg;
1001 int i;
1002
1003 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1004 if (osc_freq == utmi_parameters[i].osc_frequency)
1005 break;
1006 }
1007
1008 if (i >= ARRAY_SIZE(utmi_parameters)) {
1009 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1010 osc_freq);
1011 return;
1012 }
1013
1014 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1015
1016 /* Program UTMIP PLL stable and active counts */
1017 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1018 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1019 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1020
1021 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1022
1023 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1024 active_delay_count);
1025
1026 /* Remove power downs from UTMIP PLL control bits */
1027 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1028 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1029 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1030
1031 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1032
1033 /* Program UTMIP PLL delay and oscillator frequency counts */
1034 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1035 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1036
1037 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1038 enable_delay_count);
1039
1040 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1041 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1042 xtal_freq_count);
1043
1044 /* Remove power downs from UTMIP PLL control bits */
1045 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1046 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1047 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1048 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1049 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1050
1051 /* Setup HW control of UTMIPLL */
1052 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1053 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1054 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1055 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1056 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1057
1058 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1059 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1060 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1061 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1062
1063 udelay(1);
1064
1065 /* Setup SW override of UTMIPLL assuming USB2.0
1066 ports are assigned to USB2 */
1067 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1068 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1069 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1070 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1071
1072 udelay(1);
1073
1074 /* Enable HW control UTMIPLL */
1075 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1076 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1077 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1078}
1079
1080static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1081{
1082 pll_params->vco_min =
1083 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1084}
1085
1086static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1087 void __iomem *clk_base)
1088{
1089 u32 val;
1090 u32 step_a, step_b;
1091
1092 switch (pll_ref_freq) {
1093 case 12000000:
1094 case 13000000:
1095 case 26000000:
1096 step_a = 0x2B;
1097 step_b = 0x0B;
1098 break;
1099 case 16800000:
1100 step_a = 0x1A;
1101 step_b = 0x09;
1102 break;
1103 case 19200000:
1104 step_a = 0x12;
1105 step_b = 0x08;
1106 break;
1107 default:
1108 pr_err("%s: Unexpected reference rate %lu\n",
1109 __func__, pll_ref_freq);
1110 WARN_ON(1);
1111 return -EINVAL;
1112 }
1113
1114 val = step_a << pll_params->stepa_shift;
1115 val |= step_b << pll_params->stepb_shift;
1116 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1117
1118 return 0;
1119}
1120
1121static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1122 void __iomem *clk_base)
1123{
1124 u32 val, val_iddq;
1125
1126 val = readl_relaxed(clk_base + pll_params->base_reg);
1127 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1128
1129 if (val & BIT(30))
1130 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1131 else {
1132 val_iddq |= BIT(pll_params->iddq_bit_idx);
1133 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1134 }
1135}
1136
1137static void __init tegra114_pll_init(void __iomem *clk_base,
1138 void __iomem *pmc)
1139{
1140 u32 val;
1141 struct clk *clk;
1142
1143 /* PLLC */
1144 _clip_vco_min(&pll_c_params);
1145 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
1146 _init_iddq(&pll_c_params, clk_base);
1147 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1148 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
1149 pll_c_freq_table, NULL);
1150 clk_register_clkdev(clk, "pll_c", NULL);
1151 clks[pll_c] = clk;
1152
1153 /* PLLC_OUT1 */
1154 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1155 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1156 8, 8, 1, NULL);
1157 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1158 clk_base + PLLC_OUT, 1, 0,
1159 CLK_SET_RATE_PARENT, 0, NULL);
1160 clk_register_clkdev(clk, "pll_c_out1", NULL);
1161 clks[pll_c_out1] = clk;
1162 }
1163
1164 /* PLLC2 */
1165 _clip_vco_min(&pll_c2_params);
1166 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
1167 &pll_c2_params, TEGRA_PLL_USE_LOCK,
1168 pll_cx_freq_table, NULL);
1169 clk_register_clkdev(clk, "pll_c2", NULL);
1170 clks[pll_c2] = clk;
1171
1172 /* PLLC3 */
1173 _clip_vco_min(&pll_c3_params);
1174 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
1175 &pll_c3_params, TEGRA_PLL_USE_LOCK,
1176 pll_cx_freq_table, NULL);
1177 clk_register_clkdev(clk, "pll_c3", NULL);
1178 clks[pll_c3] = clk;
1179
1180 /* PLLP */
1181 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1182 408000000, &pll_p_params,
1183 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1184 pll_p_freq_table, NULL);
1185 clk_register_clkdev(clk, "pll_p", NULL);
1186 clks[pll_p] = clk;
1187
1188 /* PLLP_OUT1 */
1189 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1190 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1191 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1192 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1193 clk_base + PLLP_OUTA, 1, 0,
1194 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1195 &pll_div_lock);
1196 clk_register_clkdev(clk, "pll_p_out1", NULL);
1197 clks[pll_p_out1] = clk;
1198
1199 /* PLLP_OUT2 */
1200 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1201 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1202 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1203 &pll_div_lock);
1204 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1205 clk_base + PLLP_OUTA, 17, 16,
1206 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1207 &pll_div_lock);
1208 clk_register_clkdev(clk, "pll_p_out2", NULL);
1209 clks[pll_p_out2] = clk;
1210
1211 /* PLLP_OUT3 */
1212 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1213 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1214 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1215 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1216 clk_base + PLLP_OUTB, 1, 0,
1217 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1218 &pll_div_lock);
1219 clk_register_clkdev(clk, "pll_p_out3", NULL);
1220 clks[pll_p_out3] = clk;
1221
1222 /* PLLP_OUT4 */
1223 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1224 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1225 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1226 &pll_div_lock);
1227 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1228 clk_base + PLLP_OUTB, 17, 16,
1229 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1230 &pll_div_lock);
1231 clk_register_clkdev(clk, "pll_p_out4", NULL);
1232 clks[pll_p_out4] = clk;
1233
1234 /* PLLM */
1235 _clip_vco_min(&pll_m_params);
1236 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1237 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
1238 &pll_m_params, TEGRA_PLL_USE_LOCK,
1239 pll_m_freq_table, NULL);
1240 clk_register_clkdev(clk, "pll_m", NULL);
1241 clks[pll_m] = clk;
1242
1243 /* PLLM_OUT1 */
1244 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1245 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1246 8, 8, 1, NULL);
1247 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1248 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1249 CLK_SET_RATE_PARENT, 0, NULL);
1250 clk_register_clkdev(clk, "pll_m_out1", NULL);
1251 clks[pll_m_out1] = clk;
1252
1253 /* PLLM_UD */
1254 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1255 CLK_SET_RATE_PARENT, 1, 1);
1256
1257 /* PLLX */
1258 _clip_vco_min(&pll_x_params);
1259 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1260 _init_iddq(&pll_x_params, clk_base);
1261 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1262 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1263 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1264 clk_register_clkdev(clk, "pll_x", NULL);
1265 clks[pll_x] = clk;
1266 }
1267
1268 /* PLLX_OUT0 */
1269 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1270 CLK_SET_RATE_PARENT, 1, 2);
1271 clk_register_clkdev(clk, "pll_x_out0", NULL);
1272 clks[pll_x_out0] = clk;
1273
1274 /* PLLU */
1275 val = readl(clk_base + pll_u_params.base_reg);
1276 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1277 writel(val, clk_base + pll_u_params.base_reg);
1278
1279 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1280 0, &pll_u_params, TEGRA_PLLU |
1281 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1282 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1283 clk_register_clkdev(clk, "pll_u", NULL);
1284 clks[pll_u] = clk;
1285
1286 tegra114_utmi_param_configure(clk_base);
1287
1288 /* PLLU_480M */
1289 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1290 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1291 22, 0, &pll_u_lock);
1292 clk_register_clkdev(clk, "pll_u_480M", NULL);
1293 clks[pll_u_480M] = clk;
1294
1295 /* PLLU_60M */
1296 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1297 CLK_SET_RATE_PARENT, 1, 8);
1298 clk_register_clkdev(clk, "pll_u_60M", NULL);
1299 clks[pll_u_60M] = clk;
1300
1301 /* PLLU_48M */
1302 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1303 CLK_SET_RATE_PARENT, 1, 10);
1304 clk_register_clkdev(clk, "pll_u_48M", NULL);
1305 clks[pll_u_48M] = clk;
1306
1307 /* PLLU_12M */
1308 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1309 CLK_SET_RATE_PARENT, 1, 40);
1310 clk_register_clkdev(clk, "pll_u_12M", NULL);
1311 clks[pll_u_12M] = clk;
1312
1313 /* PLLD */
1314 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1315 0, &pll_d_params,
1316 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1317 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1318 clk_register_clkdev(clk, "pll_d", NULL);
1319 clks[pll_d] = clk;
1320
1321 /* PLLD_OUT0 */
1322 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1323 CLK_SET_RATE_PARENT, 1, 2);
1324 clk_register_clkdev(clk, "pll_d_out0", NULL);
1325 clks[pll_d_out0] = clk;
1326
1327 /* PLLD2 */
1328 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1329 0, &pll_d2_params,
1330 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1331 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1332 clk_register_clkdev(clk, "pll_d2", NULL);
1333 clks[pll_d2] = clk;
1334
1335 /* PLLD2_OUT0 */
1336 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1337 CLK_SET_RATE_PARENT, 1, 2);
1338 clk_register_clkdev(clk, "pll_d2_out0", NULL);
1339 clks[pll_d2_out0] = clk;
1340
1341 /* PLLA */
1342 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1343 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1344 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1345 clk_register_clkdev(clk, "pll_a", NULL);
1346 clks[pll_a] = clk;
1347
1348 /* PLLA_OUT0 */
1349 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1350 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1351 8, 8, 1, NULL);
1352 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1353 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1354 CLK_SET_RATE_PARENT, 0, NULL);
1355 clk_register_clkdev(clk, "pll_a_out0", NULL);
1356 clks[pll_a_out0] = clk;
1357
1358 /* PLLRE */
1359 _clip_vco_min(&pll_re_vco_params);
1360 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1361 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
1362 NULL, &pll_re_lock, pll_ref_freq);
1363 clk_register_clkdev(clk, "pll_re_vco", NULL);
1364 clks[pll_re_vco] = clk;
1365
1366 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1367 clk_base + PLLRE_BASE, 16, 4, 0,
1368 pll_re_div_table, &pll_re_lock);
1369 clk_register_clkdev(clk, "pll_re_out", NULL);
1370 clks[pll_re_out] = clk;
1371
1372 /* PLLE */
1373 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
1374 clk_base, 0, 100000000, &pll_e_params,
1375 pll_e_freq_table, NULL);
1376 clk_register_clkdev(clk, "pll_e_out0", NULL);
1377 clks[pll_e_out0] = clk;
1378}
1379
1380static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1381 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1382};
1383
1384static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1385 "clk_m_div4", "extern1",
1386};
1387
1388static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1389 "clk_m_div4", "extern2",
1390};
1391
1392static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1393 "clk_m_div4", "extern3",
1394};
1395
1396static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1397{
1398 struct clk *clk;
1399
1400 /* spdif_in_sync */
1401 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1402 24000000);
1403 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1404 clks[spdif_in_sync] = clk;
1405
1406 /* i2s0_sync */
1407 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1408 clk_register_clkdev(clk, "i2s0_sync", NULL);
1409 clks[i2s0_sync] = clk;
1410
1411 /* i2s1_sync */
1412 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1413 clk_register_clkdev(clk, "i2s1_sync", NULL);
1414 clks[i2s1_sync] = clk;
1415
1416 /* i2s2_sync */
1417 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1418 clk_register_clkdev(clk, "i2s2_sync", NULL);
1419 clks[i2s2_sync] = clk;
1420
1421 /* i2s3_sync */
1422 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1423 clk_register_clkdev(clk, "i2s3_sync", NULL);
1424 clks[i2s3_sync] = clk;
1425
1426 /* i2s4_sync */
1427 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1428 clk_register_clkdev(clk, "i2s4_sync", NULL);
1429 clks[i2s4_sync] = clk;
1430
1431 /* vimclk_sync */
1432 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1433 clk_register_clkdev(clk, "vimclk_sync", NULL);
1434 clks[vimclk_sync] = clk;
1435
1436 /* audio0 */
1437 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1438 ARRAY_SIZE(mux_audio_sync_clk), 0,
1439 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1440 NULL);
1441 clks[audio0_mux] = clk;
1442 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1443 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1444 CLK_GATE_SET_TO_DISABLE, NULL);
1445 clk_register_clkdev(clk, "audio0", NULL);
1446 clks[audio0] = clk;
1447
1448 /* audio1 */
1449 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1450 ARRAY_SIZE(mux_audio_sync_clk), 0,
1451 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1452 NULL);
1453 clks[audio1_mux] = clk;
1454 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1455 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1456 CLK_GATE_SET_TO_DISABLE, NULL);
1457 clk_register_clkdev(clk, "audio1", NULL);
1458 clks[audio1] = clk;
1459
1460 /* audio2 */
1461 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1462 ARRAY_SIZE(mux_audio_sync_clk), 0,
1463 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1464 NULL);
1465 clks[audio2_mux] = clk;
1466 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1467 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1468 CLK_GATE_SET_TO_DISABLE, NULL);
1469 clk_register_clkdev(clk, "audio2", NULL);
1470 clks[audio2] = clk;
1471
1472 /* audio3 */
1473 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1474 ARRAY_SIZE(mux_audio_sync_clk), 0,
1475 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1476 NULL);
1477 clks[audio3_mux] = clk;
1478 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1479 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1480 CLK_GATE_SET_TO_DISABLE, NULL);
1481 clk_register_clkdev(clk, "audio3", NULL);
1482 clks[audio3] = clk;
1483
1484 /* audio4 */
1485 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1486 ARRAY_SIZE(mux_audio_sync_clk), 0,
1487 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1488 NULL);
1489 clks[audio4_mux] = clk;
1490 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1491 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1492 CLK_GATE_SET_TO_DISABLE, NULL);
1493 clk_register_clkdev(clk, "audio4", NULL);
1494 clks[audio4] = clk;
1495
1496 /* spdif */
1497 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1498 ARRAY_SIZE(mux_audio_sync_clk), 0,
1499 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1500 NULL);
1501 clks[spdif_mux] = clk;
1502 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1503 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1504 CLK_GATE_SET_TO_DISABLE, NULL);
1505 clk_register_clkdev(clk, "spdif", NULL);
1506 clks[spdif] = clk;
1507
1508 /* audio0_2x */
1509 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1510 CLK_SET_RATE_PARENT, 2, 1);
1511 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1512 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1513 0, &clk_doubler_lock);
1514 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1515 TEGRA_PERIPH_NO_RESET, clk_base,
1516 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1517 periph_clk_enb_refcnt);
1518 clk_register_clkdev(clk, "audio0_2x", NULL);
1519 clks[audio0_2x] = clk;
1520
1521 /* audio1_2x */
1522 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1523 CLK_SET_RATE_PARENT, 2, 1);
1524 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1525 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1526 0, &clk_doubler_lock);
1527 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1528 TEGRA_PERIPH_NO_RESET, clk_base,
1529 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1530 periph_clk_enb_refcnt);
1531 clk_register_clkdev(clk, "audio1_2x", NULL);
1532 clks[audio1_2x] = clk;
1533
1534 /* audio2_2x */
1535 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1536 CLK_SET_RATE_PARENT, 2, 1);
1537 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1538 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1539 0, &clk_doubler_lock);
1540 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1541 TEGRA_PERIPH_NO_RESET, clk_base,
1542 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1543 periph_clk_enb_refcnt);
1544 clk_register_clkdev(clk, "audio2_2x", NULL);
1545 clks[audio2_2x] = clk;
1546
1547 /* audio3_2x */
1548 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1549 CLK_SET_RATE_PARENT, 2, 1);
1550 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1551 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1552 0, &clk_doubler_lock);
1553 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1554 TEGRA_PERIPH_NO_RESET, clk_base,
1555 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1556 periph_clk_enb_refcnt);
1557 clk_register_clkdev(clk, "audio3_2x", NULL);
1558 clks[audio3_2x] = clk;
1559
1560 /* audio4_2x */
1561 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1562 CLK_SET_RATE_PARENT, 2, 1);
1563 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1564 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1565 0, &clk_doubler_lock);
1566 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1567 TEGRA_PERIPH_NO_RESET, clk_base,
1568 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1569 periph_clk_enb_refcnt);
1570 clk_register_clkdev(clk, "audio4_2x", NULL);
1571 clks[audio4_2x] = clk;
1572
1573 /* spdif_2x */
1574 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1575 CLK_SET_RATE_PARENT, 2, 1);
1576 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1577 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1578 0, &clk_doubler_lock);
1579 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1580 TEGRA_PERIPH_NO_RESET, clk_base,
1581 CLK_SET_RATE_PARENT, 118,
1582 &periph_v_regs, periph_clk_enb_refcnt);
1583 clk_register_clkdev(clk, "spdif_2x", NULL);
1584 clks[spdif_2x] = clk;
1585}
1586
1587static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1588{
1589 struct clk *clk;
1590
1591 /* clk_out_1 */
1592 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1593 ARRAY_SIZE(clk_out1_parents), 0,
1594 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1595 &clk_out_lock);
1596 clks[clk_out_1_mux] = clk;
1597 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1598 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1599 &clk_out_lock);
1600 clk_register_clkdev(clk, "extern1", "clk_out_1");
1601 clks[clk_out_1] = clk;
1602
1603 /* clk_out_2 */
1604 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1605 ARRAY_SIZE(clk_out1_parents), 0,
1606 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1607 &clk_out_lock);
1608 clks[clk_out_2_mux] = clk;
1609 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1610 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1611 &clk_out_lock);
1612 clk_register_clkdev(clk, "extern2", "clk_out_2");
1613 clks[clk_out_2] = clk;
1614
1615 /* clk_out_3 */
1616 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1617 ARRAY_SIZE(clk_out1_parents), 0,
1618 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1619 &clk_out_lock);
1620 clks[clk_out_3_mux] = clk;
1621 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1622 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1623 &clk_out_lock);
1624 clk_register_clkdev(clk, "extern3", "clk_out_3");
1625 clks[clk_out_3] = clk;
1626
1627 /* blink */
1628 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1629 pmc_base + PMC_DPD_PADS_ORIDE,
1630 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1631 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1632 pmc_base + PMC_CTRL,
1633 PMC_CTRL_BLINK_ENB, 0, NULL);
1634 clk_register_clkdev(clk, "blink", NULL);
1635 clks[blink] = clk;
1636
1637}
1638
1639static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1640 "pll_p_out3", "pll_p_out2", "unused",
1641 "clk_32k", "pll_m_out1" };
1642
1643static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1644 "pll_p", "pll_p_out4", "unused",
1645 "unused", "pll_x" };
1646
1647static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1648 "pll_p", "pll_p_out4", "unused",
1649 "unused", "pll_x", "pll_x_out0" };
1650
1651static void __init tegra114_super_clk_init(void __iomem *clk_base)
1652{
1653 struct clk *clk;
1654
1655 /* CCLKG */
1656 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1657 ARRAY_SIZE(cclk_g_parents),
1658 CLK_SET_RATE_PARENT,
1659 clk_base + CCLKG_BURST_POLICY,
1660 0, 4, 0, 0, NULL);
1661 clk_register_clkdev(clk, "cclk_g", NULL);
1662 clks[cclk_g] = clk;
1663
1664 /* CCLKLP */
1665 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1666 ARRAY_SIZE(cclk_lp_parents),
1667 CLK_SET_RATE_PARENT,
1668 clk_base + CCLKLP_BURST_POLICY,
1669 0, 4, 8, 9, NULL);
1670 clk_register_clkdev(clk, "cclk_lp", NULL);
1671 clks[cclk_lp] = clk;
1672
1673 /* SCLK */
1674 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1675 ARRAY_SIZE(sclk_parents),
1676 CLK_SET_RATE_PARENT,
1677 clk_base + SCLK_BURST_POLICY,
1678 0, 4, 0, 0, NULL);
1679 clk_register_clkdev(clk, "sclk", NULL);
1680 clks[sclk] = clk;
1681
1682 /* HCLK */
1683 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1684 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1685 &sysrate_lock);
1686 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1687 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1688 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1689 clk_register_clkdev(clk, "hclk", NULL);
1690 clks[hclk] = clk;
1691
1692 /* PCLK */
1693 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1694 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1695 &sysrate_lock);
1696 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1697 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1698 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1699 clk_register_clkdev(clk, "pclk", NULL);
1700 clks[pclk] = clk;
1701}
1702
1703static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1704 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1705 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1706 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1707 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1708 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1709 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1710 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1711 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1712 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1713 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1714 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1715 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1716 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1717 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1718 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1719 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1720 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1721 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1722 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1723 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1724 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1725 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1726 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1727 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1728 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1729 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1730 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1731 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1732 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1733 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1734 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1735 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1736 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1737 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1738 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1739 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1740 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1741 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1742 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1743 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1744 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1745 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1746 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1747 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1748 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1749 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1750 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1751 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1752 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1753 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1754 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1755 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1756 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1757 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1758 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1759 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1760 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1761 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1762 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1763 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1764 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1765 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1766 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1767 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1768 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1769 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1770 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1771 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1772 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1773 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1774 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1775 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1776 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1777};
1778
1779static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1780 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1781 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1782};
1783
1784static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1785{
1786 struct tegra_periph_init_data *data;
1787 struct clk *clk;
1788 int i;
1789 u32 val;
1790
1791 /* apbdma */
1792 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1793 0, 34, &periph_h_regs,
1794 periph_clk_enb_refcnt);
1795 clks[apbdma] = clk;
1796
1797 /* rtc */
1798 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1799 TEGRA_PERIPH_ON_APB |
1800 TEGRA_PERIPH_NO_RESET, clk_base,
1801 0, 4, &periph_l_regs,
1802 periph_clk_enb_refcnt);
1803 clk_register_clkdev(clk, NULL, "rtc-tegra");
1804 clks[rtc] = clk;
1805
1806 /* kbc */
1807 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1808 TEGRA_PERIPH_ON_APB |
1809 TEGRA_PERIPH_NO_RESET, clk_base,
1810 0, 36, &periph_h_regs,
1811 periph_clk_enb_refcnt);
1812 clks[kbc] = clk;
1813
1814 /* timer */
1815 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1816 0, 5, &periph_l_regs,
1817 periph_clk_enb_refcnt);
1818 clk_register_clkdev(clk, NULL, "timer");
1819 clks[timer] = clk;
1820
1821 /* kfuse */
1822 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1823 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1824 &periph_h_regs, periph_clk_enb_refcnt);
1825 clks[kfuse] = clk;
1826
1827 /* fuse */
1828 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1829 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1830 &periph_h_regs, periph_clk_enb_refcnt);
1831 clks[fuse] = clk;
1832
1833 /* fuse_burn */
1834 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1835 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1836 &periph_h_regs, periph_clk_enb_refcnt);
1837 clks[fuse_burn] = clk;
1838
1839 /* apbif */
1840 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1841 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1842 &periph_v_regs, periph_clk_enb_refcnt);
1843 clks[apbif] = clk;
1844
1845 /* hda2hdmi */
1846 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1847 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1848 &periph_w_regs, periph_clk_enb_refcnt);
1849 clks[hda2hdmi] = clk;
1850
1851 /* vcp */
1852 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1853 29, &periph_l_regs,
1854 periph_clk_enb_refcnt);
1855 clks[vcp] = clk;
1856
1857 /* bsea */
1858 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1859 0, 62, &periph_h_regs,
1860 periph_clk_enb_refcnt);
1861 clks[bsea] = clk;
1862
1863 /* bsev */
1864 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1865 0, 63, &periph_h_regs,
1866 periph_clk_enb_refcnt);
1867 clks[bsev] = clk;
1868
1869 /* mipi-cal */
1870 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1871 0, 56, &periph_h_regs,
1872 periph_clk_enb_refcnt);
1873 clks[mipi_cal] = clk;
1874
1875 /* usbd */
1876 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
1877 0, 22, &periph_l_regs,
1878 periph_clk_enb_refcnt);
1879 clks[usbd] = clk;
1880
1881 /* usb2 */
1882 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
1883 0, 58, &periph_h_regs,
1884 periph_clk_enb_refcnt);
1885 clks[usb2] = clk;
1886
1887 /* usb3 */
1888 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
1889 0, 59, &periph_h_regs,
1890 periph_clk_enb_refcnt);
1891 clks[usb3] = clk;
1892
1893 /* csi */
1894 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1895 0, 52, &periph_h_regs,
1896 periph_clk_enb_refcnt);
1897 clks[csi] = clk;
1898
1899 /* isp */
1900 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
1901 23, &periph_l_regs,
1902 periph_clk_enb_refcnt);
1903 clks[isp] = clk;
1904
1905 /* csus */
1906 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1907 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
1908 &periph_u_regs, periph_clk_enb_refcnt);
1909 clks[csus] = clk;
1910
1911 /* dds */
1912 clk = tegra_clk_register_periph_gate("dds", "clk_m",
1913 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
1914 &periph_w_regs, periph_clk_enb_refcnt);
1915 clks[dds] = clk;
1916
1917 /* dp2 */
1918 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
1919 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
1920 &periph_w_regs, periph_clk_enb_refcnt);
1921 clks[dp2] = clk;
1922
1923 /* dtv */
1924 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1925 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
1926 &periph_u_regs, periph_clk_enb_refcnt);
1927 clks[dtv] = clk;
1928
1929 /* dsia */
1930 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1931 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1932 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1933 clks[dsia_mux] = clk;
1934 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1935 0, 48, &periph_h_regs,
1936 periph_clk_enb_refcnt);
1937 clks[dsia] = clk;
1938
1939 /* dsib */
1940 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1941 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1942 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1943 clks[dsib_mux] = clk;
1944 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1945 0, 82, &periph_u_regs,
1946 periph_clk_enb_refcnt);
1947 clks[dsib] = clk;
1948
1949 /* xusb_hs_src */
1950 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1951 val |= BIT(25); /* always select PLLU_60M */
1952 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1953
1954 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1955 1, 1);
1956 clks[xusb_hs_src] = clk;
1957
1958 /* xusb_host */
1959 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
1960 clk_base, 0, 89, &periph_u_regs,
1961 periph_clk_enb_refcnt);
1962 clks[xusb_host] = clk;
1963
1964 /* xusb_ss */
1965 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
1966 clk_base, 0, 156, &periph_w_regs,
1967 periph_clk_enb_refcnt);
1968 clks[xusb_host] = clk;
1969
1970 /* xusb_dev */
1971 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
1972 clk_base, 0, 95, &periph_u_regs,
1973 periph_clk_enb_refcnt);
1974 clks[xusb_dev] = clk;
1975
1976 /* emc */
1977 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1978 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1979 clk_base + CLK_SOURCE_EMC,
1980 29, 3, 0, NULL);
1981 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
1982 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
1983 periph_clk_enb_refcnt);
1984 clks[emc] = clk;
1985
1986 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1987 data = &tegra_periph_clk_list[i];
1988 clk = tegra_clk_register_periph(data->name, data->parent_names,
1989 data->num_parents, &data->periph,
1990 clk_base, data->offset, data->flags);
1991 clks[data->clk_id] = clk;
1992 }
1993
1994 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1995 data = &tegra_periph_nodiv_clk_list[i];
1996 clk = tegra_clk_register_periph_nodiv(data->name,
1997 data->parent_names, data->num_parents,
1998 &data->periph, clk_base, data->offset);
1999 clks[data->clk_id] = clk;
2000 }
2001}
2002
2003static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
2004
2005static const struct of_device_id pmc_match[] __initconst = {
2006 { .compatible = "nvidia,tegra114-pmc" },
2007 {},
2008};
2009
2010static __initdata struct tegra_clk_init_table init_table[] = {
2011 {uarta, pll_p, 408000000, 0},
2012 {uartb, pll_p, 408000000, 0},
2013 {uartc, pll_p, 408000000, 0},
2014 {uartd, pll_p, 408000000, 0},
2015 {pll_a, clk_max, 564480000, 1},
2016 {pll_a_out0, clk_max, 11289600, 1},
2017 {extern1, pll_a_out0, 0, 1},
2018 {clk_out_1_mux, extern1, 0, 1},
2019 {clk_out_1, clk_max, 0, 1},
2020 {i2s0, pll_a_out0, 11289600, 0},
2021 {i2s1, pll_a_out0, 11289600, 0},
2022 {i2s2, pll_a_out0, 11289600, 0},
2023 {i2s3, pll_a_out0, 11289600, 0},
2024 {i2s4, pll_a_out0, 11289600, 0},
2025 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
2026};
2027
2028static void __init tegra114_clock_apply_init_table(void)
2029{
2030 tegra_init_from_table(init_table, clks, clk_max);
2031}
2032
2033void __init tegra114_clock_init(struct device_node *np)
2034{
2035 struct device_node *node;
2036 int i;
2037
2038 clk_base = of_iomap(np, 0);
2039 if (!clk_base) {
2040 pr_err("ioremap tegra114 CAR failed\n");
2041 return;
2042 }
2043
2044 node = of_find_matching_node(NULL, pmc_match);
2045 if (!node) {
2046 pr_err("Failed to find pmc node\n");
2047 WARN_ON(1);
2048 return;
2049 }
2050
2051 pmc_base = of_iomap(node, 0);
2052 if (!pmc_base) {
2053 pr_err("Can't map pmc registers\n");
2054 WARN_ON(1);
2055 return;
2056 }
2057
2058 if (tegra114_osc_clk_init(clk_base) < 0)
2059 return;
2060
2061 tegra114_fixed_clk_init(clk_base);
2062 tegra114_pll_init(clk_base, pmc_base);
2063 tegra114_periph_clk_init(clk_base);
2064 tegra114_audio_clk_init(clk_base);
2065 tegra114_pmc_clk_init(pmc_base);
2066 tegra114_super_clk_init(clk_base);
2067
2068 for (i = 0; i < ARRAY_SIZE(clks); i++) {
2069 if (IS_ERR(clks[i])) {
2070 pr_err
2071 ("Tegra114 clk %d: register failed with %ld\n",
2072 i, PTR_ERR(clks[i]));
2073 }
2074 if (!clks[i])
2075 clks[i] = ERR_PTR(-EINVAL);
2076 }
2077
2078 clk_data.clks = clks;
2079 clk_data.clk_num = ARRAY_SIZE(clks);
2080 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2081
2082 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2083
2084 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
2085}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b92d48be4cc9..b0405b67f49c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
86#define PLLE_BASE 0xe8 86#define PLLE_BASE 0xe8
87#define PLLE_MISC 0xec 87#define PLLE_MISC 0xec
88 88
89#define PLL_BASE_LOCK 27 89#define PLL_BASE_LOCK BIT(27)
90#define PLLE_MISC_LOCK 11 90#define PLLE_MISC_LOCK BIT(11)
91 91
92#define PLL_MISC_LOCK_ENABLE 18 92#define PLL_MISC_LOCK_ENABLE 18
93#define PLLDU_MISC_LOCK_ENABLE 22 93#define PLLDU_MISC_LOCK_ENABLE 22
@@ -236,7 +236,7 @@ enum tegra20_clk {
236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, 238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2, 239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, 240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, 241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, 242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
248static struct clk_onecell_data clk_data; 248static struct clk_onecell_data clk_data;
249 249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 600000000, 600, 12, 1, 8 }, 251 { 12000000, 600000000, 600, 12, 0, 8 },
252 { 13000000, 600000000, 600, 13, 1, 8 }, 252 { 13000000, 600000000, 600, 13, 0, 8 },
253 { 19200000, 600000000, 500, 16, 1, 6 }, 253 { 19200000, 600000000, 500, 16, 0, 6 },
254 { 26000000, 600000000, 600, 26, 1, 8 }, 254 { 26000000, 600000000, 600, 26, 0, 8 },
255 { 0, 0, 0, 0, 0, 0 }, 255 { 0, 0, 0, 0, 0, 0 },
256}; 256};
257 257
258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
259 { 12000000, 666000000, 666, 12, 1, 8}, 259 { 12000000, 666000000, 666, 12, 0, 8},
260 { 13000000, 666000000, 666, 13, 1, 8}, 260 { 13000000, 666000000, 666, 13, 0, 8},
261 { 19200000, 666000000, 555, 16, 1, 8}, 261 { 19200000, 666000000, 555, 16, 0, 8},
262 { 26000000, 666000000, 666, 26, 1, 8}, 262 { 26000000, 666000000, 666, 26, 0, 8},
263 { 12000000, 600000000, 600, 12, 1, 8}, 263 { 12000000, 600000000, 600, 12, 0, 8},
264 { 13000000, 600000000, 600, 13, 1, 8}, 264 { 13000000, 600000000, 600, 13, 0, 8},
265 { 19200000, 600000000, 375, 12, 1, 6}, 265 { 19200000, 600000000, 375, 12, 0, 6},
266 { 26000000, 600000000, 600, 26, 1, 8}, 266 { 26000000, 600000000, 600, 26, 0, 8},
267 { 0, 0, 0, 0, 0, 0 }, 267 { 0, 0, 0, 0, 0, 0 },
268}; 268};
269 269
270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
271 { 12000000, 216000000, 432, 12, 2, 8}, 271 { 12000000, 216000000, 432, 12, 1, 8},
272 { 13000000, 216000000, 432, 13, 2, 8}, 272 { 13000000, 216000000, 432, 13, 1, 8},
273 { 19200000, 216000000, 90, 4, 2, 1}, 273 { 19200000, 216000000, 90, 4, 1, 1},
274 { 26000000, 216000000, 432, 26, 2, 8}, 274 { 26000000, 216000000, 432, 26, 1, 8},
275 { 12000000, 432000000, 432, 12, 1, 8}, 275 { 12000000, 432000000, 432, 12, 0, 8},
276 { 13000000, 432000000, 432, 13, 1, 8}, 276 { 13000000, 432000000, 432, 13, 0, 8},
277 { 19200000, 432000000, 90, 4, 1, 1}, 277 { 19200000, 432000000, 90, 4, 0, 1},
278 { 26000000, 432000000, 432, 26, 1, 8}, 278 { 26000000, 432000000, 432, 26, 0, 8},
279 { 0, 0, 0, 0, 0, 0 }, 279 { 0, 0, 0, 0, 0, 0 },
280}; 280};
281 281
282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
283 { 28800000, 56448000, 49, 25, 1, 1}, 283 { 28800000, 56448000, 49, 25, 0, 1},
284 { 28800000, 73728000, 64, 25, 1, 1}, 284 { 28800000, 73728000, 64, 25, 0, 1},
285 { 28800000, 24000000, 5, 6, 1, 1}, 285 { 28800000, 24000000, 5, 6, 0, 1},
286 { 0, 0, 0, 0, 0, 0 }, 286 { 0, 0, 0, 0, 0, 0 },
287}; 287};
288 288
289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
290 { 12000000, 216000000, 216, 12, 1, 4}, 290 { 12000000, 216000000, 216, 12, 0, 4},
291 { 13000000, 216000000, 216, 13, 1, 4}, 291 { 13000000, 216000000, 216, 13, 0, 4},
292 { 19200000, 216000000, 135, 12, 1, 3}, 292 { 19200000, 216000000, 135, 12, 0, 3},
293 { 26000000, 216000000, 216, 26, 1, 4}, 293 { 26000000, 216000000, 216, 26, 0, 4},
294 294
295 { 12000000, 594000000, 594, 12, 1, 8}, 295 { 12000000, 594000000, 594, 12, 0, 8},
296 { 13000000, 594000000, 594, 13, 1, 8}, 296 { 13000000, 594000000, 594, 13, 0, 8},
297 { 19200000, 594000000, 495, 16, 1, 8}, 297 { 19200000, 594000000, 495, 16, 0, 8},
298 { 26000000, 594000000, 594, 26, 1, 8}, 298 { 26000000, 594000000, 594, 26, 0, 8},
299 299
300 { 12000000, 1000000000, 1000, 12, 1, 12}, 300 { 12000000, 1000000000, 1000, 12, 0, 12},
301 { 13000000, 1000000000, 1000, 13, 1, 12}, 301 { 13000000, 1000000000, 1000, 13, 0, 12},
302 { 19200000, 1000000000, 625, 12, 1, 8}, 302 { 19200000, 1000000000, 625, 12, 0, 8},
303 { 26000000, 1000000000, 1000, 26, 1, 12}, 303 { 26000000, 1000000000, 1000, 26, 0, 12},
304 304
305 { 0, 0, 0, 0, 0, 0 }, 305 { 0, 0, 0, 0, 0, 0 },
306}; 306};
307 307
308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
309 { 12000000, 480000000, 960, 12, 2, 0}, 309 { 12000000, 480000000, 960, 12, 0, 0},
310 { 13000000, 480000000, 960, 13, 2, 0}, 310 { 13000000, 480000000, 960, 13, 0, 0},
311 { 19200000, 480000000, 200, 4, 2, 0}, 311 { 19200000, 480000000, 200, 4, 0, 0},
312 { 26000000, 480000000, 960, 26, 2, 0}, 312 { 26000000, 480000000, 960, 26, 0, 0},
313 { 0, 0, 0, 0, 0, 0 }, 313 { 0, 0, 0, 0, 0, 0 },
314}; 314};
315 315
316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
317 /* 1 GHz */ 317 /* 1 GHz */
318 { 12000000, 1000000000, 1000, 12, 1, 12}, 318 { 12000000, 1000000000, 1000, 12, 0, 12},
319 { 13000000, 1000000000, 1000, 13, 1, 12}, 319 { 13000000, 1000000000, 1000, 13, 0, 12},
320 { 19200000, 1000000000, 625, 12, 1, 8}, 320 { 19200000, 1000000000, 625, 12, 0, 8},
321 { 26000000, 1000000000, 1000, 26, 1, 12}, 321 { 26000000, 1000000000, 1000, 26, 0, 12},
322 322
323 /* 912 MHz */ 323 /* 912 MHz */
324 { 12000000, 912000000, 912, 12, 1, 12}, 324 { 12000000, 912000000, 912, 12, 0, 12},
325 { 13000000, 912000000, 912, 13, 1, 12}, 325 { 13000000, 912000000, 912, 13, 0, 12},
326 { 19200000, 912000000, 760, 16, 1, 8}, 326 { 19200000, 912000000, 760, 16, 0, 8},
327 { 26000000, 912000000, 912, 26, 1, 12}, 327 { 26000000, 912000000, 912, 26, 0, 12},
328 328
329 /* 816 MHz */ 329 /* 816 MHz */
330 { 12000000, 816000000, 816, 12, 1, 12}, 330 { 12000000, 816000000, 816, 12, 0, 12},
331 { 13000000, 816000000, 816, 13, 1, 12}, 331 { 13000000, 816000000, 816, 13, 0, 12},
332 { 19200000, 816000000, 680, 16, 1, 8}, 332 { 19200000, 816000000, 680, 16, 0, 8},
333 { 26000000, 816000000, 816, 26, 1, 12}, 333 { 26000000, 816000000, 816, 26, 0, 12},
334 334
335 /* 760 MHz */ 335 /* 760 MHz */
336 { 12000000, 760000000, 760, 12, 1, 12}, 336 { 12000000, 760000000, 760, 12, 0, 12},
337 { 13000000, 760000000, 760, 13, 1, 12}, 337 { 13000000, 760000000, 760, 13, 0, 12},
338 { 19200000, 760000000, 950, 24, 1, 8}, 338 { 19200000, 760000000, 950, 24, 0, 8},
339 { 26000000, 760000000, 760, 26, 1, 12}, 339 { 26000000, 760000000, 760, 26, 0, 12},
340 340
341 /* 750 MHz */ 341 /* 750 MHz */
342 { 12000000, 750000000, 750, 12, 1, 12}, 342 { 12000000, 750000000, 750, 12, 0, 12},
343 { 13000000, 750000000, 750, 13, 1, 12}, 343 { 13000000, 750000000, 750, 13, 0, 12},
344 { 19200000, 750000000, 625, 16, 1, 8}, 344 { 19200000, 750000000, 625, 16, 0, 8},
345 { 26000000, 750000000, 750, 26, 1, 12}, 345 { 26000000, 750000000, 750, 26, 0, 12},
346 346
347 /* 608 MHz */ 347 /* 608 MHz */
348 { 12000000, 608000000, 608, 12, 1, 12}, 348 { 12000000, 608000000, 608, 12, 0, 12},
349 { 13000000, 608000000, 608, 13, 1, 12}, 349 { 13000000, 608000000, 608, 13, 0, 12},
350 { 19200000, 608000000, 380, 12, 1, 8}, 350 { 19200000, 608000000, 380, 12, 0, 8},
351 { 26000000, 608000000, 608, 26, 1, 12}, 351 { 26000000, 608000000, 608, 26, 0, 12},
352 352
353 /* 456 MHz */ 353 /* 456 MHz */
354 { 12000000, 456000000, 456, 12, 1, 12}, 354 { 12000000, 456000000, 456, 12, 0, 12},
355 { 13000000, 456000000, 456, 13, 1, 12}, 355 { 13000000, 456000000, 456, 13, 0, 12},
356 { 19200000, 456000000, 380, 16, 1, 8}, 356 { 19200000, 456000000, 380, 16, 0, 8},
357 { 26000000, 456000000, 456, 26, 1, 12}, 357 { 26000000, 456000000, 456, 26, 0, 12},
358 358
359 /* 312 MHz */ 359 /* 312 MHz */
360 { 12000000, 312000000, 312, 12, 1, 12}, 360 { 12000000, 312000000, 312, 12, 0, 12},
361 { 13000000, 312000000, 312, 13, 1, 12}, 361 { 13000000, 312000000, 312, 13, 0, 12},
362 { 19200000, 312000000, 260, 16, 1, 8}, 362 { 19200000, 312000000, 260, 16, 0, 8},
363 { 26000000, 312000000, 312, 26, 1, 12}, 363 { 26000000, 312000000, 312, 26, 0, 12},
364 364
365 { 0, 0, 0, 0, 0, 0 }, 365 { 0, 0, 0, 0, 0, 0 },
366}; 366};
367 367
368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
369 { 12000000, 100000000, 200, 24, 1, 0 }, 369 { 12000000, 100000000, 200, 24, 0, 0 },
370 { 0, 0, 0, 0, 0, 0 }, 370 { 0, 0, 0, 0, 0, 0 },
371}; 371};
372 372
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
380 .vco_max = 1400000000, 380 .vco_max = 1400000000,
381 .base_reg = PLLC_BASE, 381 .base_reg = PLLC_BASE,
382 .misc_reg = PLLC_MISC, 382 .misc_reg = PLLC_MISC,
383 .lock_bit_idx = PLL_BASE_LOCK, 383 .lock_mask = PLL_BASE_LOCK,
384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
385 .lock_delay = 300, 385 .lock_delay = 300,
386}; 386};
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
394 .vco_max = 1200000000, 394 .vco_max = 1200000000,
395 .base_reg = PLLM_BASE, 395 .base_reg = PLLM_BASE,
396 .misc_reg = PLLM_MISC, 396 .misc_reg = PLLM_MISC,
397 .lock_bit_idx = PLL_BASE_LOCK, 397 .lock_mask = PLL_BASE_LOCK,
398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
399 .lock_delay = 300, 399 .lock_delay = 300,
400}; 400};
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
408 .vco_max = 1400000000, 408 .vco_max = 1400000000,
409 .base_reg = PLLP_BASE, 409 .base_reg = PLLP_BASE,
410 .misc_reg = PLLP_MISC, 410 .misc_reg = PLLP_MISC,
411 .lock_bit_idx = PLL_BASE_LOCK, 411 .lock_mask = PLL_BASE_LOCK,
412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
413 .lock_delay = 300, 413 .lock_delay = 300,
414}; 414};
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
422 .vco_max = 1400000000, 422 .vco_max = 1400000000,
423 .base_reg = PLLA_BASE, 423 .base_reg = PLLA_BASE,
424 .misc_reg = PLLA_MISC, 424 .misc_reg = PLLA_MISC,
425 .lock_bit_idx = PLL_BASE_LOCK, 425 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427 .lock_delay = 300, 427 .lock_delay = 300,
428}; 428};
@@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
436 .vco_max = 1000000000, 436 .vco_max = 1000000000,
437 .base_reg = PLLD_BASE, 437 .base_reg = PLLD_BASE,
438 .misc_reg = PLLD_MISC, 438 .misc_reg = PLLD_MISC,
439 .lock_bit_idx = PLL_BASE_LOCK, 439 .lock_mask = PLL_BASE_LOCK,
440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
441 .lock_delay = 1000, 441 .lock_delay = 1000,
442}; 442};
443 443
444static struct pdiv_map pllu_p[] = {
445 { .pdiv = 1, .hw_val = 1 },
446 { .pdiv = 2, .hw_val = 0 },
447 { .pdiv = 0, .hw_val = 0 },
448};
449
444static struct tegra_clk_pll_params pll_u_params = { 450static struct tegra_clk_pll_params pll_u_params = {
445 .input_min = 2000000, 451 .input_min = 2000000,
446 .input_max = 40000000, 452 .input_max = 40000000,
@@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
450 .vco_max = 960000000, 456 .vco_max = 960000000,
451 .base_reg = PLLU_BASE, 457 .base_reg = PLLU_BASE,
452 .misc_reg = PLLU_MISC, 458 .misc_reg = PLLU_MISC,
453 .lock_bit_idx = PLL_BASE_LOCK, 459 .lock_mask = PLL_BASE_LOCK,
454 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 460 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
455 .lock_delay = 1000, 461 .lock_delay = 1000,
462 .pdiv_tohw = pllu_p,
456}; 463};
457 464
458static struct tegra_clk_pll_params pll_x_params = { 465static struct tegra_clk_pll_params pll_x_params = {
@@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
464 .vco_max = 1200000000, 471 .vco_max = 1200000000,
465 .base_reg = PLLX_BASE, 472 .base_reg = PLLX_BASE,
466 .misc_reg = PLLX_MISC, 473 .misc_reg = PLLX_MISC,
467 .lock_bit_idx = PLL_BASE_LOCK, 474 .lock_mask = PLL_BASE_LOCK,
468 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 475 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
469 .lock_delay = 300, 476 .lock_delay = 300,
470}; 477};
@@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
478 .vco_max = 0, 485 .vco_max = 0,
479 .base_reg = PLLE_BASE, 486 .base_reg = PLLE_BASE,
480 .misc_reg = PLLE_MISC, 487 .misc_reg = PLLE_MISC,
481 .lock_bit_idx = PLLE_MISC_LOCK, 488 .lock_mask = PLLE_MISC_LOCK,
482 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 489 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
483 .lock_delay = 0, 490 .lock_delay = 0,
484}; 491};
@@ -1012,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
1012 data = &tegra_periph_clk_list[i]; 1019 data = &tegra_periph_clk_list[i];
1013 clk = tegra_clk_register_periph(data->name, data->parent_names, 1020 clk = tegra_clk_register_periph(data->name, data->parent_names,
1014 data->num_parents, &data->periph, 1021 data->num_parents, &data->periph,
1015 clk_base, data->offset); 1022 clk_base, data->offset, data->flags);
1016 clk_register_clkdev(clk, data->con_id, data->dev_id); 1023 clk_register_clkdev(clk, data->con_id, data->dev_id);
1017 clks[data->clk_id] = clk; 1024 clks[data->clk_id] = clk;
1018 } 1025 }
@@ -1247,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1247 {host1x, pll_c, 150000000, 0}, 1254 {host1x, pll_c, 150000000, 0},
1248 {disp1, pll_p, 600000000, 0}, 1255 {disp1, pll_p, 600000000, 0},
1249 {disp2, pll_p, 600000000, 0}, 1256 {disp2, pll_p, 600000000, 0},
1257 {gr2d, pll_c, 300000000, 0},
1258 {gr3d, pll_c, 300000000, 0},
1250 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1259 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
1251}; 1260};
1252 1261
1262static void __init tegra20_clock_apply_init_table(void)
1263{
1264 tegra_init_from_table(init_table, clks, clk_max);
1265}
1266
1253/* 1267/*
1254 * Some clocks may be used by different drivers depending on the board 1268 * Some clocks may be used by different drivers depending on the board
1255 * configuration. List those here to register them twice in the clock lookup 1269 * configuration. List those here to register them twice in the clock lookup
@@ -1316,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
1316 clk_data.clk_num = ARRAY_SIZE(clks); 1330 clk_data.clk_num = ARRAY_SIZE(clks);
1317 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 1331 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1318 1332
1319 tegra_init_from_table(init_table, clks, clk_max); 1333 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1320 1334
1321 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1335 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1322} 1336}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51bc9f3b..2dc0c5602613 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -116,8 +116,8 @@
116#define PLLDU_MISC_LOCK_ENABLE 22 116#define PLLDU_MISC_LOCK_ENABLE 22
117#define PLLE_MISC_LOCK_ENABLE 9 117#define PLLE_MISC_LOCK_ENABLE 9
118 118
119#define PLL_BASE_LOCK 27 119#define PLL_BASE_LOCK BIT(27)
120#define PLLE_MISC_LOCK 11 120#define PLLE_MISC_LOCK BIT(11)
121 121
122#define PLLE_AUX 0x48c 122#define PLLE_AUX 0x48c
123#define PLLC_OUT 0x84 123#define PLLC_OUT 0x84
@@ -330,7 +330,7 @@ enum tegra30_clk {
330 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 330 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
331 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 331 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
332 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 332 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
333 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 333 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
334 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 334 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
335 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 335 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
336 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 336 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
@@ -374,164 +374,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
374}; 374};
375 375
376static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 376static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
377 { 12000000, 1040000000, 520, 6, 1, 8}, 377 { 12000000, 1040000000, 520, 6, 0, 8},
378 { 13000000, 1040000000, 480, 6, 1, 8}, 378 { 13000000, 1040000000, 480, 6, 0, 8},
379 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ 379 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
380 { 19200000, 1040000000, 325, 6, 1, 6}, 380 { 19200000, 1040000000, 325, 6, 0, 6},
381 { 26000000, 1040000000, 520, 13, 1, 8}, 381 { 26000000, 1040000000, 520, 13, 0, 8},
382 382
383 { 12000000, 832000000, 416, 6, 1, 8}, 383 { 12000000, 832000000, 416, 6, 0, 8},
384 { 13000000, 832000000, 832, 13, 1, 8}, 384 { 13000000, 832000000, 832, 13, 0, 8},
385 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ 385 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
386 { 19200000, 832000000, 260, 6, 1, 8}, 386 { 19200000, 832000000, 260, 6, 0, 8},
387 { 26000000, 832000000, 416, 13, 1, 8}, 387 { 26000000, 832000000, 416, 13, 0, 8},
388 388
389 { 12000000, 624000000, 624, 12, 1, 8}, 389 { 12000000, 624000000, 624, 12, 0, 8},
390 { 13000000, 624000000, 624, 13, 1, 8}, 390 { 13000000, 624000000, 624, 13, 0, 8},
391 { 16800000, 600000000, 520, 14, 1, 8}, 391 { 16800000, 600000000, 520, 14, 0, 8},
392 { 19200000, 624000000, 520, 16, 1, 8}, 392 { 19200000, 624000000, 520, 16, 0, 8},
393 { 26000000, 624000000, 624, 26, 1, 8}, 393 { 26000000, 624000000, 624, 26, 0, 8},
394 394
395 { 12000000, 600000000, 600, 12, 1, 8}, 395 { 12000000, 600000000, 600, 12, 0, 8},
396 { 13000000, 600000000, 600, 13, 1, 8}, 396 { 13000000, 600000000, 600, 13, 0, 8},
397 { 16800000, 600000000, 500, 14, 1, 8}, 397 { 16800000, 600000000, 500, 14, 0, 8},
398 { 19200000, 600000000, 375, 12, 1, 6}, 398 { 19200000, 600000000, 375, 12, 0, 6},
399 { 26000000, 600000000, 600, 26, 1, 8}, 399 { 26000000, 600000000, 600, 26, 0, 8},
400 400
401 { 12000000, 520000000, 520, 12, 1, 8}, 401 { 12000000, 520000000, 520, 12, 0, 8},
402 { 13000000, 520000000, 520, 13, 1, 8}, 402 { 13000000, 520000000, 520, 13, 0, 8},
403 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ 403 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
404 { 19200000, 520000000, 325, 12, 1, 6}, 404 { 19200000, 520000000, 325, 12, 0, 6},
405 { 26000000, 520000000, 520, 26, 1, 8}, 405 { 26000000, 520000000, 520, 26, 0, 8},
406 406
407 { 12000000, 416000000, 416, 12, 1, 8}, 407 { 12000000, 416000000, 416, 12, 0, 8},
408 { 13000000, 416000000, 416, 13, 1, 8}, 408 { 13000000, 416000000, 416, 13, 0, 8},
409 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ 409 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
410 { 19200000, 416000000, 260, 12, 1, 6}, 410 { 19200000, 416000000, 260, 12, 0, 6},
411 { 26000000, 416000000, 416, 26, 1, 8}, 411 { 26000000, 416000000, 416, 26, 0, 8},
412 { 0, 0, 0, 0, 0, 0 }, 412 { 0, 0, 0, 0, 0, 0 },
413}; 413};
414 414
415static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 415static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
416 { 12000000, 666000000, 666, 12, 1, 8}, 416 { 12000000, 666000000, 666, 12, 0, 8},
417 { 13000000, 666000000, 666, 13, 1, 8}, 417 { 13000000, 666000000, 666, 13, 0, 8},
418 { 16800000, 666000000, 555, 14, 1, 8}, 418 { 16800000, 666000000, 555, 14, 0, 8},
419 { 19200000, 666000000, 555, 16, 1, 8}, 419 { 19200000, 666000000, 555, 16, 0, 8},
420 { 26000000, 666000000, 666, 26, 1, 8}, 420 { 26000000, 666000000, 666, 26, 0, 8},
421 { 12000000, 600000000, 600, 12, 1, 8}, 421 { 12000000, 600000000, 600, 12, 0, 8},
422 { 13000000, 600000000, 600, 13, 1, 8}, 422 { 13000000, 600000000, 600, 13, 0, 8},
423 { 16800000, 600000000, 500, 14, 1, 8}, 423 { 16800000, 600000000, 500, 14, 0, 8},
424 { 19200000, 600000000, 375, 12, 1, 6}, 424 { 19200000, 600000000, 375, 12, 0, 6},
425 { 26000000, 600000000, 600, 26, 1, 8}, 425 { 26000000, 600000000, 600, 26, 0, 8},
426 { 0, 0, 0, 0, 0, 0 }, 426 { 0, 0, 0, 0, 0, 0 },
427}; 427};
428 428
429static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 429static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
430 { 12000000, 216000000, 432, 12, 2, 8}, 430 { 12000000, 216000000, 432, 12, 1, 8},
431 { 13000000, 216000000, 432, 13, 2, 8}, 431 { 13000000, 216000000, 432, 13, 1, 8},
432 { 16800000, 216000000, 360, 14, 2, 8}, 432 { 16800000, 216000000, 360, 14, 1, 8},
433 { 19200000, 216000000, 360, 16, 2, 8}, 433 { 19200000, 216000000, 360, 16, 1, 8},
434 { 26000000, 216000000, 432, 26, 2, 8}, 434 { 26000000, 216000000, 432, 26, 1, 8},
435 { 0, 0, 0, 0, 0, 0 }, 435 { 0, 0, 0, 0, 0, 0 },
436}; 436};
437 437
438static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 438static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
439 { 9600000, 564480000, 294, 5, 1, 4}, 439 { 9600000, 564480000, 294, 5, 0, 4},
440 { 9600000, 552960000, 288, 5, 1, 4}, 440 { 9600000, 552960000, 288, 5, 0, 4},
441 { 9600000, 24000000, 5, 2, 1, 1}, 441 { 9600000, 24000000, 5, 2, 0, 1},
442 442
443 { 28800000, 56448000, 49, 25, 1, 1}, 443 { 28800000, 56448000, 49, 25, 0, 1},
444 { 28800000, 73728000, 64, 25, 1, 1}, 444 { 28800000, 73728000, 64, 25, 0, 1},
445 { 28800000, 24000000, 5, 6, 1, 1}, 445 { 28800000, 24000000, 5, 6, 0, 1},
446 { 0, 0, 0, 0, 0, 0 }, 446 { 0, 0, 0, 0, 0, 0 },
447}; 447};
448 448
449static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 449static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
450 { 12000000, 216000000, 216, 12, 1, 4}, 450 { 12000000, 216000000, 216, 12, 0, 4},
451 { 13000000, 216000000, 216, 13, 1, 4}, 451 { 13000000, 216000000, 216, 13, 0, 4},
452 { 16800000, 216000000, 180, 14, 1, 4}, 452 { 16800000, 216000000, 180, 14, 0, 4},
453 { 19200000, 216000000, 180, 16, 1, 4}, 453 { 19200000, 216000000, 180, 16, 0, 4},
454 { 26000000, 216000000, 216, 26, 1, 4}, 454 { 26000000, 216000000, 216, 26, 0, 4},
455 455
456 { 12000000, 594000000, 594, 12, 1, 8}, 456 { 12000000, 594000000, 594, 12, 0, 8},
457 { 13000000, 594000000, 594, 13, 1, 8}, 457 { 13000000, 594000000, 594, 13, 0, 8},
458 { 16800000, 594000000, 495, 14, 1, 8}, 458 { 16800000, 594000000, 495, 14, 0, 8},
459 { 19200000, 594000000, 495, 16, 1, 8}, 459 { 19200000, 594000000, 495, 16, 0, 8},
460 { 26000000, 594000000, 594, 26, 1, 8}, 460 { 26000000, 594000000, 594, 26, 0, 8},
461 461
462 { 12000000, 1000000000, 1000, 12, 1, 12}, 462 { 12000000, 1000000000, 1000, 12, 0, 12},
463 { 13000000, 1000000000, 1000, 13, 1, 12}, 463 { 13000000, 1000000000, 1000, 13, 0, 12},
464 { 19200000, 1000000000, 625, 12, 1, 8}, 464 { 19200000, 1000000000, 625, 12, 0, 8},
465 { 26000000, 1000000000, 1000, 26, 1, 12}, 465 { 26000000, 1000000000, 1000, 26, 0, 12},
466 466
467 { 0, 0, 0, 0, 0, 0 }, 467 { 0, 0, 0, 0, 0, 0 },
468}; 468};
469 469
470static struct pdiv_map pllu_p[] = {
471 { .pdiv = 1, .hw_val = 1 },
472 { .pdiv = 2, .hw_val = 0 },
473 { .pdiv = 0, .hw_val = 0 },
474};
475
470static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 476static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
471 { 12000000, 480000000, 960, 12, 2, 12}, 477 { 12000000, 480000000, 960, 12, 0, 12},
472 { 13000000, 480000000, 960, 13, 2, 12}, 478 { 13000000, 480000000, 960, 13, 0, 12},
473 { 16800000, 480000000, 400, 7, 2, 5}, 479 { 16800000, 480000000, 400, 7, 0, 5},
474 { 19200000, 480000000, 200, 4, 2, 3}, 480 { 19200000, 480000000, 200, 4, 0, 3},
475 { 26000000, 480000000, 960, 26, 2, 12}, 481 { 26000000, 480000000, 960, 26, 0, 12},
476 { 0, 0, 0, 0, 0, 0 }, 482 { 0, 0, 0, 0, 0, 0 },
477}; 483};
478 484
479static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 485static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
480 /* 1.7 GHz */ 486 /* 1.7 GHz */
481 { 12000000, 1700000000, 850, 6, 1, 8}, 487 { 12000000, 1700000000, 850, 6, 0, 8},
482 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ 488 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
483 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ 489 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
484 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ 490 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
485 { 26000000, 1700000000, 850, 13, 1, 8}, 491 { 26000000, 1700000000, 850, 13, 0, 8},
486 492
487 /* 1.6 GHz */ 493 /* 1.6 GHz */
488 { 12000000, 1600000000, 800, 6, 1, 8}, 494 { 12000000, 1600000000, 800, 6, 0, 8},
489 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ 495 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
490 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ 496 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
491 { 19200000, 1600000000, 500, 6, 1, 8}, 497 { 19200000, 1600000000, 500, 6, 0, 8},
492 { 26000000, 1600000000, 800, 13, 1, 8}, 498 { 26000000, 1600000000, 800, 13, 0, 8},
493 499
494 /* 1.5 GHz */ 500 /* 1.5 GHz */
495 { 12000000, 1500000000, 750, 6, 1, 8}, 501 { 12000000, 1500000000, 750, 6, 0, 8},
496 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ 502 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
497 { 16800000, 1500000000, 625, 7, 1, 8}, 503 { 16800000, 1500000000, 625, 7, 0, 8},
498 { 19200000, 1500000000, 625, 8, 1, 8}, 504 { 19200000, 1500000000, 625, 8, 0, 8},
499 { 26000000, 1500000000, 750, 13, 1, 8}, 505 { 26000000, 1500000000, 750, 13, 0, 8},
500 506
501 /* 1.4 GHz */ 507 /* 1.4 GHz */
502 { 12000000, 1400000000, 700, 6, 1, 8}, 508 { 12000000, 1400000000, 700, 6, 0, 8},
503 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ 509 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
504 { 16800000, 1400000000, 1000, 12, 1, 8}, 510 { 16800000, 1400000000, 1000, 12, 0, 8},
505 { 19200000, 1400000000, 875, 12, 1, 8}, 511 { 19200000, 1400000000, 875, 12, 0, 8},
506 { 26000000, 1400000000, 700, 13, 1, 8}, 512 { 26000000, 1400000000, 700, 13, 0, 8},
507 513
508 /* 1.3 GHz */ 514 /* 1.3 GHz */
509 { 12000000, 1300000000, 975, 9, 1, 8}, 515 { 12000000, 1300000000, 975, 9, 0, 8},
510 { 13000000, 1300000000, 1000, 10, 1, 8}, 516 { 13000000, 1300000000, 1000, 10, 0, 8},
511 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ 517 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
512 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ 518 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
513 { 26000000, 1300000000, 650, 13, 1, 8}, 519 { 26000000, 1300000000, 650, 13, 0, 8},
514 520
515 /* 1.2 GHz */ 521 /* 1.2 GHz */
516 { 12000000, 1200000000, 1000, 10, 1, 8}, 522 { 12000000, 1200000000, 1000, 10, 0, 8},
517 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ 523 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
518 { 16800000, 1200000000, 1000, 14, 1, 8}, 524 { 16800000, 1200000000, 1000, 14, 0, 8},
519 { 19200000, 1200000000, 1000, 16, 1, 8}, 525 { 19200000, 1200000000, 1000, 16, 0, 8},
520 { 26000000, 1200000000, 600, 13, 1, 8}, 526 { 26000000, 1200000000, 600, 13, 0, 8},
521 527
522 /* 1.1 GHz */ 528 /* 1.1 GHz */
523 { 12000000, 1100000000, 825, 9, 1, 8}, 529 { 12000000, 1100000000, 825, 9, 0, 8},
524 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ 530 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
525 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ 531 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
526 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ 532 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
527 { 26000000, 1100000000, 550, 13, 1, 8}, 533 { 26000000, 1100000000, 550, 13, 0, 8},
528 534
529 /* 1 GHz */ 535 /* 1 GHz */
530 { 12000000, 1000000000, 1000, 12, 1, 8}, 536 { 12000000, 1000000000, 1000, 12, 0, 8},
531 { 13000000, 1000000000, 1000, 13, 1, 8}, 537 { 13000000, 1000000000, 1000, 13, 0, 8},
532 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ 538 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
533 { 19200000, 1000000000, 625, 12, 1, 8}, 539 { 19200000, 1000000000, 625, 12, 0, 8},
534 { 26000000, 1000000000, 1000, 26, 1, 8}, 540 { 26000000, 1000000000, 1000, 26, 0, 8},
535 541
536 { 0, 0, 0, 0, 0, 0 }, 542 { 0, 0, 0, 0, 0, 0 },
537}; 543};
@@ -553,7 +559,7 @@ static struct tegra_clk_pll_params pll_c_params = {
553 .vco_max = 1400000000, 559 .vco_max = 1400000000,
554 .base_reg = PLLC_BASE, 560 .base_reg = PLLC_BASE,
555 .misc_reg = PLLC_MISC, 561 .misc_reg = PLLC_MISC,
556 .lock_bit_idx = PLL_BASE_LOCK, 562 .lock_mask = PLL_BASE_LOCK,
557 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 563 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
558 .lock_delay = 300, 564 .lock_delay = 300,
559}; 565};
@@ -567,7 +573,7 @@ static struct tegra_clk_pll_params pll_m_params = {
567 .vco_max = 1200000000, 573 .vco_max = 1200000000,
568 .base_reg = PLLM_BASE, 574 .base_reg = PLLM_BASE,
569 .misc_reg = PLLM_MISC, 575 .misc_reg = PLLM_MISC,
570 .lock_bit_idx = PLL_BASE_LOCK, 576 .lock_mask = PLL_BASE_LOCK,
571 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 577 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
572 .lock_delay = 300, 578 .lock_delay = 300,
573}; 579};
@@ -581,7 +587,7 @@ static struct tegra_clk_pll_params pll_p_params = {
581 .vco_max = 1400000000, 587 .vco_max = 1400000000,
582 .base_reg = PLLP_BASE, 588 .base_reg = PLLP_BASE,
583 .misc_reg = PLLP_MISC, 589 .misc_reg = PLLP_MISC,
584 .lock_bit_idx = PLL_BASE_LOCK, 590 .lock_mask = PLL_BASE_LOCK,
585 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 591 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
586 .lock_delay = 300, 592 .lock_delay = 300,
587}; 593};
@@ -595,7 +601,7 @@ static struct tegra_clk_pll_params pll_a_params = {
595 .vco_max = 1400000000, 601 .vco_max = 1400000000,
596 .base_reg = PLLA_BASE, 602 .base_reg = PLLA_BASE,
597 .misc_reg = PLLA_MISC, 603 .misc_reg = PLLA_MISC,
598 .lock_bit_idx = PLL_BASE_LOCK, 604 .lock_mask = PLL_BASE_LOCK,
599 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 605 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
600 .lock_delay = 300, 606 .lock_delay = 300,
601}; 607};
@@ -609,7 +615,7 @@ static struct tegra_clk_pll_params pll_d_params = {
609 .vco_max = 1000000000, 615 .vco_max = 1000000000,
610 .base_reg = PLLD_BASE, 616 .base_reg = PLLD_BASE,
611 .misc_reg = PLLD_MISC, 617 .misc_reg = PLLD_MISC,
612 .lock_bit_idx = PLL_BASE_LOCK, 618 .lock_mask = PLL_BASE_LOCK,
613 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 619 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
614 .lock_delay = 1000, 620 .lock_delay = 1000,
615}; 621};
@@ -623,7 +629,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
623 .vco_max = 1000000000, 629 .vco_max = 1000000000,
624 .base_reg = PLLD2_BASE, 630 .base_reg = PLLD2_BASE,
625 .misc_reg = PLLD2_MISC, 631 .misc_reg = PLLD2_MISC,
626 .lock_bit_idx = PLL_BASE_LOCK, 632 .lock_mask = PLL_BASE_LOCK,
627 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 633 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
628 .lock_delay = 1000, 634 .lock_delay = 1000,
629}; 635};
@@ -637,9 +643,10 @@ static struct tegra_clk_pll_params pll_u_params = {
637 .vco_max = 960000000, 643 .vco_max = 960000000,
638 .base_reg = PLLU_BASE, 644 .base_reg = PLLU_BASE,
639 .misc_reg = PLLU_MISC, 645 .misc_reg = PLLU_MISC,
640 .lock_bit_idx = PLL_BASE_LOCK, 646 .lock_mask = PLL_BASE_LOCK,
641 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 647 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
642 .lock_delay = 1000, 648 .lock_delay = 1000,
649 .pdiv_tohw = pllu_p,
643}; 650};
644 651
645static struct tegra_clk_pll_params pll_x_params = { 652static struct tegra_clk_pll_params pll_x_params = {
@@ -651,7 +658,7 @@ static struct tegra_clk_pll_params pll_x_params = {
651 .vco_max = 1700000000, 658 .vco_max = 1700000000,
652 .base_reg = PLLX_BASE, 659 .base_reg = PLLX_BASE,
653 .misc_reg = PLLX_MISC, 660 .misc_reg = PLLX_MISC,
654 .lock_bit_idx = PLL_BASE_LOCK, 661 .lock_mask = PLL_BASE_LOCK,
655 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 662 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
656 .lock_delay = 300, 663 .lock_delay = 300,
657}; 664};
@@ -665,7 +672,7 @@ static struct tegra_clk_pll_params pll_e_params = {
665 .vco_max = 2400000000U, 672 .vco_max = 2400000000U,
666 .base_reg = PLLE_BASE, 673 .base_reg = PLLE_BASE,
667 .misc_reg = PLLE_MISC, 674 .misc_reg = PLLE_MISC,
668 .lock_bit_idx = PLLE_MISC_LOCK, 675 .lock_mask = PLLE_MISC_LOCK,
669 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 676 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
670 .lock_delay = 300, 677 .lock_delay = 300,
671}; 678};
@@ -1661,7 +1668,7 @@ static void __init tegra30_periph_clk_init(void)
1661 data = &tegra_periph_clk_list[i]; 1668 data = &tegra_periph_clk_list[i];
1662 clk = tegra_clk_register_periph(data->name, data->parent_names, 1669 clk = tegra_clk_register_periph(data->name, data->parent_names,
1663 data->num_parents, &data->periph, 1670 data->num_parents, &data->periph,
1664 clk_base, data->offset); 1671 clk_base, data->offset, data->flags);
1665 clk_register_clkdev(clk, data->con_id, data->dev_id); 1672 clk_register_clkdev(clk, data->con_id, data->dev_id);
1666 clks[data->clk_id] = clk; 1673 clks[data->clk_id] = clk;
1667 } 1674 }
@@ -1911,9 +1918,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1911 {disp1, pll_p, 600000000, 0}, 1918 {disp1, pll_p, 600000000, 0},
1912 {disp2, pll_p, 600000000, 0}, 1919 {disp2, pll_p, 600000000, 0},
1913 {twd, clk_max, 0, 1}, 1920 {twd, clk_max, 0, 1},
1921 {gr2d, pll_c, 300000000, 0},
1922 {gr3d, pll_c, 300000000, 0},
1914 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1923 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1915}; 1924};
1916 1925
1926static void __init tegra30_clock_apply_init_table(void)
1927{
1928 tegra_init_from_table(init_table, clks, clk_max);
1929}
1930
1917/* 1931/*
1918 * Some clocks may be used by different drivers depending on the board 1932 * Some clocks may be used by different drivers depending on the board
1919 * configuration. List those here to register them twice in the clock lookup 1933 * configuration. List those here to register them twice in the clock lookup
@@ -1987,7 +2001,7 @@ void __init tegra30_clock_init(struct device_node *np)
1987 clk_data.clk_num = ARRAY_SIZE(clks); 2001 clk_data.clk_num = ARRAY_SIZE(clks);
1988 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2002 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1989 2003
1990 tegra_init_from_table(init_table, clks, clk_max); 2004 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1991 2005
1992 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2006 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1993} 2007}
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9af0ad3..923ca7ee4694 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -22,7 +22,8 @@
22#include "clk.h" 22#include "clk.h"
23 23
24/* Global data of Tegra CPU CAR ops */ 24/* Global data of Tegra CPU CAR ops */
25struct tegra_cpu_car_ops *tegra_cpu_car_ops; 25static struct tegra_cpu_car_ops dummy_car_ops;
26struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
26 27
27void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 28void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
28 struct clk *clks[], int clk_max) 29 struct clk *clks[], int clk_max)
@@ -76,6 +77,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
76static const struct of_device_id tegra_dt_clk_match[] = { 77static const struct of_device_id tegra_dt_clk_match[] = {
77 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init }, 78 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
78 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init }, 79 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
80 { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
79 { } 81 { }
80}; 82};
81 83
@@ -83,3 +85,13 @@ void __init tegra_clocks_init(void)
83{ 85{
84 of_clk_init(tegra_dt_clk_match); 86 of_clk_init(tegra_dt_clk_match);
85} 87}
88
89tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
90
91void __init tegra_clocks_apply_init_table(void)
92{
93 if (!tegra_clk_apply_init_table)
94 return;
95
96 tegra_clk_apply_init_table();
97}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dcaf183..e0565620d68e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -1,4 +1,4 @@
1/* 1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
117}; 117};
118 118
119/** 119/**
120 * struct pdiv_map - map post divider to hw value
121 *
122 * @pdiv: post divider
123 * @hw_val: value to be written to the PLL hw
124 */
125struct pdiv_map {
126 u8 pdiv;
127 u8 hw_val;
128};
129
130/**
120 * struct clk_pll_params - PLL parameters 131 * struct clk_pll_params - PLL parameters
121 * 132 *
122 * @input_min: Minimum input frequency 133 * @input_min: Minimum input frequency
@@ -143,9 +154,18 @@ struct tegra_clk_pll_params {
143 u32 base_reg; 154 u32 base_reg;
144 u32 misc_reg; 155 u32 misc_reg;
145 u32 lock_reg; 156 u32 lock_reg;
146 u32 lock_bit_idx; 157 u32 lock_mask;
147 u32 lock_enable_bit_idx; 158 u32 lock_enable_bit_idx;
159 u32 iddq_reg;
160 u32 iddq_bit_idx;
161 u32 aux_reg;
162 u32 dyn_ramp_reg;
163 u32 ext_misc_reg[3];
164 int stepa_shift;
165 int stepb_shift;
148 int lock_delay; 166 int lock_delay;
167 int max_p;
168 struct pdiv_map *pdiv_tohw;
149}; 169};
150 170
151/** 171/**
@@ -182,12 +202,16 @@ struct tegra_clk_pll_params {
182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 202 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
183 * of some plls. 203 * of some plls.
184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 204 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
205 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
206 * base register.
207 * TEGRA_PLL_BYPASS - PLL has bypass bit
208 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
185 */ 209 */
186struct tegra_clk_pll { 210struct tegra_clk_pll {
187 struct clk_hw hw; 211 struct clk_hw hw;
188 void __iomem *clk_base; 212 void __iomem *clk_base;
189 void __iomem *pmc; 213 void __iomem *pmc;
190 u8 flags; 214 u32 flags;
191 unsigned long fixed_rate; 215 unsigned long fixed_rate;
192 spinlock_t *lock; 216 spinlock_t *lock;
193 u8 divn_shift; 217 u8 divn_shift;
@@ -210,20 +234,64 @@ struct tegra_clk_pll {
210#define TEGRA_PLLM BIT(5) 234#define TEGRA_PLLM BIT(5)
211#define TEGRA_PLL_FIXED BIT(6) 235#define TEGRA_PLL_FIXED BIT(6)
212#define TEGRA_PLLE_CONFIGURE BIT(7) 236#define TEGRA_PLLE_CONFIGURE BIT(7)
237#define TEGRA_PLL_LOCK_MISC BIT(8)
238#define TEGRA_PLL_BYPASS BIT(9)
239#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
213 240
214extern const struct clk_ops tegra_clk_pll_ops; 241extern const struct clk_ops tegra_clk_pll_ops;
215extern const struct clk_ops tegra_clk_plle_ops; 242extern const struct clk_ops tegra_clk_plle_ops;
216struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 243struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
217 void __iomem *clk_base, void __iomem *pmc, 244 void __iomem *clk_base, void __iomem *pmc,
218 unsigned long flags, unsigned long fixed_rate, 245 unsigned long flags, unsigned long fixed_rate,
219 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 246 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
220 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 247 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
248
221struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 249struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
222 void __iomem *clk_base, void __iomem *pmc, 250 void __iomem *clk_base, void __iomem *pmc,
223 unsigned long flags, unsigned long fixed_rate, 251 unsigned long flags, unsigned long fixed_rate,
224 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 252 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
226 254
255struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
256 void __iomem *clk_base, void __iomem *pmc,
257 unsigned long flags, unsigned long fixed_rate,
258 struct tegra_clk_pll_params *pll_params,
259 u32 pll_flags,
260 struct tegra_clk_pll_freq_table *freq_table,
261 spinlock_t *lock);
262
263struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
264 void __iomem *clk_base, void __iomem *pmc,
265 unsigned long flags, unsigned long fixed_rate,
266 struct tegra_clk_pll_params *pll_params,
267 u32 pll_flags,
268 struct tegra_clk_pll_freq_table *freq_table,
269 spinlock_t *lock);
270
271struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
272 void __iomem *clk_base, void __iomem *pmc,
273 unsigned long flags, unsigned long fixed_rate,
274 struct tegra_clk_pll_params *pll_params,
275 u32 pll_flags,
276 struct tegra_clk_pll_freq_table *freq_table,
277 spinlock_t *lock);
278
279struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
280 void __iomem *clk_base, void __iomem *pmc,
281 unsigned long flags, unsigned long fixed_rate,
282 struct tegra_clk_pll_params *pll_params,
283 u32 pll_flags,
284 struct tegra_clk_pll_freq_table *freq_table,
285 spinlock_t *lock, unsigned long parent_rate);
286
287struct clk *tegra_clk_register_plle_tegra114(const char *name,
288 const char *parent_name,
289 void __iomem *clk_base, unsigned long flags,
290 unsigned long fixed_rate,
291 struct tegra_clk_pll_params *pll_params,
292 struct tegra_clk_pll_freq_table *freq_table,
293 spinlock_t *lock);
294
227/** 295/**
228 * struct tegra_clk_pll_out - PLL divider down clock 296 * struct tegra_clk_pll_out - PLL divider down clock
229 * 297 *
@@ -290,6 +358,7 @@ struct tegra_clk_periph_regs {
290 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 358 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
291 * bus to flush the write operation in apb bus. This flag indicates 359 * bus to flush the write operation in apb bus. This flag indicates
292 * that this peripheral is in apb bus. 360 * that this peripheral is in apb bus.
361 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
293 */ 362 */
294struct tegra_clk_periph_gate { 363struct tegra_clk_periph_gate {
295 u32 magic; 364 u32 magic;
@@ -309,6 +378,7 @@ struct tegra_clk_periph_gate {
309#define TEGRA_PERIPH_NO_RESET BIT(0) 378#define TEGRA_PERIPH_NO_RESET BIT(0)
310#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 379#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
311#define TEGRA_PERIPH_ON_APB BIT(2) 380#define TEGRA_PERIPH_ON_APB BIT(2)
381#define TEGRA_PERIPH_WAR_1005168 BIT(3)
312 382
313void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 383void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
314extern const struct clk_ops tegra_clk_periph_gate_ops; 384extern const struct clk_ops tegra_clk_periph_gate_ops;
@@ -349,7 +419,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
349struct clk *tegra_clk_register_periph(const char *name, 419struct clk *tegra_clk_register_periph(const char *name,
350 const char **parent_names, int num_parents, 420 const char **parent_names, int num_parents,
351 struct tegra_clk_periph *periph, void __iomem *clk_base, 421 struct tegra_clk_periph *periph, void __iomem *clk_base,
352 u32 offset); 422 u32 offset, unsigned long flags);
353struct clk *tegra_clk_register_periph_nodiv(const char *name, 423struct clk *tegra_clk_register_periph_nodiv(const char *name,
354 const char **parent_names, int num_parents, 424 const char **parent_names, int num_parents,
355 struct tegra_clk_periph *periph, void __iomem *clk_base, 425 struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -392,12 +462,14 @@ struct tegra_periph_init_data {
392 u32 offset; 462 u32 offset;
393 const char *con_id; 463 const char *con_id;
394 const char *dev_id; 464 const char *dev_id;
465 unsigned long flags;
395}; 466};
396 467
397#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 468#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
398 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 469 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
399 _div_width, _div_frac_width, _div_flags, _regs, \ 470 _div_width, _div_frac_width, _div_flags, _regs, \
400 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \ 471 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
472 _flags) \
401 { \ 473 { \
402 .name = _name, \ 474 .name = _name, \
403 .clk_id = _clk_id, \ 475 .clk_id = _clk_id, \
@@ -412,6 +484,7 @@ struct tegra_periph_init_data {
412 .offset = _offset, \ 484 .offset = _offset, \
413 .con_id = _con_id, \ 485 .con_id = _con_id, \
414 .dev_id = _dev_id, \ 486 .dev_id = _dev_id, \
487 .flags = _flags \
415 } 488 }
416 489
417#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 490#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
@@ -422,7 +495,7 @@ struct tegra_periph_init_data {
422 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 495 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
423 _div_shift, _div_width, _div_frac_width, _div_flags, \ 496 _div_shift, _div_width, _div_frac_width, _div_flags, \
424 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 497 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
425 NULL) 498 NULL, 0)
426 499
427/** 500/**
428 * struct clk_super_mux - super clock 501 * struct clk_super_mux - super clock
@@ -510,4 +583,13 @@ void tegra30_clock_init(struct device_node *np);
510static inline void tegra30_clock_init(struct device_node *np) {} 583static inline void tegra30_clock_init(struct device_node *np) {}
511#endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 584#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
512 585
586#ifdef CONFIG_ARCH_TEGRA_114_SOC
587void tegra114_clock_init(struct device_node *np);
588#else
589static inline void tegra114_clock_init(struct device_node *np) {}
590#endif /* CONFIG_ARCH_TEGRA114_SOC */
591
592typedef void (*tegra_clk_apply_init_table_func)(void);
593extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
594
513#endif /* TEGRA_CLK_H */ 595#endif /* TEGRA_CLK_H */
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 404d6f940872..642789baec74 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -123,5 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
123void tegra_periph_reset_deassert(struct clk *c); 123void tegra_periph_reset_deassert(struct clk *c);
124void tegra_periph_reset_assert(struct clk *c); 124void tegra_periph_reset_assert(struct clk *c);
125void tegra_clocks_init(void); 125void tegra_clocks_init(void);
126void tegra_clocks_apply_init_table(void);
126 127
127#endif /* __LINUX_CLK_TEGRA_H_ */ 128#endif /* __LINUX_CLK_TEGRA_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 19:15:09 -0400