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authorPatrick Boettcher <pboettcher@kernellabs.com>2009-08-17 04:13:28 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-09-18 23:14:29 -0400
commit2a6a30e05cc4afa4aa4da406ece75e6846d5b408 (patch)
tree6cec75999d37df8b2749b69e67e34e52365a9488
parent7e5ce6515d0deb76a49dcb4112a6dff5d950bfb6 (diff)
V4L/DVB (12899): DiB0070: Indenting driver with indent -linux
In order to follow a little bit the kernel coding style from now on after the generation of that driver file and indent -linux call is emitted. Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/dvb/frontends/dib0070.c768
-rw-r--r--drivers/media/dvb/frontends/dib0070.h31
2 files changed, 405 insertions, 394 deletions
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
index 2eb9bdb4dbb3..2be17b93e0bd 100644
--- a/drivers/media/dvb/frontends/dib0070.c
+++ b/drivers/media/dvb/frontends/dib0070.c
@@ -50,16 +50,16 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
50#define DIB0070S_P1A 0x02 50#define DIB0070S_P1A 0x02
51 51
52enum frontend_tune_state { 52enum frontend_tune_state {
53 CT_TUNER_START = 10, 53 CT_TUNER_START = 10,
54 CT_TUNER_STEP_0, 54 CT_TUNER_STEP_0,
55 CT_TUNER_STEP_1, 55 CT_TUNER_STEP_1,
56 CT_TUNER_STEP_2, 56 CT_TUNER_STEP_2,
57 CT_TUNER_STEP_3, 57 CT_TUNER_STEP_3,
58 CT_TUNER_STEP_4, 58 CT_TUNER_STEP_4,
59 CT_TUNER_STEP_5, 59 CT_TUNER_STEP_5,
60 CT_TUNER_STEP_6, 60 CT_TUNER_STEP_6,
61 CT_TUNER_STEP_7, 61 CT_TUNER_STEP_7,
62 CT_TUNER_STOP, 62 CT_TUNER_STOP,
63}; 63};
64 64
65#define FE_CALLBACK_TIME_NEVER 0xffffffff 65#define FE_CALLBACK_TIME_NEVER 0xffffffff
@@ -71,10 +71,10 @@ struct dib0070_state {
71 u16 wbd_ff_offset; 71 u16 wbd_ff_offset;
72 u8 revision; 72 u8 revision;
73 73
74 enum frontend_tune_state tune_state; 74 enum frontend_tune_state tune_state;
75 u32 current_rf; 75 u32 current_rf;
76 76
77 /* for the captrim binary search */ 77 /* for the captrim binary search */
78 s8 step; 78 s8 step;
79 u16 adc_diff; 79 u16 adc_diff;
80 80
@@ -85,7 +85,7 @@ struct dib0070_state {
85 const struct dib0070_tuning *current_tune_table_index; 85 const struct dib0070_tuning *current_tune_table_index;
86 const struct dib0070_lna_match *lna_match; 86 const struct dib0070_lna_match *lna_match;
87 87
88 u8 wbd_gain_current; 88 u8 wbd_gain_current;
89 u16 wbd_offset_3_3[2]; 89 u16 wbd_offset_3_3[2];
90}; 90};
91 91
@@ -93,8 +93,8 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
93{ 93{
94 u8 b[2]; 94 u8 b[2];
95 struct i2c_msg msg[2] = { 95 struct i2c_msg msg[2] = {
96 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, 96 {.addr = state->cfg->i2c_address,.flags = 0,.buf = &reg,.len = 1},
97 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 }, 97 {.addr = state->cfg->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
98 }; 98 };
99 if (i2c_transfer(state->i2c, msg, 2) != 2) { 99 if (i2c_transfer(state->i2c, msg, 2) != 2) {
100 printk(KERN_WARNING "DiB0070 I2C read failed\n"); 100 printk(KERN_WARNING "DiB0070 I2C read failed\n");
@@ -106,7 +106,7 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
106static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) 106static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
107{ 107{
108 u8 b[3] = { reg, val >> 8, val & 0xff }; 108 u8 b[3] = { reg, val >> 8, val & 0xff };
109 struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 }; 109 struct i2c_msg msg = {.addr = state->cfg->i2c_address,.flags = 0,.buf = b,.len = 3 };
110 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 110 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
111 printk(KERN_WARNING "DiB0070 I2C write failed\n"); 111 printk(KERN_WARNING "DiB0070 I2C write failed\n");
112 return -EREMOTEIO; 112 return -EREMOTEIO;
@@ -124,34 +124,34 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
124 124
125static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 125static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
126{ 126{
127 struct dib0070_state *st = fe->tuner_priv; 127 struct dib0070_state *state = fe->tuner_priv;
128 u16 tmp = dib0070_read_reg(st, 0x02) & 0x3fff; 128 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
129 129
130 if (fe->dtv_property_cache.bandwidth_hz/1000 > 7000) 130 if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 7000)
131 tmp |= (0 << 14); 131 tmp |= (0 << 14);
132 else if (fe->dtv_property_cache.bandwidth_hz/1000 > 6000) 132 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 6000)
133 tmp |= (1 << 14); 133 tmp |= (1 << 14);
134 else if (fe->dtv_property_cache.bandwidth_hz/1000 > 5000) 134 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 5000)
135 tmp |= (2 << 14); 135 tmp |= (2 << 14);
136 else 136 else
137 tmp |= (3 << 14); 137 tmp |= (3 << 14);
138 138
139 dib0070_write_reg(st, 0x02, tmp); 139 dib0070_write_reg(state, 0x02, tmp);
140 140
141 /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */ 141 /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
142 if (fe->dtv_property_cache.delivery_system == SYS_ISDBT) { 142 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
143 u16 value = dib0070_read_reg(st, 0x17); 143 u16 value = dib0070_read_reg(state, 0x17);
144 144
145 dib0070_write_reg(st, 0x17, value & 0xfffc); 145 dib0070_write_reg(state, 0x17, value & 0xfffc);
146 tmp = dib0070_read_reg(st, 0x01) & 0x01ff; 146 tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
147 dib0070_write_reg(st, 0x01, tmp | (60 << 9)); 147 dib0070_write_reg(state, 0x01, tmp | (60 << 9));
148 148
149 dib0070_write_reg(st, 0x17, value); 149 dib0070_write_reg(state, 0x17, value);
150 } 150 }
151 return 0; 151 return 0;
152} 152}
153 153
154static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *tune_state) 154static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
155{ 155{
156 int8_t step_sign; 156 int8_t step_sign;
157 u16 adc; 157 u16 adc;
@@ -159,26 +159,26 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
159 159
160 if (*tune_state == CT_TUNER_STEP_0) { 160 if (*tune_state == CT_TUNER_STEP_0) {
161 161
162 dib0070_write_reg(st, 0x0f, 0xed10); 162 dib0070_write_reg(state, 0x0f, 0xed10);
163 dib0070_write_reg(st, 0x17, 0x0034); 163 dib0070_write_reg(state, 0x17, 0x0034);
164 164
165 dib0070_write_reg(st, 0x18, 0x0032); 165 dib0070_write_reg(state, 0x18, 0x0032);
166 st->step = st->captrim = st->fcaptrim = 64; 166 state->step = state->captrim = state->fcaptrim = 64;
167 st->adc_diff = 3000; 167 state->adc_diff = 3000;
168 ret = 20; 168 ret = 20;
169 169
170 *tune_state = CT_TUNER_STEP_1; 170 *tune_state = CT_TUNER_STEP_1;
171 } else if (*tune_state == CT_TUNER_STEP_1) { 171 } else if (*tune_state == CT_TUNER_STEP_1) {
172 st->step /= 2; 172 state->step /= 2;
173 dib0070_write_reg(st, 0x14, st->lo4 | st->captrim); 173 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
174 ret = 15; 174 ret = 15;
175 175
176 *tune_state = CT_TUNER_STEP_2; 176 *tune_state = CT_TUNER_STEP_2;
177 } else if (*tune_state == CT_TUNER_STEP_2) { 177 } else if (*tune_state == CT_TUNER_STEP_2) {
178 178
179 adc = dib0070_read_reg(st, 0x19); 179 adc = dib0070_read_reg(state, 0x19);
180 180
181 dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", st->captrim, adc, (u32) adc*(u32)1800/(u32)1024); 181 dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc * (u32) 1800 / (u32) 1024);
182 182
183 if (adc >= 400) { 183 if (adc >= 400) {
184 adc -= 400; 184 adc -= 400;
@@ -188,24 +188,22 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
188 step_sign = 1; 188 step_sign = 1;
189 } 189 }
190 190
191 if (adc < st->adc_diff) { 191 if (adc < state->adc_diff) {
192 dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", st->captrim, adc, st->adc_diff); 192 dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
193 st->adc_diff = adc; 193 state->adc_diff = adc;
194 st->fcaptrim = st->captrim; 194 state->fcaptrim = state->captrim;
195
196
197 195
198 } 196 }
199 st->captrim += (step_sign * st->step); 197 state->captrim += (step_sign * state->step);
200 198
201 if (st->step >= 1) 199 if (state->step >= 1)
202 *tune_state = CT_TUNER_STEP_1; 200 *tune_state = CT_TUNER_STEP_1;
203 else 201 else
204 *tune_state = CT_TUNER_STEP_3; 202 *tune_state = CT_TUNER_STEP_3;
205 203
206 } else if (*tune_state == CT_TUNER_STEP_3) { 204 } else if (*tune_state == CT_TUNER_STEP_3) {
207 dib0070_write_reg(st, 0x14, st->lo4 | st->fcaptrim); 205 dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
208 dib0070_write_reg(st, 0x18, 0x07ff); 206 dib0070_write_reg(state, 0x18, 0x07ff);
209 *tune_state = CT_TUNER_STEP_4; 207 *tune_state = CT_TUNER_STEP_4;
210 } 208 }
211 209
@@ -215,374 +213,391 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
215static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt) 213static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
216{ 214{
217 struct dib0070_state *state = fe->tuner_priv; 215 struct dib0070_state *state = fe->tuner_priv;
218 u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); 216 u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
219 dprintk( "CTRL_LO5: 0x%x", lo5); 217 dprintk("CTRL_LO5: 0x%x", lo5);
220 return dib0070_write_reg(state, 0x15, lo5); 218 return dib0070_write_reg(state, 0x15, lo5);
221} 219}
222 220
223struct dib0070_tuning 221void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
224{
225 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
226 u8 switch_trim;
227 u8 vco_band;
228 u8 hfdiv;
229 u8 vco_multi;
230 u8 presc;
231 u8 wbdmux;
232 u16 tuner_enable;
233};
234
235struct dib0070_lna_match
236{ 222{
237 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ 223 struct dib0070_state *state = fe->tuner_priv;
238 u8 lna_band;
239};
240 224
241static const struct dib0070_tuning dib0070s_tuning_table[] = 225 if (open) {
226 dib0070_write_reg(state, 0x1b, 0xff00);
227 dib0070_write_reg(state, 0x1a, 0x0000);
228 } else {
229 dib0070_write_reg(state, 0x1b, 0x4112);
230 if (state->cfg->vga_filter != 0) {
231 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
232 dprintk("vga filter register is set to %x", state->cfg->vga_filter);
233 } else
234 dib0070_write_reg(state, 0x1a, 0x0009);
235 }
236}
242 237
243{ 238EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
244 { 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */ 239struct dib0070_tuning {
245 { 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 }, 240 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
246 { 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 }, 241 u8 switch_trim;
247 { 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */ 242 u8 vco_band;
248 { 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, 243 u8 hfdiv;
249 { 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, 244 u8 vco_multi;
250 { 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */ 245 u8 presc;
246 u8 wbdmux;
247 u16 tuner_enable;
251}; 248};
252 249
253static const struct dib0070_tuning dib0070_tuning_table[] = 250struct dib0070_lna_match {
254 251 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
255{ 252 u8 lna_band;
256 { 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
257 { 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
258 { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
259 { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
260 { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
261 { 699999, 2, 0 ,1, 4, 2, 2, 0x4000 | 0x0800 },
262 { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
263 { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
264}; 253};
265 254
266static const struct dib0070_lna_match dib0070_lna_flip_chip[] = 255static const struct dib0070_tuning dib0070s_tuning_table[] = {
256 {570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800}, /* UHF */
257 {700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800},
258 {863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800},
259 {1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND */
260 {1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
261 {2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
262 {0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000}, /* SBAND */
263};
267 264
268{ 265static const struct dib0070_tuning dib0070_tuning_table[] = {
269 { 180000, 0 }, /* VHF */ 266 {115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000}, /* FM below 92MHz cannot be tuned */
270 { 188000, 1 }, 267 {179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000}, /* VHF */
271 { 196400, 2 }, 268 {189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000},
272 { 250000, 3 }, 269 {250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000},
273 { 550000, 0 }, /* UHF */ 270 {569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800}, /* UHF */
274 { 590000, 1 }, 271 {699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800},
275 { 666000, 3 }, 272 {863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800},
276 { 864000, 5 }, 273 {0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND or everything higher than UHF */
277 { 1500000, 0 }, /* LBAND or everything higher than UHF */
278 { 1600000, 1 },
279 { 2000000, 3 },
280 { 0xffffffff, 7 },
281}; 274};
282 275
283static const struct dib0070_lna_match dib0070_lna[] = 276static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
277 {180000, 0}, /* VHF */
278 {188000, 1},
279 {196400, 2},
280 {250000, 3},
281 {550000, 0}, /* UHF */
282 {590000, 1},
283 {666000, 3},
284 {864000, 5},
285 {1500000, 0}, /* LBAND or everything higher than UHF */
286 {1600000, 1},
287 {2000000, 3},
288 {0xffffffff, 7},
289};
284 290
285{ 291static const struct dib0070_lna_match dib0070_lna[] = {
286 { 180000, 0 }, /* VHF */ 292 {180000, 0}, /* VHF */
287 { 188000, 1 }, 293 {188000, 1},
288 { 196400, 2 }, 294 {196400, 2},
289 { 250000, 3 }, 295 {250000, 3},
290 { 550000, 2 }, /* UHF */ 296 {550000, 2}, /* UHF */
291 { 650000, 3 }, 297 {650000, 3},
292 { 750000, 5 }, 298 {750000, 5},
293 { 850000, 6 }, 299 {850000, 6},
294 { 864000, 7 }, 300 {864000, 7},
295 { 1500000, 0 }, /* LBAND or everything higher than UHF */ 301 {1500000, 0}, /* LBAND or everything higher than UHF */
296 { 1600000, 1 }, 302 {1600000, 1},
297 { 2000000, 3 }, 303 {2000000, 3},
298 { 0xffffffff, 7 }, 304 {0xffffffff, 7},
299}; 305};
300 306
301#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 307#define LPF 100 // define for the loop filter 100kHz by default 16-07-06
302static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 308static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
303{ 309{
304 struct dib0070_state *st = fe->tuner_priv; 310 struct dib0070_state *state = fe->tuner_priv;
305
306 const struct dib0070_tuning *tune;
307 const struct dib0070_lna_match *lna_match;
308
309 enum frontend_tune_state *tune_state = &st->tune_state;
310 int ret = 10; /* 1ms is the default delay most of the time */
311
312 u8 band = (u8)BAND_OF_FREQUENCY(ch->frequency/1000);
313 u32 freq = ch->frequency/1000 + (band == BAND_VHF ? st->cfg->freq_offset_khz_vhf : st->cfg->freq_offset_khz_uhf);
314
315
316
317 311
312 const struct dib0070_tuning *tune;
313 const struct dib0070_lna_match *lna_match;
318 314
319#ifdef CONFIG_STANDARD_ISDBT 315 enum frontend_tune_state *tune_state = &state->tune_state;
320 if (fe->dtv_property_cache.delivery_system == SYS_ISDBT && ch->u.isdbt.sb_mode == 1) 316 int ret = 10; /* 1ms is the default delay most of the time */
321 if ( ( (ch->u.isdbt.sb_conn_total_seg % 2) && (ch->u.isdbt.sb_wanted_seg == ((ch->u.isdbt.sb_conn_total_seg/2) + 1) ) ) || 317
322 ( ( (ch->u.isdbt.sb_conn_total_seg % 2) == 0) && (ch->u.isdbt.sb_wanted_seg == (ch->u.isdbt.sb_conn_total_seg/2) ) ) || 318 u8 band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
323 ( ( (ch->u.isdbt.sb_conn_total_seg % 2) == 0) && (ch->u.isdbt.sb_wanted_seg == ((ch->u.isdbt.sb_conn_total_seg/2)+1))) ) 319 u32 freq = fe->dtv_property_cache.frequency / 1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
324 freq += 850; 320
321#ifdef CONFIG_SYS_ISDBT
322 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
323 if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
324 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
325 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
326 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
327 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
328 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
329 freq += 850;
325#endif 330#endif
326 if (st->current_rf != freq) { 331 if (state->current_rf != freq) {
327 332
328 switch (st->revision) { 333 switch (state->revision) {
329 case DIB0070S_P1A: 334 case DIB0070S_P1A:
330 tune = dib0070s_tuning_table; 335 tune = dib0070s_tuning_table;
331 lna_match = dib0070_lna; 336 lna_match = dib0070_lna;
332 break; 337 break;
333 default: 338 default:
334 tune = dib0070_tuning_table; 339 tune = dib0070_tuning_table;
335 if (st->cfg->flip_chip) 340 if (state->cfg->flip_chip)
336 lna_match = dib0070_lna_flip_chip; 341 lna_match = dib0070_lna_flip_chip;
337 else 342 else
338 lna_match = dib0070_lna; 343 lna_match = dib0070_lna;
339 break; 344 break;
340 } 345 }
341 while (freq > tune->max_freq) /* find the right one */ 346 while (freq > tune->max_freq) /* find the right one */
342 tune++; 347 tune++;
343 while (freq > lna_match->max_freq) /* find the right one */ 348 while (freq > lna_match->max_freq) /* find the right one */
344 lna_match++; 349 lna_match++;
345
346 st->current_tune_table_index = tune;
347 st->lna_match = lna_match;
348 }
349
350 if (*tune_state == CT_TUNER_START) {
351 dprintk( "Tuning for Band: %hd (%d kHz)", band, freq);
352 if (st->current_rf != freq) {
353 u8 REFDIV;
354 u32 FBDiv, Rest, FREF, VCOF_kHz;
355 u8 Den;
356
357 st->current_rf = freq;
358 st->lo4 = (st->current_tune_table_index->vco_band << 11) | (st->current_tune_table_index->hfdiv << 7);
359
360
361 dib0070_write_reg(st, 0x17, 0x30);
362
363
364 VCOF_kHz = st->current_tune_table_index->vco_multi * freq * 2;
365
366 switch (band) {
367 case BAND_VHF:
368 REFDIV = (u8) ((st->cfg->clock_khz + 9999) / 10000);
369 break;
370 case BAND_FM:
371 REFDIV = (u8) ((st->cfg->clock_khz) / 1000);
372 break;
373 default:
374 REFDIV = (u8) ( st->cfg->clock_khz / 10000);
375 break;
376 }
377 FREF = st->cfg->clock_khz / REFDIV;
378
379
380
381 switch (st->revision) {
382 case DIB0070S_P1A:
383 FBDiv = (VCOF_kHz / st->current_tune_table_index->presc / FREF);
384 Rest = (VCOF_kHz / st->current_tune_table_index->presc) - FBDiv * FREF;
385 break;
386
387 case DIB0070_P1G:
388 case DIB0070_P1F:
389 default:
390 FBDiv = (freq / (FREF / 2));
391 Rest = 2 * freq - FBDiv * FREF;
392 break;
393 }
394
395
396 if (Rest < LPF) Rest = 0;
397 else if (Rest < 2 * LPF) Rest = 2 * LPF;
398 else if (Rest > (FREF - LPF)) { Rest = 0 ; FBDiv += 1; }
399 else if (Rest > (FREF - 2 * LPF)) Rest = FREF - 2 * LPF;
400 Rest = (Rest * 6528) / (FREF / 10);
401
402 Den = 1;
403 if (Rest > 0) {
404 st->lo4 |= (1 << 14) | (1 << 12);
405 Den = 255;
406 }
407
408
409 dib0070_write_reg(st, 0x11, (u16)FBDiv);
410 dib0070_write_reg(st, 0x12, (Den << 8) | REFDIV);
411 dib0070_write_reg(st, 0x13, (u16) Rest);
412
413 if (st->revision == DIB0070S_P1A) {
414
415 if (band == BAND_SBAND) {
416 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
417 dib0070_write_reg(st, 0x1d,0xFFFF);
418 } else
419 dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
420 }
421
422 350
423 dib0070_write_reg(st, 0x20, 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | st->current_tune_table_index->tuner_enable); 351 state->current_tune_table_index = tune;
352 state->lna_match = lna_match;
353 }
424 354
425 dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF); 355 if (*tune_state == CT_TUNER_START) {
426 dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest); 356 dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
427 dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (st->lo4 >> 12) & 0x1); 357 if (state->current_rf != freq) {
428 dprintk( "HFDIV code: %hd", st->current_tune_table_index->hfdiv); 358 u8 REFDIV;
429 dprintk( "VCO = %hd", st->current_tune_table_index->vco_band); 359 u32 FBDiv, Rest, FREF, VCOF_kHz;
430 dprintk( "VCOF: ((%hd*%d) << 1))", st->current_tune_table_index->vco_multi, freq); 360 u8 Den;
361
362 state->current_rf = freq;
363 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
364
365 dib0070_write_reg(state, 0x17, 0x30);
366
367 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
368
369 switch (band) {
370 case BAND_VHF:
371 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
372 break;
373 case BAND_FM:
374 REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
375 break;
376 default:
377 REFDIV = (u8) (state->cfg->clock_khz / 10000);
378 break;
379 }
380 FREF = state->cfg->clock_khz / REFDIV;
381
382 switch (state->revision) {
383 case DIB0070S_P1A:
384 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
385 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
386 break;
387
388 case DIB0070_P1G:
389 case DIB0070_P1F:
390 default:
391 FBDiv = (freq / (FREF / 2));
392 Rest = 2 * freq - FBDiv * FREF;
393 break;
394 }
395
396 if (Rest < LPF)
397 Rest = 0;
398 else if (Rest < 2 * LPF)
399 Rest = 2 * LPF;
400 else if (Rest > (FREF - LPF)) {
401 Rest = 0;
402 FBDiv += 1;
403 } else if (Rest > (FREF - 2 * LPF))
404 Rest = FREF - 2 * LPF;
405 Rest = (Rest * 6528) / (FREF / 10);
406
407 Den = 1;
408 if (Rest > 0) {
409 state->lo4 |= (1 << 14) | (1 << 12);
410 Den = 255;
411 }
412
413 dib0070_write_reg(state, 0x11, (u16) FBDiv);
414 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
415 dib0070_write_reg(state, 0x13, (u16) Rest);
416
417 if (state->revision == DIB0070S_P1A) {
418
419 if (band == BAND_SBAND) {
420 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
421 dib0070_write_reg(state, 0x1d, 0xFFFF);
422 } else
423 dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
424 }
425
426 dib0070_write_reg(state, 0x20,
427 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
428
429 dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
430 dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
431 dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
432 dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
433 dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
434 dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
435
436 *tune_state = CT_TUNER_STEP_0;
437 } else { /* we are already tuned to this frequency - the configuration is correct */
438 ret = 50; /* wakeup time */
439 *tune_state = CT_TUNER_STEP_5;
440 }
441 } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
442
443 ret = dib0070_captrim(state, tune_state);
444
445 } else if (*tune_state == CT_TUNER_STEP_4) {
446 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
447 if (tmp != NULL) {
448 while (freq / 1000 > tmp->freq) /* find the right one */
449 tmp++;
450 dib0070_write_reg(state, 0x0f,
451 (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state->
452 current_tune_table_index->
453 wbdmux << 0));
454 state->wbd_gain_current = tmp->wbd_gain_val;
455 } else {
456 dib0070_write_reg(state, 0x0f,
457 (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
458 wbdmux << 0));
459 state->wbd_gain_current = 6;
460 }
431 461
432 *tune_state = CT_TUNER_STEP_0; 462 dib0070_write_reg(state, 0x06, 0x3fff);
433 } else { /* we are already tuned to this frequency - the configuration is correct */ 463 dib0070_write_reg(state, 0x07,
434 ret = 50; /* wakeup time */ 464 (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
435 *tune_state = CT_TUNER_STEP_5; 465 dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
436 } 466 dib0070_write_reg(state, 0x0d, 0x0d80);
437 } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
438 467
439 ret = dib0070_captrim(st, tune_state); 468 dib0070_write_reg(state, 0x18, 0x07ff);
469 dib0070_write_reg(state, 0x17, 0x0033);
440 470
441 } else if (*tune_state == CT_TUNER_STEP_4) { 471 *tune_state = CT_TUNER_STEP_5;
442 const struct dib0070_wbd_gain_cfg *tmp = st->cfg->wbd_gain; 472 } else if (*tune_state == CT_TUNER_STEP_5) {
443 if (tmp != NULL) { 473 dib0070_set_bandwidth(fe, ch);
444 while (freq/1000 > tmp->freq) /* find the right one */ 474 *tune_state = CT_TUNER_STOP;
445 tmp++;
446 dib0070_write_reg(st, 0x0f, (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (st->current_tune_table_index->wbdmux << 0));
447 st->wbd_gain_current = tmp->wbd_gain_val;
448 } else { 475 } else {
449 dib0070_write_reg(st, 0x0f, (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (st->current_tune_table_index->wbdmux << 0)); 476 ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
450 st->wbd_gain_current = 6;
451 } 477 }
452 478 return ret;
453 dib0070_write_reg(st, 0x06, 0x3fff);
454 dib0070_write_reg(st, 0x07, (st->current_tune_table_index->switch_trim << 11) | (7 << 8) | (st->lna_match->lna_band << 3) | (3 << 0));
455 dib0070_write_reg(st, 0x08, (st->lna_match->lna_band << 10) | (3 << 7) | (127));
456 dib0070_write_reg(st, 0x0d, 0x0d80);
457
458
459 dib0070_write_reg(st, 0x18, 0x07ff);
460 dib0070_write_reg(st, 0x17, 0x0033);
461
462
463 *tune_state = CT_TUNER_STEP_5;
464 } else if (*tune_state == CT_TUNER_STEP_5) {
465 dib0070_set_bandwidth(fe, ch);
466 *tune_state = CT_TUNER_STOP;
467 } else {
468 ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
469 }
470 return ret;
471} 479}
472 480
473
474static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 481static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
475{ 482{
476 struct dib0070_state *state = fe->tuner_priv; 483 struct dib0070_state *state = fe->tuner_priv;
477 uint32_t ret; 484 uint32_t ret;
478 485
479 state->tune_state = CT_TUNER_START; 486 state->tune_state = CT_TUNER_START;
480 487
481 do { 488 do {
482 ret = dib0070_tune_digital(fe, p); 489 ret = dib0070_tune_digital(fe, p);
483 if (ret != FE_CALLBACK_TIME_NEVER) 490 if (ret != FE_CALLBACK_TIME_NEVER)
484 msleep(ret/10); 491 msleep(ret / 10);
485 else 492 else
486 break; 493 break;
487 } while (state->tune_state != CT_TUNER_STOP); 494 } while (state->tune_state != CT_TUNER_STOP);
488 495
489 return 0; 496 return 0;
490} 497}
491 498
492static int dib0070_wakeup(struct dvb_frontend *fe) 499static int dib0070_wakeup(struct dvb_frontend *fe)
493{ 500{
494 struct dib0070_state *st = fe->tuner_priv; 501 struct dib0070_state *state = fe->tuner_priv;
495 if (st->cfg->sleep) 502 if (state->cfg->sleep)
496 st->cfg->sleep(fe, 0); 503 state->cfg->sleep(fe, 0);
497 return 0; 504 return 0;
498} 505}
499 506
500static int dib0070_sleep(struct dvb_frontend *fe) 507static int dib0070_sleep(struct dvb_frontend *fe)
501{ 508{
502 struct dib0070_state *st = fe->tuner_priv; 509 struct dib0070_state *state = fe->tuner_priv;
503 if (st->cfg->sleep) 510 if (state->cfg->sleep)
504 st->cfg->sleep(fe, 1); 511 state->cfg->sleep(fe, 1);
505 return 0; 512 return 0;
506} 513}
507 514
508static const u16 dib0070_p1f_defaults[] = 515static const u16 dib0070_p1f_defaults[] = {
509
510{
511 7, 0x02, 516 7, 0x02,
512 0x0008, 517 0x0008,
513 0x0000, 518 0x0000,
514 0x0000, 519 0x0000,
515 0x0000, 520 0x0000,
516 0x0000, 521 0x0000,
517 0x0002, 522 0x0002,
518 0x0100, 523 0x0100,
519 524
520 3, 0x0d, 525 3, 0x0d,
521 0x0d80, 526 0x0d80,
522 0x0001, 527 0x0001,
523 0x0000, 528 0x0000,
524 529
525 4, 0x11, 530 4, 0x11,
526 0x0000, 531 0x0000,
527 0x0103, 532 0x0103,
528 0x0000, 533 0x0000,
529 0x0000, 534 0x0000,
530 535
531 3, 0x16, 536 3, 0x16,
532 0x0004 | 0x0040, 537 0x0004 | 0x0040,
533 0x0030, 538 0x0030,
534 0x07ff, 539 0x07ff,
535 540
536 6, 0x1b, 541 6, 0x1b,
537 0x4112, 542 0x4112,
538 0xff00, 543 0xff00,
539 0xc07f, 544 0xc07f,
540 0x0000, 545 0x0000,
541 0x0180, 546 0x0180,
542 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001, 547 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
543 548
544 0, 549 0,
545}; 550};
546 551
547static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain) 552static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
548{ 553{
549 u16 tuner_en = dib0070_read_reg(state, 0x20); 554 u16 tuner_en = dib0070_read_reg(state, 0x20);
550 u16 offset; 555 u16 offset;
551 556
552 dib0070_write_reg(state, 0x18, 0x07ff); 557 dib0070_write_reg(state, 0x18, 0x07ff);
553 dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001); 558 dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
554 dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0)); 559 dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
555 msleep(9); 560 msleep(9);
556 offset = dib0070_read_reg(state, 0x19); 561 offset = dib0070_read_reg(state, 0x19);
557 dib0070_write_reg(state, 0x20, tuner_en); 562 dib0070_write_reg(state, 0x20, tuner_en);
558 return offset; 563 return offset;
559} 564}
560 565
561static void dib0070_wbd_offset_calibration(struct dib0070_state *state) 566static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
562{ 567{
563 u8 gain; 568 u8 gain;
564 for (gain = 6; gain < 8; gain++) { 569 for (gain = 6; gain < 8; gain++) {
565 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); 570 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
566 dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); 571 dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain - 6]);
567 } 572 }
568} 573}
569 574
570u16 dib0070_wbd_offset(struct dvb_frontend *fe) 575u16 dib0070_wbd_offset(struct dvb_frontend *fe)
571{ 576{
572 struct dib0070_state *st = fe->tuner_priv; 577 struct dib0070_state *state = fe->tuner_priv;
573 return st->wbd_offset_3_3[st->wbd_gain_current - 6]; 578 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
579 u32 freq = fe->dtv_property_cache.frequency / 1000;
580
581 if (tmp != NULL) {
582 while (freq / 1000 > tmp->freq) /* find the right one */
583 tmp++;
584 state->wbd_gain_current = tmp->wbd_gain_val;
585 } else
586 state->wbd_gain_current = 6;
587
588 return state->wbd_offset_3_3[state->wbd_gain_current - 6];
574} 589}
575 590
576EXPORT_SYMBOL(dib0070_wbd_offset); 591EXPORT_SYMBOL(dib0070_wbd_offset);
592
577#define pgm_read_word(w) (*w) 593#define pgm_read_word(w) (*w)
578static int dib0070_reset(struct dvb_frontend *fe) 594static int dib0070_reset(struct dvb_frontend *fe)
579{ 595{
580 struct dib0070_state *state = fe->tuner_priv; 596 struct dib0070_state *state = fe->tuner_priv;
581 u16 l, r, *n; 597 u16 l, r, *n;
582 598
583 HARD_RESET(state); 599 HARD_RESET(state);
584 600
585
586#ifndef FORCE_SBAND_TUNER 601#ifndef FORCE_SBAND_TUNER
587 if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1) 602 if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
588 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff; 603 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
@@ -590,13 +605,13 @@ static int dib0070_reset(struct dvb_frontend *fe)
590#else 605#else
591#warning forcing SBAND 606#warning forcing SBAND
592#endif 607#endif
593 state->revision = DIB0070S_P1A; 608 state->revision = DIB0070S_P1A;
594 609
595 /* P1F or not */ 610 /* P1F or not */
596 dprintk( "Revision: %x", state->revision); 611 dprintk("Revision: %x", state->revision);
597 612
598 if (state->revision == DIB0070_P1D) { 613 if (state->revision == DIB0070_P1D) {
599 dprintk( "Error: this driver is not to be used meant for P1D or earlier"); 614 dprintk("Error: this driver is not to be used meant for P1D or earlier");
600 return -EINVAL; 615 return -EINVAL;
601 } 616 }
602 617
@@ -605,7 +620,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
605 while (l) { 620 while (l) {
606 r = pgm_read_word(n++); 621 r = pgm_read_word(n++);
607 do { 622 do {
608 dib0070_write_reg(state, (u8)r, pgm_read_word(n++)); 623 dib0070_write_reg(state, (u8) r, pgm_read_word(n++));
609 r++; 624 r++;
610 } while (--l); 625 } while (--l);
611 l = pgm_read_word(n++); 626 l = pgm_read_word(n++);
@@ -618,7 +633,6 @@ static int dib0070_reset(struct dvb_frontend *fe)
618 else 633 else
619 r = 2; 634 r = 2;
620 635
621
622 r |= state->cfg->osc_buffer_state << 3; 636 r |= state->cfg->osc_buffer_state << 3;
623 637
624 dib0070_write_reg(state, 0x10, r); 638 dib0070_write_reg(state, 0x10, r);
@@ -629,19 +643,18 @@ static int dib0070_reset(struct dvb_frontend *fe)
629 dib0070_write_reg(state, 0x02, r | (1 << 5)); 643 dib0070_write_reg(state, 0x02, r | (1 << 5));
630 } 644 }
631 645
632 if (state->revision == DIB0070S_P1A) 646 if (state->revision == DIB0070S_P1A)
633 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); 647 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
634 else 648 else
635 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter); 649 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter);
636 650
637 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8); 651 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
638 652
639 dib0070_wbd_offset_calibration(state); 653 dib0070_wbd_offset_calibration(state);
640 654
641 return 0; 655 return 0;
642} 656}
643 657
644
645static int dib0070_release(struct dvb_frontend *fe) 658static int dib0070_release(struct dvb_frontend *fe)
646{ 659{
647 kfree(fe->tuner_priv); 660 kfree(fe->tuner_priv);
@@ -651,22 +664,22 @@ static int dib0070_release(struct dvb_frontend *fe)
651 664
652static const struct dvb_tuner_ops dib0070_ops = { 665static const struct dvb_tuner_ops dib0070_ops = {
653 .info = { 666 .info = {
654 .name = "DiBcom DiB0070", 667 .name = "DiBcom DiB0070",
655 .frequency_min = 45000000, 668 .frequency_min = 45000000,
656 .frequency_max = 860000000, 669 .frequency_max = 860000000,
657 .frequency_step = 1000, 670 .frequency_step = 1000,
658 }, 671 },
659 .release = dib0070_release, 672 .release = dib0070_release,
660 673
661 .init = dib0070_wakeup, 674 .init = dib0070_wakeup,
662 .sleep = dib0070_sleep, 675 .sleep = dib0070_sleep,
663 .set_params = dib0070_tune, 676 .set_params = dib0070_tune,
664 677
665// .get_frequency = dib0070_get_frequency, 678// .get_frequency = dib0070_get_frequency,
666// .get_bandwidth = dib0070_get_bandwidth 679// .get_bandwidth = dib0070_get_bandwidth
667}; 680};
668 681
669struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) 682struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
670{ 683{
671 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); 684 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
672 if (state == NULL) 685 if (state == NULL)
@@ -674,7 +687,7 @@ struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
674 687
675 state->cfg = cfg; 688 state->cfg = cfg;
676 state->i2c = i2c; 689 state->i2c = i2c;
677 state->fe = fe; 690 state->fe = fe;
678 fe->tuner_priv = state; 691 fe->tuner_priv = state;
679 692
680 if (dib0070_reset(fe) != 0) 693 if (dib0070_reset(fe) != 0)
@@ -686,11 +699,12 @@ struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
686 fe->tuner_priv = state; 699 fe->tuner_priv = state;
687 return fe; 700 return fe;
688 701
689free_mem: 702 free_mem:
690 kfree(state); 703 kfree(state);
691 fe->tuner_priv = NULL; 704 fe->tuner_priv = NULL;
692 return NULL; 705 return NULL;
693} 706}
707
694EXPORT_SYMBOL(dib0070_attach); 708EXPORT_SYMBOL(dib0070_attach);
695 709
696MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 710MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
diff --git a/drivers/media/dvb/frontends/dib0070.h b/drivers/media/dvb/frontends/dib0070.h
index 8c1c51cfaff1..8a2e1e710adb 100644
--- a/drivers/media/dvb/frontends/dib0070.h
+++ b/drivers/media/dvb/frontends/dib0070.h
@@ -16,8 +16,8 @@ struct i2c_adapter;
16#define DEFAULT_DIB0070_I2C_ADDRESS 0x60 16#define DEFAULT_DIB0070_I2C_ADDRESS 0x60
17 17
18struct dib0070_wbd_gain_cfg { 18struct dib0070_wbd_gain_cfg {
19 u16 freq; 19 u16 freq;
20 u16 wbd_gain_val; 20 u16 wbd_gain_val;
21}; 21};
22 22
23struct dib0070_config { 23struct dib0070_config {
@@ -31,32 +31,28 @@ struct dib0070_config {
31 int freq_offset_khz_uhf; 31 int freq_offset_khz_uhf;
32 int freq_offset_khz_vhf; 32 int freq_offset_khz_vhf;
33 33
34 u8 osc_buffer_state; /* 0= normal, 1= tri-state */ 34 u8 osc_buffer_state; /* 0= normal, 1= tri-state */
35 u32 clock_khz; 35 u32 clock_khz;
36 u8 clock_pad_drive; /* (Drive + 1) * 2mA */ 36 u8 clock_pad_drive; /* (Drive + 1) * 2mA */
37 37
38 u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */ 38 u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */
39 39
40 u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */ 40 u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */
41 41
42 u8 flip_chip; 42 u8 flip_chip;
43 u8 enable_third_order_filter; 43 u8 enable_third_order_filter;
44 u8 charge_pump; 44 u8 charge_pump;
45 45
46 const struct dib0070_wbd_gain_cfg * wbd_gain; 46 const struct dib0070_wbd_gain_cfg *wbd_gain;
47 47
48 u8 vga_filter; 48 u8 vga_filter;
49}; 49};
50 50
51#if defined(CONFIG_DVB_TUNER_DIB0070) || (defined(CONFIG_DVB_TUNER_DIB0070_MODULE) && defined(MODULE)) 51#if defined(CONFIG_DVB_TUNER_DIB0070) || (defined(CONFIG_DVB_TUNER_DIB0070_MODULE) && defined(MODULE))
52extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, 52extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg);
53 struct i2c_adapter *i2c,
54 struct dib0070_config *cfg);
55extern u16 dib0070_wbd_offset(struct dvb_frontend *); 53extern u16 dib0070_wbd_offset(struct dvb_frontend *);
56#else 54#else
57static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, 55static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
58 struct i2c_adapter *i2c,
59 struct dib0070_config *cfg)
60{ 56{
61 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 57 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
62 return NULL; 58 return NULL;
@@ -68,5 +64,6 @@ static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe)
68 return -ENODEV; 64 return -ENODEV;
69} 65}
70#endif 66#endif
67extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open);
71 68
72#endif 69#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 09:13:51 -0500