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authorNicolin Chen <Guangyu.Chen@freescale.com>2014-04-11 06:30:09 -0400
committerMark Brown <broonie@linaro.org>2014-04-14 16:46:46 -0400
commit2a266f8b2ae790454edb79cb8c707c9305e0307a (patch)
tree07c098d95ed91bacb084d39d06471879fe83de37
parentf84526cfae46672308a361333c76b724384b61ee (diff)
ASoC: fsl_sai: Use FSL_SAI_xXR() and regmap_update_bits() to simplify code
By doing this, the driver can drop around 50 lines and become neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--sound/soc/fsl/fsl_sai.c101
1 files changed, 25 insertions, 76 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index a25e8884b09d..c5a0e8af8226 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -119,16 +119,8 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
119 int clk_id, unsigned int freq, int fsl_dir) 119 int clk_id, unsigned int freq, int fsl_dir)
120{ 120{
121 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 121 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
122 u32 val_cr2, reg_cr2; 122 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
123 123 u32 val_cr2 = 0;
124 if (fsl_dir == FSL_FMT_TRANSMITTER)
125 reg_cr2 = FSL_SAI_TCR2;
126 else
127 reg_cr2 = FSL_SAI_RCR2;
128
129 regmap_read(sai->regmap, reg_cr2, &val_cr2);
130
131 val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
132 124
133 switch (clk_id) { 125 switch (clk_id) {
134 case FSL_SAI_CLK_BUS: 126 case FSL_SAI_CLK_BUS:
@@ -147,7 +139,8 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
147 return -EINVAL; 139 return -EINVAL;
148 } 140 }
149 141
150 regmap_write(sai->regmap, reg_cr2, val_cr2); 142 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
143 FSL_SAI_CR2_MSEL_MASK, val_cr2);
151 144
152 return 0; 145 return 0;
153} 146}
@@ -179,22 +172,10 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
179 unsigned int fmt, int fsl_dir) 172 unsigned int fmt, int fsl_dir)
180{ 173{
181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 174 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
182 u32 val_cr2, val_cr4, reg_cr2, reg_cr4; 175 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
183 176 u32 val_cr2 = 0, val_cr4 = 0;
184 if (fsl_dir == FSL_FMT_TRANSMITTER) {
185 reg_cr2 = FSL_SAI_TCR2;
186 reg_cr4 = FSL_SAI_TCR4;
187 } else {
188 reg_cr2 = FSL_SAI_RCR2;
189 reg_cr4 = FSL_SAI_RCR4;
190 }
191 177
192 regmap_read(sai->regmap, reg_cr2, &val_cr2); 178 if (!sai->big_endian_data)
193 regmap_read(sai->regmap, reg_cr4, &val_cr4);
194
195 if (sai->big_endian_data)
196 val_cr4 &= ~FSL_SAI_CR4_MF;
197 else
198 val_cr4 |= FSL_SAI_CR4_MF; 179 val_cr4 |= FSL_SAI_CR4_MF;
199 180
200 /* DAI mode */ 181 /* DAI mode */
@@ -215,7 +196,6 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
215 * frame sync asserts with the first bit of the frame. 196 * frame sync asserts with the first bit of the frame.
216 */ 197 */
217 val_cr2 |= FSL_SAI_CR2_BCP; 198 val_cr2 |= FSL_SAI_CR2_BCP;
218 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
219 break; 199 break;
220 case SND_SOC_DAIFMT_DSP_A: 200 case SND_SOC_DAIFMT_DSP_A:
221 /* 201 /*
@@ -225,7 +205,6 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
225 * data word. 205 * data word.
226 */ 206 */
227 val_cr2 |= FSL_SAI_CR2_BCP; 207 val_cr2 |= FSL_SAI_CR2_BCP;
228 val_cr4 &= ~FSL_SAI_CR4_FSP;
229 val_cr4 |= FSL_SAI_CR4_FSE; 208 val_cr4 |= FSL_SAI_CR4_FSE;
230 sai->is_dsp_mode = true; 209 sai->is_dsp_mode = true;
231 break; 210 break;
@@ -235,7 +214,6 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
235 * frame sync asserts with the first bit of the frame. 214 * frame sync asserts with the first bit of the frame.
236 */ 215 */
237 val_cr2 |= FSL_SAI_CR2_BCP; 216 val_cr2 |= FSL_SAI_CR2_BCP;
238 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
239 sai->is_dsp_mode = true; 217 sai->is_dsp_mode = true;
240 break; 218 break;
241 case SND_SOC_DAIFMT_RIGHT_J: 219 case SND_SOC_DAIFMT_RIGHT_J:
@@ -273,23 +251,22 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
273 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 251 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
274 break; 252 break;
275 case SND_SOC_DAIFMT_CBM_CFM: 253 case SND_SOC_DAIFMT_CBM_CFM:
276 val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
277 val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
278 break; 254 break;
279 case SND_SOC_DAIFMT_CBS_CFM: 255 case SND_SOC_DAIFMT_CBS_CFM:
280 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 256 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
281 val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
282 break; 257 break;
283 case SND_SOC_DAIFMT_CBM_CFS: 258 case SND_SOC_DAIFMT_CBM_CFS:
284 val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
285 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 259 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
286 break; 260 break;
287 default: 261 default:
288 return -EINVAL; 262 return -EINVAL;
289 } 263 }
290 264
291 regmap_write(sai->regmap, reg_cr2, val_cr2); 265 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
292 regmap_write(sai->regmap, reg_cr4, val_cr4); 266 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
267 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
268 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
269 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
293 270
294 return 0; 271 return 0;
295} 272}
@@ -316,29 +293,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
316 struct snd_soc_dai *cpu_dai) 293 struct snd_soc_dai *cpu_dai)
317{ 294{
318 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 295 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
319 u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr; 296 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
320 unsigned int channels = params_channels(params); 297 unsigned int channels = params_channels(params);
321 u32 word_width = snd_pcm_format_width(params_format(params)); 298 u32 word_width = snd_pcm_format_width(params_format(params));
322 299 u32 val_cr4 = 0, val_cr5 = 0;
323 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
324 reg_cr4 = FSL_SAI_TCR4;
325 reg_cr5 = FSL_SAI_TCR5;
326 reg_mr = FSL_SAI_TMR;
327 } else {
328 reg_cr4 = FSL_SAI_RCR4;
329 reg_cr5 = FSL_SAI_RCR5;
330 reg_mr = FSL_SAI_RMR;
331 }
332
333 regmap_read(sai->regmap, reg_cr4, &val_cr4);
334 regmap_read(sai->regmap, reg_cr4, &val_cr5);
335
336 val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
337 val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;
338
339 val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
340 val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
341 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
342 300
343 if (!sai->is_dsp_mode) 301 if (!sai->is_dsp_mode)
344 val_cr4 |= FSL_SAI_CR4_SYWD(word_width); 302 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
@@ -346,18 +304,20 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
346 val_cr5 |= FSL_SAI_CR5_WNW(word_width); 304 val_cr5 |= FSL_SAI_CR5_WNW(word_width);
347 val_cr5 |= FSL_SAI_CR5_W0W(word_width); 305 val_cr5 |= FSL_SAI_CR5_W0W(word_width);
348 306
349 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
350 if (sai->big_endian_data) 307 if (sai->big_endian_data)
351 val_cr5 |= FSL_SAI_CR5_FBT(0); 308 val_cr5 |= FSL_SAI_CR5_FBT(0);
352 else 309 else
353 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 310 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
354 311
355 val_cr4 |= FSL_SAI_CR4_FRSZ(channels); 312 val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
356 val_mr = ~0UL - ((1 << channels) - 1);
357 313
358 regmap_write(sai->regmap, reg_cr4, val_cr4); 314 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
359 regmap_write(sai->regmap, reg_cr5, val_cr5); 315 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
360 regmap_write(sai->regmap, reg_mr, val_mr); 316 val_cr4);
317 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
318 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
319 FSL_SAI_CR5_FBT_MASK, val_cr5);
320 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
361 321
362 return 0; 322 return 0;
363} 323}
@@ -428,8 +388,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
428 struct snd_soc_dai *cpu_dai) 388 struct snd_soc_dai *cpu_dai)
429{ 389{
430 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 390 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
391 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
431 struct device *dev = &sai->pdev->dev; 392 struct device *dev = &sai->pdev->dev;
432 u32 reg;
433 int ret; 393 int ret;
434 394
435 ret = clk_prepare_enable(sai->bus_clk); 395 ret = clk_prepare_enable(sai->bus_clk);
@@ -438,12 +398,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
438 return ret; 398 return ret;
439 } 399 }
440 400
441 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 401 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
442 reg = FSL_SAI_TCR3;
443 else
444 reg = FSL_SAI_RCR3;
445
446 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
447 FSL_SAI_CR3_TRCE); 402 FSL_SAI_CR3_TRCE);
448 403
449 return 0; 404 return 0;
@@ -453,15 +408,9 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
453 struct snd_soc_dai *cpu_dai) 408 struct snd_soc_dai *cpu_dai)
454{ 409{
455 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 410 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
456 u32 reg; 411 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
457
458 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
459 reg = FSL_SAI_TCR3;
460 else
461 reg = FSL_SAI_RCR3;
462 412
463 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE, 413 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
464 ~FSL_SAI_CR3_TRCE);
465 414
466 clk_disable_unprepare(sai->bus_clk); 415 clk_disable_unprepare(sai->bus_clk);
467} 416}