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authorLothar Waßmann <LW@KARO-electronics.de>2013-08-08 08:51:21 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-08-16 04:26:50 -0400
commit296f8cd3396866a5fbb82c2142e609f5dd56c5ca (patch)
tree965b4e23dd5634e950e0a5462e517ab7e7db115a
parent07a3ce7f4b99c765508cdd275325c1cf3bc8f076 (diff)
ARM: dts: mxs: add labels to most nodes for easier reference
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx28.dtsi48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e8e5d491d4e2..546fd7a51c1f 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -64,7 +64,7 @@
64 reg = <0x80000000 0x2000>; 64 reg = <0x80000000 0x2000>;
65 }; 65 };
66 66
67 hsadc@80002000 { 67 hsadc: hsadc@80002000 {
68 reg = <0x80002000 0x2000>; 68 reg = <0x80002000 0x2000>;
69 interrupts = <13>; 69 interrupts = <13>;
70 dmas = <&dma_apbh 12>; 70 dmas = <&dma_apbh 12>;
@@ -88,13 +88,13 @@
88 clocks = <&clks 25>; 88 clocks = <&clks 25>;
89 }; 89 };
90 90
91 perfmon@80006000 { 91 perfmon: perfmon@80006000 {
92 reg = <0x80006000 0x800>; 92 reg = <0x80006000 0x800>;
93 interrupts = <27>; 93 interrupts = <27>;
94 status = "disabled"; 94 status = "disabled";
95 }; 95 };
96 96
97 gpmi-nand@8000c000 { 97 gpmi: gpmi-nand@8000c000 {
98 compatible = "fsl,imx28-gpmi-nand"; 98 compatible = "fsl,imx28-gpmi-nand";
99 #address-cells = <1>; 99 #address-cells = <1>;
100 #size-cells = <1>; 100 #size-cells = <1>;
@@ -153,7 +153,7 @@
153 status = "disabled"; 153 status = "disabled";
154 }; 154 };
155 155
156 pinctrl@80018000 { 156 pinctrl: pinctrl@80018000 {
157 #address-cells = <1>; 157 #address-cells = <1>;
158 #size-cells = <0>; 158 #size-cells = <0>;
159 compatible = "fsl,imx28-pinctrl", "simple-bus"; 159 compatible = "fsl,imx28-pinctrl", "simple-bus";
@@ -702,14 +702,14 @@
702 }; 702 };
703 }; 703 };
704 704
705 digctl@8001c000 { 705 digctl: digctl@8001c000 {
706 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; 706 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
707 reg = <0x8001c000 0x2000>; 707 reg = <0x8001c000 0x2000>;
708 interrupts = <89>; 708 interrupts = <89>;
709 status = "disabled"; 709 status = "disabled";
710 }; 710 };
711 711
712 etm@80022000 { 712 etm: etm@80022000 {
713 reg = <0x80022000 0x2000>; 713 reg = <0x80022000 0x2000>;
714 status = "disabled"; 714 status = "disabled";
715 }; 715 };
@@ -730,19 +730,19 @@
730 clocks = <&clks 26>; 730 clocks = <&clks 26>;
731 }; 731 };
732 732
733 dcp@80028000 { 733 dcp: dcp@80028000 {
734 reg = <0x80028000 0x2000>; 734 reg = <0x80028000 0x2000>;
735 interrupts = <52 53 54>; 735 interrupts = <52 53 54>;
736 compatible = "fsl-dcp"; 736 compatible = "fsl-dcp";
737 }; 737 };
738 738
739 pxp@8002a000 { 739 pxp: pxp@8002a000 {
740 reg = <0x8002a000 0x2000>; 740 reg = <0x8002a000 0x2000>;
741 interrupts = <39>; 741 interrupts = <39>;
742 status = "disabled"; 742 status = "disabled";
743 }; 743 };
744 744
745 ocotp@8002c000 { 745 ocotp: ocotp@8002c000 {
746 compatible = "fsl,ocotp"; 746 compatible = "fsl,ocotp";
747 reg = <0x8002c000 0x2000>; 747 reg = <0x8002c000 0x2000>;
748 status = "disabled"; 748 status = "disabled";
@@ -753,7 +753,7 @@
753 status = "disabled"; 753 status = "disabled";
754 }; 754 };
755 755
756 lcdif@80030000 { 756 lcdif: lcdif@80030000 {
757 compatible = "fsl,imx28-lcdif"; 757 compatible = "fsl,imx28-lcdif";
758 reg = <0x80030000 0x2000>; 758 reg = <0x80030000 0x2000>;
759 interrupts = <38>; 759 interrupts = <38>;
@@ -781,37 +781,37 @@
781 status = "disabled"; 781 status = "disabled";
782 }; 782 };
783 783
784 simdbg@8003c000 { 784 simdbg: simdbg@8003c000 {
785 reg = <0x8003c000 0x200>; 785 reg = <0x8003c000 0x200>;
786 status = "disabled"; 786 status = "disabled";
787 }; 787 };
788 788
789 simgpmisel@8003c200 { 789 simgpmisel: simgpmisel@8003c200 {
790 reg = <0x8003c200 0x100>; 790 reg = <0x8003c200 0x100>;
791 status = "disabled"; 791 status = "disabled";
792 }; 792 };
793 793
794 simsspsel@8003c300 { 794 simsspsel: simsspsel@8003c300 {
795 reg = <0x8003c300 0x100>; 795 reg = <0x8003c300 0x100>;
796 status = "disabled"; 796 status = "disabled";
797 }; 797 };
798 798
799 simmemsel@8003c400 { 799 simmemsel: simmemsel@8003c400 {
800 reg = <0x8003c400 0x100>; 800 reg = <0x8003c400 0x100>;
801 status = "disabled"; 801 status = "disabled";
802 }; 802 };
803 803
804 gpiomon@8003c500 { 804 gpiomon: gpiomon@8003c500 {
805 reg = <0x8003c500 0x100>; 805 reg = <0x8003c500 0x100>;
806 status = "disabled"; 806 status = "disabled";
807 }; 807 };
808 808
809 simenet@8003c700 { 809 simenet: simenet@8003c700 {
810 reg = <0x8003c700 0x100>; 810 reg = <0x8003c700 0x100>;
811 status = "disabled"; 811 status = "disabled";
812 }; 812 };
813 813
814 armjtag@8003c800 { 814 armjtag: armjtag@8003c800 {
815 reg = <0x8003c800 0x100>; 815 reg = <0x8003c800 0x100>;
816 status = "disabled"; 816 status = "disabled";
817 }; 817 };
@@ -841,7 +841,7 @@
841 status = "disabled"; 841 status = "disabled";
842 }; 842 };
843 843
844 power@80044000 { 844 power: power@80044000 {
845 reg = <0x80044000 0x2000>; 845 reg = <0x80044000 0x2000>;
846 status = "disabled"; 846 status = "disabled";
847 }; 847 };
@@ -856,7 +856,7 @@
856 status = "disabled"; 856 status = "disabled";
857 }; 857 };
858 858
859 lradc@80050000 { 859 lradc: lradc@80050000 {
860 compatible = "fsl,imx28-lradc"; 860 compatible = "fsl,imx28-lradc";
861 reg = <0x80050000 0x2000>; 861 reg = <0x80050000 0x2000>;
862 interrupts = <10 14 15 16 17 18 19 862 interrupts = <10 14 15 16 17 18 19
@@ -864,7 +864,7 @@
864 status = "disabled"; 864 status = "disabled";
865 }; 865 };
866 866
867 spdif@80054000 { 867 spdif: spdif@80054000 {
868 reg = <0x80054000 0x2000>; 868 reg = <0x80054000 0x2000>;
869 interrupts = <45>; 869 interrupts = <45>;
870 dmas = <&dma_apbx 2>; 870 dmas = <&dma_apbx 2>;
@@ -872,7 +872,7 @@
872 status = "disabled"; 872 status = "disabled";
873 }; 873 };
874 874
875 rtc@80056000 { 875 mxs_rtc: rtc@80056000 {
876 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; 876 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
877 reg = <0x80056000 0x2000>; 877 reg = <0x80056000 0x2000>;
878 interrupts = <29>; 878 interrupts = <29>;
@@ -911,7 +911,7 @@
911 status = "disabled"; 911 status = "disabled";
912 }; 912 };
913 913
914 timrot@80068000 { 914 timer: timrot@80068000 {
915 compatible = "fsl,imx28-timrot", "fsl,timrot"; 915 compatible = "fsl,imx28-timrot", "fsl,timrot";
916 reg = <0x80068000 0x2000>; 916 reg = <0x80068000 0x2000>;
917 interrupts = <48 49 50 51>; 917 interrupts = <48 49 50 51>;
@@ -1018,7 +1018,7 @@
1018 status = "disabled"; 1018 status = "disabled";
1019 }; 1019 };
1020 1020
1021 dflpt@800c0000 { 1021 dflpt: dflpt@800c0000 {
1022 reg = <0x800c0000 0x10000>; 1022 reg = <0x800c0000 0x10000>;
1023 status = "disabled"; 1023 status = "disabled";
1024 }; 1024 };
@@ -1041,7 +1041,7 @@
1041 status = "disabled"; 1041 status = "disabled";
1042 }; 1042 };
1043 1043
1044 switch@800f8000 { 1044 etn_switch: switch@800f8000 {
1045 reg = <0x800f8000 0x8000>; 1045 reg = <0x800f8000 0x8000>;
1046 status = "disabled"; 1046 status = "disabled";
1047 }; 1047 };