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authorAlex Deucher <alexander.deucher@amd.com>2013-04-12 13:52:52 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 10:49:18 -0400
commit2948f5e6c211eccd58b81c15a410d9f3d9cda657 (patch)
tree86324d51dc6edbd9f279a4c955d6444aed23c1c1
parent138e4e16f0e1d7dee8e6d0534147e15c0a3d94d5 (diff)
drm/radeon: properly set up the RLC on ON/LN/TN (v3)
This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/clearstate_cayman.h1081
-rw-r--r--drivers/gpu/drm/radeon/clearstate_defs.h44
-rw-r--r--drivers/gpu/drm/radeon/clearstate_evergreen.h1080
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c339
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h19
-rw-r--r--drivers/gpu/drm/radeon/ni.c141
-rw-r--r--drivers/gpu/drm/radeon/r600.c43
-rw-r--r--drivers/gpu/drm/radeon/r600d.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon.h13
9 files changed, 2721 insertions, 43 deletions
diff --git a/drivers/gpu/drm/radeon/clearstate_cayman.h b/drivers/gpu/drm/radeon/clearstate_cayman.h
new file mode 100644
index 000000000000..c00339440c5e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_cayman.h
@@ -0,0 +1,1081 @@
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24static const u32 SECT_CONTEXT_def_1[] =
25{
26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0, // HOLE
35 0, // HOLE
36 0x00000000, // DB_STENCIL_CLEAR
37 0x00000000, // DB_DEPTH_CLEAR
38 0x00000000, // PA_SC_SCREEN_SCISSOR_TL
39 0x40004000, // PA_SC_SCREEN_SCISSOR_BR
40 0, // HOLE
41 0x00000000, // DB_DEPTH_INFO
42 0x00000000, // DB_Z_INFO
43 0x00000000, // DB_STENCIL_INFO
44 0x00000000, // DB_Z_READ_BASE
45 0x00000000, // DB_STENCIL_READ_BASE
46 0x00000000, // DB_Z_WRITE_BASE
47 0x00000000, // DB_STENCIL_WRITE_BASE
48 0x00000000, // DB_DEPTH_SIZE
49 0x00000000, // DB_DEPTH_SLICE
50 0, // HOLE
51 0, // HOLE
52 0, // HOLE
53 0, // HOLE
54 0, // HOLE
55 0, // HOLE
56 0, // HOLE
57 0, // HOLE
58 0, // HOLE
59 0, // HOLE
60 0, // HOLE
61 0, // HOLE
62 0, // HOLE
63 0, // HOLE
64 0, // HOLE
65 0, // HOLE
66 0, // HOLE
67 0, // HOLE
68 0, // HOLE
69 0, // HOLE
70 0, // HOLE
71 0, // HOLE
72 0, // HOLE
73 0, // HOLE
74 0, // HOLE
75 0, // HOLE
76 0, // HOLE
77 0, // HOLE
78 0, // HOLE
79 0, // HOLE
80 0, // HOLE
81 0, // HOLE
82 0, // HOLE
83 0, // HOLE
84 0, // HOLE
85 0, // HOLE
86 0, // HOLE
87 0, // HOLE
88 0, // HOLE
89 0, // HOLE
90 0, // HOLE
91 0, // HOLE
92 0, // HOLE
93 0, // HOLE
94 0, // HOLE
95 0, // HOLE
96 0, // HOLE
97 0, // HOLE
98 0, // HOLE
99 0, // HOLE
100 0, // HOLE
101 0, // HOLE
102 0, // HOLE
103 0, // HOLE
104 0, // HOLE
105 0, // HOLE
106 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_0
107 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_1
108 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_2
109 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_3
110 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_4
111 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_5
112 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_6
113 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_7
114 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_8
115 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_9
116 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_10
117 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_11
118 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_12
119 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_13
120 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_14
121 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_15
122 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_0
123 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_1
124 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_2
125 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_3
126 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_4
127 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_5
128 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_6
129 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_7
130 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_8
131 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_9
132 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_10
133 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_11
134 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_12
135 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_13
136 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_14
137 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_15
138 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_0
139 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_1
140 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_2
141 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_3
142 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_4
143 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_5
144 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_6
145 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_7
146 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_8
147 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_9
148 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_10
149 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_11
150 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_12
151 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_13
152 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_14
153 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_15
154 0x00000000, // PA_SC_WINDOW_OFFSET
155 0x80000000, // PA_SC_WINDOW_SCISSOR_TL
156 0x40004000, // PA_SC_WINDOW_SCISSOR_BR
157 0x0000ffff, // PA_SC_CLIPRECT_RULE
158 0x00000000, // PA_SC_CLIPRECT_0_TL
159 0x40004000, // PA_SC_CLIPRECT_0_BR
160 0x00000000, // PA_SC_CLIPRECT_1_TL
161 0x40004000, // PA_SC_CLIPRECT_1_BR
162 0x00000000, // PA_SC_CLIPRECT_2_TL
163 0x40004000, // PA_SC_CLIPRECT_2_BR
164 0x00000000, // PA_SC_CLIPRECT_3_TL
165 0x40004000, // PA_SC_CLIPRECT_3_BR
166 0xaa99aaaa, // PA_SC_EDGERULE
167 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
168 0xffffffff, // CB_TARGET_MASK
169 0xffffffff, // CB_SHADER_MASK
170 0x80000000, // PA_SC_GENERIC_SCISSOR_TL
171 0x40004000, // PA_SC_GENERIC_SCISSOR_BR
172 0x00000000, // COHER_DEST_BASE_0
173 0x00000000, // COHER_DEST_BASE_1
174 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
175 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
176 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
177 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
178 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
179 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
180 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
181 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
182 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
183 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
184 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
185 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
186 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
187 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
188 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
189 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
190 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
191 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
192 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
193 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
194 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
195 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
196 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
197 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
198 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
199 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
200 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
201 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
202 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
203 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
204 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
205 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
206 0x00000000, // PA_SC_VPORT_ZMIN_0
207 0x3f800000, // PA_SC_VPORT_ZMAX_0
208 0x00000000, // PA_SC_VPORT_ZMIN_1
209 0x3f800000, // PA_SC_VPORT_ZMAX_1
210 0x00000000, // PA_SC_VPORT_ZMIN_2
211 0x3f800000, // PA_SC_VPORT_ZMAX_2
212 0x00000000, // PA_SC_VPORT_ZMIN_3
213 0x3f800000, // PA_SC_VPORT_ZMAX_3
214 0x00000000, // PA_SC_VPORT_ZMIN_4
215 0x3f800000, // PA_SC_VPORT_ZMAX_4
216 0x00000000, // PA_SC_VPORT_ZMIN_5
217 0x3f800000, // PA_SC_VPORT_ZMAX_5
218 0x00000000, // PA_SC_VPORT_ZMIN_6
219 0x3f800000, // PA_SC_VPORT_ZMAX_6
220 0x00000000, // PA_SC_VPORT_ZMIN_7
221 0x3f800000, // PA_SC_VPORT_ZMAX_7
222 0x00000000, // PA_SC_VPORT_ZMIN_8
223 0x3f800000, // PA_SC_VPORT_ZMAX_8
224 0x00000000, // PA_SC_VPORT_ZMIN_9
225 0x3f800000, // PA_SC_VPORT_ZMAX_9
226 0x00000000, // PA_SC_VPORT_ZMIN_10
227 0x3f800000, // PA_SC_VPORT_ZMAX_10
228 0x00000000, // PA_SC_VPORT_ZMIN_11
229 0x3f800000, // PA_SC_VPORT_ZMAX_11
230 0x00000000, // PA_SC_VPORT_ZMIN_12
231 0x3f800000, // PA_SC_VPORT_ZMAX_12
232 0x00000000, // PA_SC_VPORT_ZMIN_13
233 0x3f800000, // PA_SC_VPORT_ZMAX_13
234 0x00000000, // PA_SC_VPORT_ZMIN_14
235 0x3f800000, // PA_SC_VPORT_ZMAX_14
236 0x00000000, // PA_SC_VPORT_ZMIN_15
237 0x3f800000, // PA_SC_VPORT_ZMAX_15
238 0x00000000, // SX_MISC
239 0x00000000, // SX_SURFACE_SYNC
240 0x00000000, // SX_SCATTER_EXPORT_BASE
241 0x00000000, // SX_SCATTER_EXPORT_SIZE
242 0x00000000, // CP_PERFMON_CNTX_CNTL
243 0x00000000, // CP_RINGID
244 0x00000000, // CP_VMID
245 0, // HOLE
246 0, // HOLE
247 0, // HOLE
248 0, // HOLE
249 0, // HOLE
250 0x00000000, // SQ_VTX_SEMANTIC_0
251 0x00000000, // SQ_VTX_SEMANTIC_1
252 0x00000000, // SQ_VTX_SEMANTIC_2
253 0x00000000, // SQ_VTX_SEMANTIC_3
254 0x00000000, // SQ_VTX_SEMANTIC_4
255 0x00000000, // SQ_VTX_SEMANTIC_5
256 0x00000000, // SQ_VTX_SEMANTIC_6
257 0x00000000, // SQ_VTX_SEMANTIC_7
258 0x00000000, // SQ_VTX_SEMANTIC_8
259 0x00000000, // SQ_VTX_SEMANTIC_9
260 0x00000000, // SQ_VTX_SEMANTIC_10
261 0x00000000, // SQ_VTX_SEMANTIC_11
262 0x00000000, // SQ_VTX_SEMANTIC_12
263 0x00000000, // SQ_VTX_SEMANTIC_13
264 0x00000000, // SQ_VTX_SEMANTIC_14
265 0x00000000, // SQ_VTX_SEMANTIC_15
266 0x00000000, // SQ_VTX_SEMANTIC_16
267 0x00000000, // SQ_VTX_SEMANTIC_17
268 0x00000000, // SQ_VTX_SEMANTIC_18
269 0x00000000, // SQ_VTX_SEMANTIC_19
270 0x00000000, // SQ_VTX_SEMANTIC_20
271 0x00000000, // SQ_VTX_SEMANTIC_21
272 0x00000000, // SQ_VTX_SEMANTIC_22
273 0x00000000, // SQ_VTX_SEMANTIC_23
274 0x00000000, // SQ_VTX_SEMANTIC_24
275 0x00000000, // SQ_VTX_SEMANTIC_25
276 0x00000000, // SQ_VTX_SEMANTIC_26
277 0x00000000, // SQ_VTX_SEMANTIC_27
278 0x00000000, // SQ_VTX_SEMANTIC_28
279 0x00000000, // SQ_VTX_SEMANTIC_29
280 0x00000000, // SQ_VTX_SEMANTIC_30
281 0x00000000, // SQ_VTX_SEMANTIC_31
282 0xffffffff, // VGT_MAX_VTX_INDX
283 0x00000000, // VGT_MIN_VTX_INDX
284 0x00000000, // VGT_INDX_OFFSET
285 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
286 0x00000000, // SX_ALPHA_TEST_CONTROL
287 0x00000000, // CB_BLEND_RED
288 0x00000000, // CB_BLEND_GREEN
289 0x00000000, // CB_BLEND_BLUE
290 0x00000000, // CB_BLEND_ALPHA
291 0, // HOLE
292 0, // HOLE
293 0, // HOLE
294 0x00000000, // DB_STENCILREFMASK
295 0x00000000, // DB_STENCILREFMASK_BF
296 0x00000000, // SX_ALPHA_REF
297 0x00000000, // PA_CL_VPORT_XSCALE
298 0x00000000, // PA_CL_VPORT_XOFFSET
299 0x00000000, // PA_CL_VPORT_YSCALE
300 0x00000000, // PA_CL_VPORT_YOFFSET
301 0x00000000, // PA_CL_VPORT_ZSCALE
302 0x00000000, // PA_CL_VPORT_ZOFFSET
303 0x00000000, // PA_CL_VPORT_XSCALE_1
304 0x00000000, // PA_CL_VPORT_XOFFSET_1
305 0x00000000, // PA_CL_VPORT_YSCALE_1
306 0x00000000, // PA_CL_VPORT_YOFFSET_1
307 0x00000000, // PA_CL_VPORT_ZSCALE_1
308 0x00000000, // PA_CL_VPORT_ZOFFSET_1
309 0x00000000, // PA_CL_VPORT_XSCALE_2
310 0x00000000, // PA_CL_VPORT_XOFFSET_2
311 0x00000000, // PA_CL_VPORT_YSCALE_2
312 0x00000000, // PA_CL_VPORT_YOFFSET_2
313 0x00000000, // PA_CL_VPORT_ZSCALE_2
314 0x00000000, // PA_CL_VPORT_ZOFFSET_2
315 0x00000000, // PA_CL_VPORT_XSCALE_3
316 0x00000000, // PA_CL_VPORT_XOFFSET_3
317 0x00000000, // PA_CL_VPORT_YSCALE_3
318 0x00000000, // PA_CL_VPORT_YOFFSET_3
319 0x00000000, // PA_CL_VPORT_ZSCALE_3
320 0x00000000, // PA_CL_VPORT_ZOFFSET_3
321 0x00000000, // PA_CL_VPORT_XSCALE_4
322 0x00000000, // PA_CL_VPORT_XOFFSET_4
323 0x00000000, // PA_CL_VPORT_YSCALE_4
324 0x00000000, // PA_CL_VPORT_YOFFSET_4
325 0x00000000, // PA_CL_VPORT_ZSCALE_4
326 0x00000000, // PA_CL_VPORT_ZOFFSET_4
327 0x00000000, // PA_CL_VPORT_XSCALE_5
328 0x00000000, // PA_CL_VPORT_XOFFSET_5
329 0x00000000, // PA_CL_VPORT_YSCALE_5
330 0x00000000, // PA_CL_VPORT_YOFFSET_5
331 0x00000000, // PA_CL_VPORT_ZSCALE_5
332 0x00000000, // PA_CL_VPORT_ZOFFSET_5
333 0x00000000, // PA_CL_VPORT_XSCALE_6
334 0x00000000, // PA_CL_VPORT_XOFFSET_6
335 0x00000000, // PA_CL_VPORT_YSCALE_6
336 0x00000000, // PA_CL_VPORT_YOFFSET_6
337 0x00000000, // PA_CL_VPORT_ZSCALE_6
338 0x00000000, // PA_CL_VPORT_ZOFFSET_6
339 0x00000000, // PA_CL_VPORT_XSCALE_7
340 0x00000000, // PA_CL_VPORT_XOFFSET_7
341 0x00000000, // PA_CL_VPORT_YSCALE_7
342 0x00000000, // PA_CL_VPORT_YOFFSET_7
343 0x00000000, // PA_CL_VPORT_ZSCALE_7
344 0x00000000, // PA_CL_VPORT_ZOFFSET_7
345 0x00000000, // PA_CL_VPORT_XSCALE_8
346 0x00000000, // PA_CL_VPORT_XOFFSET_8
347 0x00000000, // PA_CL_VPORT_YSCALE_8
348 0x00000000, // PA_CL_VPORT_YOFFSET_8
349 0x00000000, // PA_CL_VPORT_ZSCALE_8
350 0x00000000, // PA_CL_VPORT_ZOFFSET_8
351 0x00000000, // PA_CL_VPORT_XSCALE_9
352 0x00000000, // PA_CL_VPORT_XOFFSET_9
353 0x00000000, // PA_CL_VPORT_YSCALE_9
354 0x00000000, // PA_CL_VPORT_YOFFSET_9
355 0x00000000, // PA_CL_VPORT_ZSCALE_9
356 0x00000000, // PA_CL_VPORT_ZOFFSET_9
357 0x00000000, // PA_CL_VPORT_XSCALE_10
358 0x00000000, // PA_CL_VPORT_XOFFSET_10
359 0x00000000, // PA_CL_VPORT_YSCALE_10
360 0x00000000, // PA_CL_VPORT_YOFFSET_10
361 0x00000000, // PA_CL_VPORT_ZSCALE_10
362 0x00000000, // PA_CL_VPORT_ZOFFSET_10
363 0x00000000, // PA_CL_VPORT_XSCALE_11
364 0x00000000, // PA_CL_VPORT_XOFFSET_11
365 0x00000000, // PA_CL_VPORT_YSCALE_11
366 0x00000000, // PA_CL_VPORT_YOFFSET_11
367 0x00000000, // PA_CL_VPORT_ZSCALE_11
368 0x00000000, // PA_CL_VPORT_ZOFFSET_11
369 0x00000000, // PA_CL_VPORT_XSCALE_12
370 0x00000000, // PA_CL_VPORT_XOFFSET_12
371 0x00000000, // PA_CL_VPORT_YSCALE_12
372 0x00000000, // PA_CL_VPORT_YOFFSET_12
373 0x00000000, // PA_CL_VPORT_ZSCALE_12
374 0x00000000, // PA_CL_VPORT_ZOFFSET_12
375 0x00000000, // PA_CL_VPORT_XSCALE_13
376 0x00000000, // PA_CL_VPORT_XOFFSET_13
377 0x00000000, // PA_CL_VPORT_YSCALE_13
378 0x00000000, // PA_CL_VPORT_YOFFSET_13
379 0x00000000, // PA_CL_VPORT_ZSCALE_13
380 0x00000000, // PA_CL_VPORT_ZOFFSET_13
381 0x00000000, // PA_CL_VPORT_XSCALE_14
382 0x00000000, // PA_CL_VPORT_XOFFSET_14
383 0x00000000, // PA_CL_VPORT_YSCALE_14
384 0x00000000, // PA_CL_VPORT_YOFFSET_14
385 0x00000000, // PA_CL_VPORT_ZSCALE_14
386 0x00000000, // PA_CL_VPORT_ZOFFSET_14
387 0x00000000, // PA_CL_VPORT_XSCALE_15
388 0x00000000, // PA_CL_VPORT_XOFFSET_15
389 0x00000000, // PA_CL_VPORT_YSCALE_15
390 0x00000000, // PA_CL_VPORT_YOFFSET_15
391 0x00000000, // PA_CL_VPORT_ZSCALE_15
392 0x00000000, // PA_CL_VPORT_ZOFFSET_15
393 0x00000000, // PA_CL_UCP_0_X
394 0x00000000, // PA_CL_UCP_0_Y
395 0x00000000, // PA_CL_UCP_0_Z
396 0x00000000, // PA_CL_UCP_0_W
397 0x00000000, // PA_CL_UCP_1_X
398 0x00000000, // PA_CL_UCP_1_Y
399 0x00000000, // PA_CL_UCP_1_Z
400 0x00000000, // PA_CL_UCP_1_W
401 0x00000000, // PA_CL_UCP_2_X
402 0x00000000, // PA_CL_UCP_2_Y
403 0x00000000, // PA_CL_UCP_2_Z
404 0x00000000, // PA_CL_UCP_2_W
405 0x00000000, // PA_CL_UCP_3_X
406 0x00000000, // PA_CL_UCP_3_Y
407 0x00000000, // PA_CL_UCP_3_Z
408 0x00000000, // PA_CL_UCP_3_W
409 0x00000000, // PA_CL_UCP_4_X
410 0x00000000, // PA_CL_UCP_4_Y
411 0x00000000, // PA_CL_UCP_4_Z
412 0x00000000, // PA_CL_UCP_4_W
413 0x00000000, // PA_CL_UCP_5_X
414 0x00000000, // PA_CL_UCP_5_Y
415 0x00000000, // PA_CL_UCP_5_Z
416 0x00000000, // PA_CL_UCP_5_W
417 0x00000000, // SPI_VS_OUT_ID_0
418 0x00000000, // SPI_VS_OUT_ID_1
419 0x00000000, // SPI_VS_OUT_ID_2
420 0x00000000, // SPI_VS_OUT_ID_3
421 0x00000000, // SPI_VS_OUT_ID_4
422 0x00000000, // SPI_VS_OUT_ID_5
423 0x00000000, // SPI_VS_OUT_ID_6
424 0x00000000, // SPI_VS_OUT_ID_7
425 0x00000000, // SPI_VS_OUT_ID_8
426 0x00000000, // SPI_VS_OUT_ID_9
427 0x00000000, // SPI_PS_INPUT_CNTL_0
428 0x00000000, // SPI_PS_INPUT_CNTL_1
429 0x00000000, // SPI_PS_INPUT_CNTL_2
430 0x00000000, // SPI_PS_INPUT_CNTL_3
431 0x00000000, // SPI_PS_INPUT_CNTL_4
432 0x00000000, // SPI_PS_INPUT_CNTL_5
433 0x00000000, // SPI_PS_INPUT_CNTL_6
434 0x00000000, // SPI_PS_INPUT_CNTL_7
435 0x00000000, // SPI_PS_INPUT_CNTL_8
436 0x00000000, // SPI_PS_INPUT_CNTL_9
437 0x00000000, // SPI_PS_INPUT_CNTL_10
438 0x00000000, // SPI_PS_INPUT_CNTL_11
439 0x00000000, // SPI_PS_INPUT_CNTL_12
440 0x00000000, // SPI_PS_INPUT_CNTL_13
441 0x00000000, // SPI_PS_INPUT_CNTL_14
442 0x00000000, // SPI_PS_INPUT_CNTL_15
443 0x00000000, // SPI_PS_INPUT_CNTL_16
444 0x00000000, // SPI_PS_INPUT_CNTL_17
445 0x00000000, // SPI_PS_INPUT_CNTL_18
446 0x00000000, // SPI_PS_INPUT_CNTL_19
447 0x00000000, // SPI_PS_INPUT_CNTL_20
448 0x00000000, // SPI_PS_INPUT_CNTL_21
449 0x00000000, // SPI_PS_INPUT_CNTL_22
450 0x00000000, // SPI_PS_INPUT_CNTL_23
451 0x00000000, // SPI_PS_INPUT_CNTL_24
452 0x00000000, // SPI_PS_INPUT_CNTL_25
453 0x00000000, // SPI_PS_INPUT_CNTL_26
454 0x00000000, // SPI_PS_INPUT_CNTL_27
455 0x00000000, // SPI_PS_INPUT_CNTL_28
456 0x00000000, // SPI_PS_INPUT_CNTL_29
457 0x00000000, // SPI_PS_INPUT_CNTL_30
458 0x00000000, // SPI_PS_INPUT_CNTL_31
459 0x00000000, // SPI_VS_OUT_CONFIG
460 0x00000001, // SPI_THREAD_GROUPING
461 0x00000002, // SPI_PS_IN_CONTROL_0
462 0x00000000, // SPI_PS_IN_CONTROL_1
463 0x00000000, // SPI_INTERP_CONTROL_0
464 0x00000000, // SPI_INPUT_Z
465 0x00000000, // SPI_FOG_CNTL
466 0x00000000, // SPI_BARYC_CNTL
467 0x00000000, // SPI_PS_IN_CONTROL_2
468 0x00000000, // SPI_COMPUTE_INPUT_CNTL
469 0x00000000, // SPI_COMPUTE_NUM_THREAD_X
470 0x00000000, // SPI_COMPUTE_NUM_THREAD_Y
471 0x00000000, // SPI_COMPUTE_NUM_THREAD_Z
472 0x00000000, // SPI_GPR_MGMT
473 0x00000000, // SPI_LDS_MGMT
474 0x00000000, // SPI_STACK_MGMT
475 0x00000000, // SPI_WAVE_MGMT_1
476 0x00000000, // SPI_WAVE_MGMT_2
477 0, // HOLE
478 0, // HOLE
479 0, // HOLE
480 0, // HOLE
481 0, // HOLE
482 0x00000000, // GDS_ADDR_BASE
483 0x00003fff, // GDS_ADDR_SIZE
484 0, // HOLE
485 0, // HOLE
486 0x00000000, // GDS_ORDERED_COUNT
487 0, // HOLE
488 0, // HOLE
489 0, // HOLE
490 0x00000000, // GDS_APPEND_CONSUME_UAV0
491 0x00000000, // GDS_APPEND_CONSUME_UAV1
492 0x00000000, // GDS_APPEND_CONSUME_UAV2
493 0x00000000, // GDS_APPEND_CONSUME_UAV3
494 0x00000000, // GDS_APPEND_CONSUME_UAV4
495 0x00000000, // GDS_APPEND_CONSUME_UAV5
496 0x00000000, // GDS_APPEND_CONSUME_UAV6
497 0x00000000, // GDS_APPEND_CONSUME_UAV7
498 0x00000000, // GDS_APPEND_CONSUME_UAV8
499 0x00000000, // GDS_APPEND_CONSUME_UAV9
500 0x00000000, // GDS_APPEND_CONSUME_UAV10
501 0x00000000, // GDS_APPEND_CONSUME_UAV11
502 0, // HOLE
503 0, // HOLE
504 0, // HOLE
505 0, // HOLE
506 0x00000000, // CB_BLEND0_CONTROL
507 0x00000000, // CB_BLEND1_CONTROL
508 0x00000000, // CB_BLEND2_CONTROL
509 0x00000000, // CB_BLEND3_CONTROL
510 0x00000000, // CB_BLEND4_CONTROL
511 0x00000000, // CB_BLEND5_CONTROL
512 0x00000000, // CB_BLEND6_CONTROL
513 0x00000000, // CB_BLEND7_CONTROL
514};
515static const u32 SECT_CONTEXT_def_2[] =
516{
517 0x00000000, // PA_CL_POINT_X_RAD
518 0x00000000, // PA_CL_POINT_Y_RAD
519 0x00000000, // PA_CL_POINT_SIZE
520 0x00000000, // PA_CL_POINT_CULL_RAD
521 0x00000000, // VGT_DMA_BASE_HI
522 0x00000000, // VGT_DMA_BASE
523};
524static const u32 SECT_CONTEXT_def_3[] =
525{
526 0x00000000, // DB_DEPTH_CONTROL
527 0x00000000, // DB_EQAA
528 0x00000000, // CB_COLOR_CONTROL
529 0x00000200, // DB_SHADER_CONTROL
530 0x00000000, // PA_CL_CLIP_CNTL
531 0x00000000, // PA_SU_SC_MODE_CNTL
532 0x00000000, // PA_CL_VTE_CNTL
533 0x00000000, // PA_CL_VS_OUT_CNTL
534 0x00000000, // PA_CL_NANINF_CNTL
535 0x00000000, // PA_SU_LINE_STIPPLE_CNTL
536 0x00000000, // PA_SU_LINE_STIPPLE_SCALE
537 0x00000000, // PA_SU_PRIM_FILTER_CNTL
538 0x00000000, // SQ_LSTMP_RING_ITEMSIZE
539 0x00000000, // SQ_HSTMP_RING_ITEMSIZE
540 0, // HOLE
541 0, // HOLE
542 0x00000000, // SQ_PGM_START_PS
543 0x00000000, // SQ_PGM_RESOURCES_PS
544 0x00000000, // SQ_PGM_RESOURCES_2_PS
545 0x00000000, // SQ_PGM_EXPORTS_PS
546 0, // HOLE
547 0, // HOLE
548 0, // HOLE
549 0x00000000, // SQ_PGM_START_VS
550 0x00000000, // SQ_PGM_RESOURCES_VS
551 0x00000000, // SQ_PGM_RESOURCES_2_VS
552 0, // HOLE
553 0, // HOLE
554 0, // HOLE
555 0x00000000, // SQ_PGM_START_GS
556 0x00000000, // SQ_PGM_RESOURCES_GS
557 0x00000000, // SQ_PGM_RESOURCES_2_GS
558 0, // HOLE
559 0, // HOLE
560 0, // HOLE
561 0x00000000, // SQ_PGM_START_ES
562 0x00000000, // SQ_PGM_RESOURCES_ES
563 0x00000000, // SQ_PGM_RESOURCES_2_ES
564 0, // HOLE
565 0, // HOLE
566 0, // HOLE
567 0x00000000, // SQ_PGM_START_FS
568 0x00000000, // SQ_PGM_RESOURCES_FS
569 0, // HOLE
570 0, // HOLE
571 0, // HOLE
572 0x00000000, // SQ_PGM_START_HS
573 0x00000000, // SQ_PGM_RESOURCES_HS
574 0x00000000, // SQ_PGM_RESOURCES_2_HS
575 0, // HOLE
576 0, // HOLE
577 0, // HOLE
578 0x00000000, // SQ_PGM_START_LS
579 0x00000000, // SQ_PGM_RESOURCES_LS
580 0x00000000, // SQ_PGM_RESOURCES_2_LS
581};
582static const u32 SECT_CONTEXT_def_4[] =
583{
584 0x00000000, // SQ_LDS_ALLOC
585 0x00000000, // SQ_LDS_ALLOC_PS
586 0x00000000, // SQ_VTX_SEMANTIC_CLEAR
587 0, // HOLE
588 0x00000000, // SQ_THREAD_TRACE_CTRL
589 0, // HOLE
590 0x00000000, // SQ_ESGS_RING_ITEMSIZE
591 0x00000000, // SQ_GSVS_RING_ITEMSIZE
592 0x00000000, // SQ_ESTMP_RING_ITEMSIZE
593 0x00000000, // SQ_GSTMP_RING_ITEMSIZE
594 0x00000000, // SQ_VSTMP_RING_ITEMSIZE
595 0x00000000, // SQ_PSTMP_RING_ITEMSIZE
596 0, // HOLE
597 0x00000000, // SQ_GS_VERT_ITEMSIZE
598 0x00000000, // SQ_GS_VERT_ITEMSIZE_1
599 0x00000000, // SQ_GS_VERT_ITEMSIZE_2
600 0x00000000, // SQ_GS_VERT_ITEMSIZE_3
601 0x00000000, // SQ_GSVS_RING_OFFSET_1
602 0x00000000, // SQ_GSVS_RING_OFFSET_2
603 0x00000000, // SQ_GSVS_RING_OFFSET_3
604 0x00000000, // SQ_GWS_RING_OFFSET
605 0, // HOLE
606 0x00000000, // SQ_ALU_CONST_CACHE_PS_0
607 0x00000000, // SQ_ALU_CONST_CACHE_PS_1
608 0x00000000, // SQ_ALU_CONST_CACHE_PS_2
609 0x00000000, // SQ_ALU_CONST_CACHE_PS_3
610 0x00000000, // SQ_ALU_CONST_CACHE_PS_4
611 0x00000000, // SQ_ALU_CONST_CACHE_PS_5
612 0x00000000, // SQ_ALU_CONST_CACHE_PS_6
613 0x00000000, // SQ_ALU_CONST_CACHE_PS_7
614 0x00000000, // SQ_ALU_CONST_CACHE_PS_8
615 0x00000000, // SQ_ALU_CONST_CACHE_PS_9
616 0x00000000, // SQ_ALU_CONST_CACHE_PS_10
617 0x00000000, // SQ_ALU_CONST_CACHE_PS_11
618 0x00000000, // SQ_ALU_CONST_CACHE_PS_12
619 0x00000000, // SQ_ALU_CONST_CACHE_PS_13
620 0x00000000, // SQ_ALU_CONST_CACHE_PS_14
621 0x00000000, // SQ_ALU_CONST_CACHE_PS_15
622 0x00000000, // SQ_ALU_CONST_CACHE_VS_0
623 0x00000000, // SQ_ALU_CONST_CACHE_VS_1
624 0x00000000, // SQ_ALU_CONST_CACHE_VS_2
625 0x00000000, // SQ_ALU_CONST_CACHE_VS_3
626 0x00000000, // SQ_ALU_CONST_CACHE_VS_4
627 0x00000000, // SQ_ALU_CONST_CACHE_VS_5
628 0x00000000, // SQ_ALU_CONST_CACHE_VS_6
629 0x00000000, // SQ_ALU_CONST_CACHE_VS_7
630 0x00000000, // SQ_ALU_CONST_CACHE_VS_8
631 0x00000000, // SQ_ALU_CONST_CACHE_VS_9
632 0x00000000, // SQ_ALU_CONST_CACHE_VS_10
633 0x00000000, // SQ_ALU_CONST_CACHE_VS_11
634 0x00000000, // SQ_ALU_CONST_CACHE_VS_12
635 0x00000000, // SQ_ALU_CONST_CACHE_VS_13
636 0x00000000, // SQ_ALU_CONST_CACHE_VS_14
637 0x00000000, // SQ_ALU_CONST_CACHE_VS_15
638 0x00000000, // SQ_ALU_CONST_CACHE_GS_0
639 0x00000000, // SQ_ALU_CONST_CACHE_GS_1
640 0x00000000, // SQ_ALU_CONST_CACHE_GS_2
641 0x00000000, // SQ_ALU_CONST_CACHE_GS_3
642 0x00000000, // SQ_ALU_CONST_CACHE_GS_4
643 0x00000000, // SQ_ALU_CONST_CACHE_GS_5
644 0x00000000, // SQ_ALU_CONST_CACHE_GS_6
645 0x00000000, // SQ_ALU_CONST_CACHE_GS_7
646 0x00000000, // SQ_ALU_CONST_CACHE_GS_8
647 0x00000000, // SQ_ALU_CONST_CACHE_GS_9
648 0x00000000, // SQ_ALU_CONST_CACHE_GS_10
649 0x00000000, // SQ_ALU_CONST_CACHE_GS_11
650 0x00000000, // SQ_ALU_CONST_CACHE_GS_12
651 0x00000000, // SQ_ALU_CONST_CACHE_GS_13
652 0x00000000, // SQ_ALU_CONST_CACHE_GS_14
653 0x00000000, // SQ_ALU_CONST_CACHE_GS_15
654 0x00000000, // PA_SU_POINT_SIZE
655 0x00000000, // PA_SU_POINT_MINMAX
656 0x00000000, // PA_SU_LINE_CNTL
657 0x00000000, // PA_SC_LINE_STIPPLE
658 0x00000000, // VGT_OUTPUT_PATH_CNTL
659 0x00000000, // VGT_HOS_CNTL
660 0x00000000, // VGT_HOS_MAX_TESS_LEVEL
661 0x00000000, // VGT_HOS_MIN_TESS_LEVEL
662 0x00000000, // VGT_HOS_REUSE_DEPTH
663 0x00000000, // VGT_GROUP_PRIM_TYPE
664 0x00000000, // VGT_GROUP_FIRST_DECR
665 0x00000000, // VGT_GROUP_DECR
666 0x00000000, // VGT_GROUP_VECT_0_CNTL
667 0x00000000, // VGT_GROUP_VECT_1_CNTL
668 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
669 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
670 0x00000000, // VGT_GS_MODE
671 0, // HOLE
672 0x00000000, // PA_SC_MODE_CNTL_0
673 0x00000000, // PA_SC_MODE_CNTL_1
674 0x00000000, // VGT_ENHANCE
675 0x00000100, // VGT_GS_PER_ES
676 0x00000080, // VGT_ES_PER_GS
677 0x00000002, // VGT_GS_PER_VS
678 0, // HOLE
679 0, // HOLE
680 0, // HOLE
681 0x00000000, // VGT_GS_OUT_PRIM_TYPE
682 0x00000000, // IA_ENHANCE
683};
684static const u32 SECT_CONTEXT_def_5[] =
685{
686 0x00000000, // VGT_DMA_MAX_SIZE
687 0x00000000, // VGT_DMA_INDEX_TYPE
688 0, // HOLE
689 0x00000000, // VGT_PRIMITIVEID_EN
690 0x00000000, // VGT_DMA_NUM_INSTANCES
691};
692static const u32 SECT_CONTEXT_def_6[] =
693{
694 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
695 0, // HOLE
696 0, // HOLE
697 0x00000000, // VGT_INSTANCE_STEP_RATE_0
698 0x00000000, // VGT_INSTANCE_STEP_RATE_1
699 0x000000ff, // IA_MULTI_VGT_PARAM
700 0, // HOLE
701 0, // HOLE
702 0x00000000, // VGT_REUSE_OFF
703 0x00000000, // VGT_VTX_CNT_EN
704 0x00000000, // DB_HTILE_SURFACE
705 0x00000000, // DB_SRESULTS_COMPARE_STATE0
706 0x00000000, // DB_SRESULTS_COMPARE_STATE1
707 0x00000000, // DB_PRELOAD_CONTROL
708 0, // HOLE
709 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
710 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
711 0x00000000, // VGT_STRMOUT_BUFFER_BASE_0
712 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
713 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
714 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
715 0x00000000, // VGT_STRMOUT_BUFFER_BASE_1
716 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
717 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
718 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
719 0x00000000, // VGT_STRMOUT_BUFFER_BASE_2
720 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
721 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
722 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
723 0x00000000, // VGT_STRMOUT_BUFFER_BASE_3
724 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
725 0x00000000, // VGT_STRMOUT_BASE_OFFSET_0
726 0x00000000, // VGT_STRMOUT_BASE_OFFSET_1
727 0x00000000, // VGT_STRMOUT_BASE_OFFSET_2
728 0x00000000, // VGT_STRMOUT_BASE_OFFSET_3
729 0, // HOLE
730 0, // HOLE
731 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
732 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
733 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
734 0, // HOLE
735 0x00000000, // VGT_GS_MAX_VERT_OUT
736 0, // HOLE
737 0, // HOLE
738 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_0
739 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_1
740 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_2
741 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_3
742 0x00000000, // VGT_SHADER_STAGES_EN
743 0x00000000, // VGT_LS_HS_CONFIG
744 0, // HOLE
745 0, // HOLE
746 0, // HOLE
747 0, // HOLE
748 0x00000000, // VGT_TF_PARAM
749 0x00000000, // DB_ALPHA_TO_MASK
750};
751static const u32 SECT_CONTEXT_def_7[] =
752{
753 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
754 0x00000000, // PA_SU_POLY_OFFSET_CLAMP
755 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
756 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
757 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
758 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
759 0x00000000, // VGT_GS_INSTANCE_CNT
760 0x00000000, // VGT_STRMOUT_CONFIG
761 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
762 0x00000000, // CB_IMMED0_BASE
763 0x00000000, // CB_IMMED1_BASE
764 0x00000000, // CB_IMMED2_BASE
765 0x00000000, // CB_IMMED3_BASE
766 0x00000000, // CB_IMMED4_BASE
767 0x00000000, // CB_IMMED5_BASE
768 0x00000000, // CB_IMMED6_BASE
769 0x00000000, // CB_IMMED7_BASE
770 0x00000000, // CB_IMMED8_BASE
771 0x00000000, // CB_IMMED9_BASE
772 0x00000000, // CB_IMMED10_BASE
773 0x00000000, // CB_IMMED11_BASE
774 0, // HOLE
775 0, // HOLE
776 0x00000000, // PA_SC_CENTROID_PRIORITY_0
777 0x00000000, // PA_SC_CENTROID_PRIORITY_1
778 0x00001000, // PA_SC_LINE_CNTL
779 0x00000000, // PA_SC_AA_CONFIG
780 0x00000005, // PA_SU_VTX_CNTL
781 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
782 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
783 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
784 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
785 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
786 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
787 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
788 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
789 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
790 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
791 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
792 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
793 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
794 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
795 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
796 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
797 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
798 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
799 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
800 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
801 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
802 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
803 0x00000000, // CB_CLRCMP_CONTROL
804 0x00000000, // CB_CLRCMP_SRC
805 0x00000000, // CB_CLRCMP_DST
806 0x00000000, // CB_CLRCMP_MSK
807 0, // HOLE
808 0, // HOLE
809 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
810 0x00000010, // VGT_OUT_DEALLOC_CNTL
811 0x00000000, // CB_COLOR0_BASE
812 0x00000000, // CB_COLOR0_PITCH
813 0x00000000, // CB_COLOR0_SLICE
814 0x00000000, // CB_COLOR0_VIEW
815 0x00000000, // CB_COLOR0_INFO
816 0x00000000, // CB_COLOR0_ATTRIB
817 0x00000000, // CB_COLOR0_DIM
818 0x00000000, // CB_COLOR0_CMASK
819 0x00000000, // CB_COLOR0_CMASK_SLICE
820 0x00000000, // CB_COLOR0_FMASK
821 0x00000000, // CB_COLOR0_FMASK_SLICE
822 0x00000000, // CB_COLOR0_CLEAR_WORD0
823 0x00000000, // CB_COLOR0_CLEAR_WORD1
824 0x00000000, // CB_COLOR0_CLEAR_WORD2
825 0x00000000, // CB_COLOR0_CLEAR_WORD3
826 0x00000000, // CB_COLOR1_BASE
827 0x00000000, // CB_COLOR1_PITCH
828 0x00000000, // CB_COLOR1_SLICE
829 0x00000000, // CB_COLOR1_VIEW
830 0x00000000, // CB_COLOR1_INFO
831 0x00000000, // CB_COLOR1_ATTRIB
832 0x00000000, // CB_COLOR1_DIM
833 0x00000000, // CB_COLOR1_CMASK
834 0x00000000, // CB_COLOR1_CMASK_SLICE
835 0x00000000, // CB_COLOR1_FMASK
836 0x00000000, // CB_COLOR1_FMASK_SLICE
837 0x00000000, // CB_COLOR1_CLEAR_WORD0
838 0x00000000, // CB_COLOR1_CLEAR_WORD1
839 0x00000000, // CB_COLOR1_CLEAR_WORD2
840 0x00000000, // CB_COLOR1_CLEAR_WORD3
841 0x00000000, // CB_COLOR2_BASE
842 0x00000000, // CB_COLOR2_PITCH
843 0x00000000, // CB_COLOR2_SLICE
844 0x00000000, // CB_COLOR2_VIEW
845 0x00000000, // CB_COLOR2_INFO
846 0x00000000, // CB_COLOR2_ATTRIB
847 0x00000000, // CB_COLOR2_DIM
848 0x00000000, // CB_COLOR2_CMASK
849 0x00000000, // CB_COLOR2_CMASK_SLICE
850 0x00000000, // CB_COLOR2_FMASK
851 0x00000000, // CB_COLOR2_FMASK_SLICE
852 0x00000000, // CB_COLOR2_CLEAR_WORD0
853 0x00000000, // CB_COLOR2_CLEAR_WORD1
854 0x00000000, // CB_COLOR2_CLEAR_WORD2
855 0x00000000, // CB_COLOR2_CLEAR_WORD3
856 0x00000000, // CB_COLOR3_BASE
857 0x00000000, // CB_COLOR3_PITCH
858 0x00000000, // CB_COLOR3_SLICE
859 0x00000000, // CB_COLOR3_VIEW
860 0x00000000, // CB_COLOR3_INFO
861 0x00000000, // CB_COLOR3_ATTRIB
862 0x00000000, // CB_COLOR3_DIM
863 0x00000000, // CB_COLOR3_CMASK
864 0x00000000, // CB_COLOR3_CMASK_SLICE
865 0x00000000, // CB_COLOR3_FMASK
866 0x00000000, // CB_COLOR3_FMASK_SLICE
867 0x00000000, // CB_COLOR3_CLEAR_WORD0
868 0x00000000, // CB_COLOR3_CLEAR_WORD1
869 0x00000000, // CB_COLOR3_CLEAR_WORD2
870 0x00000000, // CB_COLOR3_CLEAR_WORD3
871 0x00000000, // CB_COLOR4_BASE
872 0x00000000, // CB_COLOR4_PITCH
873 0x00000000, // CB_COLOR4_SLICE
874 0x00000000, // CB_COLOR4_VIEW
875 0x00000000, // CB_COLOR4_INFO
876 0x00000000, // CB_COLOR4_ATTRIB
877 0x00000000, // CB_COLOR4_DIM
878 0x00000000, // CB_COLOR4_CMASK
879 0x00000000, // CB_COLOR4_CMASK_SLICE
880 0x00000000, // CB_COLOR4_FMASK
881 0x00000000, // CB_COLOR4_FMASK_SLICE
882 0x00000000, // CB_COLOR4_CLEAR_WORD0
883 0x00000000, // CB_COLOR4_CLEAR_WORD1
884 0x00000000, // CB_COLOR4_CLEAR_WORD2
885 0x00000000, // CB_COLOR4_CLEAR_WORD3
886 0x00000000, // CB_COLOR5_BASE
887 0x00000000, // CB_COLOR5_PITCH
888 0x00000000, // CB_COLOR5_SLICE
889 0x00000000, // CB_COLOR5_VIEW
890 0x00000000, // CB_COLOR5_INFO
891 0x00000000, // CB_COLOR5_ATTRIB
892 0x00000000, // CB_COLOR5_DIM
893 0x00000000, // CB_COLOR5_CMASK
894 0x00000000, // CB_COLOR5_CMASK_SLICE
895 0x00000000, // CB_COLOR5_FMASK
896 0x00000000, // CB_COLOR5_FMASK_SLICE
897 0x00000000, // CB_COLOR5_CLEAR_WORD0
898 0x00000000, // CB_COLOR5_CLEAR_WORD1
899 0x00000000, // CB_COLOR5_CLEAR_WORD2
900 0x00000000, // CB_COLOR5_CLEAR_WORD3
901 0x00000000, // CB_COLOR6_BASE
902 0x00000000, // CB_COLOR6_PITCH
903 0x00000000, // CB_COLOR6_SLICE
904 0x00000000, // CB_COLOR6_VIEW
905 0x00000000, // CB_COLOR6_INFO
906 0x00000000, // CB_COLOR6_ATTRIB
907 0x00000000, // CB_COLOR6_DIM
908 0x00000000, // CB_COLOR6_CMASK
909 0x00000000, // CB_COLOR6_CMASK_SLICE
910 0x00000000, // CB_COLOR6_FMASK
911 0x00000000, // CB_COLOR6_FMASK_SLICE
912 0x00000000, // CB_COLOR6_CLEAR_WORD0
913 0x00000000, // CB_COLOR6_CLEAR_WORD1
914 0x00000000, // CB_COLOR6_CLEAR_WORD2
915 0x00000000, // CB_COLOR6_CLEAR_WORD3
916 0x00000000, // CB_COLOR7_BASE
917 0x00000000, // CB_COLOR7_PITCH
918 0x00000000, // CB_COLOR7_SLICE
919 0x00000000, // CB_COLOR7_VIEW
920 0x00000000, // CB_COLOR7_INFO
921 0x00000000, // CB_COLOR7_ATTRIB
922 0x00000000, // CB_COLOR7_DIM
923 0x00000000, // CB_COLOR7_CMASK
924 0x00000000, // CB_COLOR7_CMASK_SLICE
925 0x00000000, // CB_COLOR7_FMASK
926 0x00000000, // CB_COLOR7_FMASK_SLICE
927 0x00000000, // CB_COLOR7_CLEAR_WORD0
928 0x00000000, // CB_COLOR7_CLEAR_WORD1
929 0x00000000, // CB_COLOR7_CLEAR_WORD2
930 0x00000000, // CB_COLOR7_CLEAR_WORD3
931 0x00000000, // CB_COLOR8_BASE
932 0x00000000, // CB_COLOR8_PITCH
933 0x00000000, // CB_COLOR8_SLICE
934 0x00000000, // CB_COLOR8_VIEW
935 0x00000000, // CB_COLOR8_INFO
936 0x00000000, // CB_COLOR8_ATTRIB
937 0x00000000, // CB_COLOR8_DIM
938 0x00000000, // CB_COLOR9_BASE
939 0x00000000, // CB_COLOR9_PITCH
940 0x00000000, // CB_COLOR9_SLICE
941 0x00000000, // CB_COLOR9_VIEW
942 0x00000000, // CB_COLOR9_INFO
943 0x00000000, // CB_COLOR9_ATTRIB
944 0x00000000, // CB_COLOR9_DIM
945 0x00000000, // CB_COLOR10_BASE
946 0x00000000, // CB_COLOR10_PITCH
947 0x00000000, // CB_COLOR10_SLICE
948 0x00000000, // CB_COLOR10_VIEW
949 0x00000000, // CB_COLOR10_INFO
950 0x00000000, // CB_COLOR10_ATTRIB
951 0x00000000, // CB_COLOR10_DIM
952 0x00000000, // CB_COLOR11_BASE
953 0x00000000, // CB_COLOR11_PITCH
954 0x00000000, // CB_COLOR11_SLICE
955 0x00000000, // CB_COLOR11_VIEW
956 0x00000000, // CB_COLOR11_INFO
957 0x00000000, // CB_COLOR11_ATTRIB
958 0x00000000, // CB_COLOR11_DIM
959 0, // HOLE
960 0, // HOLE
961 0, // HOLE
962 0, // HOLE
963 0, // HOLE
964 0, // HOLE
965 0, // HOLE
966 0, // HOLE
967 0, // HOLE
968 0, // HOLE
969 0, // HOLE
970 0, // HOLE
971 0, // HOLE
972 0, // HOLE
973 0, // HOLE
974 0, // HOLE
975 0, // HOLE
976 0, // HOLE
977 0, // HOLE
978 0, // HOLE
979 0x00000000, // SQ_ALU_CONST_CACHE_HS_0
980 0x00000000, // SQ_ALU_CONST_CACHE_HS_1
981 0x00000000, // SQ_ALU_CONST_CACHE_HS_2
982 0x00000000, // SQ_ALU_CONST_CACHE_HS_3
983 0x00000000, // SQ_ALU_CONST_CACHE_HS_4
984 0x00000000, // SQ_ALU_CONST_CACHE_HS_5
985 0x00000000, // SQ_ALU_CONST_CACHE_HS_6
986 0x00000000, // SQ_ALU_CONST_CACHE_HS_7
987 0x00000000, // SQ_ALU_CONST_CACHE_HS_8
988 0x00000000, // SQ_ALU_CONST_CACHE_HS_9
989 0x00000000, // SQ_ALU_CONST_CACHE_HS_10
990 0x00000000, // SQ_ALU_CONST_CACHE_HS_11
991 0x00000000, // SQ_ALU_CONST_CACHE_HS_12
992 0x00000000, // SQ_ALU_CONST_CACHE_HS_13
993 0x00000000, // SQ_ALU_CONST_CACHE_HS_14
994 0x00000000, // SQ_ALU_CONST_CACHE_HS_15
995 0x00000000, // SQ_ALU_CONST_CACHE_LS_0
996 0x00000000, // SQ_ALU_CONST_CACHE_LS_1
997 0x00000000, // SQ_ALU_CONST_CACHE_LS_2
998 0x00000000, // SQ_ALU_CONST_CACHE_LS_3
999 0x00000000, // SQ_ALU_CONST_CACHE_LS_4
1000 0x00000000, // SQ_ALU_CONST_CACHE_LS_5
1001 0x00000000, // SQ_ALU_CONST_CACHE_LS_6
1002 0x00000000, // SQ_ALU_CONST_CACHE_LS_7
1003 0x00000000, // SQ_ALU_CONST_CACHE_LS_8
1004 0x00000000, // SQ_ALU_CONST_CACHE_LS_9
1005 0x00000000, // SQ_ALU_CONST_CACHE_LS_10
1006 0x00000000, // SQ_ALU_CONST_CACHE_LS_11
1007 0x00000000, // SQ_ALU_CONST_CACHE_LS_12
1008 0x00000000, // SQ_ALU_CONST_CACHE_LS_13
1009 0x00000000, // SQ_ALU_CONST_CACHE_LS_14
1010 0x00000000, // SQ_ALU_CONST_CACHE_LS_15
1011 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_0
1012 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_1
1013 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_2
1014 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_3
1015 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_4
1016 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_5
1017 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_6
1018 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_7
1019 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_8
1020 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_9
1021 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_10
1022 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_11
1023 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_12
1024 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_13
1025 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_14
1026 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_15
1027 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_0
1028 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_1
1029 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_2
1030 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_3
1031 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_4
1032 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_5
1033 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_6
1034 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_7
1035 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_8
1036 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_9
1037 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_10
1038 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_11
1039 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_12
1040 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_13
1041 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_14
1042 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_15
1043};
1044static const struct cs_extent_def SECT_CONTEXT_defs[] =
1045{
1046 {SECT_CONTEXT_def_1, 0x0000a000, 488 },
1047 {SECT_CONTEXT_def_2, 0x0000a1f5, 6 },
1048 {SECT_CONTEXT_def_3, 0x0000a200, 55 },
1049 {SECT_CONTEXT_def_4, 0x0000a23a, 99 },
1050 {SECT_CONTEXT_def_5, 0x0000a29e, 5 },
1051 {SECT_CONTEXT_def_6, 0x0000a2a5, 56 },
1052 {SECT_CONTEXT_def_7, 0x0000a2de, 290 },
1053 { 0, 0, 0 }
1054};
1055static const u32 SECT_CLEAR_def_1[] =
1056{
1057 0xffffffff, // SQ_TEX_SAMPLER_CLEAR
1058 0xffffffff, // SQ_TEX_RESOURCE_CLEAR
1059 0xffffffff, // SQ_LOOP_BOOL_CLEAR
1060};
1061static const struct cs_extent_def SECT_CLEAR_defs[] =
1062{
1063 {SECT_CLEAR_def_1, 0x0000ffc0, 3 },
1064 { 0, 0, 0 }
1065};
1066static const u32 SECT_CTRLCONST_def_1[] =
1067{
1068 0x00000000, // SQ_VTX_BASE_VTX_LOC
1069 0x00000000, // SQ_VTX_START_INST_LOC
1070};
1071static const struct cs_extent_def SECT_CTRLCONST_defs[] =
1072{
1073 {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 },
1074 { 0, 0, 0 }
1075};
1076struct cs_section_def cayman_cs_data[] = {
1077 { SECT_CONTEXT_defs, SECT_CONTEXT },
1078 { SECT_CLEAR_defs, SECT_CLEAR },
1079 { SECT_CTRLCONST_defs, SECT_CTRLCONST },
1080 { 0, SECT_NONE }
1081};
diff --git a/drivers/gpu/drm/radeon/clearstate_defs.h b/drivers/gpu/drm/radeon/clearstate_defs.h
new file mode 100644
index 000000000000..3eda707d7388
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_defs.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef CLEARSTATE_DEFS_H
24#define CLEARSTATE_DEFS_H
25
26enum section_id {
27 SECT_NONE,
28 SECT_CONTEXT,
29 SECT_CLEAR,
30 SECT_CTRLCONST
31};
32
33struct cs_extent_def {
34 const unsigned int *extent;
35 const unsigned int reg_index;
36 const unsigned int reg_count;
37};
38
39struct cs_section_def {
40 const struct cs_extent_def *section;
41 const enum section_id id;
42};
43
44#endif
diff --git a/drivers/gpu/drm/radeon/clearstate_evergreen.h b/drivers/gpu/drm/radeon/clearstate_evergreen.h
new file mode 100644
index 000000000000..4791d856b7fd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_evergreen.h
@@ -0,0 +1,1080 @@
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24static const u32 SECT_CONTEXT_def_1[] =
25{
26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0, // HOLE
35 0, // HOLE
36 0x00000000, // DB_STENCIL_CLEAR
37 0x00000000, // DB_DEPTH_CLEAR
38 0x00000000, // PA_SC_SCREEN_SCISSOR_TL
39 0x40004000, // PA_SC_SCREEN_SCISSOR_BR
40 0, // HOLE
41 0, // HOLE
42 0x00000000, // DB_Z_INFO
43 0x00000000, // DB_STENCIL_INFO
44 0x00000000, // DB_Z_READ_BASE
45 0x00000000, // DB_STENCIL_READ_BASE
46 0x00000000, // DB_Z_WRITE_BASE
47 0x00000000, // DB_STENCIL_WRITE_BASE
48 0x00000000, // DB_DEPTH_SIZE
49 0x00000000, // DB_DEPTH_SLICE
50 0, // HOLE
51 0, // HOLE
52 0, // HOLE
53 0, // HOLE
54 0, // HOLE
55 0, // HOLE
56 0, // HOLE
57 0, // HOLE
58 0, // HOLE
59 0, // HOLE
60 0, // HOLE
61 0, // HOLE
62 0, // HOLE
63 0, // HOLE
64 0, // HOLE
65 0, // HOLE
66 0, // HOLE
67 0, // HOLE
68 0, // HOLE
69 0, // HOLE
70 0, // HOLE
71 0, // HOLE
72 0, // HOLE
73 0, // HOLE
74 0, // HOLE
75 0, // HOLE
76 0, // HOLE
77 0, // HOLE
78 0, // HOLE
79 0, // HOLE
80 0, // HOLE
81 0, // HOLE
82 0, // HOLE
83 0, // HOLE
84 0, // HOLE
85 0, // HOLE
86 0, // HOLE
87 0, // HOLE
88 0, // HOLE
89 0, // HOLE
90 0, // HOLE
91 0, // HOLE
92 0, // HOLE
93 0, // HOLE
94 0, // HOLE
95 0, // HOLE
96 0, // HOLE
97 0, // HOLE
98 0, // HOLE
99 0, // HOLE
100 0, // HOLE
101 0, // HOLE
102 0, // HOLE
103 0, // HOLE
104 0, // HOLE
105 0, // HOLE
106 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_0
107 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_1
108 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_2
109 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_3
110 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_4
111 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_5
112 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_6
113 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_7
114 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_8
115 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_9
116 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_10
117 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_11
118 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_12
119 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_13
120 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_14
121 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_15
122 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_0
123 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_1
124 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_2
125 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_3
126 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_4
127 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_5
128 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_6
129 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_7
130 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_8
131 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_9
132 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_10
133 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_11
134 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_12
135 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_13
136 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_14
137 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_15
138 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_0
139 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_1
140 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_2
141 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_3
142 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_4
143 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_5
144 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_6
145 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_7
146 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_8
147 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_9
148 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_10
149 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_11
150 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_12
151 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_13
152 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_14
153 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_15
154 0x00000000, // PA_SC_WINDOW_OFFSET
155 0x80000000, // PA_SC_WINDOW_SCISSOR_TL
156 0x40004000, // PA_SC_WINDOW_SCISSOR_BR
157 0x0000ffff, // PA_SC_CLIPRECT_RULE
158 0x00000000, // PA_SC_CLIPRECT_0_TL
159 0x40004000, // PA_SC_CLIPRECT_0_BR
160 0x00000000, // PA_SC_CLIPRECT_1_TL
161 0x40004000, // PA_SC_CLIPRECT_1_BR
162 0x00000000, // PA_SC_CLIPRECT_2_TL
163 0x40004000, // PA_SC_CLIPRECT_2_BR
164 0x00000000, // PA_SC_CLIPRECT_3_TL
165 0x40004000, // PA_SC_CLIPRECT_3_BR
166 0xaa99aaaa, // PA_SC_EDGERULE
167 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
168 0xffffffff, // CB_TARGET_MASK
169 0xffffffff, // CB_SHADER_MASK
170 0x80000000, // PA_SC_GENERIC_SCISSOR_TL
171 0x40004000, // PA_SC_GENERIC_SCISSOR_BR
172 0x00000000, // COHER_DEST_BASE_0
173 0x00000000, // COHER_DEST_BASE_1
174 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
175 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
176 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
177 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
178 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
179 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
180 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
181 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
182 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
183 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
184 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
185 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
186 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
187 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
188 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
189 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
190 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
191 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
192 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
193 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
194 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
195 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
196 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
197 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
198 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
199 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
200 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
201 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
202 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
203 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
204 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
205 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
206 0x00000000, // PA_SC_VPORT_ZMIN_0
207 0x3f800000, // PA_SC_VPORT_ZMAX_0
208 0x00000000, // PA_SC_VPORT_ZMIN_1
209 0x3f800000, // PA_SC_VPORT_ZMAX_1
210 0x00000000, // PA_SC_VPORT_ZMIN_2
211 0x3f800000, // PA_SC_VPORT_ZMAX_2
212 0x00000000, // PA_SC_VPORT_ZMIN_3
213 0x3f800000, // PA_SC_VPORT_ZMAX_3
214 0x00000000, // PA_SC_VPORT_ZMIN_4
215 0x3f800000, // PA_SC_VPORT_ZMAX_4
216 0x00000000, // PA_SC_VPORT_ZMIN_5
217 0x3f800000, // PA_SC_VPORT_ZMAX_5
218 0x00000000, // PA_SC_VPORT_ZMIN_6
219 0x3f800000, // PA_SC_VPORT_ZMAX_6
220 0x00000000, // PA_SC_VPORT_ZMIN_7
221 0x3f800000, // PA_SC_VPORT_ZMAX_7
222 0x00000000, // PA_SC_VPORT_ZMIN_8
223 0x3f800000, // PA_SC_VPORT_ZMAX_8
224 0x00000000, // PA_SC_VPORT_ZMIN_9
225 0x3f800000, // PA_SC_VPORT_ZMAX_9
226 0x00000000, // PA_SC_VPORT_ZMIN_10
227 0x3f800000, // PA_SC_VPORT_ZMAX_10
228 0x00000000, // PA_SC_VPORT_ZMIN_11
229 0x3f800000, // PA_SC_VPORT_ZMAX_11
230 0x00000000, // PA_SC_VPORT_ZMIN_12
231 0x3f800000, // PA_SC_VPORT_ZMAX_12
232 0x00000000, // PA_SC_VPORT_ZMIN_13
233 0x3f800000, // PA_SC_VPORT_ZMAX_13
234 0x00000000, // PA_SC_VPORT_ZMIN_14
235 0x3f800000, // PA_SC_VPORT_ZMAX_14
236 0x00000000, // PA_SC_VPORT_ZMIN_15
237 0x3f800000, // PA_SC_VPORT_ZMAX_15
238 0x00000000, // SX_MISC
239 0x00000000, // SX_SURFACE_SYNC
240 0x00000000, // CP_PERFMON_CNTX_CNTL
241 0, // HOLE
242 0, // HOLE
243 0, // HOLE
244 0, // HOLE
245 0, // HOLE
246 0, // HOLE
247 0, // HOLE
248 0, // HOLE
249 0, // HOLE
250 0x00000000, // SQ_VTX_SEMANTIC_0
251 0x00000000, // SQ_VTX_SEMANTIC_1
252 0x00000000, // SQ_VTX_SEMANTIC_2
253 0x00000000, // SQ_VTX_SEMANTIC_3
254 0x00000000, // SQ_VTX_SEMANTIC_4
255 0x00000000, // SQ_VTX_SEMANTIC_5
256 0x00000000, // SQ_VTX_SEMANTIC_6
257 0x00000000, // SQ_VTX_SEMANTIC_7
258 0x00000000, // SQ_VTX_SEMANTIC_8
259 0x00000000, // SQ_VTX_SEMANTIC_9
260 0x00000000, // SQ_VTX_SEMANTIC_10
261 0x00000000, // SQ_VTX_SEMANTIC_11
262 0x00000000, // SQ_VTX_SEMANTIC_12
263 0x00000000, // SQ_VTX_SEMANTIC_13
264 0x00000000, // SQ_VTX_SEMANTIC_14
265 0x00000000, // SQ_VTX_SEMANTIC_15
266 0x00000000, // SQ_VTX_SEMANTIC_16
267 0x00000000, // SQ_VTX_SEMANTIC_17
268 0x00000000, // SQ_VTX_SEMANTIC_18
269 0x00000000, // SQ_VTX_SEMANTIC_19
270 0x00000000, // SQ_VTX_SEMANTIC_20
271 0x00000000, // SQ_VTX_SEMANTIC_21
272 0x00000000, // SQ_VTX_SEMANTIC_22
273 0x00000000, // SQ_VTX_SEMANTIC_23
274 0x00000000, // SQ_VTX_SEMANTIC_24
275 0x00000000, // SQ_VTX_SEMANTIC_25
276 0x00000000, // SQ_VTX_SEMANTIC_26
277 0x00000000, // SQ_VTX_SEMANTIC_27
278 0x00000000, // SQ_VTX_SEMANTIC_28
279 0x00000000, // SQ_VTX_SEMANTIC_29
280 0x00000000, // SQ_VTX_SEMANTIC_30
281 0x00000000, // SQ_VTX_SEMANTIC_31
282 0xffffffff, // VGT_MAX_VTX_INDX
283 0x00000000, // VGT_MIN_VTX_INDX
284 0x00000000, // VGT_INDX_OFFSET
285 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
286 0x00000000, // SX_ALPHA_TEST_CONTROL
287 0x00000000, // CB_BLEND_RED
288 0x00000000, // CB_BLEND_GREEN
289 0x00000000, // CB_BLEND_BLUE
290 0x00000000, // CB_BLEND_ALPHA
291 0, // HOLE
292 0, // HOLE
293 0, // HOLE
294 0x00000000, // DB_STENCILREFMASK
295 0x00000000, // DB_STENCILREFMASK_BF
296 0x00000000, // SX_ALPHA_REF
297 0x00000000, // PA_CL_VPORT_XSCALE
298 0x00000000, // PA_CL_VPORT_XOFFSET
299 0x00000000, // PA_CL_VPORT_YSCALE
300 0x00000000, // PA_CL_VPORT_YOFFSET
301 0x00000000, // PA_CL_VPORT_ZSCALE
302 0x00000000, // PA_CL_VPORT_ZOFFSET
303 0x00000000, // PA_CL_VPORT_XSCALE_1
304 0x00000000, // PA_CL_VPORT_XOFFSET_1
305 0x00000000, // PA_CL_VPORT_YSCALE_1
306 0x00000000, // PA_CL_VPORT_YOFFSET_1
307 0x00000000, // PA_CL_VPORT_ZSCALE_1
308 0x00000000, // PA_CL_VPORT_ZOFFSET_1
309 0x00000000, // PA_CL_VPORT_XSCALE_2
310 0x00000000, // PA_CL_VPORT_XOFFSET_2
311 0x00000000, // PA_CL_VPORT_YSCALE_2
312 0x00000000, // PA_CL_VPORT_YOFFSET_2
313 0x00000000, // PA_CL_VPORT_ZSCALE_2
314 0x00000000, // PA_CL_VPORT_ZOFFSET_2
315 0x00000000, // PA_CL_VPORT_XSCALE_3
316 0x00000000, // PA_CL_VPORT_XOFFSET_3
317 0x00000000, // PA_CL_VPORT_YSCALE_3
318 0x00000000, // PA_CL_VPORT_YOFFSET_3
319 0x00000000, // PA_CL_VPORT_ZSCALE_3
320 0x00000000, // PA_CL_VPORT_ZOFFSET_3
321 0x00000000, // PA_CL_VPORT_XSCALE_4
322 0x00000000, // PA_CL_VPORT_XOFFSET_4
323 0x00000000, // PA_CL_VPORT_YSCALE_4
324 0x00000000, // PA_CL_VPORT_YOFFSET_4
325 0x00000000, // PA_CL_VPORT_ZSCALE_4
326 0x00000000, // PA_CL_VPORT_ZOFFSET_4
327 0x00000000, // PA_CL_VPORT_XSCALE_5
328 0x00000000, // PA_CL_VPORT_XOFFSET_5
329 0x00000000, // PA_CL_VPORT_YSCALE_5
330 0x00000000, // PA_CL_VPORT_YOFFSET_5
331 0x00000000, // PA_CL_VPORT_ZSCALE_5
332 0x00000000, // PA_CL_VPORT_ZOFFSET_5
333 0x00000000, // PA_CL_VPORT_XSCALE_6
334 0x00000000, // PA_CL_VPORT_XOFFSET_6
335 0x00000000, // PA_CL_VPORT_YSCALE_6
336 0x00000000, // PA_CL_VPORT_YOFFSET_6
337 0x00000000, // PA_CL_VPORT_ZSCALE_6
338 0x00000000, // PA_CL_VPORT_ZOFFSET_6
339 0x00000000, // PA_CL_VPORT_XSCALE_7
340 0x00000000, // PA_CL_VPORT_XOFFSET_7
341 0x00000000, // PA_CL_VPORT_YSCALE_7
342 0x00000000, // PA_CL_VPORT_YOFFSET_7
343 0x00000000, // PA_CL_VPORT_ZSCALE_7
344 0x00000000, // PA_CL_VPORT_ZOFFSET_7
345 0x00000000, // PA_CL_VPORT_XSCALE_8
346 0x00000000, // PA_CL_VPORT_XOFFSET_8
347 0x00000000, // PA_CL_VPORT_YSCALE_8
348 0x00000000, // PA_CL_VPORT_YOFFSET_8
349 0x00000000, // PA_CL_VPORT_ZSCALE_8
350 0x00000000, // PA_CL_VPORT_ZOFFSET_8
351 0x00000000, // PA_CL_VPORT_XSCALE_9
352 0x00000000, // PA_CL_VPORT_XOFFSET_9
353 0x00000000, // PA_CL_VPORT_YSCALE_9
354 0x00000000, // PA_CL_VPORT_YOFFSET_9
355 0x00000000, // PA_CL_VPORT_ZSCALE_9
356 0x00000000, // PA_CL_VPORT_ZOFFSET_9
357 0x00000000, // PA_CL_VPORT_XSCALE_10
358 0x00000000, // PA_CL_VPORT_XOFFSET_10
359 0x00000000, // PA_CL_VPORT_YSCALE_10
360 0x00000000, // PA_CL_VPORT_YOFFSET_10
361 0x00000000, // PA_CL_VPORT_ZSCALE_10
362 0x00000000, // PA_CL_VPORT_ZOFFSET_10
363 0x00000000, // PA_CL_VPORT_XSCALE_11
364 0x00000000, // PA_CL_VPORT_XOFFSET_11
365 0x00000000, // PA_CL_VPORT_YSCALE_11
366 0x00000000, // PA_CL_VPORT_YOFFSET_11
367 0x00000000, // PA_CL_VPORT_ZSCALE_11
368 0x00000000, // PA_CL_VPORT_ZOFFSET_11
369 0x00000000, // PA_CL_VPORT_XSCALE_12
370 0x00000000, // PA_CL_VPORT_XOFFSET_12
371 0x00000000, // PA_CL_VPORT_YSCALE_12
372 0x00000000, // PA_CL_VPORT_YOFFSET_12
373 0x00000000, // PA_CL_VPORT_ZSCALE_12
374 0x00000000, // PA_CL_VPORT_ZOFFSET_12
375 0x00000000, // PA_CL_VPORT_XSCALE_13
376 0x00000000, // PA_CL_VPORT_XOFFSET_13
377 0x00000000, // PA_CL_VPORT_YSCALE_13
378 0x00000000, // PA_CL_VPORT_YOFFSET_13
379 0x00000000, // PA_CL_VPORT_ZSCALE_13
380 0x00000000, // PA_CL_VPORT_ZOFFSET_13
381 0x00000000, // PA_CL_VPORT_XSCALE_14
382 0x00000000, // PA_CL_VPORT_XOFFSET_14
383 0x00000000, // PA_CL_VPORT_YSCALE_14
384 0x00000000, // PA_CL_VPORT_YOFFSET_14
385 0x00000000, // PA_CL_VPORT_ZSCALE_14
386 0x00000000, // PA_CL_VPORT_ZOFFSET_14
387 0x00000000, // PA_CL_VPORT_XSCALE_15
388 0x00000000, // PA_CL_VPORT_XOFFSET_15
389 0x00000000, // PA_CL_VPORT_YSCALE_15
390 0x00000000, // PA_CL_VPORT_YOFFSET_15
391 0x00000000, // PA_CL_VPORT_ZSCALE_15
392 0x00000000, // PA_CL_VPORT_ZOFFSET_15
393 0x00000000, // PA_CL_UCP_0_X
394 0x00000000, // PA_CL_UCP_0_Y
395 0x00000000, // PA_CL_UCP_0_Z
396 0x00000000, // PA_CL_UCP_0_W
397 0x00000000, // PA_CL_UCP_1_X
398 0x00000000, // PA_CL_UCP_1_Y
399 0x00000000, // PA_CL_UCP_1_Z
400 0x00000000, // PA_CL_UCP_1_W
401 0x00000000, // PA_CL_UCP_2_X
402 0x00000000, // PA_CL_UCP_2_Y
403 0x00000000, // PA_CL_UCP_2_Z
404 0x00000000, // PA_CL_UCP_2_W
405 0x00000000, // PA_CL_UCP_3_X
406 0x00000000, // PA_CL_UCP_3_Y
407 0x00000000, // PA_CL_UCP_3_Z
408 0x00000000, // PA_CL_UCP_3_W
409 0x00000000, // PA_CL_UCP_4_X
410 0x00000000, // PA_CL_UCP_4_Y
411 0x00000000, // PA_CL_UCP_4_Z
412 0x00000000, // PA_CL_UCP_4_W
413 0x00000000, // PA_CL_UCP_5_X
414 0x00000000, // PA_CL_UCP_5_Y
415 0x00000000, // PA_CL_UCP_5_Z
416 0x00000000, // PA_CL_UCP_5_W
417 0x00000000, // SPI_VS_OUT_ID_0
418 0x00000000, // SPI_VS_OUT_ID_1
419 0x00000000, // SPI_VS_OUT_ID_2
420 0x00000000, // SPI_VS_OUT_ID_3
421 0x00000000, // SPI_VS_OUT_ID_4
422 0x00000000, // SPI_VS_OUT_ID_5
423 0x00000000, // SPI_VS_OUT_ID_6
424 0x00000000, // SPI_VS_OUT_ID_7
425 0x00000000, // SPI_VS_OUT_ID_8
426 0x00000000, // SPI_VS_OUT_ID_9
427 0x00000000, // SPI_PS_INPUT_CNTL_0
428 0x00000000, // SPI_PS_INPUT_CNTL_1
429 0x00000000, // SPI_PS_INPUT_CNTL_2
430 0x00000000, // SPI_PS_INPUT_CNTL_3
431 0x00000000, // SPI_PS_INPUT_CNTL_4
432 0x00000000, // SPI_PS_INPUT_CNTL_5
433 0x00000000, // SPI_PS_INPUT_CNTL_6
434 0x00000000, // SPI_PS_INPUT_CNTL_7
435 0x00000000, // SPI_PS_INPUT_CNTL_8
436 0x00000000, // SPI_PS_INPUT_CNTL_9
437 0x00000000, // SPI_PS_INPUT_CNTL_10
438 0x00000000, // SPI_PS_INPUT_CNTL_11
439 0x00000000, // SPI_PS_INPUT_CNTL_12
440 0x00000000, // SPI_PS_INPUT_CNTL_13
441 0x00000000, // SPI_PS_INPUT_CNTL_14
442 0x00000000, // SPI_PS_INPUT_CNTL_15
443 0x00000000, // SPI_PS_INPUT_CNTL_16
444 0x00000000, // SPI_PS_INPUT_CNTL_17
445 0x00000000, // SPI_PS_INPUT_CNTL_18
446 0x00000000, // SPI_PS_INPUT_CNTL_19
447 0x00000000, // SPI_PS_INPUT_CNTL_20
448 0x00000000, // SPI_PS_INPUT_CNTL_21
449 0x00000000, // SPI_PS_INPUT_CNTL_22
450 0x00000000, // SPI_PS_INPUT_CNTL_23
451 0x00000000, // SPI_PS_INPUT_CNTL_24
452 0x00000000, // SPI_PS_INPUT_CNTL_25
453 0x00000000, // SPI_PS_INPUT_CNTL_26
454 0x00000000, // SPI_PS_INPUT_CNTL_27
455 0x00000000, // SPI_PS_INPUT_CNTL_28
456 0x00000000, // SPI_PS_INPUT_CNTL_29
457 0x00000000, // SPI_PS_INPUT_CNTL_30
458 0x00000000, // SPI_PS_INPUT_CNTL_31
459 0x00000000, // SPI_VS_OUT_CONFIG
460 0x00000001, // SPI_THREAD_GROUPING
461 0x00000000, // SPI_PS_IN_CONTROL_0
462 0x00000000, // SPI_PS_IN_CONTROL_1
463 0x00000000, // SPI_INTERP_CONTROL_0
464 0x00000000, // SPI_INPUT_Z
465 0x00000000, // SPI_FOG_CNTL
466 0x00000000, // SPI_BARYC_CNTL
467 0x00000000, // SPI_PS_IN_CONTROL_2
468 0x00000000, // SPI_COMPUTE_INPUT_CNTL
469 0x00000000, // SPI_COMPUTE_NUM_THREAD_X
470 0x00000000, // SPI_COMPUTE_NUM_THREAD_Y
471 0x00000000, // SPI_COMPUTE_NUM_THREAD_Z
472 0, // HOLE
473 0, // HOLE
474 0, // HOLE
475 0, // HOLE
476 0, // HOLE
477 0, // HOLE
478 0, // HOLE
479 0, // HOLE
480 0, // HOLE
481 0, // HOLE
482 0x00000000, // GDS_ADDR_BASE
483 0x00003fff, // GDS_ADDR_SIZE
484 0x00000001, // GDS_ORDERED_WAVE_PER_SE
485 0x00000000, // GDS_APPEND_CONSUME_UAV0
486 0x00000000, // GDS_APPEND_CONSUME_UAV1
487 0x00000000, // GDS_APPEND_CONSUME_UAV2
488 0x00000000, // GDS_APPEND_CONSUME_UAV3
489 0x00000000, // GDS_APPEND_CONSUME_UAV4
490 0x00000000, // GDS_APPEND_CONSUME_UAV5
491 0x00000000, // GDS_APPEND_CONSUME_UAV6
492 0x00000000, // GDS_APPEND_CONSUME_UAV7
493 0x00000000, // GDS_APPEND_CONSUME_UAV8
494 0x00000000, // GDS_APPEND_CONSUME_UAV9
495 0x00000000, // GDS_APPEND_CONSUME_UAV10
496 0x00000000, // GDS_APPEND_CONSUME_UAV11
497 0, // HOLE
498 0, // HOLE
499 0, // HOLE
500 0, // HOLE
501 0, // HOLE
502 0, // HOLE
503 0, // HOLE
504 0, // HOLE
505 0, // HOLE
506 0x00000000, // CB_BLEND0_CONTROL
507 0x00000000, // CB_BLEND1_CONTROL
508 0x00000000, // CB_BLEND2_CONTROL
509 0x00000000, // CB_BLEND3_CONTROL
510 0x00000000, // CB_BLEND4_CONTROL
511 0x00000000, // CB_BLEND5_CONTROL
512 0x00000000, // CB_BLEND6_CONTROL
513 0x00000000, // CB_BLEND7_CONTROL
514};
515static const u32 SECT_CONTEXT_def_2[] =
516{
517 0x00000000, // PA_CL_POINT_X_RAD
518 0x00000000, // PA_CL_POINT_Y_RAD
519 0x00000000, // PA_CL_POINT_SIZE
520 0x00000000, // PA_CL_POINT_CULL_RAD
521 0x00000000, // VGT_DMA_BASE_HI
522 0x00000000, // VGT_DMA_BASE
523};
524static const u32 SECT_CONTEXT_def_3[] =
525{
526 0x00000000, // DB_DEPTH_CONTROL
527 0, // HOLE
528 0x00000000, // CB_COLOR_CONTROL
529 0x00000200, // DB_SHADER_CONTROL
530 0x00000000, // PA_CL_CLIP_CNTL
531 0x00000000, // PA_SU_SC_MODE_CNTL
532 0x00000000, // PA_CL_VTE_CNTL
533 0x00000000, // PA_CL_VS_OUT_CNTL
534 0x00000000, // PA_CL_NANINF_CNTL
535 0x00000000, // PA_SU_LINE_STIPPLE_CNTL
536 0x00000000, // PA_SU_LINE_STIPPLE_SCALE
537 0x00000000, // PA_SU_PRIM_FILTER_CNTL
538 0x00000000, // SQ_LSTMP_RING_ITEMSIZE
539 0x00000000, // SQ_HSTMP_RING_ITEMSIZE
540 0x00000000, // SQ_DYN_GPR_RESOURCE_LIMIT_1
541 0, // HOLE
542 0x00000000, // SQ_PGM_START_PS
543 0x00000000, // SQ_PGM_RESOURCES_PS
544 0x00000000, // SQ_PGM_RESOURCES_2_PS
545 0x00000000, // SQ_PGM_EXPORTS_PS
546 0, // HOLE
547 0, // HOLE
548 0, // HOLE
549 0x00000000, // SQ_PGM_START_VS
550 0x00000000, // SQ_PGM_RESOURCES_VS
551 0x00000000, // SQ_PGM_RESOURCES_2_VS
552 0, // HOLE
553 0, // HOLE
554 0, // HOLE
555 0x00000000, // SQ_PGM_START_GS
556 0x00000000, // SQ_PGM_RESOURCES_GS
557 0x00000000, // SQ_PGM_RESOURCES_2_GS
558 0, // HOLE
559 0, // HOLE
560 0, // HOLE
561 0x00000000, // SQ_PGM_START_ES
562 0x00000000, // SQ_PGM_RESOURCES_ES
563 0x00000000, // SQ_PGM_RESOURCES_2_ES
564 0, // HOLE
565 0, // HOLE
566 0, // HOLE
567 0x00000000, // SQ_PGM_START_FS
568 0x00000000, // SQ_PGM_RESOURCES_FS
569 0, // HOLE
570 0, // HOLE
571 0, // HOLE
572 0x00000000, // SQ_PGM_START_HS
573 0x00000000, // SQ_PGM_RESOURCES_HS
574 0x00000000, // SQ_PGM_RESOURCES_2_HS
575 0, // HOLE
576 0, // HOLE
577 0, // HOLE
578 0x00000000, // SQ_PGM_START_LS
579 0x00000000, // SQ_PGM_RESOURCES_LS
580 0x00000000, // SQ_PGM_RESOURCES_2_LS
581};
582static const u32 SECT_CONTEXT_def_4[] =
583{
584 0x00000000, // SQ_LDS_ALLOC
585 0x00000000, // SQ_LDS_ALLOC_PS
586 0x00000000, // SQ_VTX_SEMANTIC_CLEAR
587 0, // HOLE
588 0x00000000, // SQ_THREAD_TRACE_CTRL
589 0, // HOLE
590 0x00000000, // SQ_ESGS_RING_ITEMSIZE
591 0x00000000, // SQ_GSVS_RING_ITEMSIZE
592 0x00000000, // SQ_ESTMP_RING_ITEMSIZE
593 0x00000000, // SQ_GSTMP_RING_ITEMSIZE
594 0x00000000, // SQ_VSTMP_RING_ITEMSIZE
595 0x00000000, // SQ_PSTMP_RING_ITEMSIZE
596 0, // HOLE
597 0x00000000, // SQ_GS_VERT_ITEMSIZE
598 0x00000000, // SQ_GS_VERT_ITEMSIZE_1
599 0x00000000, // SQ_GS_VERT_ITEMSIZE_2
600 0x00000000, // SQ_GS_VERT_ITEMSIZE_3
601 0x00000000, // SQ_GSVS_RING_OFFSET_1
602 0x00000000, // SQ_GSVS_RING_OFFSET_2
603 0x00000000, // SQ_GSVS_RING_OFFSET_3
604 0, // HOLE
605 0, // HOLE
606 0x00000000, // SQ_ALU_CONST_CACHE_PS_0
607 0x00000000, // SQ_ALU_CONST_CACHE_PS_1
608 0x00000000, // SQ_ALU_CONST_CACHE_PS_2
609 0x00000000, // SQ_ALU_CONST_CACHE_PS_3
610 0x00000000, // SQ_ALU_CONST_CACHE_PS_4
611 0x00000000, // SQ_ALU_CONST_CACHE_PS_5
612 0x00000000, // SQ_ALU_CONST_CACHE_PS_6
613 0x00000000, // SQ_ALU_CONST_CACHE_PS_7
614 0x00000000, // SQ_ALU_CONST_CACHE_PS_8
615 0x00000000, // SQ_ALU_CONST_CACHE_PS_9
616 0x00000000, // SQ_ALU_CONST_CACHE_PS_10
617 0x00000000, // SQ_ALU_CONST_CACHE_PS_11
618 0x00000000, // SQ_ALU_CONST_CACHE_PS_12
619 0x00000000, // SQ_ALU_CONST_CACHE_PS_13
620 0x00000000, // SQ_ALU_CONST_CACHE_PS_14
621 0x00000000, // SQ_ALU_CONST_CACHE_PS_15
622 0x00000000, // SQ_ALU_CONST_CACHE_VS_0
623 0x00000000, // SQ_ALU_CONST_CACHE_VS_1
624 0x00000000, // SQ_ALU_CONST_CACHE_VS_2
625 0x00000000, // SQ_ALU_CONST_CACHE_VS_3
626 0x00000000, // SQ_ALU_CONST_CACHE_VS_4
627 0x00000000, // SQ_ALU_CONST_CACHE_VS_5
628 0x00000000, // SQ_ALU_CONST_CACHE_VS_6
629 0x00000000, // SQ_ALU_CONST_CACHE_VS_7
630 0x00000000, // SQ_ALU_CONST_CACHE_VS_8
631 0x00000000, // SQ_ALU_CONST_CACHE_VS_9
632 0x00000000, // SQ_ALU_CONST_CACHE_VS_10
633 0x00000000, // SQ_ALU_CONST_CACHE_VS_11
634 0x00000000, // SQ_ALU_CONST_CACHE_VS_12
635 0x00000000, // SQ_ALU_CONST_CACHE_VS_13
636 0x00000000, // SQ_ALU_CONST_CACHE_VS_14
637 0x00000000, // SQ_ALU_CONST_CACHE_VS_15
638 0x00000000, // SQ_ALU_CONST_CACHE_GS_0
639 0x00000000, // SQ_ALU_CONST_CACHE_GS_1
640 0x00000000, // SQ_ALU_CONST_CACHE_GS_2
641 0x00000000, // SQ_ALU_CONST_CACHE_GS_3
642 0x00000000, // SQ_ALU_CONST_CACHE_GS_4
643 0x00000000, // SQ_ALU_CONST_CACHE_GS_5
644 0x00000000, // SQ_ALU_CONST_CACHE_GS_6
645 0x00000000, // SQ_ALU_CONST_CACHE_GS_7
646 0x00000000, // SQ_ALU_CONST_CACHE_GS_8
647 0x00000000, // SQ_ALU_CONST_CACHE_GS_9
648 0x00000000, // SQ_ALU_CONST_CACHE_GS_10
649 0x00000000, // SQ_ALU_CONST_CACHE_GS_11
650 0x00000000, // SQ_ALU_CONST_CACHE_GS_12
651 0x00000000, // SQ_ALU_CONST_CACHE_GS_13
652 0x00000000, // SQ_ALU_CONST_CACHE_GS_14
653 0x00000000, // SQ_ALU_CONST_CACHE_GS_15
654 0x00000000, // PA_SU_POINT_SIZE
655 0x00000000, // PA_SU_POINT_MINMAX
656 0x00000000, // PA_SU_LINE_CNTL
657 0x00000000, // PA_SC_LINE_STIPPLE
658 0x00000000, // VGT_OUTPUT_PATH_CNTL
659 0x00000000, // VGT_HOS_CNTL
660 0x00000000, // VGT_HOS_MAX_TESS_LEVEL
661 0x00000000, // VGT_HOS_MIN_TESS_LEVEL
662 0x00000000, // VGT_HOS_REUSE_DEPTH
663 0x00000000, // VGT_GROUP_PRIM_TYPE
664 0x00000000, // VGT_GROUP_FIRST_DECR
665 0x00000000, // VGT_GROUP_DECR
666 0x00000000, // VGT_GROUP_VECT_0_CNTL
667 0x00000000, // VGT_GROUP_VECT_1_CNTL
668 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
669 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
670 0x00000000, // VGT_GS_MODE
671 0, // HOLE
672 0x00000000, // PA_SC_MODE_CNTL_0
673 0x00000000, // PA_SC_MODE_CNTL_1
674 0x00000000, // VGT_ENHANCE
675 0x00000000, // VGT_GS_PER_ES
676 0x00000000, // VGT_ES_PER_GS
677 0x00000000, // VGT_GS_PER_VS
678 0, // HOLE
679 0, // HOLE
680 0, // HOLE
681 0x00000000, // VGT_GS_OUT_PRIM_TYPE
682};
683static const u32 SECT_CONTEXT_def_5[] =
684{
685 0x00000000, // VGT_DMA_MAX_SIZE
686 0x00000000, // VGT_DMA_INDEX_TYPE
687 0, // HOLE
688 0x00000000, // VGT_PRIMITIVEID_EN
689 0x00000000, // VGT_DMA_NUM_INSTANCES
690};
691static const u32 SECT_CONTEXT_def_6[] =
692{
693 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
694 0, // HOLE
695 0, // HOLE
696 0x00000000, // VGT_INSTANCE_STEP_RATE_0
697 0x00000000, // VGT_INSTANCE_STEP_RATE_1
698 0, // HOLE
699 0, // HOLE
700 0, // HOLE
701 0x00000000, // VGT_REUSE_OFF
702 0x00000000, // VGT_VTX_CNT_EN
703 0x00000000, // DB_HTILE_SURFACE
704 0x00000000, // DB_SRESULTS_COMPARE_STATE0
705 0x00000000, // DB_SRESULTS_COMPARE_STATE1
706 0x00000000, // DB_PRELOAD_CONTROL
707 0, // HOLE
708 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
709 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
710 0x00000000, // VGT_STRMOUT_BUFFER_BASE_0
711 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
712 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
713 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
714 0x00000000, // VGT_STRMOUT_BUFFER_BASE_1
715 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
716 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
717 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
718 0x00000000, // VGT_STRMOUT_BUFFER_BASE_2
719 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
720 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
721 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
722 0x00000000, // VGT_STRMOUT_BUFFER_BASE_3
723 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
724 0x00000000, // VGT_STRMOUT_BASE_OFFSET_0
725 0x00000000, // VGT_STRMOUT_BASE_OFFSET_1
726 0x00000000, // VGT_STRMOUT_BASE_OFFSET_2
727 0x00000000, // VGT_STRMOUT_BASE_OFFSET_3
728 0, // HOLE
729 0, // HOLE
730 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
731 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
732 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
733 0, // HOLE
734 0x00000000, // VGT_GS_MAX_VERT_OUT
735 0, // HOLE
736 0, // HOLE
737 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_0
738 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_1
739 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_2
740 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_3
741 0x00000000, // VGT_SHADER_STAGES_EN
742 0x00000000, // VGT_LS_HS_CONFIG
743 0x00000000, // VGT_LS_SIZE
744 0x00000000, // VGT_HS_SIZE
745 0x00000000, // VGT_LS_HS_ALLOC
746 0x00000000, // VGT_HS_PATCH_CONST
747 0x00000000, // VGT_TF_PARAM
748 0x00000000, // DB_ALPHA_TO_MASK
749};
750static const u32 SECT_CONTEXT_def_7[] =
751{
752 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
753 0x00000000, // PA_SU_POLY_OFFSET_CLAMP
754 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
755 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
756 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
757 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
758 0x00000000, // VGT_GS_INSTANCE_CNT
759 0x00000000, // VGT_STRMOUT_CONFIG
760 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
761 0x00000000, // CB_IMMED0_BASE
762 0x00000000, // CB_IMMED1_BASE
763 0x00000000, // CB_IMMED2_BASE
764 0x00000000, // CB_IMMED3_BASE
765 0x00000000, // CB_IMMED4_BASE
766 0x00000000, // CB_IMMED5_BASE
767 0x00000000, // CB_IMMED6_BASE
768 0x00000000, // CB_IMMED7_BASE
769 0x00000000, // CB_IMMED8_BASE
770 0x00000000, // CB_IMMED9_BASE
771 0x00000000, // CB_IMMED10_BASE
772 0x00000000, // CB_IMMED11_BASE
773 0, // HOLE
774 0, // HOLE
775 0, // HOLE
776 0, // HOLE
777 0, // HOLE
778 0, // HOLE
779 0, // HOLE
780 0, // HOLE
781 0, // HOLE
782 0, // HOLE
783 0, // HOLE
784 0, // HOLE
785 0, // HOLE
786 0x00001000, // PA_SC_LINE_CNTL
787 0x00000000, // PA_SC_AA_CONFIG
788 0x00000005, // PA_SU_VTX_CNTL
789 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
790 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
791 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
792 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
793 0x00000000, // PA_SC_AA_SAMPLE_LOCS_0
794 0x00000000, // PA_SC_AA_SAMPLE_LOCS_1
795 0x00000000, // PA_SC_AA_SAMPLE_LOCS_2
796 0x00000000, // PA_SC_AA_SAMPLE_LOCS_3
797 0x00000000, // PA_SC_AA_SAMPLE_LOCS_4
798 0x00000000, // PA_SC_AA_SAMPLE_LOCS_5
799 0x00000000, // PA_SC_AA_SAMPLE_LOCS_6
800 0x00000000, // PA_SC_AA_SAMPLE_LOCS_7
801 0xffffffff, // PA_SC_AA_MASK
802 0x00000000, // CB_CLRCMP_CONTROL
803 0x00000000, // CB_CLRCMP_SRC
804 0x00000000, // CB_CLRCMP_DST
805 0x00000000, // CB_CLRCMP_MSK
806 0, // HOLE
807 0, // HOLE
808 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
809 0x00000010, // VGT_OUT_DEALLOC_CNTL
810 0x00000000, // CB_COLOR0_BASE
811 0x00000000, // CB_COLOR0_PITCH
812 0x00000000, // CB_COLOR0_SLICE
813 0x00000000, // CB_COLOR0_VIEW
814 0x00000000, // CB_COLOR0_INFO
815 0x00000000, // CB_COLOR0_ATTRIB
816 0x00000000, // CB_COLOR0_DIM
817 0x00000000, // CB_COLOR0_CMASK
818 0x00000000, // CB_COLOR0_CMASK_SLICE
819 0x00000000, // CB_COLOR0_FMASK
820 0x00000000, // CB_COLOR0_FMASK_SLICE
821 0x00000000, // CB_COLOR0_CLEAR_WORD0
822 0x00000000, // CB_COLOR0_CLEAR_WORD1
823 0x00000000, // CB_COLOR0_CLEAR_WORD2
824 0x00000000, // CB_COLOR0_CLEAR_WORD3
825 0x00000000, // CB_COLOR1_BASE
826 0x00000000, // CB_COLOR1_PITCH
827 0x00000000, // CB_COLOR1_SLICE
828 0x00000000, // CB_COLOR1_VIEW
829 0x00000000, // CB_COLOR1_INFO
830 0x00000000, // CB_COLOR1_ATTRIB
831 0x00000000, // CB_COLOR1_DIM
832 0x00000000, // CB_COLOR1_CMASK
833 0x00000000, // CB_COLOR1_CMASK_SLICE
834 0x00000000, // CB_COLOR1_FMASK
835 0x00000000, // CB_COLOR1_FMASK_SLICE
836 0x00000000, // CB_COLOR1_CLEAR_WORD0
837 0x00000000, // CB_COLOR1_CLEAR_WORD1
838 0x00000000, // CB_COLOR1_CLEAR_WORD2
839 0x00000000, // CB_COLOR1_CLEAR_WORD3
840 0x00000000, // CB_COLOR2_BASE
841 0x00000000, // CB_COLOR2_PITCH
842 0x00000000, // CB_COLOR2_SLICE
843 0x00000000, // CB_COLOR2_VIEW
844 0x00000000, // CB_COLOR2_INFO
845 0x00000000, // CB_COLOR2_ATTRIB
846 0x00000000, // CB_COLOR2_DIM
847 0x00000000, // CB_COLOR2_CMASK
848 0x00000000, // CB_COLOR2_CMASK_SLICE
849 0x00000000, // CB_COLOR2_FMASK
850 0x00000000, // CB_COLOR2_FMASK_SLICE
851 0x00000000, // CB_COLOR2_CLEAR_WORD0
852 0x00000000, // CB_COLOR2_CLEAR_WORD1
853 0x00000000, // CB_COLOR2_CLEAR_WORD2
854 0x00000000, // CB_COLOR2_CLEAR_WORD3
855 0x00000000, // CB_COLOR3_BASE
856 0x00000000, // CB_COLOR3_PITCH
857 0x00000000, // CB_COLOR3_SLICE
858 0x00000000, // CB_COLOR3_VIEW
859 0x00000000, // CB_COLOR3_INFO
860 0x00000000, // CB_COLOR3_ATTRIB
861 0x00000000, // CB_COLOR3_DIM
862 0x00000000, // CB_COLOR3_CMASK
863 0x00000000, // CB_COLOR3_CMASK_SLICE
864 0x00000000, // CB_COLOR3_FMASK
865 0x00000000, // CB_COLOR3_FMASK_SLICE
866 0x00000000, // CB_COLOR3_CLEAR_WORD0
867 0x00000000, // CB_COLOR3_CLEAR_WORD1
868 0x00000000, // CB_COLOR3_CLEAR_WORD2
869 0x00000000, // CB_COLOR3_CLEAR_WORD3
870 0x00000000, // CB_COLOR4_BASE
871 0x00000000, // CB_COLOR4_PITCH
872 0x00000000, // CB_COLOR4_SLICE
873 0x00000000, // CB_COLOR4_VIEW
874 0x00000000, // CB_COLOR4_INFO
875 0x00000000, // CB_COLOR4_ATTRIB
876 0x00000000, // CB_COLOR4_DIM
877 0x00000000, // CB_COLOR4_CMASK
878 0x00000000, // CB_COLOR4_CMASK_SLICE
879 0x00000000, // CB_COLOR4_FMASK
880 0x00000000, // CB_COLOR4_FMASK_SLICE
881 0x00000000, // CB_COLOR4_CLEAR_WORD0
882 0x00000000, // CB_COLOR4_CLEAR_WORD1
883 0x00000000, // CB_COLOR4_CLEAR_WORD2
884 0x00000000, // CB_COLOR4_CLEAR_WORD3
885 0x00000000, // CB_COLOR5_BASE
886 0x00000000, // CB_COLOR5_PITCH
887 0x00000000, // CB_COLOR5_SLICE
888 0x00000000, // CB_COLOR5_VIEW
889 0x00000000, // CB_COLOR5_INFO
890 0x00000000, // CB_COLOR5_ATTRIB
891 0x00000000, // CB_COLOR5_DIM
892 0x00000000, // CB_COLOR5_CMASK
893 0x00000000, // CB_COLOR5_CMASK_SLICE
894 0x00000000, // CB_COLOR5_FMASK
895 0x00000000, // CB_COLOR5_FMASK_SLICE
896 0x00000000, // CB_COLOR5_CLEAR_WORD0
897 0x00000000, // CB_COLOR5_CLEAR_WORD1
898 0x00000000, // CB_COLOR5_CLEAR_WORD2
899 0x00000000, // CB_COLOR5_CLEAR_WORD3
900 0x00000000, // CB_COLOR6_BASE
901 0x00000000, // CB_COLOR6_PITCH
902 0x00000000, // CB_COLOR6_SLICE
903 0x00000000, // CB_COLOR6_VIEW
904 0x00000000, // CB_COLOR6_INFO
905 0x00000000, // CB_COLOR6_ATTRIB
906 0x00000000, // CB_COLOR6_DIM
907 0x00000000, // CB_COLOR6_CMASK
908 0x00000000, // CB_COLOR6_CMASK_SLICE
909 0x00000000, // CB_COLOR6_FMASK
910 0x00000000, // CB_COLOR6_FMASK_SLICE
911 0x00000000, // CB_COLOR6_CLEAR_WORD0
912 0x00000000, // CB_COLOR6_CLEAR_WORD1
913 0x00000000, // CB_COLOR6_CLEAR_WORD2
914 0x00000000, // CB_COLOR6_CLEAR_WORD3
915 0x00000000, // CB_COLOR7_BASE
916 0x00000000, // CB_COLOR7_PITCH
917 0x00000000, // CB_COLOR7_SLICE
918 0x00000000, // CB_COLOR7_VIEW
919 0x00000000, // CB_COLOR7_INFO
920 0x00000000, // CB_COLOR7_ATTRIB
921 0x00000000, // CB_COLOR7_DIM
922 0x00000000, // CB_COLOR7_CMASK
923 0x00000000, // CB_COLOR7_CMASK_SLICE
924 0x00000000, // CB_COLOR7_FMASK
925 0x00000000, // CB_COLOR7_FMASK_SLICE
926 0x00000000, // CB_COLOR7_CLEAR_WORD0
927 0x00000000, // CB_COLOR7_CLEAR_WORD1
928 0x00000000, // CB_COLOR7_CLEAR_WORD2
929 0x00000000, // CB_COLOR7_CLEAR_WORD3
930 0x00000000, // CB_COLOR8_BASE
931 0x00000000, // CB_COLOR8_PITCH
932 0x00000000, // CB_COLOR8_SLICE
933 0x00000000, // CB_COLOR8_VIEW
934 0x00000000, // CB_COLOR8_INFO
935 0x00000000, // CB_COLOR8_ATTRIB
936 0x00000000, // CB_COLOR8_DIM
937 0x00000000, // CB_COLOR9_BASE
938 0x00000000, // CB_COLOR9_PITCH
939 0x00000000, // CB_COLOR9_SLICE
940 0x00000000, // CB_COLOR9_VIEW
941 0x00000000, // CB_COLOR9_INFO
942 0x00000000, // CB_COLOR9_ATTRIB
943 0x00000000, // CB_COLOR9_DIM
944 0x00000000, // CB_COLOR10_BASE
945 0x00000000, // CB_COLOR10_PITCH
946 0x00000000, // CB_COLOR10_SLICE
947 0x00000000, // CB_COLOR10_VIEW
948 0x00000000, // CB_COLOR10_INFO
949 0x00000000, // CB_COLOR10_ATTRIB
950 0x00000000, // CB_COLOR10_DIM
951 0x00000000, // CB_COLOR11_BASE
952 0x00000000, // CB_COLOR11_PITCH
953 0x00000000, // CB_COLOR11_SLICE
954 0x00000000, // CB_COLOR11_VIEW
955 0x00000000, // CB_COLOR11_INFO
956 0x00000000, // CB_COLOR11_ATTRIB
957 0x00000000, // CB_COLOR11_DIM
958 0, // HOLE
959 0, // HOLE
960 0, // HOLE
961 0, // HOLE
962 0, // HOLE
963 0, // HOLE
964 0, // HOLE
965 0, // HOLE
966 0, // HOLE
967 0, // HOLE
968 0, // HOLE
969 0, // HOLE
970 0, // HOLE
971 0, // HOLE
972 0, // HOLE
973 0, // HOLE
974 0, // HOLE
975 0, // HOLE
976 0, // HOLE
977 0, // HOLE
978 0x00000000, // SQ_ALU_CONST_CACHE_HS_0
979 0x00000000, // SQ_ALU_CONST_CACHE_HS_1
980 0x00000000, // SQ_ALU_CONST_CACHE_HS_2
981 0x00000000, // SQ_ALU_CONST_CACHE_HS_3
982 0x00000000, // SQ_ALU_CONST_CACHE_HS_4
983 0x00000000, // SQ_ALU_CONST_CACHE_HS_5
984 0x00000000, // SQ_ALU_CONST_CACHE_HS_6
985 0x00000000, // SQ_ALU_CONST_CACHE_HS_7
986 0x00000000, // SQ_ALU_CONST_CACHE_HS_8
987 0x00000000, // SQ_ALU_CONST_CACHE_HS_9
988 0x00000000, // SQ_ALU_CONST_CACHE_HS_10
989 0x00000000, // SQ_ALU_CONST_CACHE_HS_11
990 0x00000000, // SQ_ALU_CONST_CACHE_HS_12
991 0x00000000, // SQ_ALU_CONST_CACHE_HS_13
992 0x00000000, // SQ_ALU_CONST_CACHE_HS_14
993 0x00000000, // SQ_ALU_CONST_CACHE_HS_15
994 0x00000000, // SQ_ALU_CONST_CACHE_LS_0
995 0x00000000, // SQ_ALU_CONST_CACHE_LS_1
996 0x00000000, // SQ_ALU_CONST_CACHE_LS_2
997 0x00000000, // SQ_ALU_CONST_CACHE_LS_3
998 0x00000000, // SQ_ALU_CONST_CACHE_LS_4
999 0x00000000, // SQ_ALU_CONST_CACHE_LS_5
1000 0x00000000, // SQ_ALU_CONST_CACHE_LS_6
1001 0x00000000, // SQ_ALU_CONST_CACHE_LS_7
1002 0x00000000, // SQ_ALU_CONST_CACHE_LS_8
1003 0x00000000, // SQ_ALU_CONST_CACHE_LS_9
1004 0x00000000, // SQ_ALU_CONST_CACHE_LS_10
1005 0x00000000, // SQ_ALU_CONST_CACHE_LS_11
1006 0x00000000, // SQ_ALU_CONST_CACHE_LS_12
1007 0x00000000, // SQ_ALU_CONST_CACHE_LS_13
1008 0x00000000, // SQ_ALU_CONST_CACHE_LS_14
1009 0x00000000, // SQ_ALU_CONST_CACHE_LS_15
1010 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_0
1011 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_1
1012 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_2
1013 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_3
1014 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_4
1015 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_5
1016 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_6
1017 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_7
1018 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_8
1019 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_9
1020 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_10
1021 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_11
1022 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_12
1023 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_13
1024 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_14
1025 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_15
1026 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_0
1027 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_1
1028 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_2
1029 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_3
1030 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_4
1031 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_5
1032 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_6
1033 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_7
1034 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_8
1035 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_9
1036 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_10
1037 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_11
1038 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_12
1039 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_13
1040 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_14
1041 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_15
1042};
1043static const struct cs_extent_def SECT_CONTEXT_defs[] =
1044{
1045 {SECT_CONTEXT_def_1, 0x0000a000, 488 },
1046 {SECT_CONTEXT_def_2, 0x0000a1f5, 6 },
1047 {SECT_CONTEXT_def_3, 0x0000a200, 55 },
1048 {SECT_CONTEXT_def_4, 0x0000a23a, 98 },
1049 {SECT_CONTEXT_def_5, 0x0000a29e, 5 },
1050 {SECT_CONTEXT_def_6, 0x0000a2a5, 56 },
1051 {SECT_CONTEXT_def_7, 0x0000a2de, 290 },
1052 { 0, 0, 0 }
1053};
1054static const u32 SECT_CLEAR_def_1[] =
1055{
1056 0xffffffff, // SQ_TEX_SAMPLER_CLEAR
1057 0xffffffff, // SQ_TEX_RESOURCE_CLEAR
1058 0xffffffff, // SQ_LOOP_BOOL_CLEAR
1059};
1060static const struct cs_extent_def SECT_CLEAR_defs[] =
1061{
1062 {SECT_CLEAR_def_1, 0x0000ffc0, 3 },
1063 { 0, 0, 0 }
1064};
1065static const u32 SECT_CTRLCONST_def_1[] =
1066{
1067 0x00000000, // SQ_VTX_BASE_VTX_LOC
1068 0x00000000, // SQ_VTX_START_INST_LOC
1069};
1070static const struct cs_extent_def SECT_CTRLCONST_defs[] =
1071{
1072 {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 },
1073 { 0, 0, 0 }
1074};
1075struct cs_section_def evergreen_cs_data[] = {
1076 { SECT_CONTEXT_defs, SECT_CONTEXT },
1077 { SECT_CLEAR_defs, SECT_CLEAR },
1078 { SECT_CTRLCONST_defs, SECT_CTRLCONST },
1079 { 0, SECT_NONE }
1080};
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 6b559cb53837..b9f64f0e003d 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -45,6 +45,94 @@ static const u32 crtc_offsets[6] =
45 EVERGREEN_CRTC5_REGISTER_OFFSET 45 EVERGREEN_CRTC5_REGISTER_OFFSET
46}; 46};
47 47
48#include "clearstate_evergreen.h"
49
50static u32 sumo_rlc_save_restore_register_list[] =
51{
52 0x98fc,
53 0x9830,
54 0x9834,
55 0x9838,
56 0x9870,
57 0x9874,
58 0x8a14,
59 0x8b24,
60 0x8bcc,
61 0x8b10,
62 0x8d00,
63 0x8d04,
64 0x8c00,
65 0x8c04,
66 0x8c08,
67 0x8c0c,
68 0x8d8c,
69 0x8c20,
70 0x8c24,
71 0x8c28,
72 0x8c18,
73 0x8c1c,
74 0x8cf0,
75 0x8e2c,
76 0x8e38,
77 0x8c30,
78 0x9508,
79 0x9688,
80 0x9608,
81 0x960c,
82 0x9610,
83 0x9614,
84 0x88c4,
85 0x88d4,
86 0xa008,
87 0x900c,
88 0x9100,
89 0x913c,
90 0x98f8,
91 0x98f4,
92 0x9b7c,
93 0x3f8c,
94 0x8950,
95 0x8954,
96 0x8a18,
97 0x8b28,
98 0x9144,
99 0x9148,
100 0x914c,
101 0x3f90,
102 0x3f94,
103 0x915c,
104 0x9160,
105 0x9178,
106 0x917c,
107 0x9180,
108 0x918c,
109 0x9190,
110 0x9194,
111 0x9198,
112 0x919c,
113 0x91a8,
114 0x91ac,
115 0x91b0,
116 0x91b4,
117 0x91b8,
118 0x91c4,
119 0x91c8,
120 0x91cc,
121 0x91d0,
122 0x91d4,
123 0x91e0,
124 0x91e4,
125 0x91ec,
126 0x91f0,
127 0x91f4,
128 0x9200,
129 0x9204,
130 0x929c,
131 0x9150,
132 0x802c,
133};
134static u32 sumo_rlc_save_restore_register_list_size = ARRAY_SIZE(sumo_rlc_save_restore_register_list);
135
48static void evergreen_gpu_init(struct radeon_device *rdev); 136static void evergreen_gpu_init(struct radeon_device *rdev);
49void evergreen_fini(struct radeon_device *rdev); 137void evergreen_fini(struct radeon_device *rdev);
50void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 138void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
@@ -3723,6 +3811,241 @@ bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
3723 return radeon_ring_test_lockup(rdev, ring); 3811 return radeon_ring_test_lockup(rdev, ring);
3724} 3812}
3725 3813
3814/*
3815 * RLC
3816 */
3817#define RLC_SAVE_RESTORE_LIST_END_MARKER 0x00000000
3818#define RLC_CLEAR_STATE_END_MARKER 0x00000001
3819
3820void sumo_rlc_fini(struct radeon_device *rdev)
3821{
3822 int r;
3823
3824 /* save restore block */
3825 if (rdev->rlc.save_restore_obj) {
3826 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3827 if (unlikely(r != 0))
3828 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3829 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3830 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3831
3832 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3833 rdev->rlc.save_restore_obj = NULL;
3834 }
3835
3836 /* clear state block */
3837 if (rdev->rlc.clear_state_obj) {
3838 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3839 if (unlikely(r != 0))
3840 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3841 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3842 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3843
3844 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3845 rdev->rlc.clear_state_obj = NULL;
3846 }
3847}
3848
3849int sumo_rlc_init(struct radeon_device *rdev)
3850{
3851 u32 *src_ptr;
3852 volatile u32 *dst_ptr;
3853 u32 dws, data, i, j, k, reg_num;
3854 u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index;
3855 u64 reg_list_mc_addr;
3856 struct cs_section_def *cs_data;
3857 int r;
3858
3859 src_ptr = rdev->rlc.reg_list;
3860 dws = rdev->rlc.reg_list_size;
3861 cs_data = rdev->rlc.cs_data;
3862
3863 /* save restore block */
3864 if (rdev->rlc.save_restore_obj == NULL) {
3865 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
3866 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
3867 if (r) {
3868 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3869 return r;
3870 }
3871 }
3872
3873 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3874 if (unlikely(r != 0)) {
3875 sumo_rlc_fini(rdev);
3876 return r;
3877 }
3878 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3879 &rdev->rlc.save_restore_gpu_addr);
3880 if (r) {
3881 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3882 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3883 sumo_rlc_fini(rdev);
3884 return r;
3885 }
3886 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
3887 if (r) {
3888 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
3889 sumo_rlc_fini(rdev);
3890 return r;
3891 }
3892 /* write the sr buffer */
3893 dst_ptr = rdev->rlc.sr_ptr;
3894 /* format:
3895 * dw0: (reg2 << 16) | reg1
3896 * dw1: reg1 save space
3897 * dw2: reg2 save space
3898 */
3899 for (i = 0; i < dws; i++) {
3900 data = src_ptr[i] >> 2;
3901 i++;
3902 if (i < dws)
3903 data |= (src_ptr[i] >> 2) << 16;
3904 j = (((i - 1) * 3) / 2);
3905 dst_ptr[j] = data;
3906 }
3907 j = ((i * 3) / 2);
3908 dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
3909
3910 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
3911 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3912
3913 /* clear state block */
3914 reg_list_num = 0;
3915 dws = 0;
3916 for (i = 0; cs_data[i].section != NULL; i++) {
3917 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
3918 reg_list_num++;
3919 dws += cs_data[i].section[j].reg_count;
3920 }
3921 }
3922 reg_list_blk_index = (3 * reg_list_num + 2);
3923 dws += reg_list_blk_index;
3924
3925 if (rdev->rlc.clear_state_obj == NULL) {
3926 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
3927 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
3928 if (r) {
3929 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3930 sumo_rlc_fini(rdev);
3931 return r;
3932 }
3933 }
3934 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3935 if (unlikely(r != 0)) {
3936 sumo_rlc_fini(rdev);
3937 return r;
3938 }
3939 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3940 &rdev->rlc.clear_state_gpu_addr);
3941 if (r) {
3942
3943 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3944 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3945 sumo_rlc_fini(rdev);
3946 return r;
3947 }
3948 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
3949 if (r) {
3950 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
3951 sumo_rlc_fini(rdev);
3952 return r;
3953 }
3954 /* set up the cs buffer */
3955 dst_ptr = rdev->rlc.cs_ptr;
3956 reg_list_hdr_blk_index = 0;
3957 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
3958 data = upper_32_bits(reg_list_mc_addr);
3959 dst_ptr[reg_list_hdr_blk_index] = data;
3960 reg_list_hdr_blk_index++;
3961 for (i = 0; cs_data[i].section != NULL; i++) {
3962 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
3963 reg_num = cs_data[i].section[j].reg_count;
3964 data = reg_list_mc_addr & 0xffffffff;
3965 dst_ptr[reg_list_hdr_blk_index] = data;
3966 reg_list_hdr_blk_index++;
3967
3968 data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
3969 dst_ptr[reg_list_hdr_blk_index] = data;
3970 reg_list_hdr_blk_index++;
3971
3972 data = 0x08000000 | (reg_num * 4);
3973 dst_ptr[reg_list_hdr_blk_index] = data;
3974 reg_list_hdr_blk_index++;
3975
3976 for (k = 0; k < reg_num; k++) {
3977 data = cs_data[i].section[j].extent[k];
3978 dst_ptr[reg_list_blk_index + k] = data;
3979 }
3980 reg_list_mc_addr += reg_num * 4;
3981 reg_list_blk_index += reg_num;
3982 }
3983 }
3984 dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
3985
3986 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
3987 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3988
3989 return 0;
3990}
3991
3992static void evergreen_rlc_start(struct radeon_device *rdev)
3993{
3994 if (rdev->flags & RADEON_IS_IGP)
3995 WREG32(RLC_CNTL, RLC_ENABLE | GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC);
3996 else
3997 WREG32(RLC_CNTL, RLC_ENABLE);
3998}
3999
4000int evergreen_rlc_resume(struct radeon_device *rdev)
4001{
4002 u32 i;
4003 const __be32 *fw_data;
4004
4005 if (!rdev->rlc_fw)
4006 return -EINVAL;
4007
4008 r600_rlc_stop(rdev);
4009
4010 WREG32(RLC_HB_CNTL, 0);
4011
4012 if (rdev->flags & RADEON_IS_IGP) {
4013 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4014 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
4015 } else {
4016 WREG32(RLC_HB_BASE, 0);
4017 WREG32(RLC_HB_RPTR, 0);
4018 WREG32(RLC_HB_WPTR, 0);
4019 }
4020 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
4021 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
4022 WREG32(RLC_MC_CNTL, 0);
4023 WREG32(RLC_UCODE_CNTL, 0);
4024
4025 fw_data = (const __be32 *)rdev->rlc_fw->data;
4026 if (rdev->family >= CHIP_ARUBA) {
4027 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
4028 WREG32(RLC_UCODE_ADDR, i);
4029 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4030 }
4031 } else if (rdev->family >= CHIP_CAYMAN) {
4032 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
4033 WREG32(RLC_UCODE_ADDR, i);
4034 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4035 }
4036 } else {
4037 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
4038 WREG32(RLC_UCODE_ADDR, i);
4039 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4040 }
4041 }
4042 WREG32(RLC_UCODE_ADDR, 0);
4043
4044 evergreen_rlc_start(rdev);
4045
4046 return 0;
4047}
4048
3726/* Interrupts */ 4049/* Interrupts */
3727 4050
3728u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) 4051u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
@@ -4721,6 +5044,18 @@ static int evergreen_startup(struct radeon_device *rdev)
4721 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 5044 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4722 } 5045 }
4723 5046
5047 /* allocate rlc buffers */
5048 if (rdev->flags & RADEON_IS_IGP) {
5049 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5050 rdev->rlc.reg_list_size = sumo_rlc_save_restore_register_list_size;
5051 rdev->rlc.cs_data = evergreen_cs_data;
5052 r = sumo_rlc_init(rdev);
5053 if (r) {
5054 DRM_ERROR("Failed to init rlc BOs!\n");
5055 return r;
5056 }
5057 }
5058
4724 /* allocate wb buffer */ 5059 /* allocate wb buffer */
4725 r = radeon_wb_init(rdev); 5060 r = radeon_wb_init(rdev);
4726 if (r) 5061 if (r)
@@ -4952,6 +5287,8 @@ int evergreen_init(struct radeon_device *rdev)
4952 r700_cp_fini(rdev); 5287 r700_cp_fini(rdev);
4953 r600_dma_fini(rdev); 5288 r600_dma_fini(rdev);
4954 r600_irq_fini(rdev); 5289 r600_irq_fini(rdev);
5290 if (rdev->flags & RADEON_IS_IGP)
5291 sumo_rlc_fini(rdev);
4955 radeon_wb_fini(rdev); 5292 radeon_wb_fini(rdev);
4956 radeon_ib_pool_fini(rdev); 5293 radeon_ib_pool_fini(rdev);
4957 radeon_irq_kms_fini(rdev); 5294 radeon_irq_kms_fini(rdev);
@@ -4980,6 +5317,8 @@ void evergreen_fini(struct radeon_device *rdev)
4980 r700_cp_fini(rdev); 5317 r700_cp_fini(rdev);
4981 r600_dma_fini(rdev); 5318 r600_dma_fini(rdev);
4982 r600_irq_fini(rdev); 5319 r600_irq_fini(rdev);
5320 if (rdev->flags & RADEON_IS_IGP)
5321 sumo_rlc_fini(rdev);
4983 radeon_wb_fini(rdev); 5322 radeon_wb_fini(rdev);
4984 radeon_ib_pool_fini(rdev); 5323 radeon_ib_pool_fini(rdev);
4985 radeon_irq_kms_fini(rdev); 5324 radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 75c05631146d..8603b7cf31a7 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -90,6 +90,25 @@
90#define CG_VCLK_STATUS 0x61c 90#define CG_VCLK_STATUS 0x61c
91#define CG_SCRATCH1 0x820 91#define CG_SCRATCH1 0x820
92 92
93#define RLC_CNTL 0x3f00
94# define RLC_ENABLE (1 << 0)
95# define GFX_POWER_GATING_ENABLE (1 << 7)
96# define GFX_POWER_GATING_SRC (1 << 8)
97#define RLC_HB_BASE 0x3f10
98#define RLC_HB_CNTL 0x3f0c
99#define RLC_HB_RPTR 0x3f20
100#define RLC_HB_WPTR 0x3f1c
101#define RLC_HB_WPTR_LSB_ADDR 0x3f14
102#define RLC_HB_WPTR_MSB_ADDR 0x3f18
103#define RLC_MC_CNTL 0x3f44
104#define RLC_UCODE_CNTL 0x3f48
105#define RLC_UCODE_ADDR 0x3f2c
106#define RLC_UCODE_DATA 0x3f30
107
108/* new for TN */
109#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
110#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
111
93#define GRBM_GFX_INDEX 0x802C 112#define GRBM_GFX_INDEX 0x802C
94#define INSTANCE_INDEX(x) ((x) << 0) 113#define INSTANCE_INDEX(x) ((x) << 0)
95#define SE_INDEX(x) ((x) << 16) 114#define SE_INDEX(x) ((x) << 16)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 92843461320d..c73d71340d27 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -34,6 +34,134 @@
34#include "ni_reg.h" 34#include "ni_reg.h"
35#include "cayman_blit_shaders.h" 35#include "cayman_blit_shaders.h"
36#include "radeon_ucode.h" 36#include "radeon_ucode.h"
37#include "clearstate_cayman.h"
38
39static u32 tn_rlc_save_restore_register_list[] =
40{
41 0x98fc,
42 0x98f0,
43 0x9834,
44 0x9838,
45 0x9870,
46 0x9874,
47 0x8a14,
48 0x8b24,
49 0x8bcc,
50 0x8b10,
51 0x8c30,
52 0x8d00,
53 0x8d04,
54 0x8c00,
55 0x8c04,
56 0x8c10,
57 0x8c14,
58 0x8d8c,
59 0x8cf0,
60 0x8e38,
61 0x9508,
62 0x9688,
63 0x9608,
64 0x960c,
65 0x9610,
66 0x9614,
67 0x88c4,
68 0x8978,
69 0x88d4,
70 0x900c,
71 0x9100,
72 0x913c,
73 0x90e8,
74 0x9354,
75 0xa008,
76 0x98f8,
77 0x9148,
78 0x914c,
79 0x3f94,
80 0x98f4,
81 0x9b7c,
82 0x3f8c,
83 0x8950,
84 0x8954,
85 0x8a18,
86 0x8b28,
87 0x9144,
88 0x3f90,
89 0x915c,
90 0x9160,
91 0x9178,
92 0x917c,
93 0x9180,
94 0x918c,
95 0x9190,
96 0x9194,
97 0x9198,
98 0x919c,
99 0x91a8,
100 0x91ac,
101 0x91b0,
102 0x91b4,
103 0x91b8,
104 0x91c4,
105 0x91c8,
106 0x91cc,
107 0x91d0,
108 0x91d4,
109 0x91e0,
110 0x91e4,
111 0x91ec,
112 0x91f0,
113 0x91f4,
114 0x9200,
115 0x9204,
116 0x929c,
117 0x8030,
118 0x9150,
119 0x9a60,
120 0x920c,
121 0x9210,
122 0x9228,
123 0x922c,
124 0x9244,
125 0x9248,
126 0x91e8,
127 0x9294,
128 0x9208,
129 0x9224,
130 0x9240,
131 0x9220,
132 0x923c,
133 0x9258,
134 0x9744,
135 0xa200,
136 0xa204,
137 0xa208,
138 0xa20c,
139 0x8d58,
140 0x9030,
141 0x9034,
142 0x9038,
143 0x903c,
144 0x9040,
145 0x9654,
146 0x897c,
147 0xa210,
148 0xa214,
149 0x9868,
150 0xa02c,
151 0x9664,
152 0x9698,
153 0x949c,
154 0x8e10,
155 0x8e18,
156 0x8c50,
157 0x8c58,
158 0x8c60,
159 0x8c68,
160 0x89b4,
161 0x9830,
162 0x802c,
163};
164static u32 tn_rlc_save_restore_register_list_size = ARRAY_SIZE(tn_rlc_save_restore_register_list);
37 165
38extern bool evergreen_is_display_hung(struct radeon_device *rdev); 166extern bool evergreen_is_display_hung(struct radeon_device *rdev);
39extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 167extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
@@ -45,8 +173,8 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev);
45extern int evergreen_mc_init(struct radeon_device *rdev); 173extern int evergreen_mc_init(struct radeon_device *rdev);
46extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 174extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
47extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 175extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
48extern void si_rlc_fini(struct radeon_device *rdev); 176extern void sumo_rlc_fini(struct radeon_device *rdev);
49extern int si_rlc_init(struct radeon_device *rdev); 177extern int sumo_rlc_init(struct radeon_device *rdev);
50 178
51/* Firmware Names */ 179/* Firmware Names */
52MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 180MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -1969,7 +2097,10 @@ static int cayman_startup(struct radeon_device *rdev)
1969 2097
1970 /* allocate rlc buffers */ 2098 /* allocate rlc buffers */
1971 if (rdev->flags & RADEON_IS_IGP) { 2099 if (rdev->flags & RADEON_IS_IGP) {
1972 r = si_rlc_init(rdev); 2100 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2101 rdev->rlc.reg_list_size = tn_rlc_save_restore_register_list_size;
2102 rdev->rlc.cs_data = cayman_cs_data;
2103 r = sumo_rlc_init(rdev);
1973 if (r) { 2104 if (r) {
1974 DRM_ERROR("Failed to init rlc BOs!\n"); 2105 DRM_ERROR("Failed to init rlc BOs!\n");
1975 return r; 2106 return r;
@@ -2226,7 +2357,7 @@ int cayman_init(struct radeon_device *rdev)
2226 cayman_dma_fini(rdev); 2357 cayman_dma_fini(rdev);
2227 r600_irq_fini(rdev); 2358 r600_irq_fini(rdev);
2228 if (rdev->flags & RADEON_IS_IGP) 2359 if (rdev->flags & RADEON_IS_IGP)
2229 si_rlc_fini(rdev); 2360 sumo_rlc_fini(rdev);
2230 radeon_wb_fini(rdev); 2361 radeon_wb_fini(rdev);
2231 radeon_ib_pool_fini(rdev); 2362 radeon_ib_pool_fini(rdev);
2232 radeon_vm_manager_fini(rdev); 2363 radeon_vm_manager_fini(rdev);
@@ -2257,7 +2388,7 @@ void cayman_fini(struct radeon_device *rdev)
2257 cayman_dma_fini(rdev); 2388 cayman_dma_fini(rdev);
2258 r600_irq_fini(rdev); 2389 r600_irq_fini(rdev);
2259 if (rdev->flags & RADEON_IS_IGP) 2390 if (rdev->flags & RADEON_IS_IGP)
2260 si_rlc_fini(rdev); 2391 sumo_rlc_fini(rdev);
2261 radeon_wb_fini(rdev); 2392 radeon_wb_fini(rdev);
2262 radeon_vm_manager_fini(rdev); 2393 radeon_vm_manager_fini(rdev);
2263 radeon_ib_pool_fini(rdev); 2394 radeon_ib_pool_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 608926180e0c..4678ed102af6 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -97,6 +97,7 @@ static void r600_gpu_init(struct radeon_device *rdev);
97void r600_fini(struct radeon_device *rdev); 97void r600_fini(struct radeon_device *rdev);
98void r600_irq_disable(struct radeon_device *rdev); 98void r600_irq_disable(struct radeon_device *rdev);
99static void r600_pcie_gen2_enable(struct radeon_device *rdev); 99static void r600_pcie_gen2_enable(struct radeon_device *rdev);
100extern int evergreen_rlc_resume(struct radeon_device *rdev);
100 101
101/** 102/**
102 * r600_get_xclk - get the xclk 103 * r600_get_xclk - get the xclk
@@ -3778,7 +3779,7 @@ static void r600_rlc_start(struct radeon_device *rdev)
3778 WREG32(RLC_CNTL, RLC_ENABLE); 3779 WREG32(RLC_CNTL, RLC_ENABLE);
3779} 3780}
3780 3781
3781static int r600_rlc_init(struct radeon_device *rdev) 3782static int r600_rlc_resume(struct radeon_device *rdev)
3782{ 3783{
3783 u32 i; 3784 u32 i;
3784 const __be32 *fw_data; 3785 const __be32 *fw_data;
@@ -3790,39 +3791,16 @@ static int r600_rlc_init(struct radeon_device *rdev)
3790 3791
3791 WREG32(RLC_HB_CNTL, 0); 3792 WREG32(RLC_HB_CNTL, 0);
3792 3793
3793 if (rdev->family == CHIP_ARUBA) { 3794 WREG32(RLC_HB_BASE, 0);
3794 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3795 WREG32(RLC_HB_RPTR, 0);
3795 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3796 WREG32(RLC_HB_WPTR, 0);
3796 } 3797 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3797 if (rdev->family <= CHIP_CAYMAN) { 3798 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3798 WREG32(RLC_HB_BASE, 0);
3799 WREG32(RLC_HB_RPTR, 0);
3800 WREG32(RLC_HB_WPTR, 0);
3801 }
3802 if (rdev->family <= CHIP_CAICOS) {
3803 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3804 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3805 }
3806 WREG32(RLC_MC_CNTL, 0); 3799 WREG32(RLC_MC_CNTL, 0);
3807 WREG32(RLC_UCODE_CNTL, 0); 3800 WREG32(RLC_UCODE_CNTL, 0);
3808 3801
3809 fw_data = (const __be32 *)rdev->rlc_fw->data; 3802 fw_data = (const __be32 *)rdev->rlc_fw->data;
3810 if (rdev->family >= CHIP_ARUBA) { 3803 if (rdev->family >= CHIP_RV770) {
3811 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3812 WREG32(RLC_UCODE_ADDR, i);
3813 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3814 }
3815 } else if (rdev->family >= CHIP_CAYMAN) {
3816 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3817 WREG32(RLC_UCODE_ADDR, i);
3818 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3819 }
3820 } else if (rdev->family >= CHIP_CEDAR) {
3821 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3822 WREG32(RLC_UCODE_ADDR, i);
3823 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3824 }
3825 } else if (rdev->family >= CHIP_RV770) {
3826 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3804 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3827 WREG32(RLC_UCODE_ADDR, i); 3805 WREG32(RLC_UCODE_ADDR, i);
3828 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3806 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
@@ -3936,7 +3914,10 @@ int r600_irq_init(struct radeon_device *rdev)
3936 r600_disable_interrupts(rdev); 3914 r600_disable_interrupts(rdev);
3937 3915
3938 /* init rlc */ 3916 /* init rlc */
3939 ret = r600_rlc_init(rdev); 3917 if (rdev->family >= CHIP_CEDAR)
3918 ret = evergreen_rlc_resume(rdev);
3919 else
3920 ret = r600_rlc_resume(rdev);
3940 if (ret) { 3921 if (ret) {
3941 r600_ih_ring_fini(rdev); 3922 r600_ih_ring_fini(rdev);
3942 return ret; 3923 return ret;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 79df558f8c40..a3f926c8f5e9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -684,10 +684,6 @@
684#define RLC_UCODE_ADDR 0x3f2c 684#define RLC_UCODE_ADDR 0x3f2c
685#define RLC_UCODE_DATA 0x3f30 685#define RLC_UCODE_DATA 0x3f30
686 686
687/* new for TN */
688#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
689#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
690
691#define SRBM_SOFT_RESET 0xe60 687#define SRBM_SOFT_RESET 0xe60
692# define SOFT_RESET_DMA (1 << 12) 688# define SOFT_RESET_DMA (1 << 12)
693# define SOFT_RESET_RLC (1 << 13) 689# define SOFT_RESET_RLC (1 << 13)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 91e615ff4288..f904ded90e0c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -821,15 +821,22 @@ struct r600_blit {
821}; 821};
822 822
823/* 823/*
824 * SI RLC stuff 824 * RLC stuff
825 */ 825 */
826struct si_rlc { 826#include "clearstate_defs.h"
827
828struct radeon_rlc {
827 /* for power gating */ 829 /* for power gating */
828 struct radeon_bo *save_restore_obj; 830 struct radeon_bo *save_restore_obj;
829 uint64_t save_restore_gpu_addr; 831 uint64_t save_restore_gpu_addr;
832 volatile uint32_t *sr_ptr;
833 u32 *reg_list;
834 u32 reg_list_size;
830 /* for clear state */ 835 /* for clear state */
831 struct radeon_bo *clear_state_obj; 836 struct radeon_bo *clear_state_obj;
832 uint64_t clear_state_gpu_addr; 837 uint64_t clear_state_gpu_addr;
838 volatile uint32_t *cs_ptr;
839 struct cs_section_def *cs_data;
833}; 840};
834 841
835int radeon_ib_get(struct radeon_device *rdev, int ring, 842int radeon_ib_get(struct radeon_device *rdev, int ring,
@@ -1773,7 +1780,7 @@ struct radeon_device {
1773 struct r600_vram_scratch vram_scratch; 1780 struct r600_vram_scratch vram_scratch;
1774 int msi_enabled; /* msi enabled */ 1781 int msi_enabled; /* msi enabled */
1775 struct r600_ih ih; /* r6/700 interrupt ring */ 1782 struct r600_ih ih; /* r6/700 interrupt ring */
1776 struct si_rlc rlc; 1783 struct radeon_rlc rlc;
1777 struct radeon_mec mec; 1784 struct radeon_mec mec;
1778 struct work_struct hotplug_work; 1785 struct work_struct hotplug_work;
1779 struct work_struct audio_work; 1786 struct work_struct audio_work;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 19:33:37 -0400