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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2013-05-10 21:08:01 -0400
committerJason Cooper <jason@lakedaemon.net>2013-05-29 15:20:04 -0400
commit29020c9a400d89798df2171fe95291d1bb295563 (patch)
tree32089cd0e1ba0e8862d7e4bccc47f58a63ffc5d6
parent3d9939c92efdd4ced672b94994959ca71b141cb8 (diff)
clk: mvebu: introduce per-clock-gate flags
Clock gates found on MVEBU SoCs get registered by a common function. To allow specific SoCs to provide tweaks introduce flags to the clock gate descriptor instead of filling up the common function SoC specific tweaks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--drivers/clk/mvebu/clk-gating-ctrl.c165
1 files changed, 78 insertions, 87 deletions
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 2f037235bdbd..1df6c4e4c200 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
28 const char *name; 28 const char *name;
29 const char *parent; 29 const char *parent;
30 int bit_idx; 30 int bit_idx;
31 unsigned long flags;
31}; 32};
32 33
33#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 34#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,11 @@ static void __init mvebu_clk_gating_setup(
88 } 89 }
89 90
90 for (n = 0; n < ctrl->num_gates; n++) { 91 for (n = 0; n < ctrl->num_gates; n++) {
91 u8 flags = 0;
92 const char *parent = 92 const char *parent =
93 (descr[n].parent) ? descr[n].parent : default_parent; 93 (descr[n].parent) ? descr[n].parent : default_parent;
94
95 /*
96 * On Armada 370, the DDR clock is a special case: it
97 * isn't taken by any driver, but should anyway be
98 * kept enabled, so we mark it as IGNORE_UNUSED for
99 * now.
100 */
101 if (!strcmp(descr[n].name, "ddr"))
102 flags |= CLK_IGNORE_UNUSED;
103
104 ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent, 94 ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
105 flags, base, descr[n].bit_idx, 0, &ctrl->lock); 95 descr[n].flags, base, descr[n].bit_idx,
96 0, &ctrl->lock);
106 WARN_ON(IS_ERR(ctrl->gates[n])); 97 WARN_ON(IS_ERR(ctrl->gates[n]));
107 } 98 }
108 of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl); 99 of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,99 +105,99 @@ static void __init mvebu_clk_gating_setup(
114 105
115#ifdef CONFIG_MACH_ARMADA_370 106#ifdef CONFIG_MACH_ARMADA_370
116static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = { 107static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
117 { "audio", NULL, 0 }, 108 { "audio", NULL, 0, 0 },
118 { "pex0_en", NULL, 1 }, 109 { "pex0_en", NULL, 1, 0 },
119 { "pex1_en", NULL, 2 }, 110 { "pex1_en", NULL, 2, 0 },
120 { "ge1", NULL, 3 }, 111 { "ge1", NULL, 3, 0 },
121 { "ge0", NULL, 4 }, 112 { "ge0", NULL, 4, 0 },
122 { "pex0", "pex0_en", 5 }, 113 { "pex0", "pex0_en", 5, 0 },
123 { "pex1", "pex1_en", 9 }, 114 { "pex1", "pex1_en", 9, 0 },
124 { "sata0", NULL, 15 }, 115 { "sata0", NULL, 15, 0 },
125 { "sdio", NULL, 17 }, 116 { "sdio", NULL, 17, 0 },
126 { "tdm", NULL, 25 }, 117 { "tdm", NULL, 25, 0 },
127 { "ddr", NULL, 28 }, 118 { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
128 { "sata1", NULL, 30 }, 119 { "sata1", NULL, 30, 0 },
129 { } 120 { }
130}; 121};
131#endif 122#endif
132 123
133#ifdef CONFIG_MACH_ARMADA_XP 124#ifdef CONFIG_MACH_ARMADA_XP
134static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = { 125static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
135 { "audio", NULL, 0 }, 126 { "audio", NULL, 0, 0 },
136 { "ge3", NULL, 1 }, 127 { "ge3", NULL, 1, 0 },
137 { "ge2", NULL, 2 }, 128 { "ge2", NULL, 2, 0 },
138 { "ge1", NULL, 3 }, 129 { "ge1", NULL, 3, 0 },
139 { "ge0", NULL, 4 }, 130 { "ge0", NULL, 4, 0 },
140 { "pex00", NULL, 5 }, 131 { "pex00", NULL, 5, 0 },
141 { "pex01", NULL, 6 }, 132 { "pex01", NULL, 6, 0 },
142 { "pex02", NULL, 7 }, 133 { "pex02", NULL, 7, 0 },
143 { "pex03", NULL, 8 }, 134 { "pex03", NULL, 8, 0 },
144 { "pex10", NULL, 9 }, 135 { "pex10", NULL, 9, 0 },
145 { "pex11", NULL, 10 }, 136 { "pex11", NULL, 10, 0 },
146 { "pex12", NULL, 11 }, 137 { "pex12", NULL, 11, 0 },
147 { "pex13", NULL, 12 }, 138 { "pex13", NULL, 12, 0 },
148 { "bp", NULL, 13 }, 139 { "bp", NULL, 13, 0 },
149 { "sata0lnk", NULL, 14 }, 140 { "sata0lnk", NULL, 14, 0 },
150 { "sata0", "sata0lnk", 15 }, 141 { "sata0", "sata0lnk", 15, 0 },
151 { "lcd", NULL, 16 }, 142 { "lcd", NULL, 16, 0 },
152 { "sdio", NULL, 17 }, 143 { "sdio", NULL, 17, 0 },
153 { "usb0", NULL, 18 }, 144 { "usb0", NULL, 18, 0 },
154 { "usb1", NULL, 19 }, 145 { "usb1", NULL, 19, 0 },
155 { "usb2", NULL, 20 }, 146 { "usb2", NULL, 20, 0 },
156 { "xor0", NULL, 22 }, 147 { "xor0", NULL, 22, 0 },
157 { "crypto", NULL, 23 }, 148 { "crypto", NULL, 23, 0 },
158 { "tdm", NULL, 25 }, 149 { "tdm", NULL, 25, 0 },
159 { "pex20", NULL, 26 }, 150 { "pex20", NULL, 26, 0 },
160 { "pex30", NULL, 27 }, 151 { "pex30", NULL, 27, 0 },
161 { "xor1", NULL, 28 }, 152 { "xor1", NULL, 28, 0 },
162 { "sata1lnk", NULL, 29 }, 153 { "sata1lnk", NULL, 29, 0 },
163 { "sata1", "sata1lnk", 30 }, 154 { "sata1", "sata1lnk", 30, 0 },
164 { } 155 { }
165}; 156};
166#endif 157#endif
167 158
168#ifdef CONFIG_ARCH_DOVE 159#ifdef CONFIG_ARCH_DOVE
169static const struct mvebu_soc_descr __initconst dove_gating_descr[] = { 160static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
170 { "usb0", NULL, 0 }, 161 { "usb0", NULL, 0, 0 },
171 { "usb1", NULL, 1 }, 162 { "usb1", NULL, 1, 0 },
172 { "ge", "gephy", 2 }, 163 { "ge", "gephy", 2, 0 },
173 { "sata", NULL, 3 }, 164 { "sata", NULL, 3, 0 },
174 { "pex0", NULL, 4 }, 165 { "pex0", NULL, 4, 0 },
175 { "pex1", NULL, 5 }, 166 { "pex1", NULL, 5, 0 },
176 { "sdio0", NULL, 8 }, 167 { "sdio0", NULL, 8, 0 },
177 { "sdio1", NULL, 9 }, 168 { "sdio1", NULL, 9, 0 },
178 { "nand", NULL, 10 }, 169 { "nand", NULL, 10, 0 },
179 { "camera", NULL, 11 }, 170 { "camera", NULL, 11, 0 },
180 { "i2s0", NULL, 12 }, 171 { "i2s0", NULL, 12, 0 },
181 { "i2s1", NULL, 13 }, 172 { "i2s1", NULL, 13, 0 },
182 { "crypto", NULL, 15 }, 173 { "crypto", NULL, 15, 0 },
183 { "ac97", NULL, 21 }, 174 { "ac97", NULL, 21, 0 },
184 { "pdma", NULL, 22 }, 175 { "pdma", NULL, 22, 0 },
185 { "xor0", NULL, 23 }, 176 { "xor0", NULL, 23, 0 },
186 { "xor1", NULL, 24 }, 177 { "xor1", NULL, 24, 0 },
187 { "gephy", NULL, 30 }, 178 { "gephy", NULL, 30, 0 },
188 { } 179 { }
189}; 180};
190#endif 181#endif
191 182
192#ifdef CONFIG_ARCH_KIRKWOOD 183#ifdef CONFIG_ARCH_KIRKWOOD
193static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = { 184static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
194 { "ge0", NULL, 0 }, 185 { "ge0", NULL, 0, 0 },
195 { "pex0", NULL, 2 }, 186 { "pex0", NULL, 2, 0 },
196 { "usb0", NULL, 3 }, 187 { "usb0", NULL, 3, 0 },
197 { "sdio", NULL, 4 }, 188 { "sdio", NULL, 4, 0 },
198 { "tsu", NULL, 5 }, 189 { "tsu", NULL, 5, 0 },
199 { "runit", NULL, 7 }, 190 { "runit", NULL, 7, 0 },
200 { "xor0", NULL, 8 }, 191 { "xor0", NULL, 8, 0 },
201 { "audio", NULL, 9 }, 192 { "audio", NULL, 9, 0 },
202 { "powersave", "cpuclk", 11 }, 193 { "powersave", "cpuclk", 11, 0 },
203 { "sata0", NULL, 14 }, 194 { "sata0", NULL, 14, 0 },
204 { "sata1", NULL, 15 }, 195 { "sata1", NULL, 15, 0 },
205 { "xor1", NULL, 16 }, 196 { "xor1", NULL, 16, 0 },
206 { "crypto", NULL, 17 }, 197 { "crypto", NULL, 17, 0 },
207 { "pex1", NULL, 18 }, 198 { "pex1", NULL, 18, 0 },
208 { "ge1", NULL, 19 }, 199 { "ge1", NULL, 19, 0 },
209 { "tdm", NULL, 20 }, 200 { "tdm", NULL, 20, 0 },
210 { } 201 { }
211}; 202};
212#endif 203#endif