MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions

MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

3 files changed, 20 insertions, 1 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 721f8fe705a4..fc0cf5ac0cf7 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -34,7 +34,7 @@ enum major_op {
         ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
         lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
         sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
-        scd_op, sdc1_op, sdc2_op, sd_op
+        scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
 };
 
 /*
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index c61a41df3363..249c61c9acf1 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -807,6 +807,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                 /* Compact branch: BEQZC || JIC */
                 regs->cp0_epc += 8;
                 break;
+        case bnezcjialc_op:
+                if (!cpu_has_mips_r6) {
+                        ret = -SIGILL;
+                        break;
+                }
+                /* Compact branch: BNEZC || JIALC */
+                if (insn.i_format.rs)
+                        regs->regs[31] = epc + 4;
+                regs->cp0_epc += 8;
+                break;
 #endif
         case cbcond0_op:
         case cbcond1_op:
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f00af84f017d..6e7920b20822 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -686,6 +686,15 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                         dec_insn.next_pc_inc;
 
                 return 1;
+        case bnezcjialc_op:
+                if (!cpu_has_mips_r6)
+                        break;
+                if (!insn.i_format.rs)
+                        regs->regs[31] = regs->cp0_epc + 4;
+                *contpc = regs->cp0_epc + dec_insn.pc_inc +
+                        dec_insn.next_pc_inc;
+
+                return 1;
 #endif
         case cop0_op:
         case cop1_op: