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authorEric Anholt <eric@anholt.net>2008-09-15 16:13:34 -0400
committerDave Airlie <airlied@linux.ie>2008-10-17 17:10:52 -0400
commit28af0a2767412937e8424364a8ece9b230bdbc83 (patch)
treee8883735390a123c0e88f53aa85568772d1e4d6a
parent4f481ed22ec0d412336a13dc4477f6d0f3688882 (diff)
drm: G33-class hardware has a newer 965-style MCH (no DCC register).
Fixes bad software fallback rendering in Mesa in dual-channel configurations. d9a2470012588dc5313a5ac8bb2f03575af00e99 Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 0c1b3a0834e1..6b3f1e4a34a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
96 */ 96 */
97 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 97 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
98 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 98 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
99 } else if (!IS_I965G(dev) || IS_I965GM(dev)) { 99 } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
100 uint32_t dcc; 100 uint32_t dcc;
101 101
102 /* On 915-945 and GM965, channel interleave by the CPU is 102 /* On 915-945 and GM965, channel interleave by the CPU is