diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-09-04 11:30:03 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-17 04:01:46 -0400 |
commit | 282740f73a93461645bb87cd62e428aa625619fb (patch) | |
tree | 4033edcd656bed75a0ba8acc0d56852faa0c4b66 | |
parent | cf532bb255920202b6483914b0e19a55f0067729 (diff) |
drm/i915: Add double_wide readout and checking
Read the double wide pipe information from hardware in
i9xx_get_pipe_config(), and check it in intel_pipe_config_compare()
For gen4+ double_wide is always false so the comparison can be done
on all platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 94c85214daf4..d01a800f8a36 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5042,6 +5042,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, | |||
5042 | } | 5042 | } |
5043 | } | 5043 | } |
5044 | 5044 | ||
5045 | if (INTEL_INFO(dev)->gen < 4) | ||
5046 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | ||
5047 | |||
5045 | intel_get_pipe_timings(crtc, pipe_config); | 5048 | intel_get_pipe_timings(crtc, pipe_config); |
5046 | 5049 | ||
5047 | i9xx_get_pfit_config(crtc, pipe_config); | 5050 | i9xx_get_pfit_config(crtc, pipe_config); |
@@ -8761,6 +8764,8 @@ intel_pipe_config_compare(struct drm_device *dev, | |||
8761 | 8764 | ||
8762 | PIPE_CONF_CHECK_I(ips_enabled); | 8765 | PIPE_CONF_CHECK_I(ips_enabled); |
8763 | 8766 | ||
8767 | PIPE_CONF_CHECK_I(double_wide); | ||
8768 | |||
8764 | PIPE_CONF_CHECK_I(shared_dpll); | 8769 | PIPE_CONF_CHECK_I(shared_dpll); |
8765 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); | 8770 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8766 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); | 8771 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |