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authorPaul Walmsley <paul@pwsan.com>2011-07-09 21:14:08 -0400
committerPaul Walmsley <paul@pwsan.com>2011-07-09 21:14:08 -0400
commit273b9465bc68d4f4bcdedc34411b231e26b48416 (patch)
tree48715a8535f1676b4dda99c6dac17b255dd7fa89
parentd826ebfa49aeb8a8f4d216165e5e00826741ad9c (diff)
omap_hwmod: share identical omap_hwmod_class, omap_hwmod_class_sysconfig arrays
To reduce kernel source file data duplication, share struct omap_hwmod_class and omap_hwmod_class_sysconfig arrays across OMAP2xxx and 3xxx hwmod data files. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c267
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c273
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c228
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c123
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c105
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h11
6 files changed, 364 insertions, 643 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6acc01f58902..f3901abf2c28 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -274,24 +274,6 @@ static struct omap_hwmod omap2420_iva_hwmod = {
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
275}; 275};
276 276
277/* Timer Common */
278static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
279 .rev_offs = 0x0000,
280 .sysc_offs = 0x0010,
281 .syss_offs = 0x0014,
282 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
283 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
284 SYSC_HAS_AUTOIDLE),
285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
286 .sysc_fields = &omap_hwmod_sysc_type1,
287};
288
289static struct omap_hwmod_class omap2420_timer_hwmod_class = {
290 .name = "timer",
291 .sysc = &omap2420_timer_sysc,
292 .rev = OMAP_TIMER_IP_VERSION_1,
293};
294
295/* timer1 */ 277/* timer1 */
296static struct omap_hwmod omap2420_timer1_hwmod; 278static struct omap_hwmod omap2420_timer1_hwmod;
297 279
@@ -334,7 +316,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
334 }, 316 },
335 .slaves = omap2420_timer1_slaves, 317 .slaves = omap2420_timer1_slaves,
336 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
337 .class = &omap2420_timer_hwmod_class, 319 .class = &omap2xxx_timer_hwmod_class,
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
339}; 321};
340 322
@@ -371,7 +353,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
371 }, 353 },
372 .slaves = omap2420_timer2_slaves, 354 .slaves = omap2420_timer2_slaves,
373 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
374 .class = &omap2420_timer_hwmod_class, 356 .class = &omap2xxx_timer_hwmod_class,
375 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
376}; 358};
377 359
@@ -408,7 +390,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
408 }, 390 },
409 .slaves = omap2420_timer3_slaves, 391 .slaves = omap2420_timer3_slaves,
410 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
411 .class = &omap2420_timer_hwmod_class, 393 .class = &omap2xxx_timer_hwmod_class,
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
413}; 395};
414 396
@@ -445,7 +427,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
445 }, 427 },
446 .slaves = omap2420_timer4_slaves, 428 .slaves = omap2420_timer4_slaves,
447 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
448 .class = &omap2420_timer_hwmod_class, 430 .class = &omap2xxx_timer_hwmod_class,
449 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
450}; 432};
451 433
@@ -482,7 +464,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
482 }, 464 },
483 .slaves = omap2420_timer5_slaves, 465 .slaves = omap2420_timer5_slaves,
484 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
485 .class = &omap2420_timer_hwmod_class, 467 .class = &omap2xxx_timer_hwmod_class,
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
487}; 469};
488 470
@@ -520,7 +502,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
520 }, 502 },
521 .slaves = omap2420_timer6_slaves, 503 .slaves = omap2420_timer6_slaves,
522 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
523 .class = &omap2420_timer_hwmod_class, 505 .class = &omap2xxx_timer_hwmod_class,
524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
525}; 507};
526 508
@@ -557,7 +539,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
557 }, 539 },
558 .slaves = omap2420_timer7_slaves, 540 .slaves = omap2420_timer7_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
560 .class = &omap2420_timer_hwmod_class, 542 .class = &omap2xxx_timer_hwmod_class,
561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
562}; 544};
563 545
@@ -594,7 +576,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
594 }, 576 },
595 .slaves = omap2420_timer8_slaves, 577 .slaves = omap2420_timer8_slaves,
596 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
597 .class = &omap2420_timer_hwmod_class, 579 .class = &omap2xxx_timer_hwmod_class,
598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
599}; 581};
600 582
@@ -631,7 +613,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
631 }, 613 },
632 .slaves = omap2420_timer9_slaves, 614 .slaves = omap2420_timer9_slaves,
633 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
634 .class = &omap2420_timer_hwmod_class, 616 .class = &omap2xxx_timer_hwmod_class,
635 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
636}; 618};
637 619
@@ -668,7 +650,7 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
668 }, 650 },
669 .slaves = omap2420_timer10_slaves, 651 .slaves = omap2420_timer10_slaves,
670 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
671 .class = &omap2420_timer_hwmod_class, 653 .class = &omap2xxx_timer_hwmod_class,
672 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
673}; 655};
674 656
@@ -705,7 +687,7 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
705 }, 687 },
706 .slaves = omap2420_timer11_slaves, 688 .slaves = omap2420_timer11_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
708 .class = &omap2420_timer_hwmod_class, 690 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
710}; 692};
711 693
@@ -742,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
742 }, 724 },
743 .slaves = omap2420_timer12_slaves, 725 .slaves = omap2420_timer12_slaves,
744 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
745 .class = &omap2420_timer_hwmod_class, 727 .class = &omap2xxx_timer_hwmod_class,
746 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
747}; 729};
748 730
@@ -764,27 +746,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
764 .user = OCP_USER_MPU | OCP_USER_SDMA, 746 .user = OCP_USER_MPU | OCP_USER_SDMA,
765}; 747};
766 748
767/*
768 * 'wd_timer' class
769 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
770 * overflow condition
771 */
772
773static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
774 .rev_offs = 0x0000,
775 .sysc_offs = 0x0010,
776 .syss_offs = 0x0014,
777 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
778 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
779 .sysc_fields = &omap_hwmod_sysc_type1,
780};
781
782static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
783 .name = "wd_timer",
784 .sysc = &omap2420_wd_timer_sysc,
785 .pre_shutdown = &omap2_wd_timer_disable
786};
787
788/* wd_timer2 */ 749/* wd_timer2 */
789static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 750static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
790 &omap2420_l4_wkup__wd_timer2, 751 &omap2420_l4_wkup__wd_timer2,
@@ -792,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
792 753
793static struct omap_hwmod omap2420_wd_timer2_hwmod = { 754static struct omap_hwmod omap2420_wd_timer2_hwmod = {
794 .name = "wd_timer2", 755 .name = "wd_timer2",
795 .class = &omap2420_wd_timer_hwmod_class, 756 .class = &omap2xxx_wd_timer_hwmod_class,
796 .main_clk = "mpu_wdt_fck", 757 .main_clk = "mpu_wdt_fck",
797 .prcm = { 758 .prcm = {
798 .omap2 = { 759 .omap2 = {
@@ -808,24 +769,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
808 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
809}; 770};
810 771
811/* UART */
812
813static struct omap_hwmod_class_sysconfig uart_sysc = {
814 .rev_offs = 0x50,
815 .sysc_offs = 0x54,
816 .syss_offs = 0x58,
817 .sysc_flags = (SYSC_HAS_SIDLEMODE |
818 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
819 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
820 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
821 .sysc_fields = &omap_hwmod_sysc_type1,
822};
823
824static struct omap_hwmod_class uart_class = {
825 .name = "uart",
826 .sysc = &uart_sysc,
827};
828
829/* UART1 */ 772/* UART1 */
830 773
831static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 774static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
@@ -848,7 +791,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
848 }, 791 },
849 .slaves = omap2420_uart1_slaves, 792 .slaves = omap2420_uart1_slaves,
850 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
851 .class = &uart_class, 794 .class = &omap2_uart_class,
852 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
853}; 796};
854 797
@@ -874,7 +817,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
874 }, 817 },
875 .slaves = omap2420_uart2_slaves, 818 .slaves = omap2420_uart2_slaves,
876 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
877 .class = &uart_class, 820 .class = &omap2_uart_class,
878 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
879}; 822};
880 823
@@ -900,28 +843,10 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
900 }, 843 },
901 .slaves = omap2420_uart3_slaves, 844 .slaves = omap2420_uart3_slaves,
902 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
903 .class = &uart_class, 846 .class = &omap2_uart_class,
904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
905}; 848};
906 849
907/*
908 * 'dss' class
909 * display sub-system
910 */
911
912static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
913 .rev_offs = 0x0000,
914 .sysc_offs = 0x0010,
915 .syss_offs = 0x0014,
916 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
917 .sysc_fields = &omap_hwmod_sysc_type1,
918};
919
920static struct omap_hwmod_class omap2420_dss_hwmod_class = {
921 .name = "dss",
922 .sysc = &omap2420_dss_sysc,
923};
924
925/* dss */ 850/* dss */
926/* dss master ports */ 851/* dss master ports */
927static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 852static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
@@ -955,7 +880,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
955 880
956static struct omap_hwmod omap2420_dss_core_hwmod = { 881static struct omap_hwmod omap2420_dss_core_hwmod = {
957 .name = "dss_core", 882 .name = "dss_core",
958 .class = &omap2420_dss_hwmod_class, 883 .class = &omap2_dss_hwmod_class,
959 .main_clk = "dss1_fck", /* instead of dss_fck */ 884 .main_clk = "dss1_fck", /* instead of dss_fck */
960 .sdma_reqs = omap2xxx_dss_sdma_chs, 885 .sdma_reqs = omap2xxx_dss_sdma_chs,
961 .prcm = { 886 .prcm = {
@@ -977,27 +902,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
977 .flags = HWMOD_NO_IDLEST, 902 .flags = HWMOD_NO_IDLEST,
978}; 903};
979 904
980/*
981 * 'dispc' class
982 * display controller
983 */
984
985static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
986 .rev_offs = 0x0000,
987 .sysc_offs = 0x0010,
988 .syss_offs = 0x0014,
989 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
990 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
991 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
992 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
993 .sysc_fields = &omap_hwmod_sysc_type1,
994};
995
996static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
997 .name = "dispc",
998 .sysc = &omap2420_dispc_sysc,
999};
1000
1001/* l4_core -> dss_dispc */ 905/* l4_core -> dss_dispc */
1002static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 906static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1003 .master = &omap2420_l4_core_hwmod, 907 .master = &omap2420_l4_core_hwmod,
@@ -1020,7 +924,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1020 924
1021static struct omap_hwmod omap2420_dss_dispc_hwmod = { 925static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1022 .name = "dss_dispc", 926 .name = "dss_dispc",
1023 .class = &omap2420_dispc_hwmod_class, 927 .class = &omap2_dispc_hwmod_class,
1024 .mpu_irqs = omap2_dispc_irqs, 928 .mpu_irqs = omap2_dispc_irqs,
1025 .main_clk = "dss1_fck", 929 .main_clk = "dss1_fck",
1026 .prcm = { 930 .prcm = {
@@ -1038,26 +942,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1038 .flags = HWMOD_NO_IDLEST, 942 .flags = HWMOD_NO_IDLEST,
1039}; 943};
1040 944
1041/*
1042 * 'rfbi' class
1043 * remote frame buffer interface
1044 */
1045
1046static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1047 .rev_offs = 0x0000,
1048 .sysc_offs = 0x0010,
1049 .syss_offs = 0x0014,
1050 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1051 SYSC_HAS_AUTOIDLE),
1052 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1053 .sysc_fields = &omap_hwmod_sysc_type1,
1054};
1055
1056static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1057 .name = "rfbi",
1058 .sysc = &omap2420_rfbi_sysc,
1059};
1060
1061/* l4_core -> dss_rfbi */ 945/* l4_core -> dss_rfbi */
1062static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 946static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1063 .master = &omap2420_l4_core_hwmod, 947 .master = &omap2420_l4_core_hwmod,
@@ -1080,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1080 964
1081static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 965static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1082 .name = "dss_rfbi", 966 .name = "dss_rfbi",
1083 .class = &omap2420_rfbi_hwmod_class, 967 .class = &omap2_rfbi_hwmod_class,
1084 .main_clk = "dss1_fck", 968 .main_clk = "dss1_fck",
1085 .prcm = { 969 .prcm = {
1086 .omap2 = { 970 .omap2 = {
@@ -1095,15 +979,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1095 .flags = HWMOD_NO_IDLEST, 979 .flags = HWMOD_NO_IDLEST,
1096}; 980};
1097 981
1098/*
1099 * 'venc' class
1100 * video encoder
1101 */
1102
1103static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1104 .name = "venc",
1105};
1106
1107/* l4_core -> dss_venc */ 982/* l4_core -> dss_venc */
1108static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 983static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1109 .master = &omap2420_l4_core_hwmod, 984 .master = &omap2420_l4_core_hwmod,
@@ -1127,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1127 1002
1128static struct omap_hwmod omap2420_dss_venc_hwmod = { 1003static struct omap_hwmod omap2420_dss_venc_hwmod = {
1129 .name = "dss_venc", 1004 .name = "dss_venc",
1130 .class = &omap2420_venc_hwmod_class, 1005 .class = &omap2_venc_hwmod_class,
1131 .main_clk = "dss1_fck", 1006 .main_clk = "dss1_fck",
1132 .prcm = { 1007 .prcm = {
1133 .omap2 = { 1008 .omap2 = {
@@ -1292,27 +1167,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1292 .dbck_flag = false, 1167 .dbck_flag = false,
1293}; 1168};
1294 1169
1295static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1296 .rev_offs = 0x0000,
1297 .sysc_offs = 0x0010,
1298 .syss_offs = 0x0014,
1299 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1300 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1301 SYSS_HAS_RESET_STATUS),
1302 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1303 .sysc_fields = &omap_hwmod_sysc_type1,
1304};
1305
1306/*
1307 * 'gpio' class
1308 * general purpose io module
1309 */
1310static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1311 .name = "gpio",
1312 .sysc = &omap242x_gpio_sysc,
1313 .rev = 0,
1314};
1315
1316/* gpio1 */ 1170/* gpio1 */
1317static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1171static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1318 &omap2420_l4_wkup__gpio1, 1172 &omap2420_l4_wkup__gpio1,
@@ -1334,7 +1188,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
1334 }, 1188 },
1335 .slaves = omap2420_gpio1_slaves, 1189 .slaves = omap2420_gpio1_slaves,
1336 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1190 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1337 .class = &omap242x_gpio_hwmod_class, 1191 .class = &omap2xxx_gpio_hwmod_class,
1338 .dev_attr = &gpio_dev_attr, 1192 .dev_attr = &gpio_dev_attr,
1339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1193 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1340}; 1194};
@@ -1360,7 +1214,7 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
1360 }, 1214 },
1361 .slaves = omap2420_gpio2_slaves, 1215 .slaves = omap2420_gpio2_slaves,
1362 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1216 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1363 .class = &omap242x_gpio_hwmod_class, 1217 .class = &omap2xxx_gpio_hwmod_class,
1364 .dev_attr = &gpio_dev_attr, 1218 .dev_attr = &gpio_dev_attr,
1365 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1366}; 1220};
@@ -1386,7 +1240,7 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
1386 }, 1240 },
1387 .slaves = omap2420_gpio3_slaves, 1241 .slaves = omap2420_gpio3_slaves,
1388 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1242 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1389 .class = &omap242x_gpio_hwmod_class, 1243 .class = &omap2xxx_gpio_hwmod_class,
1390 .dev_attr = &gpio_dev_attr, 1244 .dev_attr = &gpio_dev_attr,
1391 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1392}; 1246};
@@ -1412,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
1412 }, 1266 },
1413 .slaves = omap2420_gpio4_slaves, 1267 .slaves = omap2420_gpio4_slaves,
1414 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1268 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1415 .class = &omap242x_gpio_hwmod_class, 1269 .class = &omap2xxx_gpio_hwmod_class,
1416 .dev_attr = &gpio_dev_attr, 1270 .dev_attr = &gpio_dev_attr,
1417 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1271 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1418}; 1272};
1419 1273
1420/* system dma */
1421static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1422 .rev_offs = 0x0000,
1423 .sysc_offs = 0x002c,
1424 .syss_offs = 0x0028,
1425 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1426 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1427 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1428 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1429 .sysc_fields = &omap_hwmod_sysc_type1,
1430};
1431
1432static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1433 .name = "dma",
1434 .sysc = &omap2420_dma_sysc,
1435};
1436
1437/* dma attributes */ 1274/* dma attributes */
1438static struct omap_dma_dev_attr dma_dev_attr = { 1275static struct omap_dma_dev_attr dma_dev_attr = {
1439 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1276 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1470,7 +1307,7 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1470 1307
1471static struct omap_hwmod omap2420_dma_system_hwmod = { 1308static struct omap_hwmod omap2420_dma_system_hwmod = {
1472 .name = "dma", 1309 .name = "dma",
1473 .class = &omap2420_dma_hwmod_class, 1310 .class = &omap2xxx_dma_hwmod_class,
1474 .mpu_irqs = omap2_dma_system_irqs, 1311 .mpu_irqs = omap2_dma_system_irqs,
1475 .main_clk = "core_l3_ck", 1312 .main_clk = "core_l3_ck",
1476 .slaves = omap2420_dma_system_slaves, 1313 .slaves = omap2420_dma_system_slaves,
@@ -1482,27 +1319,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1482 .flags = HWMOD_NO_IDLEST, 1319 .flags = HWMOD_NO_IDLEST,
1483}; 1320};
1484 1321
1485/*
1486 * 'mailbox' class
1487 * mailbox module allowing communication between the on-chip processors
1488 * using a queued mailbox-interrupt mechanism.
1489 */
1490
1491static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1492 .rev_offs = 0x000,
1493 .sysc_offs = 0x010,
1494 .syss_offs = 0x014,
1495 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1496 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1497 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1498 .sysc_fields = &omap_hwmod_sysc_type1,
1499};
1500
1501static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1502 .name = "mailbox",
1503 .sysc = &omap2420_mailbox_sysc,
1504};
1505
1506/* mailbox */ 1322/* mailbox */
1507static struct omap_hwmod omap2420_mailbox_hwmod; 1323static struct omap_hwmod omap2420_mailbox_hwmod;
1508static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1324static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
@@ -1526,7 +1342,7 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1526 1342
1527static struct omap_hwmod omap2420_mailbox_hwmod = { 1343static struct omap_hwmod omap2420_mailbox_hwmod = {
1528 .name = "mailbox", 1344 .name = "mailbox",
1529 .class = &omap2420_mailbox_hwmod_class, 1345 .class = &omap2xxx_mailbox_hwmod_class,
1530 .mpu_irqs = omap2420_mailbox_irqs, 1346 .mpu_irqs = omap2420_mailbox_irqs,
1531 .main_clk = "mailboxes_ick", 1347 .main_clk = "mailboxes_ick",
1532 .prcm = { 1348 .prcm = {
@@ -1543,29 +1359,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
1543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1359 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1544}; 1360};
1545 1361
1546/*
1547 * 'mcspi' class
1548 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1549 * bus
1550 */
1551
1552static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1553 .rev_offs = 0x0000,
1554 .sysc_offs = 0x0010,
1555 .syss_offs = 0x0014,
1556 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1557 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1558 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1559 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1560 .sysc_fields = &omap_hwmod_sysc_type1,
1561};
1562
1563static struct omap_hwmod_class omap2420_mcspi_class = {
1564 .name = "mcspi",
1565 .sysc = &omap2420_mcspi_sysc,
1566 .rev = OMAP2_MCSPI_REV,
1567};
1568
1569/* mcspi1 */ 1362/* mcspi1 */
1570static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1363static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1571 &omap2420_l4_core__mcspi1, 1364 &omap2420_l4_core__mcspi1,
@@ -1591,8 +1384,8 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
1591 }, 1384 },
1592 .slaves = omap2420_mcspi1_slaves, 1385 .slaves = omap2420_mcspi1_slaves,
1593 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1386 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1594 .class = &omap2420_mcspi_class, 1387 .class = &omap2xxx_mcspi_class,
1595 .dev_attr = &omap_mcspi1_dev_attr, 1388 .dev_attr = &omap_mcspi1_dev_attr,
1596 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1597}; 1390};
1598 1391
@@ -1621,8 +1414,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
1621 }, 1414 },
1622 .slaves = omap2420_mcspi2_slaves, 1415 .slaves = omap2420_mcspi2_slaves,
1623 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1416 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1624 .class = &omap2420_mcspi_class, 1417 .class = &omap2xxx_mcspi_class,
1625 .dev_attr = &omap_mcspi2_dev_attr, 1418 .dev_attr = &omap_mcspi2_dev_attr,
1626 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1419 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1627}; 1420};
1628 1421
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 639acd598c92..2a52f025bd06 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -347,24 +347,6 @@ static struct omap_hwmod omap2430_iva_hwmod = {
347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
348}; 348};
349 349
350/* Timer Common */
351static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
352 .rev_offs = 0x0000,
353 .sysc_offs = 0x0010,
354 .syss_offs = 0x0014,
355 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
356 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
357 SYSC_HAS_AUTOIDLE),
358 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
359 .sysc_fields = &omap_hwmod_sysc_type1,
360};
361
362static struct omap_hwmod_class omap2430_timer_hwmod_class = {
363 .name = "timer",
364 .sysc = &omap2430_timer_sysc,
365 .rev = OMAP_TIMER_IP_VERSION_1,
366};
367
368/* timer1 */ 350/* timer1 */
369static struct omap_hwmod omap2430_timer1_hwmod; 351static struct omap_hwmod omap2430_timer1_hwmod;
370 352
@@ -407,7 +389,7 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
407 }, 389 },
408 .slaves = omap2430_timer1_slaves, 390 .slaves = omap2430_timer1_slaves,
409 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), 391 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
410 .class = &omap2430_timer_hwmod_class, 392 .class = &omap2xxx_timer_hwmod_class,
411 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
412}; 394};
413 395
@@ -444,7 +426,7 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
444 }, 426 },
445 .slaves = omap2430_timer2_slaves, 427 .slaves = omap2430_timer2_slaves,
446 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), 428 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
447 .class = &omap2430_timer_hwmod_class, 429 .class = &omap2xxx_timer_hwmod_class,
448 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 430 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
449}; 431};
450 432
@@ -481,7 +463,7 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
481 }, 463 },
482 .slaves = omap2430_timer3_slaves, 464 .slaves = omap2430_timer3_slaves,
483 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), 465 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
484 .class = &omap2430_timer_hwmod_class, 466 .class = &omap2xxx_timer_hwmod_class,
485 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 467 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
486}; 468};
487 469
@@ -518,7 +500,7 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
518 }, 500 },
519 .slaves = omap2430_timer4_slaves, 501 .slaves = omap2430_timer4_slaves,
520 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), 502 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
521 .class = &omap2430_timer_hwmod_class, 503 .class = &omap2xxx_timer_hwmod_class,
522 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 504 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
523}; 505};
524 506
@@ -555,7 +537,7 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
555 }, 537 },
556 .slaves = omap2430_timer5_slaves, 538 .slaves = omap2430_timer5_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), 539 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
558 .class = &omap2430_timer_hwmod_class, 540 .class = &omap2xxx_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 541 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560}; 542};
561 543
@@ -592,7 +574,7 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
592 }, 574 },
593 .slaves = omap2430_timer6_slaves, 575 .slaves = omap2430_timer6_slaves,
594 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), 576 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
595 .class = &omap2430_timer_hwmod_class, 577 .class = &omap2xxx_timer_hwmod_class,
596 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 578 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
597}; 579};
598 580
@@ -629,7 +611,7 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
629 }, 611 },
630 .slaves = omap2430_timer7_slaves, 612 .slaves = omap2430_timer7_slaves,
631 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), 613 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
632 .class = &omap2430_timer_hwmod_class, 614 .class = &omap2xxx_timer_hwmod_class,
633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 615 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
634}; 616};
635 617
@@ -666,7 +648,7 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
666 }, 648 },
667 .slaves = omap2430_timer8_slaves, 649 .slaves = omap2430_timer8_slaves,
668 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), 650 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
669 .class = &omap2430_timer_hwmod_class, 651 .class = &omap2xxx_timer_hwmod_class,
670 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 652 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
671}; 653};
672 654
@@ -703,7 +685,7 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
703 }, 685 },
704 .slaves = omap2430_timer9_slaves, 686 .slaves = omap2430_timer9_slaves,
705 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), 687 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
706 .class = &omap2430_timer_hwmod_class, 688 .class = &omap2xxx_timer_hwmod_class,
707 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 689 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
708}; 690};
709 691
@@ -740,7 +722,7 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
740 }, 722 },
741 .slaves = omap2430_timer10_slaves, 723 .slaves = omap2430_timer10_slaves,
742 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), 724 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
743 .class = &omap2430_timer_hwmod_class, 725 .class = &omap2xxx_timer_hwmod_class,
744 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 726 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
745}; 727};
746 728
@@ -777,7 +759,7 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
777 }, 759 },
778 .slaves = omap2430_timer11_slaves, 760 .slaves = omap2430_timer11_slaves,
779 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), 761 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
780 .class = &omap2430_timer_hwmod_class, 762 .class = &omap2xxx_timer_hwmod_class,
781 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 763 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
782}; 764};
783 765
@@ -814,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
814 }, 796 },
815 .slaves = omap2430_timer12_slaves, 797 .slaves = omap2430_timer12_slaves,
816 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), 798 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
817 .class = &omap2430_timer_hwmod_class, 799 .class = &omap2xxx_timer_hwmod_class,
818 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
819}; 801};
820 802
@@ -836,27 +818,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
836 .user = OCP_USER_MPU | OCP_USER_SDMA, 818 .user = OCP_USER_MPU | OCP_USER_SDMA,
837}; 819};
838 820
839/*
840 * 'wd_timer' class
841 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
842 * overflow condition
843 */
844
845static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
846 .rev_offs = 0x0,
847 .sysc_offs = 0x0010,
848 .syss_offs = 0x0014,
849 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
850 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
851 .sysc_fields = &omap_hwmod_sysc_type1,
852};
853
854static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
855 .name = "wd_timer",
856 .sysc = &omap2430_wd_timer_sysc,
857 .pre_shutdown = &omap2_wd_timer_disable
858};
859
860/* wd_timer2 */ 821/* wd_timer2 */
861static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { 822static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
862 &omap2430_l4_wkup__wd_timer2, 823 &omap2430_l4_wkup__wd_timer2,
@@ -864,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
864 825
865static struct omap_hwmod omap2430_wd_timer2_hwmod = { 826static struct omap_hwmod omap2430_wd_timer2_hwmod = {
866 .name = "wd_timer2", 827 .name = "wd_timer2",
867 .class = &omap2430_wd_timer_hwmod_class, 828 .class = &omap2xxx_wd_timer_hwmod_class,
868 .main_clk = "mpu_wdt_fck", 829 .main_clk = "mpu_wdt_fck",
869 .prcm = { 830 .prcm = {
870 .omap2 = { 831 .omap2 = {
@@ -880,24 +841,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
880 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 841 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
881}; 842};
882 843
883/* UART */
884
885static struct omap_hwmod_class_sysconfig uart_sysc = {
886 .rev_offs = 0x50,
887 .sysc_offs = 0x54,
888 .syss_offs = 0x58,
889 .sysc_flags = (SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
891 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 .sysc_fields = &omap_hwmod_sysc_type1,
894};
895
896static struct omap_hwmod_class uart_class = {
897 .name = "uart",
898 .sysc = &uart_sysc,
899};
900
901/* UART1 */ 844/* UART1 */
902 845
903static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { 846static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
@@ -920,7 +863,7 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
920 }, 863 },
921 .slaves = omap2430_uart1_slaves, 864 .slaves = omap2430_uart1_slaves,
922 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), 865 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
923 .class = &uart_class, 866 .class = &omap2_uart_class,
924 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 867 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
925}; 868};
926 869
@@ -946,7 +889,7 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
946 }, 889 },
947 .slaves = omap2430_uart2_slaves, 890 .slaves = omap2430_uart2_slaves,
948 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), 891 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
949 .class = &uart_class, 892 .class = &omap2_uart_class,
950 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 893 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
951}; 894};
952 895
@@ -972,28 +915,10 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
972 }, 915 },
973 .slaves = omap2430_uart3_slaves, 916 .slaves = omap2430_uart3_slaves,
974 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), 917 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
975 .class = &uart_class, 918 .class = &omap2_uart_class,
976 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 919 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
977}; 920};
978 921
979/*
980 * 'dss' class
981 * display sub-system
982 */
983
984static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
985 .rev_offs = 0x0000,
986 .sysc_offs = 0x0010,
987 .syss_offs = 0x0014,
988 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
989 .sysc_fields = &omap_hwmod_sysc_type1,
990};
991
992static struct omap_hwmod_class omap2430_dss_hwmod_class = {
993 .name = "dss",
994 .sysc = &omap2430_dss_sysc,
995};
996
997/* dss */ 922/* dss */
998/* dss master ports */ 923/* dss master ports */
999static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { 924static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
@@ -1021,7 +946,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1021 946
1022static struct omap_hwmod omap2430_dss_core_hwmod = { 947static struct omap_hwmod omap2430_dss_core_hwmod = {
1023 .name = "dss_core", 948 .name = "dss_core",
1024 .class = &omap2430_dss_hwmod_class, 949 .class = &omap2_dss_hwmod_class,
1025 .main_clk = "dss1_fck", /* instead of dss_fck */ 950 .main_clk = "dss1_fck", /* instead of dss_fck */
1026 .sdma_reqs = omap2xxx_dss_sdma_chs, 951 .sdma_reqs = omap2xxx_dss_sdma_chs,
1027 .prcm = { 952 .prcm = {
@@ -1043,27 +968,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
1043 .flags = HWMOD_NO_IDLEST, 968 .flags = HWMOD_NO_IDLEST,
1044}; 969};
1045 970
1046/*
1047 * 'dispc' class
1048 * display controller
1049 */
1050
1051static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .syss_offs = 0x0014,
1055 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1056 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1059 .sysc_fields = &omap_hwmod_sysc_type1,
1060};
1061
1062static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1063 .name = "dispc",
1064 .sysc = &omap2430_dispc_sysc,
1065};
1066
1067/* l4_core -> dss_dispc */ 971/* l4_core -> dss_dispc */
1068static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { 972static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1069 .master = &omap2430_l4_core_hwmod, 973 .master = &omap2430_l4_core_hwmod,
@@ -1080,7 +984,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1080 984
1081static struct omap_hwmod omap2430_dss_dispc_hwmod = { 985static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1082 .name = "dss_dispc", 986 .name = "dss_dispc",
1083 .class = &omap2430_dispc_hwmod_class, 987 .class = &omap2_dispc_hwmod_class,
1084 .mpu_irqs = omap2_dispc_irqs, 988 .mpu_irqs = omap2_dispc_irqs,
1085 .main_clk = "dss1_fck", 989 .main_clk = "dss1_fck",
1086 .prcm = { 990 .prcm = {
@@ -1098,26 +1002,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1098 .flags = HWMOD_NO_IDLEST, 1002 .flags = HWMOD_NO_IDLEST,
1099}; 1003};
1100 1004
1101/*
1102 * 'rfbi' class
1103 * remote frame buffer interface
1104 */
1105
1106static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1107 .rev_offs = 0x0000,
1108 .sysc_offs = 0x0010,
1109 .syss_offs = 0x0014,
1110 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1111 SYSC_HAS_AUTOIDLE),
1112 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1113 .sysc_fields = &omap_hwmod_sysc_type1,
1114};
1115
1116static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1117 .name = "rfbi",
1118 .sysc = &omap2430_rfbi_sysc,
1119};
1120
1121/* l4_core -> dss_rfbi */ 1005/* l4_core -> dss_rfbi */
1122static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { 1006static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1123 .master = &omap2430_l4_core_hwmod, 1007 .master = &omap2430_l4_core_hwmod,
@@ -1134,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1134 1018
1135static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1136 .name = "dss_rfbi", 1020 .name = "dss_rfbi",
1137 .class = &omap2430_rfbi_hwmod_class, 1021 .class = &omap2_rfbi_hwmod_class,
1138 .main_clk = "dss1_fck", 1022 .main_clk = "dss1_fck",
1139 .prcm = { 1023 .prcm = {
1140 .omap2 = { 1024 .omap2 = {
@@ -1149,15 +1033,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1149 .flags = HWMOD_NO_IDLEST, 1033 .flags = HWMOD_NO_IDLEST,
1150}; 1034};
1151 1035
1152/*
1153 * 'venc' class
1154 * video encoder
1155 */
1156
1157static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1158 .name = "venc",
1159};
1160
1161/* l4_core -> dss_venc */ 1036/* l4_core -> dss_venc */
1162static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1037static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1163 .master = &omap2430_l4_core_hwmod, 1038 .master = &omap2430_l4_core_hwmod,
@@ -1175,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1175 1050
1176static struct omap_hwmod omap2430_dss_venc_hwmod = { 1051static struct omap_hwmod omap2430_dss_venc_hwmod = {
1177 .name = "dss_venc", 1052 .name = "dss_venc",
1178 .class = &omap2430_venc_hwmod_class, 1053 .class = &omap2_venc_hwmod_class,
1179 .main_clk = "dss1_fck", 1054 .main_clk = "dss1_fck",
1180 .prcm = { 1055 .prcm = {
1181 .omap2 = { 1056 .omap2 = {
@@ -1367,27 +1242,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1367 .dbck_flag = false, 1242 .dbck_flag = false,
1368}; 1243};
1369 1244
1370static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1371 .rev_offs = 0x0000,
1372 .sysc_offs = 0x0010,
1373 .syss_offs = 0x0014,
1374 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1375 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1376 SYSS_HAS_RESET_STATUS),
1377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1378 .sysc_fields = &omap_hwmod_sysc_type1,
1379};
1380
1381/*
1382 * 'gpio' class
1383 * general purpose io module
1384 */
1385static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1386 .name = "gpio",
1387 .sysc = &omap243x_gpio_sysc,
1388 .rev = 0,
1389};
1390
1391/* gpio1 */ 1245/* gpio1 */
1392static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { 1246static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1393 &omap2430_l4_wkup__gpio1, 1247 &omap2430_l4_wkup__gpio1,
@@ -1409,7 +1263,7 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
1409 }, 1263 },
1410 .slaves = omap2430_gpio1_slaves, 1264 .slaves = omap2430_gpio1_slaves,
1411 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), 1265 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1412 .class = &omap243x_gpio_hwmod_class, 1266 .class = &omap2xxx_gpio_hwmod_class,
1413 .dev_attr = &gpio_dev_attr, 1267 .dev_attr = &gpio_dev_attr,
1414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1415}; 1269};
@@ -1435,7 +1289,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
1435 }, 1289 },
1436 .slaves = omap2430_gpio2_slaves, 1290 .slaves = omap2430_gpio2_slaves,
1437 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), 1291 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1438 .class = &omap243x_gpio_hwmod_class, 1292 .class = &omap2xxx_gpio_hwmod_class,
1439 .dev_attr = &gpio_dev_attr, 1293 .dev_attr = &gpio_dev_attr,
1440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1441}; 1295};
@@ -1461,7 +1315,7 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
1461 }, 1315 },
1462 .slaves = omap2430_gpio3_slaves, 1316 .slaves = omap2430_gpio3_slaves,
1463 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), 1317 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1464 .class = &omap243x_gpio_hwmod_class, 1318 .class = &omap2xxx_gpio_hwmod_class,
1465 .dev_attr = &gpio_dev_attr, 1319 .dev_attr = &gpio_dev_attr,
1466 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1467}; 1321};
@@ -1487,7 +1341,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
1487 }, 1341 },
1488 .slaves = omap2430_gpio4_slaves, 1342 .slaves = omap2430_gpio4_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), 1343 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1490 .class = &omap243x_gpio_hwmod_class, 1344 .class = &omap2xxx_gpio_hwmod_class,
1491 .dev_attr = &gpio_dev_attr, 1345 .dev_attr = &gpio_dev_attr,
1492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1493}; 1347};
@@ -1518,28 +1372,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1518 }, 1372 },
1519 .slaves = omap2430_gpio5_slaves, 1373 .slaves = omap2430_gpio5_slaves,
1520 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), 1374 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1521 .class = &omap243x_gpio_hwmod_class, 1375 .class = &omap2xxx_gpio_hwmod_class,
1522 .dev_attr = &gpio_dev_attr, 1376 .dev_attr = &gpio_dev_attr,
1523 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1377 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1524}; 1378};
1525 1379
1526/* dma_system */
1527static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1528 .rev_offs = 0x0000,
1529 .sysc_offs = 0x002c,
1530 .syss_offs = 0x0028,
1531 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1532 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1533 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1534 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1535 .sysc_fields = &omap_hwmod_sysc_type1,
1536};
1537
1538static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1539 .name = "dma",
1540 .sysc = &omap2430_dma_sysc,
1541};
1542
1543/* dma attributes */ 1380/* dma attributes */
1544static struct omap_dma_dev_attr dma_dev_attr = { 1381static struct omap_dma_dev_attr dma_dev_attr = {
1545 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1382 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1576,7 +1413,7 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1576 1413
1577static struct omap_hwmod omap2430_dma_system_hwmod = { 1414static struct omap_hwmod omap2430_dma_system_hwmod = {
1578 .name = "dma", 1415 .name = "dma",
1579 .class = &omap2430_dma_hwmod_class, 1416 .class = &omap2xxx_dma_hwmod_class,
1580 .mpu_irqs = omap2_dma_system_irqs, 1417 .mpu_irqs = omap2_dma_system_irqs,
1581 .main_clk = "core_l3_ck", 1418 .main_clk = "core_l3_ck",
1582 .slaves = omap2430_dma_system_slaves, 1419 .slaves = omap2430_dma_system_slaves,
@@ -1588,27 +1425,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
1588 .flags = HWMOD_NO_IDLEST, 1425 .flags = HWMOD_NO_IDLEST,
1589}; 1426};
1590 1427
1591/*
1592 * 'mailbox' class
1593 * mailbox module allowing communication between the on-chip processors
1594 * using a queued mailbox-interrupt mechanism.
1595 */
1596
1597static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1598 .rev_offs = 0x000,
1599 .sysc_offs = 0x010,
1600 .syss_offs = 0x014,
1601 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1602 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1604 .sysc_fields = &omap_hwmod_sysc_type1,
1605};
1606
1607static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1608 .name = "mailbox",
1609 .sysc = &omap2430_mailbox_sysc,
1610};
1611
1612/* mailbox */ 1428/* mailbox */
1613static struct omap_hwmod omap2430_mailbox_hwmod; 1429static struct omap_hwmod omap2430_mailbox_hwmod;
1614static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 1430static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
@@ -1631,7 +1447,7 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1631 1447
1632static struct omap_hwmod omap2430_mailbox_hwmod = { 1448static struct omap_hwmod omap2430_mailbox_hwmod = {
1633 .name = "mailbox", 1449 .name = "mailbox",
1634 .class = &omap2430_mailbox_hwmod_class, 1450 .class = &omap2xxx_mailbox_hwmod_class,
1635 .mpu_irqs = omap2430_mailbox_irqs, 1451 .mpu_irqs = omap2430_mailbox_irqs,
1636 .main_clk = "mailboxes_ick", 1452 .main_clk = "mailboxes_ick",
1637 .prcm = { 1453 .prcm = {
@@ -1648,29 +1464,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
1648 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1649}; 1465};
1650 1466
1651/*
1652 * 'mcspi' class
1653 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1654 * bus
1655 */
1656
1657static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
1658 .rev_offs = 0x0000,
1659 .sysc_offs = 0x0010,
1660 .syss_offs = 0x0014,
1661 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1662 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1663 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1664 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1665 .sysc_fields = &omap_hwmod_sysc_type1,
1666};
1667
1668static struct omap_hwmod_class omap2430_mcspi_class = {
1669 .name = "mcspi",
1670 .sysc = &omap2430_mcspi_sysc,
1671 .rev = OMAP2_MCSPI_REV,
1672};
1673
1674/* mcspi1 */ 1467/* mcspi1 */
1675static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { 1468static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1676 &omap2430_l4_core__mcspi1, 1469 &omap2430_l4_core__mcspi1,
@@ -1696,8 +1489,8 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
1696 }, 1489 },
1697 .slaves = omap2430_mcspi1_slaves, 1490 .slaves = omap2430_mcspi1_slaves,
1698 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), 1491 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1699 .class = &omap2430_mcspi_class, 1492 .class = &omap2xxx_mcspi_class,
1700 .dev_attr = &omap_mcspi1_dev_attr, 1493 .dev_attr = &omap_mcspi1_dev_attr,
1701 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1494 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1702}; 1495};
1703 1496
@@ -1726,8 +1519,8 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
1726 }, 1519 },
1727 .slaves = omap2430_mcspi2_slaves, 1520 .slaves = omap2430_mcspi2_slaves,
1728 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), 1521 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1729 .class = &omap2430_mcspi_class, 1522 .class = &omap2xxx_mcspi_class,
1730 .dev_attr = &omap_mcspi2_dev_attr, 1523 .dev_attr = &omap_mcspi2_dev_attr,
1731 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1732}; 1525};
1733 1526
@@ -1769,8 +1562,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
1769 }, 1562 },
1770 .slaves = omap2430_mcspi3_slaves, 1563 .slaves = omap2430_mcspi3_slaves,
1771 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), 1564 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1772 .class = &omap2430_mcspi_class, 1565 .class = &omap2xxx_mcspi_class,
1773 .dev_attr = &omap_mcspi3_dev_attr, 1566 .dev_attr = &omap_mcspi3_dev_attr,
1774 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1775}; 1568};
1776 1569
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 7c4f5ab374a7..c451729d289a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -16,6 +16,164 @@
16 16
17#include "omap_hwmod_common_data.h" 17#include "omap_hwmod_common_data.h"
18 18
19/* UART */
20
21static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
22 .rev_offs = 0x50,
23 .sysc_offs = 0x54,
24 .syss_offs = 0x58,
25 .sysc_flags = (SYSC_HAS_SIDLEMODE |
26 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
27 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
29 .sysc_fields = &omap_hwmod_sysc_type1,
30};
31
32struct omap_hwmod_class omap2_uart_class = {
33 .name = "uart",
34 .sysc = &omap2_uart_sysc,
35};
36
37/*
38 * 'dss' class
39 * display sub-system
40 */
41
42static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss",
52 .sysc = &omap2_dss_sysc,
53};
54
55/*
56 * 'dispc' class
57 * display controller
58 */
59
60static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
61 .rev_offs = 0x0000,
62 .sysc_offs = 0x0010,
63 .syss_offs = 0x0014,
64 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
65 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
66 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
67 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
68 .sysc_fields = &omap_hwmod_sysc_type1,
69};
70
71struct omap_hwmod_class omap2_dispc_hwmod_class = {
72 .name = "dispc",
73 .sysc = &omap2_dispc_sysc,
74};
75
76/*
77 * 'rfbi' class
78 * remote frame buffer interface
79 */
80
81static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
86 SYSC_HAS_AUTOIDLE),
87 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
88 .sysc_fields = &omap_hwmod_sysc_type1,
89};
90
91struct omap_hwmod_class omap2_rfbi_hwmod_class = {
92 .name = "rfbi",
93 .sysc = &omap2_rfbi_sysc,
94};
95
96/*
97 * 'venc' class
98 * video encoder
99 */
100
101struct omap_hwmod_class omap2_venc_hwmod_class = {
102 .name = "venc",
103};
104
105
106/* Common DMA request line data */
107struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
108 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
109 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
110 { .dma_req = -1 }
111};
112
113struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
114 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
115 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
116 { .dma_req = -1 }
117};
118
119struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
120 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
121 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
122 { .dma_req = -1 }
123};
124
125struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
126 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
127 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
128 { .dma_req = -1 }
129};
130
131struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
132 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
133 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
134 { .dma_req = -1 }
135};
136
137struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
138 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
139 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
140 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
141 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
142 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
143 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
144 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
145 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
146 { .dma_req = -1 }
147};
148
149struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
150 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
151 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
152 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
153 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
154 { .dma_req = -1 }
155};
156
157struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
158 { .name = "rx", .dma_req = 32 },
159 { .name = "tx", .dma_req = 31 },
160 { .dma_req = -1 }
161};
162
163struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
164 { .name = "rx", .dma_req = 34 },
165 { .name = "tx", .dma_req = 33 },
166 { .dma_req = -1 }
167};
168
169struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
170 { .name = "rx", .dma_req = 18 },
171 { .name = "tx", .dma_req = 17 },
172 { .dma_req = -1 }
173};
174
175/* Other IP block data */
176
19 177
20/* 178/*
21 * omap_hwmod class data 179 * omap_hwmod class data
@@ -162,73 +320,3 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
162 { .irq = -1 } 320 { .irq = -1 }
163}; 321};
164 322
165/* Common DMA request line data */
166struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
167 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
168 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
169 { .dma_req = -1 }
170};
171
172struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
173 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
174 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
175 { .dma_req = -1 }
176};
177
178struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
179 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
180 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
181 { .dma_req = -1 }
182};
183
184struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
185 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
186 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
187 { .dma_req = -1 }
188};
189
190struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
191 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
192 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
193 { .dma_req = -1 }
194};
195
196struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
197 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
198 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
199 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
200 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
201 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
202 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
203 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
204 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
205 { .dma_req = -1 }
206};
207
208struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
209 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
210 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
211 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
212 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
213 { .dma_req = -1 }
214};
215
216struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
217 { .name = "rx", .dma_req = 32 },
218 { .name = "tx", .dma_req = 31 },
219 { .dma_req = -1 }
220};
221
222struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
223 { .name = "rx", .dma_req = 34 },
224 { .name = "tx", .dma_req = 33 },
225 { .dma_req = -1 }
226};
227
228struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
229 { .name = "rx", .dma_req = 18 },
230 { .name = "tx", .dma_req = 17 },
231 { .dma_req = -1 }
232};
233
234
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index f5b63efb1b67..177dee20faef 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -11,10 +11,13 @@
11#include <plat/omap_hwmod.h> 11#include <plat/omap_hwmod.h>
12#include <plat/serial.h> 12#include <plat/serial.h>
13#include <plat/dma.h> 13#include <plat/dma.h>
14#include <plat/dmtimer.h>
15#include <plat/mcspi.h>
14 16
15#include <mach/irqs.h> 17#include <mach/irqs.h>
16 18
17#include "omap_hwmod_common_data.h" 19#include "omap_hwmod_common_data.h"
20#include "wd_timer.h"
18 21
19struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { 22struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
20 { .irq = 48, }, 23 { .irq = 48, },
@@ -25,3 +28,123 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
25 { .name = "dispc", .dma_req = 5 }, 28 { .name = "dispc", .dma_req = 5 },
26 { .dma_req = -1 } 29 { .dma_req = -1 }
27}; 30};
31/* OMAP2xxx Timer Common */
32static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
33 .rev_offs = 0x0000,
34 .sysc_offs = 0x0010,
35 .syss_offs = 0x0014,
36 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
37 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
38 SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
40 .sysc_fields = &omap_hwmod_sysc_type1,
41};
42
43struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
44 .name = "timer",
45 .sysc = &omap2xxx_timer_sysc,
46 .rev = OMAP_TIMER_IP_VERSION_1,
47};
48
49/*
50 * 'wd_timer' class
51 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
52 * overflow condition
53 */
54
55static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
56 .rev_offs = 0x0000,
57 .sysc_offs = 0x0010,
58 .syss_offs = 0x0014,
59 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
60 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
62};
63
64struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
65 .name = "wd_timer",
66 .sysc = &omap2xxx_wd_timer_sysc,
67 .pre_shutdown = &omap2_wd_timer_disable
68};
69
70/*
71 * 'gpio' class
72 * general purpose io module
73 */
74static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
75 .rev_offs = 0x0000,
76 .sysc_offs = 0x0010,
77 .syss_offs = 0x0014,
78 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
79 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
80 SYSS_HAS_RESET_STATUS),
81 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
82 .sysc_fields = &omap_hwmod_sysc_type1,
83};
84
85struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
86 .name = "gpio",
87 .sysc = &omap2xxx_gpio_sysc,
88 .rev = 0,
89};
90
91/* system dma */
92static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
93 .rev_offs = 0x0000,
94 .sysc_offs = 0x002c,
95 .syss_offs = 0x0028,
96 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
97 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
98 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
99 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
100 .sysc_fields = &omap_hwmod_sysc_type1,
101};
102
103struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
104 .name = "dma",
105 .sysc = &omap2xxx_dma_sysc,
106};
107
108/*
109 * 'mailbox' class
110 * mailbox module allowing communication between the on-chip processors
111 * using a queued mailbox-interrupt mechanism.
112 */
113
114static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
115 .rev_offs = 0x000,
116 .sysc_offs = 0x010,
117 .syss_offs = 0x014,
118 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
119 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
121 .sysc_fields = &omap_hwmod_sysc_type1,
122};
123
124struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
125 .name = "mailbox",
126 .sysc = &omap2xxx_mailbox_sysc,
127};
128
129/*
130 * 'mcspi' class
131 * multichannel serial port interface (mcspi) / master/slave synchronous serial
132 * bus
133 */
134
135static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
141 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
143 .sysc_fields = &omap_hwmod_sysc_type1,
144};
145
146struct omap_hwmod_class omap2xxx_mcspi_class = {
147 .name = "mcspi",
148 .sysc = &omap2xxx_mcspi_sysc,
149 .rev = OMAP2_MCSPI_REV,
150};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 001f67b8777d..1a52716e48bf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1190,24 +1190,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1190 .flags = HWMOD_SWSUP_SIDLE, 1190 .flags = HWMOD_SWSUP_SIDLE,
1191}; 1191};
1192 1192
1193/* UART common */
1194
1195static struct omap_hwmod_class_sysconfig uart_sysc = {
1196 .rev_offs = 0x50,
1197 .sysc_offs = 0x54,
1198 .syss_offs = 0x58,
1199 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1200 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1201 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1202 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1203 .sysc_fields = &omap_hwmod_sysc_type1,
1204};
1205
1206static struct omap_hwmod_class uart_class = {
1207 .name = "uart",
1208 .sysc = &uart_sysc,
1209};
1210
1211/* UART1 */ 1193/* UART1 */
1212 1194
1213static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 1195static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
@@ -1230,7 +1212,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1230 }, 1212 },
1231 .slaves = omap3xxx_uart1_slaves, 1213 .slaves = omap3xxx_uart1_slaves,
1232 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1233 .class = &uart_class, 1215 .class = &omap2_uart_class,
1234 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1235}; 1217};
1236 1218
@@ -1256,7 +1238,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1256 }, 1238 },
1257 .slaves = omap3xxx_uart2_slaves, 1239 .slaves = omap3xxx_uart2_slaves,
1258 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1259 .class = &uart_class, 1241 .class = &omap2_uart_class,
1260 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1261}; 1243};
1262 1244
@@ -1282,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1282 }, 1264 },
1283 .slaves = omap3xxx_uart3_slaves, 1265 .slaves = omap3xxx_uart3_slaves,
1284 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1285 .class = &uart_class, 1267 .class = &omap2_uart_class,
1286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287}; 1269};
1288 1270
@@ -1319,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1319 }, 1301 },
1320 .slaves = omap3xxx_uart4_slaves, 1302 .slaves = omap3xxx_uart4_slaves,
1321 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1322 .class = &uart_class, 1304 .class = &omap2_uart_class,
1323 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1324}; 1306};
1325 1307
@@ -1328,24 +1310,6 @@ static struct omap_hwmod_class i2c_class = {
1328 .sysc = &i2c_sysc, 1310 .sysc = &i2c_sysc,
1329}; 1311};
1330 1312
1331/*
1332 * 'dss' class
1333 * display sub-system
1334 */
1335
1336static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1337 .rev_offs = 0x0000,
1338 .sysc_offs = 0x0010,
1339 .syss_offs = 0x0014,
1340 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1341 .sysc_fields = &omap_hwmod_sysc_type1,
1342};
1343
1344static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1345 .name = "dss",
1346 .sysc = &omap3xxx_dss_sysc,
1347};
1348
1349static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 1313static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350 { .name = "dispc", .dma_req = 5 }, 1314 { .name = "dispc", .dma_req = 5 },
1351 { .name = "dsi1", .dma_req = 74 }, 1315 { .name = "dsi1", .dma_req = 74 },
@@ -1406,7 +1370,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1406 1370
1407static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1371static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1408 .name = "dss_core", 1372 .name = "dss_core",
1409 .class = &omap3xxx_dss_hwmod_class, 1373 .class = &omap2_dss_hwmod_class,
1410 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1374 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1411 .sdma_reqs = omap3xxx_dss_sdma_chs, 1375 .sdma_reqs = omap3xxx_dss_sdma_chs,
1412 .prcm = { 1376 .prcm = {
@@ -1430,7 +1394,7 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1430 1394
1431static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1395static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1432 .name = "dss_core", 1396 .name = "dss_core",
1433 .class = &omap3xxx_dss_hwmod_class, 1397 .class = &omap2_dss_hwmod_class,
1434 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1398 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1435 .sdma_reqs = omap3xxx_dss_sdma_chs, 1399 .sdma_reqs = omap3xxx_dss_sdma_chs,
1436 .prcm = { 1400 .prcm = {
@@ -1453,28 +1417,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1453 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), 1417 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1454}; 1418};
1455 1419
1456/*
1457 * 'dispc' class
1458 * display controller
1459 */
1460
1461static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1462 .rev_offs = 0x0000,
1463 .sysc_offs = 0x0010,
1464 .syss_offs = 0x0014,
1465 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1466 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1467 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1468 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1469 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1470 .sysc_fields = &omap_hwmod_sysc_type1,
1471};
1472
1473static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1474 .name = "dispc",
1475 .sysc = &omap3xxx_dispc_sysc,
1476};
1477
1478/* l4_core -> dss_dispc */ 1420/* l4_core -> dss_dispc */
1479static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1421static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1480 .master = &omap3xxx_l4_core_hwmod, 1422 .master = &omap3xxx_l4_core_hwmod,
@@ -1498,7 +1440,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1498 1440
1499static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1441static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1500 .name = "dss_dispc", 1442 .name = "dss_dispc",
1501 .class = &omap3xxx_dispc_hwmod_class, 1443 .class = &omap2_dispc_hwmod_class,
1502 .mpu_irqs = omap2_dispc_irqs, 1444 .mpu_irqs = omap2_dispc_irqs,
1503 .main_clk = "dss1_alwon_fck", 1445 .main_clk = "dss1_alwon_fck",
1504 .prcm = { 1446 .prcm = {
@@ -1580,26 +1522,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1580 .flags = HWMOD_NO_IDLEST, 1522 .flags = HWMOD_NO_IDLEST,
1581}; 1523};
1582 1524
1583/*
1584 * 'rfbi' class
1585 * remote frame buffer interface
1586 */
1587
1588static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1589 .rev_offs = 0x0000,
1590 .sysc_offs = 0x0010,
1591 .syss_offs = 0x0014,
1592 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1593 SYSC_HAS_AUTOIDLE),
1594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1595 .sysc_fields = &omap_hwmod_sysc_type1,
1596};
1597
1598static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1599 .name = "rfbi",
1600 .sysc = &omap3xxx_rfbi_sysc,
1601};
1602
1603/* l4_core -> dss_rfbi */ 1525/* l4_core -> dss_rfbi */
1604static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1526static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1605 .master = &omap3xxx_l4_core_hwmod, 1527 .master = &omap3xxx_l4_core_hwmod,
@@ -1623,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1623 1545
1624static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1546static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1625 .name = "dss_rfbi", 1547 .name = "dss_rfbi",
1626 .class = &omap3xxx_rfbi_hwmod_class, 1548 .class = &omap2_rfbi_hwmod_class,
1627 .main_clk = "dss1_alwon_fck", 1549 .main_clk = "dss1_alwon_fck",
1628 .prcm = { 1550 .prcm = {
1629 .omap2 = { 1551 .omap2 = {
@@ -1640,15 +1562,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1640 .flags = HWMOD_NO_IDLEST, 1562 .flags = HWMOD_NO_IDLEST,
1641}; 1563};
1642 1564
1643/*
1644 * 'venc' class
1645 * video encoder
1646 */
1647
1648static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1649 .name = "venc",
1650};
1651
1652/* l4_core -> dss_venc */ 1565/* l4_core -> dss_venc */
1653static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1566static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1654 .master = &omap3xxx_l4_core_hwmod, 1567 .master = &omap3xxx_l4_core_hwmod,
@@ -1673,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1673 1586
1674static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1587static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1675 .name = "dss_venc", 1588 .name = "dss_venc",
1676 .class = &omap3xxx_venc_hwmod_class, 1589 .class = &omap2_venc_hwmod_class,
1677 .main_clk = "dss1_alwon_fck", 1590 .main_clk = "dss1_alwon_fck",
1678 .prcm = { 1591 .prcm = {
1679 .omap2 = { 1592 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index b636cf6a62d4..39a7c37f4587 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -98,6 +98,17 @@ extern struct omap_hwmod_class l3_hwmod_class;
98extern struct omap_hwmod_class l4_hwmod_class; 98extern struct omap_hwmod_class l4_hwmod_class;
99extern struct omap_hwmod_class mpu_hwmod_class; 99extern struct omap_hwmod_class mpu_hwmod_class;
100extern struct omap_hwmod_class iva_hwmod_class; 100extern struct omap_hwmod_class iva_hwmod_class;
101extern struct omap_hwmod_class omap2_uart_class;
102extern struct omap_hwmod_class omap2_dss_hwmod_class;
103extern struct omap_hwmod_class omap2_dispc_hwmod_class;
104extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
105extern struct omap_hwmod_class omap2_venc_hwmod_class;
101 106
107extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
108extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
109extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
110extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class;
102 113
103#endif 114#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 14:46:07 -0400