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authorAKASHI Takahiro <takahiro.akashi@linaro.org>2014-04-30 05:54:30 -0400
committerWill Deacon <will.deacon@arm.com>2014-05-29 04:04:31 -0400
commit26e9b83a7d3e9dbe276301b637f65321bdd0939b (patch)
tree19aee72866e30f2f5b21826b8def8d5dee09e17a
parent2eb8b396dc6ecf797925cc6bad4c0c6dfbdf4d44 (diff)
arm64: add __ASSEMBLY__ in asm/insn.h
Since insn.h is indirectly included in asm/entry-ftrace.S, we need to exclude some declarations by __ASSEMBLY__. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm64/include/asm/insn.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index c44ad39ed310..dc1f73b13e74 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -21,6 +21,7 @@
21/* A64 instructions are always 32 bits. */ 21/* A64 instructions are always 32 bits. */
22#define AARCH64_INSN_SIZE 4 22#define AARCH64_INSN_SIZE 4
23 23
24#ifndef __ASSEMBLY__
24/* 25/*
25 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a 26 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
26 * Section C3.1 "A64 instruction index by encoding": 27 * Section C3.1 "A64 instruction index by encoding":
@@ -104,5 +105,6 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
104int aarch64_insn_patch_text_nosync(void *addr, u32 insn); 105int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
105int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt); 106int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
106int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt); 107int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
108#endif /* __ASSEMBLY__ */
107 109
108#endif /* __ASM_INSN_H */ 110#endif /* __ASM_INSN_H */