diff options
author | Kenneth Graunke <kenneth@whitecape.org> | 2012-10-07 11:51:07 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-12 04:59:02 -0400 |
commit | 26b6e44afb58432a5e998da0343757404f9de9ee (patch) | |
tree | 8437adced85f96dbe2c41b6a9d8eea316d12dcd4 | |
parent | 6ce9410047f9f06c1b3336d5215402b77d6fd70f (diff) |
drm/i915: Set guardband clipping workaround bit in the right register.
A previous patch, namely:
commit bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed Apr 11 20:42:41 2012 +0200
drm/i915: implement w/a for incorrect guarband clipping
accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with
clipping. This patch changes it to be set in 3D_CHICKEN3, where it
belongs.
The game "Dante" demonstrates random clipping issues when guardband
clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the
workaround is actually necessary.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 64c1be0a9cfd..a4162ddff6c5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -521,7 +521,7 @@ | |||
521 | */ | 521 | */ |
522 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | 522 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
523 | #define _3D_CHICKEN3 0x02090 | 523 | #define _3D_CHICKEN3 0x02090 |
524 | #define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) | 524 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
525 | 525 | ||
526 | #define MI_MODE 0x0209c | 526 | #define MI_MODE 0x0209c |
527 | # define VS_TIMER_DISPATCH (1 << 6) | 527 | # define VS_TIMER_DISPATCH (1 << 6) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b3b4b6cea8b0..72f41aaa71ff 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -3442,8 +3442,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) | |||
3442 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | 3442 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
3443 | 3443 | ||
3444 | /* Bspec says we need to always set all mask bits. */ | 3444 | /* Bspec says we need to always set all mask bits. */ |
3445 | I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) | | 3445 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3446 | _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); | 3446 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
3447 | 3447 | ||
3448 | /* | 3448 | /* |
3449 | * According to the spec the following bits should be | 3449 | * According to the spec the following bits should be |