diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2012-12-05 12:46:04 -0500 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2012-12-06 14:58:57 -0500 |
| commit | 26107309c08f8548a2e0aef0d0aabd64bc2d22c1 (patch) | |
| tree | 195b0d5b03f6b0a78591e71eb397fcb0309dd972 | |
| parent | f924e1e989b0bdaf6472668400d67a2142cb6b60 (diff) | |
ssb: set the PMU watchdog if available
Some ssb based devices have a PMU and the PMU watchdog register should
be used instead of the register in the chip common part, if the device
has a PMU. This patch also calculates the maximal number the watchdog
could be set to.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/ssb/driver_chipcommon.c | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 603b63032e93..6e080f6a07a5 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c | |||
| @@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc) | |||
| 288 | return 20000000; | 288 | return 20000000; |
| 289 | } | 289 | } |
| 290 | 290 | ||
| 291 | static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc) | ||
| 292 | { | ||
| 293 | u32 nb; | ||
| 294 | |||
| 295 | if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { | ||
| 296 | if (cc->dev->id.revision < 26) | ||
| 297 | nb = 16; | ||
| 298 | else | ||
| 299 | nb = (cc->dev->id.revision >= 37) ? 32 : 24; | ||
| 300 | } else { | ||
| 301 | nb = 28; | ||
| 302 | } | ||
| 303 | if (nb == 32) | ||
| 304 | return 0xffffffff; | ||
| 305 | else | ||
| 306 | return (1 << nb) - 1; | ||
| 307 | } | ||
| 308 | |||
| 291 | void ssb_chipcommon_init(struct ssb_chipcommon *cc) | 309 | void ssb_chipcommon_init(struct ssb_chipcommon *cc) |
| 292 | { | 310 | { |
| 293 | if (!cc->dev) | 311 | if (!cc->dev) |
| @@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_chipcommon *cc, | |||
| 405 | /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ | 423 | /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ |
| 406 | void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) | 424 | void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) |
| 407 | { | 425 | { |
| 408 | /* instant NMI */ | 426 | u32 maxt; |
| 409 | chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); | 427 | enum ssb_clkmode clkmode; |
| 428 | |||
| 429 | maxt = ssb_chipco_watchdog_get_max_timer(cc); | ||
| 430 | if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { | ||
| 431 | if (ticks == 1) | ||
| 432 | ticks = 2; | ||
| 433 | else if (ticks > maxt) | ||
| 434 | ticks = maxt; | ||
| 435 | chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks); | ||
| 436 | } else { | ||
| 437 | clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC; | ||
| 438 | ssb_chipco_set_clockmode(cc, clkmode); | ||
| 439 | if (ticks > maxt) | ||
| 440 | ticks = maxt; | ||
| 441 | /* instant NMI */ | ||
| 442 | chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); | ||
| 443 | } | ||
| 410 | } | 444 | } |
| 411 | 445 | ||
| 412 | void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) | 446 | void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
