drm/radeon/kms: add support for interrupts on SI

This is mostly identical to evergreen/ni, however
there are some additional fields in the IV vector
for RINGID and VMID.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 881 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 5eb23829353f..924b68718b82 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2778,7 +2778,7 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
         rdev->ih.rptr = 0;
 }
 
-static int r600_ih_ring_alloc(struct radeon_device *rdev)
+int r600_ih_ring_alloc(struct radeon_device *rdev)
 {
         int r;
 
@@ -2814,7 +2814,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev)
         return 0;
 }
 
-static void r600_ih_ring_fini(struct radeon_device *rdev)
+void r600_ih_ring_fini(struct radeon_device *rdev)
 {
         int r;
         if (rdev->ih.ring_obj) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 4252cd0ab64b..6aecbf54cd5d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -55,6 +55,8 @@ MODULE_FIRMWARE("radeon/VERDE_ce.bin");
 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
 
+extern int r600_ih_ring_alloc(struct radeon_device *rdev);
+extern void r600_ih_ring_fini(struct radeon_device *rdev);
 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
@@ -3072,3 +3074,722 @@ static int si_rlc_resume(struct radeon_device *rdev)
         return 0;
 }
 
+static void si_enable_interrupts(struct radeon_device *rdev)
+{
+        u32 ih_cntl = RREG32(IH_CNTL);
+        u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+
+        ih_cntl |= ENABLE_INTR;
+        ih_rb_cntl |= IH_RB_ENABLE;
+        WREG32(IH_CNTL, ih_cntl);
+        WREG32(IH_RB_CNTL, ih_rb_cntl);
+        rdev->ih.enabled = true;
+}
+
+static void si_disable_interrupts(struct radeon_device *rdev)
+{
+        u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+        u32 ih_cntl = RREG32(IH_CNTL);
+
+        ih_rb_cntl &= ~IH_RB_ENABLE;
+        ih_cntl &= ~ENABLE_INTR;
+        WREG32(IH_RB_CNTL, ih_rb_cntl);
+        WREG32(IH_CNTL, ih_cntl);
+        /* set rptr, wptr to 0 */
+        WREG32(IH_RB_RPTR, 0);
+        WREG32(IH_RB_WPTR, 0);
+        rdev->ih.enabled = false;
+        rdev->ih.wptr = 0;
+        rdev->ih.rptr = 0;
+}
+
+static void si_disable_interrupt_state(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+        WREG32(CP_INT_CNTL_RING1, 0);
+        WREG32(CP_INT_CNTL_RING2, 0);
+        WREG32(GRBM_INT_CNTL, 0);
+        WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+        WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+        if (rdev->num_crtc >= 4) {
+                WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+                WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+        }
+        if (rdev->num_crtc >= 6) {
+                WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+                WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+        }
+
+        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+        if (rdev->num_crtc >= 4) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+        }
+        if (rdev->num_crtc >= 6) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+        }
+
+        WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+
+        tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD1_INT_CONTROL, tmp);
+        tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD2_INT_CONTROL, tmp);
+        tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD3_INT_CONTROL, tmp);
+        tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD4_INT_CONTROL, tmp);
+        tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD5_INT_CONTROL, tmp);
+        tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD6_INT_CONTROL, tmp);
+
+}
+
+static int si_irq_init(struct radeon_device *rdev)
+{
+        int ret = 0;
+        int rb_bufsz;
+        u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
+
+        /* allocate ring */
+        ret = r600_ih_ring_alloc(rdev);
+        if (ret)
+                return ret;
+
+        /* disable irqs */
+        si_disable_interrupts(rdev);
+
+        /* init rlc */
+        ret = si_rlc_resume(rdev);
+        if (ret) {
+                r600_ih_ring_fini(rdev);
+                return ret;
+        }
+
+        /* setup interrupt control */
+        /* set dummy read address to ring address */
+        WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
+        interrupt_cntl = RREG32(INTERRUPT_CNTL);
+        /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
+         * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
+         */
+        interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
+        /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
+        interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
+        WREG32(INTERRUPT_CNTL, interrupt_cntl);
+
+        WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
+        rb_bufsz = drm_order(rdev->ih.ring_size / 4);
+
+        ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
+                      IH_WPTR_OVERFLOW_CLEAR |
+                      (rb_bufsz << 1));
+
+        if (rdev->wb.enabled)
+                ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
+
+        /* set the writeback address whether it's enabled or not */
+        WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
+        WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
+
+        WREG32(IH_RB_CNTL, ih_rb_cntl);
+
+        /* set rptr, wptr to 0 */
+        WREG32(IH_RB_RPTR, 0);
+        WREG32(IH_RB_WPTR, 0);
+
+        /* Default settings for IH_CNTL (disabled at first) */
+        ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
+        /* RPTR_REARM only works if msi's are enabled */
+        if (rdev->msi_enabled)
+                ih_cntl |= RPTR_REARM;
+        WREG32(IH_CNTL, ih_cntl);
+
+        /* force the active interrupt state to all disabled */
+        si_disable_interrupt_state(rdev);
+
+        /* enable irqs */
+        si_enable_interrupts(rdev);
+
+        return ret;
+}
+
+int si_irq_set(struct radeon_device *rdev)
+{
+        u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
+        u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;